Optimization method of FPGA carry chain unit

Abstract

The application discloses an optimization method of an FPGA carry chain unit, comprising the following steps: traversing each calculation unit from the head and / or tail of a to-be-optimized carry chain; determining whether an element meeting a preset condition exists in each calculation unit to obtain a to-be-optimized element, wherein the preset condition comprises at least one of the following: input is a constant, output is a constant, and input is the same; deleting the to-be-optimized element from the to-be-optimized carry chain and reconstructing the connection topology of the to-be-optimized carry chain to obtain an optimized carry chain. The application simplifies the part that can be reused or the logic calculation process of which can be omitted in the to-be-optimized carry chain by deleting and reconstructing the connection topology of the to-be-optimized carry chain, thereby reducing the resource quantity of the FPGA chip occupied by the carry chain; since the application does not use a lookup table to optimize the carry chain, the delay caused by this method can be avoided, and the calculation efficiency is ensured while the resource occupation is reduced.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology, specifically relating to an optimization method for FPGA carry chain units. Background Technology

[0002] Field-Programmable Gate Arrays (FPGAs), as the core devices of reconfigurable computing, utilize configurable logic blocks (CLBs) within their cores, which are flexibly configured through programmable interconnect networks to achieve different functions. CLBs contain various hardware resources, typically including lookup tables (LUTs), multiplexers (MUXs), carry chains, and flip-flops (FFs). The carry chain is a dedicated hardware structure in FPGAs used to accelerate arithmetic operations. In arithmetic operations (such as addition and subtraction), the carry signal needs to be passed step-by-step from the least significant bit to the most significant bit. Traditional methods use general-purpose logic units (such as LUTs) to implement carry logic, but this incurs a delay due to waiting at each level. The carry chain, by directly transmitting the carry signal through a dedicated hardware path, avoids this delay and is a key resource for arithmetic modules such as high-speed adders and counters.

[0003] As FPGA applications expand to high-performance computing (such as AI inference and 5G baseband), the complexity of arithmetic logic is increasing exponentially, the required computational operations are increasing dramatically, and the corresponding carry chain resources are also increasing dramatically.

[0004] Because there is an upper limit to the number of FPGA resources, some methods use lookup tables to implement the corresponding logic of the carry chain when the carry chain resource limit is reached in the FPGA design. This reduces the use of the carry chain and thus overcomes the resource bottleneck of the carry chain. However, the carry latency implemented by lookup tables is much higher than that of the carry chain, resulting in higher latency and a decrease in clock frequency. Functionally, this means slower computing speed, increased time to complete a calculation task, and inability to obtain effective calculation results within a limited runtime.

[0005] Another approach is to directly select an FPGA chip with a higher resource count. However, the resource count and price of an FPGA chip are strongly positively correlated. When the required carry chain resources exceed the upper limit, more resources are needed to enable the FPGA chip to perform the expected function, thus requiring a more advanced and expensive FPGA chip.

[0006] Therefore, current carry chain optimization methods suffer from high costs and poor computational efficiency of the optimized carry chain.

[0007] To address the aforementioned issues, an optimization method for FPGA carry chain units is needed to achieve high-performance arithmetic operations under the constraint of limited FPGA chip resources by reducing the use of carry chain resources. Summary of the Invention

[0008] This invention provides an optimization method for FPGA carry chain units, which can solve the above-mentioned technical problems.

[0009] This invention provides an optimization method for an FPGA carry chain unit. The method is used on an FPGA chip, which includes at least one carry chain to be optimized. The carry chain to be optimized consists of multiple cascaded computing units. The method includes:

[0010] Traverse each computational unit starting from the head and / or tail of the carry chain to be optimized;

[0011] Determine whether there is a component in each computing unit that meets preset conditions to obtain the component to be optimized, wherein the preset conditions include at least one of the following: the input is constant, the output is constant, or the inputs are the same;

[0012] Remove the element to be optimized from the carry chain to be optimized, and reconstruct the connection topology of the carry chain to be optimized to obtain the optimized carry chain.

[0013] The beneficial effects of the present invention compared with the prior art are as follows: The present invention simplifies the reusable or omitting parts of the carry chain by deleting and reconstructing the connection topology of the carry chain to be optimized, thereby reducing the amount of FPGA chip resources occupied by the carry chain; Since the present invention does not use LUT to optimize the carry chain, the delay caused by this method can be avoided, and the computational efficiency is guaranteed while reducing resource consumption. Attached Figure Description

[0014] Figure 1 A schematic diagram of a carry chain to be optimized, provided for an embodiment of the present invention;

[0015] Figure 2 A flowchart illustrating the implementation of an optimization method for an FPGA carry chain unit provided in an embodiment of the present invention;

[0016] Figure 3a This is a schematic diagram of a structure for deleting the carry chain after deleting the i-th level data selector, provided by an embodiment of the present invention.

[0017] Figure 3b This is a schematic diagram of a structure for deleting the carry chain after the i-th level XOR gate, provided by an embodiment of the present invention;

[0018] Figure 3c This is a schematic diagram of a structure for deleting the carry chain after deleting the i-th level data selector and the i-th level XOR gate, provided in an embodiment of the present invention.

[0019] Figure 4 This is a schematic diagram of a carry chain structure provided in an embodiment of the present invention;

[0020] Figure 5a This is a schematic diagram of the carry chain to be optimized after deleting the data selector and reconstructing the topology connection when the output is constant, according to an embodiment of the present invention.

[0021] Figure 5b This is a schematic diagram of the carry chain to be optimized after deleting the data selector and reconstructing the topology connection when Si is a constant 1 or the inputs are equal, provided by an embodiment of the present invention.

[0022] Figure 5c This is a schematic diagram of the carry chain to be optimized after deleting the data selector and reconstructing the topology connection when Si is a constant 0 or the inputs are equal, provided by an embodiment of the present invention.

[0023] Figure 6a This is a schematic diagram of the carry chain to be optimized after deleting the XOR gate and reconstructing the topology connection when COi-1 is a constant of 0, according to an embodiment of the present invention.

[0024] Figure 6b This is a schematic diagram of the carry chain to be optimized after deleting the XOR gate and reconstructing the topology connection when COi-1 is a constant of 1, provided by an embodiment of the present invention.

[0025] Figure 7a This is a schematic diagram of the carry chain structure to be optimized after deleting the XOR gate and data selector and reconstructing the topology connection when Si, I1i, and COi-1 are all constants, provided as an embodiment of the present invention.

[0026] Figure 7b This is a schematic diagram of the carry chain to be optimized after deleting the XOR gate and data selector and reconstructing the topology connection when I1i and COi-1 are constant 1, as provided in an embodiment of the present invention.

[0027] Figure 7c A schematic diagram of the carry chain to be optimized after deleting the XOR gate and data selector and reconstructing the topology connection when I1i and COi-1 are constant 1, provided as an embodiment of the present invention.

[0028] Figure 8 This is a schematic diagram illustrating an optimized carry chain scenario provided by an embodiment of the present invention.

[0029] Figure label:

[0030] XOR(i): XOR gate of level i; MUX(i): data selector of level i; COi: carry data of level i; Si: signal data of level i; Oi: calculation result of level i; I1i: data to be calculated of level i; SO: signal data output terminal; DO: input terminal; IO: output terminal of data to be calculated.

[0031] Figure label:

[0032] XOR(i): XOR gate of level i; MUX(i): data selector of level i; COi: carry data of level i; Si: signal data of level i; Oi: calculation result of level i; I1i: data to be calculated of level i; SO: signal data output terminal; DO: input terminal; IO: output terminal of data to be calculated. Detailed Implementation

[0033] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of the invention. However, those skilled in the art will understand that the invention can be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods are omitted so as not to obscure the description of the invention with unnecessary detail.

[0034] It should be understood that, when used in this specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.

[0035] It should also be understood that the term “and / or” as used in this specification and the appended claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0036] As used in this specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if [described condition or event] is detected" may be interpreted, depending on the context, as meaning "once determined," "in response to determination," "once [described condition or event] is detected," or "in response to detection of [described condition or event]."

[0037] Furthermore, in the description of this invention and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0038] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of the invention include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0039] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0040] Example 1

[0041] Figure 1 The diagram shown illustrates a carry chain structure to be optimized according to an embodiment of the present invention. See also, as an example and not a limitation. Figure 1 A carry chain to be optimized can consist of Imax cascaded computational units.

[0042] In one possible implementation, see Figure 1 Each computational unit may include a data selector and an exclusive OR gate (XOR gate).

[0043] Specifically, when i is greater than 0, the I0 input of the i-th level XOR gate XOR(i) in the (i+1)-th calculation unit can be connected to the output of the (i-1)-th level data selector MUX(i-1) in the i-th calculation unit. The I0 input input inputs the (i-1)-th level carry data COi-1 to the XOR gate XOR(i); the I1 input input is connected to the signal data output SO, inputting the i-th level signal data Si; the output is connected to the sum input DO, outputting the i-th level calculation result Oi to the sum input DO.

[0044] Specifically, when i is greater than 0, the I0 input of the i-th level data selector MUX(i) can also be connected to the output of the (i-1)-th level data selector MUX(i-1), and the I0 input input inputs the (i-1)-th level carry data COi-1 to the i-th level data selector MUX(i); the I1 input is connected to the output of the data to be calculated IO, and the i-th level data to be calculated I1i is input; the signal input is connected to the signal data output SO, and the i-th level signal data Si is input; the output is connected to the I0 input of the (i+1)-th level data selector MUX(i+1) and the (i+1)-th level XOR gate XOR(i+1), and outputs the i-th level carry data COi to them.

[0045] Here, i can be a non-negative integer less than or equal to Imax-1. When i=0, the signal input to the I0 input terminal of the 0th level XOR (0) and the 0th level data selector MUX (0) in the first calculation unit can be the set initial carry signal Cin.

[0046] In one example, the combinational logic expression of the i-th level data selector MUX(i) can be represented as:

[0047] (1.1),

[0048] in, Indicates negation.

[0049] In one example, the combinational logic expression of the i-th level XOR gate XOR(i) can be represented as:

[0050] (1.2).

[0051] Example 2

[0052] Figure 2 The diagram illustrates an implementation flowchart of an optimization method for an FPGA carry chain unit provided by an embodiment of the present invention. As an example and not a limitation, the method may include steps S201-S205, which are described below.

[0053] S201, traverse each computational unit starting from the head and / or tail of the carry chain to be optimized.

[0054] In one example, you can start from the head or tail of the carry chain to be optimized and traverse and check the data selectors and XOR gates in each computational unit to determine whether they meet the preset conditions.

[0055] In another example, you can also start by traversing the carry chain to be optimized and checking the data selector / XOR gate in each computational unit, and then start by traversing the carry chain to check the XOR gate / data selector in each computational unit.

[0056] Starting from the head and / or tail of the carry chain, prioritize deleting components at both ends. This ensures that the carry chain to be optimized is not split into two, thus guaranteeing the integrity of the carry chain.

[0057] S202, determine whether there are any components in each computing unit that meet the preset conditions, and obtain the components to be optimized.

[0058] In some embodiments, the element to be optimized may include a data selector and / or an XOR gate.

[0059] For example, users can select the type of component to be optimized based on the resource usage within the FPGA chip. For instance, if the number of data selectors / XOR gates within the FPGA chip is limited, while other component resources are sufficient, and it's necessary to prioritize releasing data selectors / XOR gates, the user can filter data selectors / XOR gates from the computing units that meet preset conditions. Alternatively, when both data selector and XOR gate resources are scarce in the FPGA chip, users can simultaneously filter data selectors and XOR gates that meet preset conditions.

[0060] It should be understood that when the components to be optimized here include data selectors and XOR gates, the data selectors and XOR gates that are optimized out can belong to the same computational unit or different computational units.

[0061] In one possible implementation, the preset conditions may include at least one of the following: the input is constant, the output is constant, or the input is the same.

[0062] For example, the output being constant requires that each input be constant. The preset condition includes the condition that the output is constant, which implicitly means that the inputs are all constant.

[0063] In one example, if the component to be optimized includes a data selector, the preset conditions include the first type of preset conditions, which may specifically include: the i-th level carry data COi is constant (output is constant), the i-th level signal data Si is constant (input is constant), or the i-th level data to be calculated I1i is equal to the (i-1)-th level carry data COi-1 (input is equal).

[0064] In another example, if the component to be optimized includes an XOR gate, the preset conditions include a second type of preset conditions, which may specifically include: the i-th level calculation result Oi is a constant (the output is constant) or the (i-1)-th level carry data COi-1 is a constant (the input is constant).

[0065] S203, remove the element to be optimized from the carry chain to be optimized, and reconstruct the connection topology of the carry chain to be optimized to obtain the optimized carry chain.

[0066] In one possible implementation, the element to be optimized can be removed from the carry chain by disconnecting the element from other elements in the carry chain.

[0067] In one example, see Figure 3aIf the element to be optimized includes the i-th level data selector MUX(i), then the connection between the I0 input of the i-th level data selector MUX(i) and the output of the (i-1)-th level data selector MUX(i-1), the connection between the I1 input and the output of the data to be calculated IO, the connection between the signal input and the signal data output SO, and the connection between the output and the I0 input of the (i+1)-th level data selector MUX(i+1) and the (i+1)-th level XOR gate XOR(i+1) can be removed from the carry chain to be optimized.

[0068] See another example. Figure 3b If the element to be optimized includes the i-th level XOR gate XOR(i), the connection between the I0 input terminal of the i-th level XOR gate XOR(i) and the output terminal of the (i-1)-th level data selector MUX(i-1), the connection between the I1 input terminal and the signal data output terminal SO, and the connection between the output terminal and the input terminal DO can be disconnected, thereby removing the i-th level XOR gate XOR(i) from the carry chain to be optimized.

[0069] In yet another example, see Figure 3c If the components to be optimized include the i-th level data selector MUX(i) and the i-th level XOR gate XOR(i), then the above can be referred to. Figure 3a , Figure 3b The method disconnects these two elements from the rest of the carry chain and ports, removing them from the carry chain to be optimized.

[0070] In one possible implementation, after deleting a component, the connection topology of the carry chain to be optimized can be reconstructed based on the preset conditions satisfied by the component to be optimized, thus obtaining the optimized carry chain.

[0071] Optionally, the optimization method may also include steps S204-S205.

[0072] S204 determines whether there is a logically identical carry chain in the FPGA chip.

[0073] For example, logical similarity means that both the input and output are identical. See also Figure 4 The complete carry chain structure shown, where the inputs and outputs are identical, means that the initial carry signal Cin, the i-th level signal data Si, and the i-th level data to be calculated I1i are all identical. Since the data at the input terminals of MUX(i) and XOR(i) I0 is COi-1, these two data must be identical when the aforementioned data are the same, therefore, no comparison is needed here.

[0074] S205: Select one optimized carry chain from the carry chains with the same logic and keep it, delete the remaining optimized carry chains, and reconstruct the output relationship of the kept carry chain to obtain the optimized FPGA chip.

[0075] For example, the output of the retained carry chain can be connected to the input DO of other deleted carry chains to obtain an optimized FPGA chip.

[0076] For example, refer to the two netlists shown in Table 1 below, where xor_i represents the i-th level XOR gate XOR(i), and I0(∙), I1(∙), and O(∙) after xor_i represent the data COi-1 / Cin input at the I0 input terminal, the data Si input at the I1 input terminal, and the data Oi output at the output terminal of the i-th level XOR gate XOR(i), respectively; mux_i represents the i-th level data selector MUX(i), and I0(∙), I1(∙), S(∙), and O(∙) after mux_i represent the data COi-1 / Cin input at the I0 input terminal, the data I1i input at the I1 input terminal, the data Si input at the signal input terminal, and the data COi output at the output terminal of the i-th level data selector MUX(i), respectively. As can be seen from Table 1, the inputs and outputs of the first and second calculation units in the carry chain aft_opt and carry chain bef_opt are the same. Therefore, the carry chain bef_opt can be retained, the first and second calculation units in the carry chain bef_opt can be deleted, and then the outputs COi and Oi of the 0th and 1st levels of the carry chain bef_opt can be connected to the output ports of the 0th and 1st levels of the carry chain aft_opt, respectively.

[0077] Table 1

[0078]

[0079] The method provided by the present invention optimizes the carry chain by deleting and reconstructing the connection topology of the carry chain to be optimized, thereby simplifying the reusable or omitted parts of the logic calculation process, thereby reducing the amount of FPGA chip resources occupied by the carry chain; since the present invention does not use LUT, it can ensure computational efficiency while reducing resource consumption.

[0080] By deleting and optimizing carry chains with identical logic, the resources occupied by the carry chain on the FPGA chip can be further reduced.

[0081] Example 3

[0082] Figures 5a-5c The diagram shown is a schematic representation of the carry chain to be optimized after deleting the data selector and reconstructing the topology connection, according to an embodiment of the present invention.

[0083] Here, we discuss the case where the only element to be optimized in the same computing unit is the data selector.

[0084] As an example, see Figure 5a If the i-th level signal data Si, the i-th level data to be calculated I1i, and the (i-1)-th level carry data COi-1 are all constants, then the output of the i-th level data selector, i.e. the i-th level carry data COi, is also constant. In this case, after deleting the i-th level data selector MUX(i), the pre-calculated i-th level carry data COi can be directly output to the (i+1)-th level data selector MUX(i+1) and the (i+1)-th level XOR gate XOR(i+1).

[0085] Optionally, if the value of COi is the same as one of Si, I1i, or COi-1, such as Si, the signal data output terminal SO can be connected to the I0 input terminal of the (i+1)th stage data selector MUX(i+1) and the (i+1)th stage XOR gate XOR(i+1), and Si can be used as the output of COi.

[0086] As another example, if the carry data Si of the i-th level is constant, according to the above formula (1.1), it can be seen that when Si=1, the COi output by the i-th level signal data selector is I1i; when Si=0, the COi output by the i-th level signal data selector is COi-1. Therefore, see Figure 5b When Si is a constant of 1, after deleting the i-th level data selector MUX(i), the output terminal IO of the data to be calculated can be connected to the input terminal I0 of the (i+1)-th level data selector MUX(i+1) and the (i+1)-th level XOR gate XOR(i+1), and I1i can be used as the output COi. See also Figure 5c When Si is a constant 0, after deleting the i-th level data selector MUX(i), the output of the (i-1)-th level data selector MUX(i-1) can be connected to the I0 input of the (i+1)-th level data selector MUX(i+1) and the (i+1)-th level XOR gate XOR(i+1), and COi-1 can be used as the output of COi.

[0087] As another example, if the data to be calculated at level i, I1i, is equal to the carry data at level (i-1), then according to the above formula (1.1), COi = COi-1 = I1i; therefore, see... Figure 5b It can be connected to the output terminal IO of the data to be calculated and the input terminal I0 of the (i+1)th stage data selector MUX(i+1) and the (i+1)th stage XOR gate XOR(i+1), and output I1i as COi; see [link to documentation]. Figure 5cAlternatively, the output of the (i-1)th level data selector MUX(i-1) can be connected to the I0 input of the (i+1)th level data selector MUX(i+1) and the (i+1)th level XOR gate XOR(i+1), so that COi-1 is output as COi.

[0088] Example 4

[0089] Figures 6a-6b The diagram shown is a schematic representation of the carry chain to be optimized after deleting the XOR gate and reconstructing the topology connection, as provided in an embodiment of the present invention.

[0090] Here, we discuss the case where the only element to be optimized in the same computational unit is an XOR gate.

[0091] As an example, if the signal data Si of level i and the carry data COi-1 of level i-1 are both constants, then the calculation result Oi of level i is also constant. Therefore, after deleting the XOR gate XOR(i) of level i, the pre-calculated calculation result Oi of level i can be directly output to the input terminal.

[0092] Similarly, if the value of Oi is the same as one of Si or COi-1, such as COi-1, the output of the (i-1)th level data selector MUX(i-1) can be connected to the input DO, and COi-1 can be used as the output of Oi.

[0093] As another example, see Figure 6a If only COi-1 is constant between COi-1 and Si, and COi-1=0, according to the above formula (1.2), it can be seen that Oi= Si; therefore, after deleting the i-th level XOR gate XOR(i), the signal data output terminal SO and the input terminal DO can be connected, and the i-th level signal data Si can be output as the i-th level calculation result Oi.

[0094] As yet another example, see Figure 6b If only COi-1 is constant between COi-1 and Si, and COi-1=1, then according to the above formula (1.2), it can be seen that... Therefore, after deleting the i-th level XOR gate XOR(i), the signal data output terminal SO and the input terminal DO can be connected, and the i-th level signal data Si can be inverted and output as the i-th level calculation result Oi.

[0095] Optionally, an inverter can be added between the signal data output terminal SO and the input terminal DO to perform an inversion operation and output the inverted value of Si to the input terminal.

[0096] Example 5

[0097] Figures 7a-7cThe diagram shown is a schematic representation of the carry chain to be optimized after deleting the XOR gate and data selector and reconstructing the topology connection, as provided in an embodiment of the present invention.

[0098] Here, we discuss the case where the elements to be optimized in the same computing unit include both XOR gates and data selectors.

[0099] Referring to Table 2 below, it can be seen that the components to be optimized include XOR gates and data selectors of the same computing unit, which can occur under the following three conditions: (1) Si, I1i, and COi-1 are all constants, (2) I1i = COi-1 is a constant 1, and (3) I1i = COi-1 is a constant 0.

[0100] As an example, see Figure 7a If the i-th level calculation unit satisfies the above condition (1), after deleting the i-th level data selector MUX(i) and the i-th level XOR gate XOR(i), the pre-calculated i-th level carry data COi can be directly output to the i+1 level data selector MUX(i+1) and the i+1 level XOR gate XOR(i+1), and the pre-calculated i-th level calculation result Oi can be output to the input terminal DO.

[0101] As another example, see Figure 7b If the i-th level calculation unit satisfies the above condition (2), after deleting the i-th level data selector MUX(i) and the i-th level XOR gate XOR(i), the output terminal of the (i-1)-th level data selector MUX(i-1) and the I0 input terminal of the (i+1)-th level data selector MUX(i+1) and the I0 input terminal of the (i+1)-th level XOR gate XOR(i+1) can be connected. The signal data output terminal SO and the sum input terminal DO are connected and an inverter is added thereto. The carry data COi-1 of the (i-1)-th level is used as the carry data COi of the i-th level and input to the I0 input terminal of the (i+1)-th level data selector and the (i+1)-th level XOR gate. The i-th level signal data Si is inverted and used as the i-th level calculation result Oi is output.

[0102] Or see Figure 7c If the i-th level calculation unit satisfies the above condition (2), after deleting the i-th level data selector MUX(i) and the i-th level XOR gate XOR(i), the input terminal IO of the data to be calculated can be connected to the I0 input terminal of the (i+1)-th level data selector MUX(i+1) and the I0 input terminal of the (i+1)-th level XOR gate XOR(i+1), the signal data output terminal SO is connected to the input terminal DO and an inverter is added thereto, the i-th level data to be calculated I1i is input as the i-th level carry data COi to the I0 input terminal of the (i+1)-th level data selector MUX(i+1) and the (i+1)-th level XOR gate XOR(i+1), and the i-th level signal data Si is inverted and output as the i-th level calculation result Oi.

[0103] As another example, if the i-th level computational unit satisfies the above condition (3), it can be processed according to the above... Figure 7b The carry chain to be optimized is reconstructed in the following way, and the reconstruction method of each port is the same as... Figure 7b The process is the same, except that the i-th level signal data Si is directly output as the i-th level calculation result Oi, without adding an inverter.

[0104] Alternatively, if the i-th level computational unit satisfies the above condition (3), it can be performed according to the above... Figure 7c The carry chain to be optimized is reconstructed in the following way, and the reconstruction method of each port is the same as... Figure 7c The process is the same, except that the i-th level signal data Si is directly output as the i-th level calculation result Oi, without adding an inverter.

[0105] Table 2: Components to be optimized include data selectors and XOR gates within the same computing unit.

[0106]

[0107] Example 6

[0108] Figure 8 The diagram shown is a scenario illustration of an optimized carry chain provided by an embodiment of the present invention.

[0109] For example, referring to the netlist of the carry chain before and after optimization shown in Table 3 below, it can be seen that the carry chain includes a total of 4 levels of operation units. Similarly, xor_i represents the i-th level XOR gate XOR(i), and I0(∙), I1(∙), and O(∙) after xor_i represent the data COi-1 / Cin input at the I0 input terminal, the data Si input at the I1 input terminal, and the data Oi output at the output terminal of the i-th level XOR gate XOR(i), respectively; mux_i represents the i-th level data selector MUX(i), and I0(∙), I1(∙), S(∙), and O(∙) after mux_i represent the data COi-1 / Cin input at the I0 input terminal, the data I1i input at the I1 input terminal, the data Si input at the signal input terminal, and the data COi output at the output terminal of the i-th level data selector MUX(i), respectively.

[0110] Table 3

[0111]

[0112] Specifically, see Figure 8As shown in Table 3 above, we can start processing mux_0 from the beginning. We can see that the inputs of mux_0 are all constants. According to the logical expression (1.1), the output is a constant 0. This mux_0 can be optimized by removing it and passing the GND signal through it, directly connecting to the I0 pins of xor_1 and mux_1. The inputs of xor_0 are all constants. According to the logical expression (1.2), the output is a constant 1. This xor_0 can be optimized by removing it and passing the VCC signal directly to the input port DO as the O0 output. After processing mux_0 and xor_0, we begin processing mux_1. The I0 pin of mux_1 is reconnected to GND, and I1 is also connected to GND. The signals at both inputs are consistent, so this mux_1 can be optimized by removing it and passing the GND signal through it, directly connecting to the I0 pins of xor_2 and mux_2. The I0 input of xor_1 is reconnected to GND. According to the logical expression, the output is the input signal 'a'. This XOR can be optimized by removing the XOR and directly connecting 'a' to the AND input port DO as output O1. It can be seen that not all inputs of mux_2 are constants. The input signal at the signal input terminal is the variable 'a'. Furthermore, the I0 input of mux_2 is reconnected to GND, and I1 is connected to the input signal 'b'. The two input signals are inconsistent and cannot be removed. The I0 input of xor_2 is reconnected to GND. According to the logical expression, the output is 'a'. This XOR can be optimized by removing the XOR and directly connecting 'a' to the AND input port DO as output O2. Simultaneously, mux_3 is processed from the end. Not all inputs of mux_3 are constants. The input signal at the signal input terminal is the constant VCC. This MUX can be optimized by removing the MUX and passing the signal from input I1 through the MUX, directly connecting 'a' to AND_0. Figure 8 The topmost AND gate's I0 input is XOR_3. According to the logical expression, XOR_3's output is the inverted value of input I1. This XOR can be replaced with an inverter (INV). The INV input is connected to the original I1 signal, and the INV output is connected to the AND input port DO as the O3 output. Since the processing steps for the first three computational units have already been described when processing from scratch, they will not be repeated here. The optimized carry chain netlist is shown in Table 3 above.

[0113] Through the above processing, it can be Figure 8 The carry chain to be optimized is simplified to Figure 8 The optimized carry chain, through the optimized process of this invention, can reduce the occupation of data selectors and XOR gates by nearly 3 / 4, greatly freeing up resources in the FPGA chip.

[0114] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

Claims

1. An optimization method for an FPGA carry chain unit, characterized in that, The method is used on an FPGA chip, the FPGA chip including at least one carry chain to be optimized, the carry chain to be optimized consisting of multiple cascaded computing units, the method including: Traverse each computational unit starting from the head and / or tail of the carry chain to be optimized; Determine whether there is a component in each computing unit that meets preset conditions to obtain the component to be optimized, wherein the preset conditions include at least one of the following: the input is constant, the output is constant, or the inputs are the same; Remove the element to be optimized from the carry chain to be optimized, and reconstruct the connection topology of the carry chain to be optimized to obtain the optimized carry chain. The computing unit includes a data selector and an XOR gate, and the element to be optimized includes a data selector and / or an XOR gate. The I0 input of the i-th stage XOR gate is connected to the output of the (i-1)-th stage data selector, and the output of the (i-1)-th stage data selector inputs the (i-1)-th stage carry data COi-1 to the I0 input of the i-th stage XOR gate; the I1 input of the i-th stage XOR gate is connected to the signal data output, and the signal data output inputs the i-th stage signal data Si to the I1 input of the i-th stage XOR gate; the output of the i-th stage XOR gate is connected to the sum input, and the output of the i-th stage XOR gate outputs the i-th stage calculation result Oi to the sum input; i is a non-negative integer less than or equal to Imax-1, and Imax is the total number of calculation units in the carry chain to be optimized. The I0 input of the i-th level data selector is also connected to the output of the (i-1)-th level data selector. The output of the (i-1)-th level data selector inputs the (i-1)-th level carry data COi-1 to the I0 input of the i-th level data selector. The I1 input of the i-th level data selector is connected to the output of the data to be calculated. The output of the data to be calculated inputs the i-th level data to be calculated I1i to the I1 input of the i-th level data selector. The signal input of the i-th level data selector is connected to the signal data output. The signal data output input inputs the i-th level signal data Si to the signal input of the i-th level data selector. The output of the i-th level data selector is connected to the I0 input of the (i+1)-th level data selector and the (i+1)-th level XOR gate. The i-th level data selector outputs the i-th level carry data COi to the I0 input of the (i+1)-th level data selector and the (i+1)-th level XOR gate. Wherein, if the i-th level data selector is the element to be optimized, the preset conditions specifically include: the i-th level carry data COi is a constant, the i-th level signal data Si is a constant, or the i-th level data to be calculated I1i is equal to the (i-1)-th level carry data COi-1; if the i-th level XOR gate is the element to be optimized, the preset conditions specifically include: the i-th level calculation result Oi is a constant or the (i-1)-th level carry data COi-1 is a constant; If the i-th level data selector is the element to be optimized, and the i-th level carry data COi is a constant, then the connection topology of the carry chain to be optimized is reconstructed, including: directly inputting the pre-calculated i-th level carry data COi into the I0 input terminal of the (i+1)-th level data selector and the (i+1)-th level XOR gate. If the i-th level data selector is the element to be optimized, and the i-th level signal data Si is a constant 1, then the connection topology of the carry chain to be optimized is reconstructed, including: connecting the output terminal of the data to be calculated to the (i+1)-th level data selector and the I0 input terminal of the (i+1)-th level XOR gate, and using the i-th level data to be calculated I1i as the i-th level carry data COi, and inputting it to the (i+1)-th level data selector and the I0 input terminal of the (i+1)-th level XOR gate; If the i-th level data selector is the element to be optimized, and the i-th level signal data Si is a constant 0, then the connection topology of the carry chain to be optimized is reconstructed, including: connecting the output terminal of the (i-1)-th level data selector with the I0 input terminal of the (i+1)-th level data selector and the (i+1)-th level XOR gate, and inputting the (i-1)-th level carry data COi-1 as the i-th level carry data COi to the I0 input terminal of the (i+1)-th level data selector and the (i+1)-th level XOR gate; If the i-th level data selector is the element to be optimized, and the i-th level data to be calculated I1i is equal to the (i-1)-th level carry data COi-1, then the connection topology of the carry chain to be optimized is reconstructed, including: connecting the output terminal of the data to be calculated to the (i+1)-th level data selector and the I0 input terminal of the (i+1)-th level XOR gate, and using the i-th level data to be calculated I1i as the i-th level carry data COi, inputting it to the (i+1)-th level data selector and the I0 input terminal of the (i+1)-th level XOR gate; Alternatively, connect the output of the (i-1)th level data selector to the I0 input of the (i+1)th level data selector and the (i+1)th level XOR gate, and input the (i-1)th level carry data COi-1 as the i-th level carry data COi to the I0 input of the (i+1)th level data selector and the (i+1)th level XOR gate. If the i-th level XOR gate is the element to be optimized, and the i-th level calculation result Oi is a constant, then the connection topology of the carry chain to be optimized is reconstructed, including: directly outputting the pre-calculated i-th level calculation result Oi to the input terminal; If the i-th level XOR gate is the element to be optimized, and the (i-1)-th level carry data COi-1 is a constant 0, then the connection topology of the carry chain to be optimized is reconstructed, including: Connect the signal data output terminal to the sum input terminal, and output the i-th level signal data Si as the i-th level calculation result Oi; If the i-th level XOR gate is the element to be optimized, and the (i-1)-th level carry data COi-1 is a constant 1, then the connection topology of the carry chain to be optimized is reconstructed, including: connecting the signal data output terminal and the sum input terminal, and inverting the i-th level signal data Si and outputting it as the i-th level calculation result Oi.

2. The method according to claim 1, characterized in that, The method further includes: Determine whether there are logically identical carry chains in the FPGA chip, wherein the logically identical carry chains include at least two optimized carry chains with identical inputs and outputs; Select one optimized carry chain from the carry chains with the same logic and keep it, delete the rest of the optimized carry chains, and reconstruct the output relationship of the kept carry chain to obtain the optimized FPGA chip; The output relationship of the reconstructed carry chain includes: Connect the output port of the retained carry chain to the input port connected to the remaining deleted carry chains.

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