Offset self-calibration method and high-speed amplification circuit

Abstract

The invention provides a maladjustment self-calibration method. The maladjustment self-calibration method comprises the following steps: 1) short-circuiting input signal ends VINP and VINN of an amplifying circuit to a common-mode voltage VCOM; 2) detecting an output signal difference value of the signal output ends VOUTP and VOUTN of the amplification circuit through a comparator, wherein the difference value is an offset error and generates high and low level signals; 3) accumulating the high and low level signals in a preset period through a counter to obtain an error value, converting the error value into a digital control signal through a register, and returning the digital control signal to the amplification circuit; and 4) the amplification circuit adjusts the input end to compensate the grid bias voltage of the CMOS circuit according to the digital control signal, and adjusts the offset error value to the reduction direction. The invention further provides a high-speed amplification circuit which uses the offset calibration method.

Description

TECHNICAL FIELD

[0001] The present application relates to integrated circuits, and more particularly to high-speed amplification circuits. BACKGROUND

[0002] With the increasing speed of analog signal transmission, the demand for high-speed and high-precision ADCs for converting high-speed analog signals into digital signals with high precision is increasingly urgent. Generally, high-speed and high-precision analog-digital conversion circuits are implemented in a pipeline structure (sampling rate > 500 Msps, conversion precision > 12 Bit), and the first stage of the pipeline structure requires high-speed and high-precision signal processing, in which the core circuit is a residual amplifier. When the residual amplifier has a misadjustment error higher than 1 LSB, an error code is generated, resulting in a decrease in overall conversion precision. It is necessary to eliminate the misadjustment error through a calibration circuit to improve the conversion precision of the ADC. Traditional calibration methods include adjusting the current of an internal current source or controlling the charge of the circuit, etc. However, the calibration circuit is relatively large and generally includes an ADC, a DAC, etc., resulting in waste of area and power consumption. SUMMARY

[0003] The main technical problem to be solved by the present application is to provide a misadjustment self-calibration method that relies on a hardware mode to realize misadjustment calibration and reduce circuit area and save power consumption.

[0004] To solve the above technical problems, the present application provides a misadjustment self-calibration method, including the following steps:

[0005] 1) short-circuiting the input signal ends VINP and VINN of an amplification circuit to a common-mode voltage VCOM;

[0006] 2) detecting the output signal difference of the signal output ends VOUTP and VOUTN of the amplification circuit through a comparator, the difference being a misadjustment error and generating a high-low level signal;

[0007] 3) accumulating the high-low level signal through a counter in a preset period to obtain an error value, and converting the error value into a digital control signal through a register and returning the digital control signal to the amplification circuit;

[0008] 4) adjusting the input end compensation CMOS gate bias voltage of the amplification circuit according to the digital control signal to adjust the misadjustment error value in a decreasing direction.

[0009] In a preferred embodiment: the digital control signal is divided into a coarse adjustment signal and a fine adjustment signal; wherein the coarse adjustment signal is foreground calibration, and the fine adjustment signal is background calibration.

[0010] In a preferred embodiment, the compensation of the gate bias voltage of the CMOS circuit in step 4 specifically refers to adding a mirror MOS transistor to each MOS transistor at the input end of the circuit, and adjusting the gate current of each MOS transistor at the input end of the circuit by adjusting the size of the gate voltage of the mirror MOS transistor.

[0011] In a preferred embodiment, the source of the mirror MOS transistor and the corresponding MOS transistor at the input end of the circuit are connected to each other, and the drain is connected to each other.

[0012] The mirror MOS transistor is divided into two groups, one group of gate is connected to the first DAC through the first branch, and the other group of gate is connected to the second DAC through the second branch.

[0013] In a preferred embodiment, when the comparator outputs high level, the coarse adjustment signal controls the switch on the first branch to be closed and the switch on the second branch to be opened, and the gate voltage of the first group of mirror MOS transistors is adjusted by the first DAC; when the comparator outputs high level, the coarse adjustment signal controls the switch on the second branch to be closed and the switch on the first branch to be opened, and the gate voltage of the second group of mirror MOS transistors is adjusted by the second DAC.

[0014] In a preferred embodiment, when the comparator outputs high level, the fine adjustment control signal controls the switch on the first branch or the second branch to be closed, and the calibration bit of the fine adjustment signal is +1; when the comparator outputs low level, the fine adjustment control signal controls the switch on the first branch or the second branch to be closed, and the calibration bit of the fine adjustment signal is -1.

[0015] In a preferred embodiment, the error value obtained by the counter accumulating the high and low level signals in a preset period in step 3 specifically refers to that if the number of high level signals accumulated by the counter in the preset period is greater than the number of low level signals, it indicates that the unadjusted voltage is monotonously rising, otherwise it indicates that the unadjusted voltage is monotonously falling; if the number of high level signals accumulated by the counter in the preset period is equal to the number of low level signals, it indicates that the voltage is not unadjusted.

[0016] The application also provides a high-speed amplification circuit using the unadjusted calibration method as described above.

[0017] In a preferred embodiment, it includes an amplification circuit, a comparator, a counter and a register.

[0018] The input end of the amplification circuit is connected to the input signal VINP and VINN, and the input signal VINP and VINN are connected to the common mode voltage VCOM through the calibration always-on switch; when the calibration clock CAL_CLK is high, the input signal end VINP, VINN is shorted to the common mode voltage VCOM.

[0019] The input end and the output end of the amplifier circuit are connected via a clock reset switch, and the clock reset switch is closed when the clock reset signal is at a high level;

[0020] The comparator is connected to two output terminals of the amplifier circuit, the output terminal of the comparator is connected to a counter, the output terminal of the counter is connected to a register, and the register outputs a digital control signal to the amplifier circuit.

[0021] In a preferred embodiment, when the calibration clock CAL_CLK is at a high level, the clock reset signal is also at a high level.

[0022] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0023] The present invention provides an offset self-calibration method, which adopts a calibration mode of a digitally controlled input terminal compensation circuit bias voltage, has a large calibration range, high calibration accuracy, and a small area, and does not hinder the normal operation of an amplifier circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 is a block diagram of a high-speed amplifier circuit in a preferred embodiment of the present invention;

[0025] Figure 2 A timing diagram of a clock in a preferred embodiment of the present invention;

[0026] Figure 3 A circuit diagram of a preferred embodiment of the present invention when the clock reset signal is at a high level;

[0027] Figure 4 This is a diagram showing the internal structure of the amplifier circuit in a preferred embodiment of the present invention;

[0028] Figure 5 This is the voltage change diagram of VOUTP and VOUTN during front-end calibration;

[0029] Figure 6 a and b are schematic diagrams of the output of the counter before calibration, and c is a schematic diagram of the output of the counter after calibration. DETAILED DESCRIPTION

[0030] In order to make the technical solutions and features of the present invention clearer, the present invention is further described in detail below with reference to the accompanying drawings and specific examples. It should be understood that these examples are only used to illustrate the present invention and are not used to limit the scope of the present invention. After reading the present invention, modifications of various equivalent forms of the present invention by those skilled in the art all fall within the scope defined by the claims attached to this application.

[0031] refer to Figure 1 ,This embodiment provides a high-speed amplifier circuit, including: an amplifier circuit, a comparator, a counter and a register;

[0032] The input end of the amplification circuit is connected to input signals VINP and VINN, which are connected to a common-mode voltage VCOM through a calibration always-on switch. When a calibration clock CAL CLK is high, the input signal ends VINP and VINN are shorted to the common-mode voltage VCOM.

[0033] The input end and the output end of the amplification circuit are connected through a clock reset switch, which is closed when a clock reset signal RESET CLK is high.

[0034] The comparator is connected to the two output ends of the amplification circuit, the output end of the comparator is connected to the counter, and the output end of the counter is connected to the register. The register outputs a digital control signal to the amplification circuit.

[0035] In this embodiment, when RESET CLK is high initially, CAL CLK is also high, as shown in FIG. 2. At this time, the input end is short-circuited, ensuring that the voltages at the two input ends VINP and VINN are equal to VCOM, i.e., the common-mode voltage. The output end is connected to the relevant input end, and calibration begins at this time. The entire circuit is as shown in FIG. 3. Figure 2 Figure 3

[0036] Specifically, the calibration includes the following steps:

[0037] 1) Short-circuit the input signal ends VINP and VINN of the amplification circuit to the common-mode voltage VCOM;

[0038] 2) Detect the output signal difference of the signal output ends VOUTP and VOUTN of the amplification circuit through the comparator, which is the offset error and generates a high-low signal;

[0039] 3) Accumulate the high-low signal in a preset period through the counter to obtain an error value, and convert the error value into a digital control signal through the register and return it to the amplification circuit;

[0040] 4) The amplification circuit adjusts the input end compensation CMOS gate bias voltage according to the digital control signal, and adjusts the offset error value in the decreasing direction.

[0041] In this embodiment, in order to increase the accuracy of calibration, the digital control signal is divided into coarse adjustment signal and fine adjustment signal; wherein the coarse adjustment signal is foreground calibration, and the fine adjustment signal is background calibration. The calibration range of coarse calibration is wide, for example, the calibration range is plus or minus 50 mV, and the accuracy is 5 mV; fine calibration is calibrated within 5 mV, and the calibration accuracy can reach 500 uV.

[0042] ​​The compensation of the gate bias voltage of the CMOS circuit in step 4 refers to that a mirror MOS is added to each MOS at the input end of the circuit, and the gate current of the MOS at the input end of the circuit is adjusted by adjusting the size of the gate voltage of the mirror MOS. In the embodiment, there are four MOSs at the input end of the circuit, which are M1, M2, M3 and M4. Therefore, there are also four mirror MOSs, which are M11, M22, M33 and M44. The source of the mirror MOS is connected to the source of the corresponding MOS at the input end of the circuit, and the drain of the mirror MOS is connected to the drain of the corresponding MOS at the input end of the circuit.

[0043] The mirror MOSs are divided into two groups, specifically, M11 and M33 are in one group, and M22 and M44 are in another group. The gate of M11 and M33 is connected to the first DAC through the first branch, and the gate of M22 and M44 is connected to the second DAC through the second branch.

[0044] When the comparator outputs a high level during coarse adjustment, the highest bit OFFSET_A<5> in the coarse adjustment signal OFFSET_A<5:0> controls the closing of the switch on the first branch and the opening of the switch on the second branch, so as to adjust the gate voltage of the first group of mirror MOSs through the first DAC. When the comparator outputs a high level, the highest bit OFFSET_A<5> in the coarse adjustment signal OFFSET_A<5:0> controls the closing of the switch on the second branch and the opening of the switch on the first branch, so as to adjust the gate voltage of the second group of mirror MOSs through the second DAC. Finally, VOUTP is adjusted to VOUTN (with a maximum error of 5mV). Front-end calibration is completed. At this time, the digital code of OFFSET_A<4:0> jumps between +1 and -1. During calibration, the voltage changes of VOUTP and VOUTN are as shown in the following table. Figure 5

[0045] After coarse adjustment, fine adjustment is entered, OFFSET_A<5> is 0, and the coarse adjustment switch is closed. When the comparator outputs a high level, the fine adjustment control signal OFFSET_FINE<4:0> controls the closing of the switch on the first branch or the second branch, and the calibration bit of the fine adjustment signal is +1. When the comparator outputs a low level, the fine adjustment control signal OFFSET_FINE<4:0> controls the closing of the switch on the first branch or the second branch, and the calibration bit of the fine adjustment signal is -1. Since fine calibration is performed in two directions, the switch of the control branch does not need to be changed. The FINE signal always controls one branch and adds or subtracts 1 in two directions.

[0046] In step 3, the error value is obtained by counting the high and low level signals in a preset period through the counter. If the number of high levels counted by the counter in the preset period is greater than the number of low levels, it indicates that the unadjusted voltage monotonously rises, and vice versa. For example, Figure 6 ​If the number of high level equals to the number of low level, it means that the voltage is not unadjusted. It can be seen that the ratio of high level to low level of the counter output is 1:1 after calibration.

[0047] The above is only one embodiment of the present application, but the design concept of the present application is not limited to this, any non-essential changes to the present application using this concept, all belong to the infringement of the scope of the present application.

Claims

1. A method of misadjustment self-correction, characterized by The method comprises the following steps: 1) short-circuiting input signal ends VINP and VINN of an amplification circuit to a common-mode voltage VCOM; 2) detecting an output signal difference of signal output ends VOUTP and VOUTN of the amplification circuit by a comparator, the difference being a misadjustment error and generating a high-low level signal; 3) accumulating the high-low level signal in a preset period by a counter to obtain an error value, and converting the error value into a digital control signal by a register and returning the digital control signal to the amplification circuit; 4) adjusting a gate bias voltage of a compensation CMOS circuit at the input end of the amplification circuit according to the digital control signal to adjust the misadjustment error value in a decreasing direction.

2. A method of self-calibration for misalignment according to claim 1, characterized in that: The digital control signal is divided into a coarse adjustment signal and a fine adjustment signal; the coarse adjustment signal is foreground calibration, and the fine adjustment signal is background calibration.

3. A method of self-calibration for misalignment according to claim 1, characterized in that: The gate bias voltage of the compensation CMOS circuit in step 4 specifically refers to adding a mirror MOS tube to the MOS tube at the circuit signal input end respectively, and adjusting the gate current of the MOS tube at the circuit signal input end by adjusting the size of the gate voltage of the mirror MOS tube.

4. A method of self-calibration for misalignment according to claim 3, characterized in that: The source and drain of the mirror MOS tube and the corresponding MOS tube at the circuit signal input end are connected to each other; The mirror MOS tubes are divided into two groups, and the gate of one group is connected to a first DAC through a first branch, and the gate of the other group is connected to a second DAC through a second branch.

5. A method of self-calibration for misalignment according to claim 4, characterized in that: When the comparator outputs a high level, the coarse adjustment signal controls the switch on the first branch to be closed and the switch on the second branch to be opened, and adjusts the gate voltage of the first group of mirror MOS tubes through the first DAC; when the comparator outputs a high level, the coarse adjustment signal controls the switch on the second branch to be closed and the switch on the first branch to be opened, and adjusts the gate voltage of the second group of mirror MOS tubes through the second DAC.

6. A method of self-calibration for misalignment according to claim 4, characterized in that: When the comparator outputs a high level, the fine adjustment control signal controls the switches on the first branch or the second branch to be closed respectively, and the calibration bit of the fine adjustment signal is +1; when the comparator outputs a low level, the fine adjustment control signal controls the switches on the first branch or the second branch to be closed respectively, and the calibration bit of the fine adjustment signal is -1.

7. A method of self-calibration for misalignment as claimed in claim 4, wherein: In step 3, accumulating the high-low level signal in a preset period by a counter to obtain an error value specifically refers to that if the number of high levels accumulated by the counter in the preset period is greater than the number of low levels, it indicates that the misadjustment voltage monotonously rises, otherwise it indicates that the misadjustment voltage monotonously falls; if the number of high levels accumulated by the counter in the preset period is equal to the number of low levels, it indicates that the voltage is not misadjusted.

8. A high speed amplification circuit, characterized by The misadjustment calibration method of any one of claims 1-8 is used.

9. A high speed amplification circuit as claimed in claim 8, characterized in that It comprises: an amplification circuit, a comparator, a counter and a register; the input end of the amplification circuit is connected to input signals VINP and VINN, and the input signals VINP and VINN are connected to a common-mode voltage VCOM through a calibration always-on switch; when a calibration clock CAL_CLK is at a high level, the input signal ends VINP and VINN are short-circuited to the common-mode voltage VCOM; the input end and the output end of the amplification circuit are connected through a clock reset switch, and the clock reset switch is closed when a clock reset signal is at a high level; The comparator is connected to two output terminals of the amplification circuit, an output terminal of the comparator is connected to a counter, an output terminal of the counter is connected to a register, and the register outputs a digital control signal to the amplification circuit.

10. A high speed amplification circuit as claimed in claim 8, characterized in that: When the calibration clock CAL_CLK is high, the clock reset signal is also high.

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