Power transistor and manufacturing method thereof

Abstract

The invention relates to a power transistor and a manufacturing method thereof. The invention provides a method for manufacturing a power transistor, which comprises the following steps of: providing a semiconductor substrate which comprises a first epitaxial layer and a second epitaxial layer, and the second epitaxial layer is arranged on the first epitaxial layer in advance so as to be used as an electronic component layer of the power transistor; and performing a carrier injection procedure on the second epitaxial layer to enable the selected carrier to penetrate through the second epitaxial layer so as to form at least one doped subsection in the first epitaxial layer.

Description

Technical Field

[0001] This disclosure relates to a power transistor and a method for manufacturing the same, and more particularly to a method for manufacturing a power transistor that reduces process complexity, reduces process steps and costs, and increases productivity, as well as the power transistor manufactured using this method. Background Technology

[0002] In the traditional process of manufacturing SiC MOSFETs, it is necessary to etch a silicon carbide semiconductor substrate to form multiple trenches and a protection substrate. Then, carrier implantation is performed on the silicon carbide semiconductor substrate with high energy to dope the silicon carbide semiconductor substrate. This allows the active region, source, body diode, and floating edge guard ring of the power transistor to be defined.

[0003] However, due to the extremely high density of silicon carbide (SiC), it is virtually impossible to introduce dopants via thermal diffusion. Dopants can only be implanted through forced implantation using a carrier implanter. Carrier implantation of SiC semiconductor substrates requires very high energy and is time-consuming. Furthermore, the need to create specific masks of particular materials in selected areas to shield against high-energy carrier implantation further complicates the process. Therefore, traditional processes for manufacturing SiC MosFets are not only complex and costly, but also time-consuming and labor-intensive, resulting in reduced productivity.

[0004] Besides, the most advanced SiC MOSFET technology currently on the power semiconductor market is Infineon's CoolSiC technology, a patented hybrid superjunction technology. This technology uses extremely small cell pitches on the order of 1-3 micrometers (µm) and is Infineon's second-generation SiC microtrench technology, currently holding approximately 10-20% of the SiC MOSFET market. The advantages offered by microtrench CoolSiC are significant. Due to the influence of the special crystal plane on current conduction in the vertical channel structure (inverted channel), the clean, defect-free channel crystal structure allows for high electron mobility, resulting in the lowest possible channel resistance and a reduction in the overall device on-resistance Rdson as the current density per unit area increases.

[0005] However, trench silicon carbide power transistors require higher breakdown voltage and lower leakage current. Therefore, a novel superjunction structure for semiconductors is desired to further improve breakdown voltage and reduce leakage current. Summary of the Invention

[0006] In view of this, a novel superjunction technique is proposed to improve the situation. A very deep, lightly doped P-type pillar region is created beneath the P-body region. This lightly doped P-type pillar region neutralizes the N-type doping concentration in the adjacent drift region, temporarily reducing the N-type doping concentration in the drift region when the device is turned off. This reduced N-type concentration allows the drift region to withstand a higher breakdown voltage than conventional structures during device turn-off, and returns to normal concentration when the device is turned on, resulting in a lower Rdson. Compared to conventional structures, the device does not require intentionally reducing the N-type doping concentration in the drift region during manufacturing to increase the breakdown voltage, ultimately leading to an improved Rdson.

[0007] In view of this, this disclosure proposes a method for manufacturing power transistors, which involves pre-fabricating at least one carrier layer on a silicon carbide semiconductor substrate to define the active region, source, body diode, and floating edge guard ring of the power transistor. The fabrication method involves growing crystals on a conventional silicon carbide semiconductor substrate using chemical vapor deposition (CVD). Dopant is mixed with air in a confined space, and the required doping concentration is achieved by controlling the flow rate of the material. This fabrication method can be outsourced to semiconductor material suppliers, costing only slightly more than conventional materials, and is more economical than subsequent complex, time-consuming, and costly processes. Furthermore, the reduced process complexity and time savings contribute to increased production efficiency.

[0008] In one embodiment, a typical silicon carbide semiconductor substrate may include an N-type heavily doped semiconductor layer, an N-type epitaxial layer, and a buffer layer between them. The improved silicon carbide semiconductor substrate disclosed herein, in addition to including a typical silicon carbide semiconductor substrate, adds a P-type epitaxial layer on the N-type epitaxial layer using the doping method described above, and an N-type heavily doped epitaxial layer on the P-type epitaxial layer. The P-type epitaxial layer serves as a precursor structure for the active region of the power transistor, forming the active channel of the active region in a subsequent etching process; the N-type heavily doped epitaxial layer serves as a precursor structure for the source of the power transistor, forming the source in a subsequent etching process. Neither of these requires high-energy carrier implantation into the typical silicon carbide semiconductor substrate, reducing process complexity and time while increasing throughput. The source, active channel, and N-type epitaxial layer can form a vertical active region.

[0009] In one embodiment, only one carrier implantation process is required to implant P-type carriers into a modified silicon carbide semiconductor substrate at high energy to form a plurality of highly doped P-type epitaxial portions. A portion of these highly doped P-type epitaxial portions can serve as the body substrate of a silicon carbide MOSFET, forming a body diode with the N-type epitaxial layer, and can be electrically connected to the source contact pad via a dielectric that can smooth or eliminate the potential barrier between the semiconductor and the metal. Another portion can serve as a P-type floating ring for a source protection zone, forming a protection diode with the N-type epitaxial layer to provide reverse protection when the power transistor encounters a reverse backflow current.

[0010] In one embodiment, a trench-type power transistor can combine a P-type epitaxial layer and an N-type epitaxial layer, which serve as the precursor structure of the active region of the power transistor, to form a first breakdown diode. When the power transistor is off, although the gate has not yet been activated, its drain is supplied with a relatively high voltage, reaching several kilovolts. The depletion region formed by this first breakdown diode under reverse bias can withstand high voltage and reduce leakage current. However, to achieve a higher breakdown voltage and lower leakage current, the embodiments disclosed herein propose forming at least one P-type lightly doped pillar in the N-type epitaxial layer in the semiconductor substrate, which, together with the N-type epitaxial layer, forms a second breakdown diode. This further enhances the provision of a higher breakdown voltage and lower leakage current when the power transistor is off, and provides a lower on-resistance Rdson when the power transistor is operating. The size of the at least one P-type lightly doped pillar is larger than the size of the P-type epitaxial layer, which serves as the precursor structure of the active region of the power transistor, and the size of the depletion region formed by the second breakdown diode under reverse bias is larger than the size of the depletion region formed by the second breakdown diode under reverse bias.

[0011] In one embodiment, the at least one P-type low-doped pillar can be implanted into a semiconductor substrate pre-configured with an N-type high-doped epitaxial layer and a P-type epitaxial layer in the initial step of a process using a high-energy carrier implantation. This high-energy carrier implantation allows selected carriers to penetrate the N-type high-doped epitaxial layer and the P-type epitaxial layer to form a P-type low-doped pillar beneath them. Before performing the high-energy carrier implantation, a hard mask can be configured on the N-type high-doped epitaxial layer to shield or block the passage of high-energy carriers, thereby defining which regions need to be implanted with the P-type low-doped pillar.

[0012] In one embodiment, the regions of the trench power transistor can be disposed below the gate or below the substrate. The P-type lightly doped pillar can be disposed only below the substrate between the two gates, only below the gate, or simultaneously below the substrate and the gate. The width of the P-type lightly doped pillar disposed below the gate can be greater than the width of the P-type lightly doped pillar disposed below the substrate. If the P-type lightly doped pillar is disposed only below the substrate between the two gates, the depletion region of the second breakdown diode is smaller; if the P-type lightly doped pillar is disposed only below the two gates, the depletion region of the second breakdown diode is larger; if the P-type lightly doped pillar is disposed simultaneously below the substrate and below the gate, the number of depletion regions of the second breakdown diode between the substrate and the gate increases and becomes denser, resulting in better breakdown resistance and leakage current prevention.

[0013] In one embodiment, this disclosure provides a method for forming a power transistor with a superjunction structure on a silicon carbide (SiC) substrate, comprising the following steps: providing a silicon carbide semiconductor substrate, wherein the silicon carbide semiconductor substrate includes a first type highly doped silicon carbide layer, a first type silicon carbide epitaxial layer, a second type silicon carbide epitaxial layer, and the second type silicon carbide epitaxial layer is pre-disposed on the first type silicon carbide epitaxial layer to serve as an active channel of a power transistor. The first type of highly doped silicon carbide epitaxial layer is pre-disposed on the second type of silicon carbide epitaxial layer to serve as a first electrode of the power transistor; an insulating layer is formed on the first type of highly doped silicon carbide epitaxial layer; a metal mask layer is grown on the insulating layer, wherein the metal mask layer includes a carrier implantation blocking region and a carrier implantation penetration region; a first high-energy carrier is implanted into a working region of the first type of silicon carbide epitaxial layer through the carrier implantation penetration region to form at least one second type of low-doped portion; the metal mask layer and the insulating layer are removed; the first type of highly doped silicon carbide epitaxial layer, the second type of silicon carbide epitaxial layer, and the first type of silicon carbide epitaxial layer are etched to form a protective substrate and an active cell region substrate having at least one trench, wherein the active cell region... The substrate is located within the working region, and the at least one trench corresponds to the at least one second-type low-doped portion; a gate insulating layer is deposited on the protection zone substrate and the active cell region substrate; a polysilicon is deposited on each trench of the at least one trench to form at least one gate; a first isolation layer is deposited on the protection zone substrate and the active cell region substrate; and the first isolation layer, the gate insulating layer, the first-type high-doped silicon carbide epitaxial layer, and the second-type silicon carbide epitaxial layer are etched between the at least one trench and between the active cell region substrate and the protection zone substrate, and the first isolation layer and the gate insulating layer are etched at multiple intervals on the protection zone substrate.

[0014] In one embodiment, this disclosure provides a power transistor comprising a semiconductor substrate having an active cell and a breakdown-resistant epitaxial portion. The active cell includes at least one gate and two vertical active regions on either side thereof. The breakdown-resistant epitaxial portion is disposed below the at least one gate.

[0015] In one embodiment, this disclosure provides a method for manufacturing a power transistor, comprising the following steps: providing a semiconductor substrate, wherein the semiconductor substrate includes a first epitaxial layer and a second epitaxial layer, and the second epitaxial layer is pre-disposed on the first epitaxial layer to serve as an electronic component layer of the power transistor; and performing a carrier implantation process on the second epitaxial layer to allow selected carriers to penetrate the second epitaxial layer and form at least one doped portion within the first epitaxial layer.

[0016] In one embodiment, this disclosure provides a method for forming a power transistor with a superjunction structure on a silicon carbide (SiC) substrate, the SiC substrate having a substrate, the method comprising the following steps: providing a semiconductor substrate, wherein the semiconductor substrate includes a first type highly doped semiconductor layer, a first type epitaxial layer, a second type epitaxial layer, and the second type epitaxial layer is pre-disposed on the first epitaxial layer to serve as an active channel of the power transistor. The first type of highly doped epitaxial layer is pre-configured on the second type of epitaxial layer to serve as a first electrode of the power transistor; an insulating layer is formed on the first type of highly doped epitaxial layer; a metal masking layer is formed on the insulating layer, wherein the metal masking layer includes a carrier implantation blocking region and a carrier implantation penetration region; a first high-energy carrier is implanted into a working region of the first type of epitaxial layer through the carrier implantation penetration region to form at least one second type of low-doped portion, wherein the at least one second type of low-doped portion is below the substrate; the metal masking layer and the insulating layer are removed; and the first type of highly doped epitaxial layer, the second type of epitaxial layer, and the first type of epitaxial layer are etched to form a protective environment substrate and an active cell region substrate having at least one trench.

[0017] In one embodiment, this disclosure provides a power transistor comprising a semiconductor substrate having an active cell, a substrate, and a breakdown-resistant epitaxial portion. The active cell includes two gates, each gate having a vertical active region on each side, and each vertical active region including an upper first-type doped region and a middle second-type doped region. The substrate is disposed adjacent to the middle second-type doped region of each gate. The breakdown-resistant epitaxial portion is disposed below the substrate.

[0018] In one embodiment, this disclosure provides a method for manufacturing a power transistor, the power transistor comprising a substrate, the method comprising the following steps: providing a silicon carbide semiconductor substrate, wherein the silicon carbide semiconductor substrate comprises a first type highly doped silicon carbide layer, a first type silicon carbide epitaxial layer, a second type silicon carbide epitaxial layer, and the second type silicon carbide epitaxial layer is pre-disposed on the first type silicon carbide epitaxial layer for use as an active channel of a power transistor. The first type of highly doped silicon carbide epitaxial layer is pre-disposed on the second type of silicon carbide epitaxial layer to serve as a first electrode of the power transistor; an insulating layer is formed on the first type of highly doped silicon carbide epitaxial layer; a metal mask layer is grown on the insulating layer, wherein the metal mask layer includes a carrier implantation blocking region and a carrier implantation penetration region; a first high-energy carrier is implanted into a working region of the first type of silicon carbide epitaxial layer through the carrier implantation penetration region to form at least one second type of low-doped portion, wherein the at least one second type of low-doped portion is below the substrate.

[0019] In one embodiment, this disclosure provides a method for manufacturing a power transistor, comprising the following steps: providing a semiconductor substrate, wherein the semiconductor substrate includes a first epitaxial layer and a second epitaxial layer, and the second epitaxial layer is pre-disposed on the first epitaxial layer as an electronic component layer of the power transistor; defining the location of a substrate of the electronic component layer; and performing a carrier implantation process on the second epitaxial layer to allow selected carriers to penetrate the second epitaxial layer and form at least one doped portion within the first epitaxial layer, wherein the at least one doped portion is below the substrate.

[0020] The figures and text in the implementation methods can be further explained to understand the technical solutions disclosed herein. Attached Figure Description

[0021] Figures 1 to 18 This is a schematic diagram of a method for manufacturing a power transistor according to a preferred embodiment of the present invention.

[0022] Figure 19 This is a schematic diagram of a power transistor according to a preferred embodiment of the present invention.

[0023] Figure 20 This is a disclosure Figure 19 Simplified diagram.

[0024] Figure 21 This is a schematic diagram of a method for manufacturing a power transistor according to another preferred embodiment of the present invention.

[0025] Figure 22 This is a schematic diagram of a method for manufacturing a power transistor according to another preferred embodiment of the present invention.

[0026] Figure 23 This is a schematic diagram of a power transistor according to another preferred embodiment of the present invention.

[0027] Figure 24 This is a disclosure Figure 23 Simplified diagram.

[0028] Figure 25 This is a schematic diagram of a method for manufacturing a power transistor according to another preferred embodiment of the present invention.

[0029] Figure 26 This is a schematic diagram of a method for manufacturing a power transistor according to another preferred embodiment of the present invention. Detailed Implementation

[0030] Please refer to the accompanying drawings of this disclosure for detailed description, which are illustrated by way of example to show various different embodiments of this disclosure and to provide an understanding of how to implement this disclosure. The embodiments disclosed herein provide sufficient content for those skilled in the art to implement the embodiments disclosed herein, or to implement embodiments derived from the content disclosed herein. It should be noted that these embodiments are not mutually exclusive, and some embodiments can be appropriately combined with one or more other embodiments to form new embodiments; that is, the implementation of this disclosure is not limited to the embodiments disclosed below. Furthermore, for the sake of brevity and clarity, excessive details are not disclosed in the embodiments; even when specific details are disclosed, they are only illustrative to make the reader clear, and the relevant specific details in the embodiments are not intended to limit the disclosure of this case.

[0031] Please see Figures 1 to 18 This is a preferred embodiment of the present disclosure of a method for manufacturing a power transistor 10 (such as...). Figure 19 The schematic diagram of method S10 (shown) includes the following steps: Step S101, as shown Figure 1 As shown, a silicon carbide semiconductor substrate 101 is provided, wherein the silicon carbide semiconductor substrate 101 includes a first type highly doped silicon carbide layer 1011, a first type silicon carbide epitaxial layer 1012, a second type silicon carbide epitaxial layer 1013, and a first type highly doped silicon carbide epitaxial layer 1014. The second type silicon carbide epitaxial layer 1013 is pre-disposed on the first type silicon carbide epitaxial layer 1012 to serve as an active channel (ACH) of a power transistor 10, and the first type highly doped silicon carbide epitaxial layer 1014 is pre-disposed on the second type silicon carbide epitaxial layer 1013 to serve as a first electrode E1 of the power transistor. Figure 19 As shown. Step S102, as... Figure 2As shown, an insulating layer OXI, a metal seed layer MS, and a photoresist layer PR are formed on the first type of highly doped silicon carbide epitaxial layer 1014, wherein the thickness of the photoresist layer PR is greater than the thickness of the metal seed layer MS. Step S103, as follows Figure 3 As shown, the photoresist layer PR is etched to form a carrier injection blocking region PB in the etched area and a carrier injection penetrating region PT in the unetched area. Step S104, as... Figure 4 As shown, metal is grown on the metal seed layer MS in the carrier injection blocking region PB. Step S105, as follows: Figure 5 As shown, the photoresist layer PR is removed to form a metal mask layer HM, wherein the metal mask layer HM includes a carrier injection blocking region PB and a carrier injection penetrating region PT. Step S106, as... Figure 6 As shown, a first high-energy carrier HEI is injected into a working region WA of the first type silicon carbide epitaxial layer 1012 through the carrier injection penetration region PT to form at least one second type low-doped portion PP. The at least one second type low-doped portion PP may include two wider second type low-doped portions PP1 and PP2 and one narrower second type low-doped portion PP3. The wider second type low-doped portions PP1 and PP2 may be disposed below the gate of the trench power transistor, and the narrower second type low-doped portion PP3 may be disposed below the substrate of the trench power transistor. This will be described in detail later. Those skilled in the art will understand that there can be one or more of these structures, and various possible combinations can be made, such as configuring only one or two of the wider type-2 low-doped portions PP1 and PP2, configuring only one of the narrower type-2 low-doped portions PP3 without configuring the wider type-2 low-doped portions PP1 and PP2, configuring only one of the wider type-2 low-doped portions PP1 / PP2 and one of the narrower type-2 low-doped portions, or configuring all two of the wider type-2 low-doped portions PP1 and PP2 and one of the narrower type-2 low-doped portions, etc. Step S107: Remove the metal mask layer HM and the insulating layer OXI to complete half of the finished product HP1. However, in order to increase the size and / or number of depletion regions to strengthen the breakdown resistance structure, increase the breakdown voltage, and reduce leakage current, it is preferable to implement this by configuring all two of the wider type-2 low-doped portions PP1 and PP2 and one of the narrower type-2 low-doped portions.

[0032] Following on from above, step S108, as follows: Figure 8As shown, the first type highly doped silicon carbide epitaxial layer 1014, the second type silicon carbide epitaxial layer 1013, and the first type silicon carbide epitaxial layer 1012 are etched to form a protective environment substrate PA and an active cell region substrate ACR having at least one trench TCH, wherein the active cell region substrate ACR is within the working region WA, and the at least one trench TCH corresponds to the at least one second type low-doped portion PP. Step S109, as... Figure 9 As shown, a gate insulating layer GO is deposited on the protected area substrate PA and the active cell region substrate ACR. Step S110, as follows: Figure 10 As shown, a polysilicon PLY is deposited on each trench of the at least one trench TCH to form at least one gate GA. Step S111, as follows: Figure 11 As shown, a first isolation layer ISO1 is deposited on the protected area substrate PA and the active unit region substrate ACR. Step S112 includes steps S112-1 and S112-2, as follows. Figure 12 As shown, the first isolation layer ISO1, the gate insulating layer GO, the first type highly doped silicon carbide epitaxial layer 1014, and the second type silicon carbide epitaxial layer 1013 are etched between the at least one trench TCH and between the active cell region substrate ACR and the protective environment substrate PA, and the first isolation layer ISO1 and the gate insulating layer GO are etched in the plurality of spaced portions SPC of the protective environment substrate PA.

[0033] In any embodiment disclosed herein, method S10 further includes the following steps: Step S112-2, as follows Figure 12 As shown, a first-type silicon carbide epitaxial layer 1012 is implanted with a second-type highly doped carrier P+ between at least one trench GA, between the active cell region substrate ACR and the protective environment substrate PA, and in the plurality of spaced portions SPC of the protective environment substrate PA, wherein: the second-type highly doped carrier P+ forms a first and second-type highly doped semiconductor well P+W1 in the first-type silicon carbide epitaxial layer 1012 between at least one trench GA; the second-type highly doped carrier P+ in the active cell region substrate ACR and the protective environment substrate SPC... A second type II highly doped semiconductor well P+W2 is formed in the first type silicon carbide epitaxial layer 1012 between the bottom PA; a third type II highly doped semiconductor well P+W3 is formed in the first type silicon carbide epitaxial layer 1012 of the complex spaced portion SPC by the second type highly doped carrier P+; and a complex PN junction (not shown) is formed between the second type II highly doped semiconductor well P+W2 and the first type silicon carbide epitaxial layer 1012, wherein the complex PN junction is configured to buffer a high operating voltage in reverse bias. Figures 1-20In the process, the silicon carbide semiconductor substrate 101 further includes a buffer layer 1015 that connects the first type highly doped silicon carbide layer 1011 and the first type silicon carbide epitaxial layer 1012.

[0034] In any embodiment disclosed herein, method S10 further includes the following steps: Step S113-1, as follows Figure 13 As shown, a second insulating layer ISO2 is deposited on the first insulating layer ISO1 and the plurality of spaced portions SPC of the protected substrate PA, wherein the materials of the first and second insulating layers can be silicon dioxide. Step S113-2, as follows Figure 13 As shown, the first isolation layer ISO1 and the second isolation layer ISO2 are etched on both sides of each gate of the at least one gate GA, exposing the first type highly doped silicon carbide epitaxial layer 1014 on both sides of the GAL to form the first electrode E1, wherein the second type silicon carbide epitaxial layer 1013 on both sides of the GAL serves as the active channel ACH, and the first electrode E1 (as shown) Figure 19 (As shown) is a source S1. Step S114, as follows: Figure 14 As shown, a connection material precursor 1016 is deposited on the active unit substrate ACR, the protective environment substrate PA, and the bottom 1011B of the first-type highly doped silicon carbide layer 1011, wherein the connection material precursor 1016 is a nickel metal. Step S115, as follows Figure 15 As shown, the connection material precursor 1016 is etched onto the substrate PA of the protected area, and the connection material precursor 1016 is etched between the two gates GA to give it a specific thickness 1017T. The connection material precursor 1016 with the specific thickness 1017T is then sintered to form a connection material 1017, wherein the connection material is nickel silicide. Step S116, as follows Figure 16 As shown, a gate contact pad (not shown) is etched to form a gate contact pad opening (not shown), and a gate wire material is filled into the gate contact pad opening (not shown), wherein the gate wire material is aluminum. Figure 16 The gate contact pads, gate contact pad openings, and gate wire material protrude beyond the paper plane, therefore... Figure 16 The cross-section was not shown. Step S117, as follows: Figure 17 As shown, a top metal layer TM is deposited on the second isolation layer ISO2 of the active cell region substrate ACR and on the connection material 1017 between the two gates GA, wherein the top metal layer TM serves as a source electrode pad SPD. Then, a protective layer PAL is deposited on the protective protection substrate PA and a portion of the top metal layer TM of the active cell AC. Step S118, as... Figure 18As shown, the connecting material 1017 at the bottom 1101B of the first type of highly doped silicon carbide layer 1011 can be electroplated with silver metal to serve as the second electrode E2 of the power transistor 10, which is the drain electrode D1.

[0035] In any embodiment disclosed herein, method S10 further includes the following steps: depositing a metal seed layer MS having a first thickness on the insulating layer OXI; depositing a photoresist layer PR having a second thickness on the metal seed layer MS; removing a first portion of the photoresist layer PR by a first micro-development process, leaving a second portion of the photoresist layer PR; forming a metal mask layer HM having the second thickness on the metal seed layer MS by a metal electroplating process, wherein the carrier implantation blocking region has the second thickness, the carrier implantation penetrating region has the first thickness, and the second thickness is greater than the first thickness; removing the second portion of the photoresist layer PR; and performing a carrier implantation procedure, wherein the carrier implantation procedure includes performing multiple carrier implantations at different energy intensities into a first epitaxial portion and a second epitaxial portion of the at least one second-type low-doped portion PP to form a first second-type low-doped carrier portion and a second second-type low-doped carrier portion, respectively, wherein the energy intensity is related to a depth implanted into the at least one second-type low-doped portion.

[0036] Please see Figure 19 This is a schematic diagram of the power transistor 10 according to a preferred embodiment of this disclosure. Please refer to [link / reference]. Figure 20 , it is Figure 19 A simplified diagram. Figure 20 In the embodiment, the power transistor 10 includes a semiconductor substrate 101, which has an active cell (AC) and breakdown-resistant epitaxial regions 1012P1 and 1012P2. The active cell AC includes at least one gate GA and two vertical active regions VACH on both sides thereof. The breakdown-resistant epitaxial regions 1012P1 and 1012P2 are disposed below the at least one gate GA.

[0037] exist Figure 19In the embodiments described, the breakdown-resistant epitaxial portions 1012P1 and 1012P2 of the power transistor 10 are, for example, P-type lightly doped pillars, which can be disposed below the gate GA. Another breakdown-resistant epitaxial portion 1012P1 can be disposed below the substrate, which is, for example, a second-type heavily doped epitaxial portion 126 serving as the body substrate BB of the power transistor 10. The width of the P-type lightly doped pillar disposed below the gate GA can be greater than the width of the P-type lightly doped pillar disposed below the substrate. If the P-type low-doped pillar is only disposed below the body substrate BB between the two gates, the depletion region of the breakdown-resistant epitaxial portion 1012P3 is smaller; if the P-type low-doped pillar is only disposed below the two gates GA, the depletion regions of the breakdown-resistant epitaxial portions 1012P1 and 1012P2 are larger; if the P-type low-doped pillar is disposed below both the body substrate BB and the gate GA, the number of depletion regions of the breakdown-resistant epitaxial portions 1012P3, 1012P1, and 1012P2 between the body substrate BB and the gate GA increases and becomes denser, resulting in better breakdown resistance and leakage current prevention.

[0038] In any embodiment disclosed herein, the P-type lightly doped pillar may be disposed only below the substrate BOD between the two gate GAs (e.g., Figure 24 (As shown), it can be configured only below the gate GA, or it can be configured simultaneously below the substrate BOD and below the gate GA.

[0039] In any embodiment disclosed herein, the power transistor 10 includes a semiconductor substrate 12, a protective structure PS, and a transition structure TS. The semiconductor substrate 12 includes a first-type epitaxial layer 121 and an active cell 122. The active cell 122 is disposed on the semiconductor substrate 12 and includes at least one gate GA, wherein each side GAL of the gate GA has a second-type epitaxial portion 123 on the first-type epitaxial layer 121 and a first-type highly doped epitaxial portion 124 on the second-type epitaxial portion 123. The protective structure PS is disposed on the semiconductor substrate 12. The transition structure TS is disposed between the active cell 122 and the protective structure PS and has a second-type highly doped epitaxial portion 125.

[0040] In any of the embodiments disclosed herein, the active unit 122 further includes a second-type highly doped epitaxial portion 126 disposed between the at least one gate GA and between the two second-type epitaxial portions 123, wherein the second-type highly doped epitaxial portion 126 is configured as a body substrate BB of the power transistor 10, and the second-type epitaxial portion 123 is configured as an active region of the power transistor 10. The transition structure TS is configured as a single-level PN diode, which protects the power transistor 10 when the single-level PN diode is reverse biased, and includes the first-type epitaxial layer 121, a horizontal high position portion 1251 disposed on the first-type epitaxial layer 121, a horizontal low position portion 1253 disposed on the first-type epitaxial layer 121, and a stepped transition portion 1252 disposed on the first-type epitaxial layer 121 and connecting the horizontal high position portion 1251 and the horizontal low position portion 1253. The semiconductor substrate 12 is a silicon carbide semiconductor substrate 101, and the power transistor 10 is a trench power transistor. The first type is N-type, and the second type is P-type. Each gate of the at least one gate GA includes a polysilicon PLY disposed in a trench TCH and a gate insulating layer GO disposed on both sides and the bottom of the trench TCH. The first type highly doped epitaxial portion 124 on both sides of the gate GA serves as a source S1 of the power transistor 10. The active unit 122 also includes a first insulating layer ISO1 disposed on the gate GA and a top metal layer TM disposed on the active unit 122, wherein the top metal layer TM serves as a source electrode pad SPD, the first insulating layer ISO1 is configured to isolate the gate GA from the source electrode pad SPD, and a portion of the source S1 is electrically connected to the source electrode pad SPD. The silicon carbide semiconductor substrate 101 further includes a buffer layer 1015, a first-type highly doped silicon carbide layer 1011, and a bottom metal layer BM. The buffer layer 1015 connects the first-type highly doped silicon carbide layer 1011 and the first-type epitaxial layer 121, and the bottom metal layer BM serves as a drain D1 of the power transistor 10. The protection structure PS is configured as a multi-level PN diode to protect the power transistor 10 when the multi-level PN diode is reverse biased. The protection structure PS includes a plurality of floating edge rings FR and a second isolation layer ISO2. Each of the plurality of floating edge rings FR includes a second-type highly doped epitaxial portion FR1, FR2, ..., FRn, and the second-type highly doped epitaxial portion FR1, FR2, ..., FRn forms a PN semiconductor junction with a portion of the first-type epitaxial layer 121. The second isolation layer ISO2 is configured to isolate the plurality of floating edge rings FR from the source electrode pad SPD.The protective layer PAL is disposed on the complex floating edge ring FR and the source electrode pad SPD.

[0041] It is worth noting that the microstructure of the second-type highly doped epitaxial portion 126, which serves as the body substrate BB of the power transistor 10, differs under a microscope from the microstructure of the second-type epitaxial portion 123, which serves as an active region of the power transistor 10 on either side of it. This is because the body substrate BB is formed by high-energy carrier implantation, while the active region is pre-formed by doping P-type carriers using vapor deposition during silicon carbide growth. Furthermore, the active region is fully fabricated before the etching and micro-development processes begin, reducing the need for subsequent time-consuming high-energy carrier implantation processes, thus saving production time and improving production efficiency.

[0042] In addition, besides the vertical active regions VHC on both sides of the gate GA forming depletion regions with the first type epitaxial layer 1012 when the power transistor 10 is turned off, depletion regions can also be formed between the breakdown epitaxial portions 1012PP1 and 1012PP2 disposed below the gate GA and the first type epitaxial layer 1012, and between the breakdown epitaxial portion 1012PP3 disposed below the body substrate BB and the first type epitaxial layer 1012. The larger and denser these depletion regions are, the better the effect of improving the breakdown voltage and reducing the leakage current.

[0043] In summary, a method for forming a superjunction structure of a power transistor on a silicon carbide (SiC) substrate can be described, comprising the following steps: providing a silicon carbide semiconductor substrate, wherein the silicon carbide semiconductor substrate includes a first type highly doped silicon carbide layer, a first type silicon carbide epitaxial layer, a second type silicon carbide epitaxial layer, and the second type silicon carbide epitaxial layer is pre-disposed on the first type silicon carbide epitaxial layer to serve as an active channel of a power transistor. The first type of highly doped silicon carbide epitaxial layer is pre-disposed on the second type of silicon carbide epitaxial layer to serve as a first electrode of the power transistor; an insulating layer is formed on the first type of highly doped silicon carbide layer; a metal mask layer is grown on the insulating layer, wherein the metal mask layer includes a carrier implantation blocking region and a carrier implantation penetration region; a first high-energy carrier is implanted into a working region of the first type of silicon carbide epitaxial layer through the carrier implantation penetration region to form at least one second type of low-doped portion; the metal mask layer and the insulating layer are removed; the first type of highly doped silicon carbide epitaxial layer, the second type of silicon carbide epitaxial layer, and the first type of silicon carbide epitaxial layer are etched to form a protective substrate and an active cell region substrate having at least one trench, wherein the active cell region... The substrate is located within the working region, and the at least one trench corresponds to the at least one second-type low-doped portion; a gate insulating layer is deposited on the protection zone substrate and the active cell region substrate; a polysilicon is deposited on each trench of the at least one trench to form at least one gate; a first isolation layer is deposited on the protection zone substrate and the active cell region substrate; and the first isolation layer, the gate insulating layer, the first-type high-doped silicon carbide epitaxial layer, and the second-type silicon carbide epitaxial layer are etched between the at least one trench and between the active cell region substrate and the protection zone substrate, and the first isolation layer and the gate insulating layer are etched at multiple intervals on the protection zone substrate.

[0044] Please see Figure 21This is a schematic diagram of method S20 for manufacturing a power transistor 10 according to another preferred embodiment of the present invention. Method S20 includes the following steps: Step S201, providing a semiconductor substrate, wherein the semiconductor substrate includes a first-type highly doped semiconductor layer, a first-type epitaxial layer, a second-type epitaxial layer, and a first-type highly doped epitaxial layer, the second-type epitaxial layer being pre-disposed on the first epitaxial layer to serve as an active channel of the power transistor, and the first-type highly doped epitaxial layer being pre-disposed on the second epitaxial layer to serve as a first electrode of the power transistor; Step S202, forming an insulating layer on the first-type highly doped silicon carbide layer; Step... S203, a metal mask layer is formed on the insulating layer, wherein the metal mask layer includes a carrier implantation blocking region and a carrier implantation penetrating region; step S204, a first high-energy carrier is implanted into a working region of the first type silicon carbide epitaxial layer through the carrier implantation penetrating region to form at least one second type low-doped portion; step S205, the metal mask layer and the insulating layer are removed; and step S206, the first type high-doped epitaxial layer, the second type epitaxial layer, and the first type epitaxial layer are etched to form a protective environment substrate and an active cell region substrate having at least one trench.

[0045] Step S201 is the process of forming a precursor, and the semiconductor substrate is used as a raw material and is already prepared before the production of the power transistor 10. Steps S203 to S204 involve implanting an epitaxial layer onto the semiconductor substrate with high-energy carriers before etching, so as to form breakdown-resistant epitaxial portions 1012P1, 1012P2, and 1012P3 in the epitaxial layer.

[0046] exist Figure 21 The embodiments described herein can be combined with any embodiment disclosed herein to form new embodiments. For example, method S20 further includes the following steps: Figure 9 As shown, a gate insulating layer GO is deposited on the protected area substrate PA and the active cell region substrate ACR. Step S110, as follows: Figure 10 As shown, a polysilicon PLY is deposited on each trench of the at least one trench TCH to form at least one gate GA. Step S111, as follows: Figure 11 As shown, a first isolation layer ISO1 is deposited on the protected area substrate PA and the active unit region substrate ACR. Step S106-1, as follows: Figure 6As shown, the first isolation layer ISO1, the gate insulating layer GO, the first type highly doped silicon carbide epitaxial layer 1014, and the second type silicon carbide epitaxial layer 1013 are etched between the at least one trench TCH and between the active cell region substrate ACR and the protective environment substrate PA, and the first isolation layer ISO1 and the gate insulating layer GO are etched in the plurality of spaced portions SPC of the protective environment substrate PA.

[0047] In any embodiment of this disclosure, method S20 further includes the following steps: Step S112-1, as follows Figure 12 As shown, a first-type silicon carbide epitaxial layer 1012 is implanted with a second-type highly doped carrier P+ between at least one trench GA, between the active cell region substrate ACR and the protective environment substrate PA, and in the plurality of spaced portions SPC of the protective environment substrate PA, wherein: the second-type highly doped carrier P+ forms a first and second-type highly doped semiconductor well P+W1 in the first-type silicon carbide epitaxial layer 1012 between at least one trench GA; the second-type highly doped carrier P+ in the active cell region substrate ACR and the protective environment substrate SPC... A second type II highly doped semiconductor well P+W2 is formed in the first type silicon carbide epitaxial layer 1012 between the bottom PA; a third type II highly doped semiconductor well P+W3 is formed in the first type silicon carbide epitaxial layer 1012 of the complex spaced portion SPC by the second type highly doped carrier P+; and a complex PN junction (not shown) is formed between the second type II highly doped semiconductor well P+W2 and the first type silicon carbide epitaxial layer 1012, wherein the complex PN junction is configured to buffer a high operating voltage in reverse bias. Figures 1 to 19 In the process, the silicon carbide semiconductor substrate 101 further includes a buffer layer 1015 that connects the first type highly doped silicon carbide layer 1011 and the first type silicon carbide epitaxial layer 1012.

[0048] In any embodiment of this disclosure, method S20 further includes the following steps: step S113, as follows Figure 13 As shown, a second isolation layer ISO2 is deposited on the first isolation layer ISO1 and the plurality of spaced portions SPC of the protected area substrate PA, wherein the material of the first and second isolation layers can be silicon dioxide. Then, the first isolation layer ISO1 and the second isolation layer ISO2 are etched on both sides of each gate of the at least one gate GA, so that the first type highly doped silicon carbide epitaxial layer 1014 on both sides of the GAL is exposed to form the first electrode E1, wherein the second type silicon carbide epitaxial layer 1013 on both sides of the GAL serves as the active channel ACH, and the first electrode E1 (as shown) Figure 12 (As shown) is a source S1. Step S114, as follows: Figure 14As shown, a connection material precursor 1016 is deposited on the active unit substrate ACR, the protective environment substrate PA, and the bottom 1011B of the first-type highly doped silicon carbide layer 1011, wherein the connection material precursor 1016 is a nickel metal. Step S115, as follows Figure 15 As shown, the connection material precursor 1016 is etched onto the substrate PA of the protected area, and the connection material precursor 1016 is etched between the two gates GA to give it a specific thickness 1017T. The connection material precursor 1016 with the specific thickness 1017T is then sintered to form a connection material 1017, wherein the connection material is nickel silicide. Step S116, as follows Figure 16 As shown, a gate contact pad (not shown) is etched to form a gate contact pad opening (not shown), and a gate wire material is filled into the gate contact pad opening (not shown), wherein the gate wire material is aluminum. Figure 16 The gate contact pads, gate contact pad openings, and gate wire material protrude beyond the paper plane, therefore... Figure 10 The cross-section was not shown. Step S117, as follows: Figure 17 As shown, a top metal layer TM is deposited on the second isolation layer ISO2 of the active cell region substrate ACR and on the connection material 1017 between the two gates GA, wherein the top metal layer TM serves as a source electrode pad SPD. Then, as... Figure 17 As shown, a protective layer PAL is deposited on a portion of the top metal layer TM of the protected substrate PA and the active unit AC. Figure 18 In this process, the connecting material 1017 at the bottom 1101B of the first type of highly doped silicon carbide layer 1011 can be electroplated with silver metal to serve as the drain D1 of the power transistor 10.

[0049] In any embodiment disclosed herein, the semiconductor substrate 12 is a wide-energy silicon semiconductor substrate, which is a silicon carbide semiconductor substrate 101. The first type highly doped semiconductor layer is a first type highly doped silicon carbide semiconductor layer 1011, the first type epitaxial layer 121 is a first type silicon carbide epitaxial layer 1012, and the second type epitaxial layer P-E (e.g., ...) Figure 1 As shown, a second-type silicon carbide epitaxial layer 1013 and a first-type highly doped epitaxial layer N+Epi (as shown) are... Figure 1The image shows a first-type highly doped silicon carbide epitaxial layer 1014. The first type is N-type, and the second type is P-type. The silicon carbide semiconductor substrate 101 also includes a buffer layer 1015 connecting the first-type highly doped silicon carbide layer 1011 and the first-type silicon carbide epitaxial layer 1012. The silicon carbide semiconductor substrate 101 also includes a bottom metal layer BM, disposed below the first-type highly doped silicon carbide layer 1011, to serve as a second electrode E2 of the power transistor 10 (e.g., ...). Figure 18 As shown in the diagram, the second electrode E2 is a drain D1 of the power transistor 10. The width of the plurality of spaced portions SPCs on the protected substrate PA increases as they approach an edge of the protected substrate PA. The number and width of the plurality of spaced portions SPCs depend on a voltage rating of the power transistor 10. Before all micro-development and etching processes, the second type silicon carbide epitaxial layer 1013 and the first type highly doped silicon carbide epitaxial layer 1014 are first disposed on the first type silicon carbide epitaxial layer 1012 to eliminate or reduce subsequent high-energy carrier implantation.

[0050] Please see Figure 22 This is a schematic diagram of method S30 for manufacturing a power transistor 10 according to another preferred embodiment of the present invention. Method S30 includes the following steps: step S301, providing a semiconductor substrate, wherein the semiconductor substrate includes a first epitaxial layer and a second epitaxial layer, and the second epitaxial layer is pre-disposed on the first epitaxial layer as an electronic component layer of the power transistor; and step S302, performing a carrier implantation process on the second epitaxial layer to allow selected carriers to penetrate the second epitaxial layer and form at least one doped portion in the first epitaxial layer.

[0051] exist Figure 22 The embodiments described herein can be combined with any of the embodiments disclosed to form new embodiments. For example, method S30 further includes etching the second epitaxial layer and the first epitaxial layer to form a protective environment substrate PS and an electronic component layer substrate having at least one trench TCH. The at least one doped portion is at least one low-doped portion. The first epitaxial layer is a first-type epitaxial layer 121, the second epitaxial layer includes a first-type highly doped epitaxial layer 1014 and a second-type epitaxial layer 1013, and the at least one low-doped portion is a second-type low-doped portion PP.

[0052] In any embodiment disclosed herein, the semiconductor substrate 12 is a wide-energy silicon semiconductor substrate, which is a silicon carbide semiconductor substrate 101. The first epitaxial layer is a first-type epitaxial layer 121, and the second epitaxial layer includes a first-type highly doped epitaxial layer N+Epi and a second-type epitaxial layer PEpi (e.g., ...). Figure 1(As shown). The first type is N-type, and the second type is P-type. The semiconductor substrate 12 includes a first-type highly doped semiconductor layer, a first-type epitaxial layer 121, and a second-type epitaxial layer P-E (as shown). Figure 1 As shown), and a type I highly doped epitaxial layer N+Epi (as shown) Figure 1 As shown, the second type epitaxial layer PEp1 is pre-disposed on the first type epitaxial layer 121 to serve as an active channel ACH of the power transistor 10, and the first type highly doped epitaxial layer N+Epi is pre-disposed on the second type epitaxial layer PEp1 to serve as a first electrode E1 of the power transistor 10. The second type epitaxial layer PEp1 includes a second type epitaxial portion 123, and the electronic component layer includes the second type epitaxial portion PEp1 as an active region of the power transistor 10. The electronic component layer substrate includes an active cell region substrate ACR and a protective layer substrate PA. The first type of highly doped semiconductor layer is a first type of highly doped silicon carbide semiconductor layer 1011, the first type of epitaxial layer 121 is a first type of silicon carbide epitaxial layer 1012, the second type of epitaxial layer PEp is a second type of silicon carbide epitaxial layer 1013, and the first type of highly doped epitaxial layer N+Epi is a first type of highly doped silicon carbide epitaxial layer 1014. The silicon carbide semiconductor substrate 101 further includes a buffer layer 1015 connecting the first type of highly doped silicon carbide layer 1014 and the first type of silicon carbide epitaxial layer 1013. The silicon carbide semiconductor substrate 101 further includes a bottom metal layer BM disposed below the first type of highly doped silicon carbide layer 1011 to serve as a second electrode E2 of the power transistor 10, wherein the second electrode E2 is a drain D1 of the power transistor 10.

[0053] In any embodiment disclosed herein, the width of the plurality of spaced SPC portions on the protected substrate PA increases as they approach an edge of the protected substrate PA. The number and width of the plurality of spaced SPC portions depend on a voltage rating of the power transistor 10. Before all micro-development and etching processes, the second type silicon carbide epitaxial layer 1013 and the first type highly doped silicon carbide epitaxial layer 1014 are first disposed on the first type silicon carbide epitaxial layer 1012 to eliminate or reduce subsequent high-energy carrier implantation.

[0054] In any of the embodiments disclosed herein, when the power transistor 10 is off, a first junction depletion region is formed between the active channel ACH and the first type epitaxial layer 1012, and a second junction depletion region is formed between the at least one second type low-doped portion PP and the first type epitaxial layer 1012, wherein the second junction depletion region is larger than the first junction depletion region.

[0055] In any embodiment of this disclosure, method S30 can be combined with any embodiment of this disclosure to form another embodiment. For example, method S30 further includes the following steps: etching the first type highly doped epitaxial layer 1014, the second type epitaxial layer 1013, and the first type epitaxial layer 1012 to form the protective environment substrate PA and the active cell region substrate ACR having at least one trench TCH; Figure 9 As shown, a gate insulating layer GO is deposited on the protected area substrate PA and the active cell region substrate ACR. Step S110, as follows: Figure 10 As shown, a polysilicon PLY is deposited on each trench of the at least one trench TCH to form at least one gate GA. Step S111, as follows: Figure 11 As shown, a first isolation layer ISO1 is deposited on the protected area substrate PA and the active unit region substrate ACR. Step S112-1, as follows: Figure 12As shown, the first isolation layer ISO1, the gate insulating layer GO, the first type highly doped silicon carbide epitaxial layer 1014, and the second type silicon carbide epitaxial layer 1013 are etched between the at least one trench TCH and between the active cell region substrate ACR and the protective environment substrate PA. The first isolation layer ISO1 and the gate insulating layer GO are also etched in the plurality of spaced portions SPC of the protective environment substrate PA. A second type highly doped carrier P+ is implanted into the first type epitaxial layer 1012 between the at least one trench GA, between the active cell region substrate ACR and the protective environment substrate PA, and in the plurality of spaced portions SPC of the protective environment substrate PA. The second type highly doped carrier P+ forms a first and second type highly doped semiconductor well P+W1 in the first type epitaxial layer 1012 between the at least one trench GA. The second type highly doped carrier P+ forms a first and second type highly doped semiconductor well P+W1 in the active cell region substrate ACR and the protective environment substrate PA. A second type II highly doped semiconductor well P+W2 is formed in the first type epitaxial layer 1012; a third type II highly doped semiconductor well P+W3 is formed in the first type epitaxial layer 1012 of the complex spaced portion SPC of the second type II highly doped carrier P+; and a complex PN junction is formed between the third type II highly doped semiconductor well P+W3 and the first type epitaxial layer, wherein the complex PN junction is configured to buffer a high operating voltage in reverse bias; a second isolation layer ISO2 is deposited on the first isolation layer ISO1 and the complex spaced portion SPC of the protected area substrate PA; the first isolation layer ISO1 and the second isolation layer ISO2 are etched on both sides of each gate of the at least one gate GA, so that the first type II highly doped epitaxial layer 1014 on both sides of the GAL is exposed to form the first electrode E1, wherein the second type epitaxial layer 1013 on both sides of the GAL serves as the active channel. The first electrode E1 is a source electrode S1; a connection material precursor 1016 is deposited on the active cell substrate ACR, the protective environment substrate PA, and the bottom of the first type highly doped silicon carbide layer 1011, wherein the connection material precursor 1016 is a nickel metal; the connection material precursor 1016 on the protective environment substrate PA is etched, and the connection material precursor 1016 between the two gates GA is etched to give it a specific thickness 1017T, and the connection material precursor 1016 with the specific thickness 1017T is sintered to form a connection material 1017, wherein the connection material 1017 is a nickel silicide; Figure 16As shown, a gate contact pad (not shown) is etched to form a gate contact pad opening (not shown), and a gate wire material (not shown) is filled into the gate contact pad opening, wherein the gate wire material is an aluminum metal; a top metal layer (TM) is deposited on the second isolation layer ISO2 of the active cell region substrate ACR and on the connection material 1017 between the two gates GA, wherein the top metal layer TM serves as a source electrode pad SPD; and a protective layer PAL is deposited on a portion of the top metal layer TM of the protective PAL region substrate PA and the active cell AC.

[0056] Please see Figure 23 This is a schematic diagram of a power transistor 20 according to another preferred embodiment of the present disclosure. Please refer to [link / reference]. Figure 24 , it is Figure 23 A simplified schematic diagram is shown. The power transistor 20 includes a semiconductor substrate 201, which has an active cell AC, a substrate BOD, and a breakdown-resistant epitaxial portion 2012P3. The active cell AC includes two gates GA, each gate GA having a vertical active region VACH on each side, and each vertical active region VACH including an upper first type doped region 2013 and a middle second type doped region 2012. The substrate BOD is adjacent to the middle second type doped region 2012 of each gate GA. The breakdown-resistant epitaxial portion 2012P3 is disposed below the substrate BOD.

[0057] From all the above embodiments, a method for forming a power transistor with a superjunction structure on a silicon carbide (SiC) substrate can be summarized, the silicon carbide substrate having a substrate, the method comprising the following steps: providing a semiconductor substrate, wherein the semiconductor substrate includes a first type highly doped semiconductor layer, a first type epitaxial layer, a second type epitaxial layer, and the second type epitaxial layer is pre-disposed on the first type epitaxial layer to serve as an active channel of the power transistor. The first type of highly doped epitaxial layer is pre-configured on the second type of epitaxial layer to serve as a first electrode of the power transistor; an insulating layer is formed on the first type of highly doped silicon carbide layer; a metal mask layer is formed on the insulating layer, wherein the metal mask layer includes a carrier implantation blocking region and a carrier implantation penetration region; a first high-energy carrier is implanted into a working region of the first type of silicon carbide epitaxial layer through the carrier implantation penetration region to form at least one second type of low-doped portion, wherein the at least one second type of low-doped portion is below the substrate; the metal mask layer and the insulating layer are removed; and the first type of highly doped epitaxial layer, the second type of epitaxial layer, and the first type of epitaxial layer are etched to form a protected environment substrate and an active cell region substrate having at least one trench.

[0058] Please see Figure 25 This is a schematic diagram of a method S40 for manufacturing a power transistor according to a preferred embodiment of the present invention. The power transistor includes a substrate, and the method S40 includes the following steps: Step S401, providing a silicon carbide semiconductor substrate, wherein the silicon carbide semiconductor substrate includes a first type highly doped silicon carbide layer, a first type silicon carbide epitaxial layer, a second type silicon carbide epitaxial layer, and the second type silicon carbide epitaxial layer is pre-disposed on the first type silicon carbide epitaxial layer to serve as an active channel of the power transistor, and the first type highly doped silicon carbide epitaxial layer is pre-disposed on the second type silicon carbide epitaxial layer to serve as a first electrode of the power transistor. Step S402, forming an insulating layer on the first type highly doped silicon carbide layer. Step S403, growing and forming a metal mask layer on the insulating layer, wherein the metal mask layer includes a carrier injection blocking region and a carrier injection penetration region. Step S404: A first high-energy carrier is injected into a working region of the first type silicon carbide epitaxial layer through the carrier implantation penetration region to form at least one second type low-doped portion, wherein the at least one second type low-doped portion is below the substrate.

[0059] Please see Figure 26This is a schematic diagram of a method S50 for manufacturing a power transistor according to a preferred embodiment of the present disclosure. The method S50 for manufacturing a power transistor includes the following steps: Step S501, providing a semiconductor substrate, wherein the semiconductor substrate includes a first epitaxial layer and a second epitaxial layer, and the second epitaxial layer is pre-disposed on the first epitaxial layer as an electronic component layer of the power transistor. Step S502, defining the location of a substrate for the electronic component layer. Step S503, performing a carrier implantation process on the second epitaxial layer to allow selected carriers to penetrate the second epitaxial layer and form at least one doped portion within the first epitaxial layer, wherein the at least one doped portion is below the substrate.

[0060] Figures 25-26 The embodiments can be combined with the foregoing embodiments to form another new embodiment, which can be understood by those skilled in the art from the foregoing content, and will not be repeated here.

[0061] The numerous variations and other embodiments disclosed herein will be beneficial to those skilled in the art in understanding the teachings presented in the foregoing description and related drawings. Therefore, it should be understood that this disclosure is not limited to the specific embodiments disclosed, and that the variations and other embodiments are intended to be included within the scope of protection of the appended claims.

[0062] Symbol Explanation

[0063] 10: Power Transistors

[0064] 101: Silicon carbide semiconductor substrate

[0065] 1011: Type I highly doped silicon carbide layer

[0066] 1012: Type I silicon carbide epitaxial layer

[0067] 1013: Type II silicon carbide epitaxial layer

[0068] 1014: Type I highly doped silicon carbide epitaxial layer

[0069] 1015: Buffer layer

[0070] PR: Photoresist layer

[0071] MS: Metal Seed Layer

[0072] HM: Metallic masking layer

[0073] OXI: Insulating layer

[0074] PB: Carrier Injection Barrier Region

[0075] PT: Carrier injection penetration region

[0076] HEI: The First High-Energy Carrier

[0077] PP: at least one type II low-doped fraction

[0078] PP1, PP2: wider type II low-doped distribution

[0079] PP3: Narrower type II low-doped fraction

[0080] HP1: Semi-finished product

[0081] 1012PP1, 1012PP2, 1012PP3: Piercing-resistant epitaxial portion

[0082] AC: Active unit

[0083] 2012: In the type II doped region

[0084] 2013: In the upper type I doped region

[0085] 2012P3: Resistance to Penetration of the Extensional Part

[0086] ACR: Active cell region substrate

[0087] PA: Base of the protected area

[0088] PAL: Protective Layer

[0089] TCH: Trench

[0090] GO: Gate insulating layer

[0091] PLY: Polycrystalline Silicon

[0092] GA: gate

[0093] GAL: Gate sides

[0094] ISO1: First isolation layer

[0095] ISO2: Second isolation layer

[0096] SPC: Complex Interval Part

[0097] P+: Type II highly doped carrier

[0098] P+W1: Type I and II highly doped semiconductor wells

[0099] P+W2: Type II highly doped semiconductor well

[0100] P+W3: Type II highly doped semiconductor well

[0101] E1: First electrode

[0102] E2: Second electrode

[0103] S1: Source

[0104] D1: Drain

[0105] ACH: Active Channel

[0106] VACH: Vertical Active Area

[0107] 1016: Precursor material for bonding

[0108] 1017T: Specific thickness

[0109] 1017: Connecting Material

[0110] 1011B: Bottom of the first type of heavily doped silicon carbide layer

[0111] TM: Top Metal Layer

[0112] BM: Bottom Metal Layer

[0113] SPD: Source electrode pad

[0114] 12: Semiconductor substrate

[0115] 121: Type I epitaxial layer

[0116] 122: Active unit

[0117] 123: Type II extension

[0118] 124: Type I highly doped epitaxial region

[0119] 125, 126, FR1, FR2, ..., FRn: Type II highly doped epitaxial regions

[0120] BB: Body base

[0121] TS: Transition Structure

[0122] 1251: Horizontal high position distribution

[0123] 1252: Stepped Turning Section

[0124] 1253: Horizontal low position distribution

[0125] FR: Complex floating edge ring.

Claims

1. A method for forming a superjunction structure of a power transistor on a silicon carbide substrate, comprising the following steps: A silicon carbide semiconductor substrate is provided, wherein the silicon carbide semiconductor substrate includes a first type highly doped silicon carbide layer, a first type silicon carbide epitaxial layer, a second type silicon carbide epitaxial layer, and a first type highly doped silicon carbide epitaxial layer, wherein the second type silicon carbide epitaxial layer is pre-disposed on the first type silicon carbide epitaxial layer to serve as an active channel of a power transistor, and the first type highly doped silicon carbide epitaxial layer is pre-disposed on the second type silicon carbide epitaxial layer to serve as a first electrode of the power transistor; An insulating layer is formed on the first type of highly doped silicon carbide epitaxial layer; A metal masking layer is grown on the insulating layer, wherein the metal masking layer includes a carrier injection blocking region and a carrier injection penetration region. A first high-energy carrier is implanted into a working region of the first type silicon carbide epitaxial layer through the carrier implantation penetration region to form at least one second type low-doped portion; Remove the metal shielding layer and the insulating layer; The first type of highly doped silicon carbide epitaxial layer, the second type of silicon carbide epitaxial layer, and the first type of silicon carbide epitaxial layer are etched to form a protective environment substrate and an active cell region substrate having at least one trench, wherein the active cell region substrate is in the working area, and the at least one trench corresponds to the at least one second type of low doped portion. A gate insulating layer is deposited on the substrate of the protected area and the substrate of the active cell region; A polysilicon is deposited on each trench of the at least one trench to form at least one gate; A first isolation layer was deposited on the substrate of the protected area and the substrate of the active unit area; as well as The first isolation layer, the gate insulating layer, the first type highly doped silicon carbide epitaxial layer, and the second type silicon carbide epitaxial layer are etched between the at least one trench and between the active cell region substrate and the protective environment substrate, and the first isolation layer and the gate insulating layer are etched at multiple intervals in the protective environment substrate.

2. The method of claim 1, further comprising the following steps: The first type silicon carbide epitaxial layer is implanted with a second type highly doped carrier between the at least one trench, between the active cell region substrate and the protective zone substrate, and in the plurality of spaced portions of the protective zone substrate, wherein: The second type of highly doped carrier forms a first and second type of highly doped semiconductor well in the first type of silicon carbide epitaxial layer between at least one trench; The second type of highly doped carrier forms a second type of highly doped semiconductor well in the first type of silicon carbide epitaxial layer between the active cell region substrate and the protective zone substrate; The second type of highly doped carrier forms a third second type of highly doped semiconductor well in the first type of silicon carbide epitaxial layer in the complex interval portion; and A complex PN junction is formed between the second type-2 highly doped semiconductor well and the first type silicon carbide epitaxial layer, wherein the complex PN junction is configured to buffer a high operating voltage in reverse bias. A second insulating layer is deposited on the first insulating layer and the plurality of spaced portions of the substrate of the protected area; The first isolation layer and the second isolation layer are etched on both sides of each gate of the at least one gate, exposing the first type highly doped silicon carbide epitaxial layer on both sides to form the first electrode, wherein: The second type of silicon carbide epitaxial layer on both sides serves as the active channel, and the first electrode is a source electrode; and When the power transistor is off, a first junction depletion region is formed between the active channel and the first type epitaxial layer, and a second junction depletion region is formed between the at least one second type low-doped portion and the first type epitaxial layer, wherein the second junction depletion region is larger than the first junction depletion region. A connection material precursor is deposited on the active cell substrate, the protective cell substrate, and the bottom of the first type of highly doped silicon carbide layer, wherein the connection material precursor is a nickel metal; The connection material precursor is etched onto the substrate of the protected area, the connection material precursor is etched between the two gates to give it a specific thickness, and the connection material precursor with the specific thickness is sintered to form a connection material, wherein the connection material is a nickel silicide. Etch a gate contact pad to form a gate contact pad opening, and fill the gate contact pad opening with a gate wire material, wherein the gate wire material is an aluminum metal. A top metal layer is deposited on the second insulating layer of the active cell region substrate and on the interconnect material between the two gates, wherein the top metal layer serves as a source electrode pad; and A protective layer is deposited on the substrate of the protected area and a portion of the top metal layer of the substrate of the active unit area.

3. The method of claim 1, wherein: The first type is type N, while the second type is type P; The silicon carbide semiconductor substrate also includes a buffer layer that connects the first type highly doped silicon carbide layer and the first type silicon carbide epitaxial layer; The silicon carbide semiconductor substrate further includes a bottom metal layer disposed below the first type of highly doped silicon carbide layer to serve as a second electrode of the power transistor, wherein the second electrode is a drain of the power transistor; The width of the plurality of intervals in the base of the protected area is wider the closer it is to one edge of the base of the protected area; The number and width of the complex intervals depend on the voltage rating of the power transistor. Before all micro-development and etching processes, the second type silicon carbide epitaxial layer and the first type highly doped silicon carbide epitaxial layer are first disposed on the first type silicon carbide epitaxial layer to eliminate or reduce subsequent high-energy carrier implantation. The method also includes the following steps: A metal seed layer having a first thickness is deposited on the insulating layer; A photoresist layer with a second thickness is deposited on the metal seed layer; A first portion of the photoresist layer is removed using a first micro-development process, leaving a second portion of the photoresist layer. A metal mask layer having the second thickness is formed on the metal seed layer by a metal electroplating method, wherein the carrier injection blocking region has the second thickness, the carrier injection penetration region has the first thickness, and the second thickness is greater than the first thickness. Remove the second portion of the photoresist layer; as well as Perform a carrier implantation procedure, wherein the carrier implantation procedure includes performing multiple carrier implantations at different energy intensities into a first epitaxial portion and a second epitaxial portion of the at least one second-type low-doped portion to form a first second-type low-doped carrier portion and a second second-type low-doped carrier portion, respectively, wherein the energy intensity is related to a depth of implantation of the at least one second-type low-doped portion.

4. A power transistor comprising a semiconductor substrate, the power transistor having: An active cell includes at least one gate and two vertical active regions on either side thereof; and A breakdown-resistant epitaxial portion is disposed below the at least one gate.

5. The power transistor as claimed in claim 4, wherein: The semiconductor substrate includes a first type epitaxial layer; The active unit is disposed on the semiconductor substrate and includes at least one gate, wherein the vertical active region includes a second type epitaxial portion on the first type epitaxial layer and a first type highly doped epitaxial portion on the second type epitaxial portion; The breakdown-resistant epitaxial portion is a type II low-doped epitaxial portion; The power transistor also includes: A protective structure is disposed on the semiconductor substrate; and A transition structure is disposed between the active unit and the protective structure, and has a second type of highly doped epitaxial portion; The active unit further includes a second type highly doped epitaxial portion disposed between the at least one gate and between the two second type epitaxial portions, wherein the second type highly doped epitaxial portion is configured as an integral substrate of the power transistor and the second type epitaxial portion serves as an active region of the power transistor. The active unit also includes another second-type low-doped epitaxial portion disposed at the bottom of the second-type high-doped epitaxial portion. When the power transistor is off, a first junction depletion region is formed between the active channel and the first-type epitaxial layer, and a second junction depletion region is formed between the at least one second-type low-doped portion and the first epitaxial layer, wherein: The width of the second type of low-doped epitaxial portion is greater than the width of the other second type of low-doped epitaxial portion; and The depletion region of the second node is larger than that of the first node; The transition structure is configured as a single-level PN diode to protect the power transistor when the single-level PN diode is reverse biased, and includes the first type epitaxial layer, a horizontal high position portion disposed on the first type epitaxial layer, a horizontal low position portion disposed on the first type epitaxial layer, and a stepped transition portion disposed on the first type epitaxial layer and connecting the horizontal high position portion and the horizontal low position portion; The semiconductor substrate is a silicon carbide semiconductor substrate, and the power transistor is a trench power transistor. The first type is type N, while the second type is type P; Each of the at least one gate includes a polysilicon disposed in a trench and a gate insulating layer disposed on both sides and the bottom of the trench; The first type of highly doped epitaxial portion on both sides of the gate serves as a source of the power transistor; The active cell further includes a first insulating layer disposed on the gate and a top metal layer disposed on the active cell, wherein the top metal layer serves as a source electrode pad, the first insulating layer is configured to isolate the gate from the source electrode pad, and a portion of the source electrode is electrically connected to the source electrode pad; and The silicon carbide semiconductor substrate further includes a buffer layer, a first-type highly doped silicon carbide layer, and a bottom metal layer, wherein the buffer layer connects the first-type highly doped silicon carbide layer and the first-type epitaxial layer, and the bottom metal layer serves as a drain of the power transistor. The protection structure is configured as a multi-stage PN diode and protects the power transistor when the multi-stage PN diode is reverse biased. The protective structure includes: A complex floating edge ring, wherein each floating edge ring of the complex floating edge ring includes a second type highly doped epitaxial portion, and the second type highly doped epitaxial portion forms a PN semiconductor junction with a portion of the first type epitaxial layer; A second insulating layer, configured to isolate the plurality of floating edge rings from the source electrode pad; and A protective layer is disposed on the plurality of floating edge rings and the source electrode pad.

6. A method for manufacturing a power transistor, comprising the following steps: A semiconductor substrate is provided, wherein the semiconductor substrate includes a first type highly doped semiconductor layer, a first type epitaxial layer, a second type epitaxial layer, and a first type highly doped epitaxial layer, wherein the second type epitaxial layer is pre-disposed on the first type epitaxial layer to serve as an active channel of the power transistor, and the first type highly doped epitaxial layer is pre-disposed on the second epitaxial layer to serve as a first electrode of the power transistor; An insulating layer is formed on the first type of highly doped epitaxial layer; A metal shielding layer is formed on the insulating layer, wherein the metal shielding layer includes a carrier injection blocking region and a carrier injection penetration region. A first high-energy carrier is injected into a working region of the first type epitaxial layer through the carrier injection penetration region to form at least one second type low-doped portion; Remove the metal shielding layer and the insulating layer; as well as The first type of highly doped epitaxial layer, the second type of epitaxial layer, and the first type of epitaxial layer are etched to form a protected area substrate and an active cell region substrate having at least one trench.

7. The method of claim 6, further comprising the following steps: A gate insulating layer is deposited on the substrate of the protected area and the substrate of the active cell region; A polysilicon is deposited on each trench of the at least one trench to form at least one gate; A first isolation layer was deposited on the substrate of the protected area and the substrate of the active unit area; as well as The first isolation layer, the gate insulating layer, the first type highly doped epitaxial layer, and the second type epitaxial layer are etched between the at least one trench and between the active cell region substrate and the protective zone substrate, and the first isolation layer and the gate insulating layer are etched at multiple intervals in the protective zone substrate. The first-type epitaxial layer is implanted with a second-type highly doped carrier between the at least one trench, between the active cell region substrate and the protective zone substrate, and in the plurality of spaced portions of the protective zone substrate, wherein: The second type highly doped carrier forms a first and second type highly doped semiconductor well in the first type epitaxial layer between at least one trench, and when the power transistor is turned off, a first junction depletion region is formed between the active channel and the first type epitaxial layer, and a second junction depletion region is formed between the at least one second type low doped portion and the first epitaxial layer, wherein the second junction depletion region is larger than the first junction depletion region; The second type of highly doped carrier forms a second type of highly doped semiconductor well in the first type epitaxial layer between the active cell region substrate and the protective zone substrate; The second type of highly doped carrier forms a third second type of highly doped semiconductor well in the first type epitaxial layer in the complex interval portion; and A complex PN junction is formed between the second type of highly doped semiconductor well and the first type of epitaxial layer, wherein the complex PN junction is configured to buffer a high operating voltage in reverse bias. A second insulating layer is deposited on the first insulating layer and the plurality of spaced portions of the substrate of the protected area; The first isolation layer and the second isolation layer are etched on both sides of each gate of the at least one gate, exposing the first type highly doped epitaxial layer on both sides to form the first electrode, wherein: The second type epitaxial layer on both sides serves as the active channel, and the first electrode is a source electrode; and When the power transistor is off, a first junction depletion region is formed between the active channel and the first type epitaxial layer, and a second junction depletion region is formed between the at least one second type low-doped portion and the first type epitaxial layer, wherein the second junction depletion region is larger than the first junction depletion region; A connection material precursor is deposited on the active cell region substrate, the protective environment substrate, and the bottom of the first type of highly doped semiconductor layer, wherein the connection material precursor is a nickel metal; The connection material precursor is etched onto the substrate of the protected area, the connection material precursor is etched between the two gates to give it a specific thickness, and the connection material precursor with the specific thickness is sintered to form a connection material, wherein the connection material is a nickel silicide. Etch a gate contact pad to form a gate contact pad opening, and fill the gate contact pad opening with a gate wire material, wherein the gate wire material is an aluminum metal. A top metal layer is deposited on the second insulating layer of the active cell region substrate and on the interconnect material between the two gates, wherein the top metal layer serves as a source electrode pad; and A protective layer is deposited on the substrate of the protected area and a portion of the top metal layer of the substrate of the active unit area.

8. The method of claim 7, wherein: The semiconductor substrate is a wide-energy silicon semiconductor substrate, wherein the wide-energy silicon semiconductor substrate is a silicon carbide semiconductor substrate; The first type of highly doped semiconductor layer is a first type of highly doped silicon carbide semiconductor layer, the first type of epitaxial layer is a first type of silicon carbide epitaxial layer, the second type of epitaxial layer is a second type of silicon carbide epitaxial layer, and the first type of highly doped epitaxial layer is a first type of highly doped silicon carbide epitaxial layer. The first type is type N, while the second type is type P; The silicon carbide semiconductor substrate further includes a buffer layer that connects the first type highly doped silicon carbide semiconductor layer and the first type silicon carbide epitaxial layer; The silicon carbide semiconductor substrate further includes a bottom metal layer disposed below the first type highly doped silicon carbide semiconductor layer to serve as a second electrode of the power transistor, wherein the second electrode is a drain of the power transistor; The width of the plurality of intervals in the base of the protected area is wider the closer it is to one edge of the base of the protected area; The number and width of the complex intervals depend on the voltage rating of the power transistor. as well as Before all micro-development and etching processes, the second type silicon carbide epitaxial layer and the first type highly doped silicon carbide epitaxial layer are first disposed on the first type silicon carbide epitaxial layer to avoid or reduce subsequent high-energy carrier implantation.

9. A method for manufacturing a power transistor, comprising the following steps: A semiconductor substrate is provided, wherein the semiconductor substrate includes a first epitaxial layer and a second epitaxial layer, and the second epitaxial layer is pre-disposed on the first epitaxial layer to serve as an electronic component layer of the power transistor; and A carrier implantation procedure is performed on the second epitaxial layer to allow selected carriers to penetrate the second epitaxial layer and form at least one doped portion within the first epitaxial layer.

10. The method of claim 9, wherein: The method also includes etching the second epitaxial layer and the first epitaxial layer to form a protective environment substrate and an electronic component layer substrate having at least one trench; The at least one doped portion is at least one low-doped portion; The first epitaxial layer is a first type epitaxial layer, the second epitaxial layer includes a first type highly doped epitaxial layer and a second type epitaxial layer, and the at least one low-doped portion is a second type low-doped portion; The semiconductor substrate is a wide-energy silicon semiconductor substrate, wherein the wide-energy silicon semiconductor substrate is a silicon carbide semiconductor substrate; The first type is type N, while the second type is type P; The semiconductor substrate includes a first type highly doped semiconductor layer, a first type epitaxial layer, a second type epitaxial layer, and the first type highly doped epitaxial layer. The second type epitaxial layer is pre-disposed on the first type epitaxial layer to serve as an active channel of the power transistor, and the first type highly doped epitaxial layer is pre-disposed on the second epitaxial layer to serve as a first electrode of the power transistor. The carrier injection procedure includes the following steps: An insulating layer is formed on the first type of highly doped epitaxial layer; A metal masking layer is grown on the insulating layer, wherein the metal masking layer includes a carrier injection blocking region and a carrier injection penetration region. A first high-energy carrier is implanted into a working region of the first-type epitaxial layer through the carrier implantation penetration region to form at least one second-type low-doped portion; and Remove the metal shielding layer and the insulating layer; The method also includes the following steps: A metal seed layer having a first thickness is deposited on the insulating layer; A photoresist layer with a second thickness is deposited on the metal seed layer; A first portion of the photoresist layer is removed using a first micro-development process, leaving a second portion of the photoresist layer. A metal mask layer having the second thickness is grown on the metal seed layer using a metal electroplating method, wherein the carrier injection blocking region has the second thickness, the carrier injection penetration region has the first thickness, and the second thickness is greater than the first thickness; and Remove the second portion of the photoresist layer; The second type epitaxial layer includes a second type epitaxial portion, and the electronic component layer includes the second type epitaxial portion as an active region of the power transistor; The electronic component layer substrate includes an active cell region substrate and a protective layer substrate; The first type of highly doped semiconductor layer is a first type of highly doped silicon carbide semiconductor layer, the first type of epitaxial layer is a first type of silicon carbide epitaxial layer, the second type of epitaxial layer is a second type of silicon carbide epitaxial layer, and the first type of highly doped epitaxial layer is a first type of highly doped silicon carbide epitaxial layer. The silicon carbide semiconductor substrate further includes a buffer layer that connects the first type highly doped silicon carbide semiconductor layer and the first type silicon carbide epitaxial layer; The silicon carbide semiconductor substrate further includes a bottom metal layer disposed below the first type highly doped silicon carbide semiconductor layer to serve as a second electrode of the power transistor, wherein the second electrode is a drain of the power transistor; The width of the multiple intervals in the base of the protected area is wider the closer it is to one edge of the base of the protected area; The number and width of the complex intervals depend on the voltage rating of the power transistor. Before all micro-development and etching processes, the second type silicon carbide epitaxial layer and the first type highly doped silicon carbide epitaxial layer are first disposed on the first type silicon carbide epitaxial layer to eliminate or reduce subsequent high-energy carrier implantation. The method also includes the following steps: The first type highly doped epitaxial layer, the second type epitaxial layer, and the first type epitaxial layer are etched to form the protection zone substrate and the active cell region substrate having at least one trench; A gate insulating layer is deposited on the substrate of the protected area and the substrate of the active cell region; A polysilicon is deposited on each trench of the at least one trench to form at least one gate; A first isolation layer was deposited on the substrate of the protected area and the substrate of the active unit area; The first isolation layer, the gate insulating layer, the first type highly doped epitaxial layer, and the second type epitaxial layer are etched between the at least one trench and between the active cell region substrate and the protective zone substrate, and the first isolation layer and the gate insulating layer are etched at multiple intervals in the protective zone substrate. The first-type epitaxial layer is implanted with a second-type highly doped carrier between the at least one trench, between the active cell region substrate and the protective zone substrate, and in the plurality of spaced portions of the protective zone substrate, wherein: The second type of highly doped carrier forms a first and second type of highly doped semiconductor well in the first type epitaxial layer between at least one trench; The second type of highly doped carrier forms a second type of highly doped semiconductor well in the first type epitaxial layer between the active cell region substrate and the protective zone substrate; The second type of highly doped carrier forms a third second type of highly doped semiconductor well in the first type epitaxial layer in the complex interval portion; and A complex PN junction is formed between the second type of highly doped semiconductor well and the first type of epitaxial layer, wherein the complex PN junction is configured to buffer a high operating voltage in reverse bias. A second insulating layer is deposited on the first insulating layer and the plurality of spaced portions of the substrate of the protected area; The first isolation layer and the second isolation layer are etched on both sides of each gate of the at least one gate, exposing the first type highly doped epitaxial layer on both sides to form the first electrode, wherein: The second type epitaxial layer on both sides serves as the active channel, and the first electrode is a source electrode; and When the power transistor is off, a first junction depletion region is formed between the active channel and the first type epitaxial layer, and a second junction depletion region is formed between the at least one second type low-doped portion and the first type epitaxial layer, wherein the second junction depletion region is larger than the first junction depletion region. A connection material precursor is deposited on the active cell substrate, the protective cell substrate, and the bottom of the first type of highly doped silicon carbide layer, wherein the connection material precursor is a nickel metal; The connection material precursor is etched onto the substrate of the protected area, the connection material precursor is etched between the two gates to give it a specific thickness, and the connection material precursor with the specific thickness is sintered to form a connection material, wherein the connection material is a nickel silicide. Etch a gate contact pad to form a gate contact pad opening, and fill the gate contact pad opening with a gate wire material, wherein the gate wire material is an aluminum metal. A top metal layer is deposited on the second insulating layer of the active cell region substrate and on the interconnect material between the two gates, wherein the top metal layer serves as a source electrode pad; and A protective layer is deposited on the substrate of the protected area and a portion of the top metal layer of the substrate of the active unit area.

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