Chip aging compensation method and device, equipment and storage medium

Abstract

The invention provides a chip aging compensation method, device and equipment and a storage medium, the method is applied to a chip post-silicon test stage or a chip use stage, and the method comprises the following steps: obtaining a frequency degradation rate of a chip; and under the condition that the frequency degradation rate of the chip is greater than a preset threshold value, obtaining a target compensation voltage corresponding to the frequency degradation rate of the chip based on a corresponding relationship between the frequency degradation rate of the chip and the compensation voltage, so as to realize aging compensation of the chip through the target compensation voltage. According to the method, the effectiveness and accuracy of chip aging compensation can be improved, the hardware cost is lower, and the resource utilization rate is higher.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a chip aging compensation method, apparatus, device, and storage medium. Background Technology

[0002] Chip aging compensation typically refers to delaying or compensating for frequency degradation by adjusting the chip's operating state after it has been determined that the chip's frequency is degrading.

[0003] Current chip aging compensation schemes typically employ global derating or hardware redundancy. For example, when chip frequency degradation is detected, the overall operating voltage or frequency of the chip is reduced to prevent further performance degradation due to high-intensity operation. Alternatively, redundant CPU cores or memory blocks are incorporated into the chip, activating them when frequency degradation is detected. These aging compensation schemes either degrade overall chip performance, sacrificing the available computing power of certain modules, or result in high hardware costs and low resource utilization. Summary of the Invention

[0004] To address the aforementioned technical issues, this application provides a chip aging compensation method, apparatus, device, and storage medium, which can improve the effectiveness and accuracy of chip aging compensation, and has lower hardware costs and higher resource utilization.

[0005] The first aspect of this application provides a chip aging compensation method, which is applied in the post-silicon testing stage or the chip usage stage. The method includes: obtaining the frequency degradation rate of the chip; when the frequency degradation rate of the chip is greater than a preset threshold, obtaining a target compensation voltage corresponding to the frequency degradation rate of the chip based on the correspondence between the frequency degradation rate of the chip and the compensation voltage, so as to achieve aging compensation of the chip through the target compensation voltage.

[0006] A second aspect of this application provides a chip aging compensation apparatus, characterized in that the apparatus is used to perform aging compensation on the chip during the post-silicon testing stage or the chip usage stage, the apparatus comprising:

[0007] An aging determination unit is used to obtain the frequency degradation rate of the chip.

[0008] An aging compensation unit is used to obtain a target compensation voltage corresponding to the frequency degradation rate of the chip based on the correspondence between the frequency degradation rate of the chip and the compensation voltage when the frequency degradation rate of the chip is greater than a preset threshold, so as to achieve aging compensation of the chip through the target compensation voltage.

[0009] A third aspect of this application provides an electronic device, including: a processor and a memory; the memory is connected to the processor and is used to store a program; the processor is used to implement the above-described chip aging compensation method by running the program in the memory.

[0010] A fourth aspect of this application provides a computer-readable storage medium including a computer program that, when run by a processor, causes the processor to perform the chip aging compensation method described above.

[0011] The chip aging compensation method proposed in this application predetermines the correspondence between the chip's frequency degradation rate and the compensation voltage required to restore the chip to its initial frequency state.

[0012] Based on the aforementioned correspondence, when the frequency degradation rate of the chip is determined to be greater than a preset threshold, a target compensation voltage is determined based on the chip's frequency degradation rate and the aforementioned correspondence. This target compensation voltage is then used to compensate for the chip's aging. The above solution increases the chip's frequency through voltage compensation, thereby achieving chip aging compensation. This solution can improve chip performance during aging and has low hardware cost and high resource utilization.

[0013] Furthermore, the solution in this application pre-obtains the correspondence between the frequency degradation rate and the compensation voltage of the chip. Different chips can have their own corresponding correspondence between frequency degradation rate and compensation voltage. This allows for differentiated and personalized voltage compensation when aging compensation is performed on different chips, based on the corresponding correspondence between frequency degradation rate and compensation voltage of each chip. This enables voltage compensation to adapt to the differentiated needs of different chips, improving the effectiveness and accuracy of aging compensation.

[0014] In some implementations, the correspondence between the chip's frequency degradation rate and the compensation voltage is carried out in a lookup table. The lookup table includes the correspondence between the output value of the chip's aging sensor, the chip's frequency degradation rate, and the compensation voltage required to restore the chip to its initial frequency state. The chip's aging sensor is used to sense the chip's aging.

[0015] This implementation method carries the correspondence between the chip's frequency degradation rate and the compensation voltage in a lookup table, making the presentation of this correspondence simpler and clearer, and improving the efficiency of using this correspondence to supplement the chip voltage.

[0016] In some implementations, the query table is constructed through the following process:

[0017] The chip was placed in an aging environment to undergo accelerated aging tests.

[0018] After the chip undergoes accelerated aging testing, a voltage compensation test is performed on the chip.

[0019] Based on the voltage of the chip, the output value of the aging sensor, and the frequency of the chip obtained during the voltage compensation test, the correspondence between the output value of the aging sensor, the frequency degradation rate of the chip, and the compensation voltage required to restore the chip to its initial frequency state is determined, and the lookup table is constructed based on the determined correspondence.

[0020] This implementation method determines the correspondence between the chip's frequency degradation rate and the compensation voltage required to restore the chip to its initial frequency state through accelerated aging tests and voltage compensation tests. This correspondence is obtained with higher efficiency and accuracy.

[0021] In some implementations, obtaining the frequency degradation rate of the chip includes:

[0022] Obtain the output value of the aging sensor of the chip;

[0023] Based on the output value and the lookup table, the frequency degradation rate of the chip is determined.

[0024] This implementation method determines the chip's frequency degradation rate based on a pre-built lookup table and the output value of the aging sensor, which can improve the efficiency of determining the chip's frequency degradation rate.

[0025] In some implementations, during the accelerated aging test of the chip, the correspondence between the change in the output value of the aging sensor and the frequency degradation rate of the chip is determined based on the output value of the aging sensor and the frequency of the chip.

[0026] Obtaining the frequency degradation rate of the chip includes: obtaining the output value of the aging sensor of the chip; determining the change in the output value of the aging sensor by calculating the difference between the output value and the initial output value; wherein the initial output value is the output value of the aging sensor when the chip is in the initial frequency state; and determining the frequency degradation rate of the chip based on the change in the output value of the aging sensor and the correspondence between the change in the output value of the aging sensor and the frequency degradation rate of the chip.

[0027] This implementation quantifies the frequency change of the chip by changing the output value of the aging sensor. In other words, it determines the frequency degradation rate of the chip by using the output value of the aging sensor, which can improve the efficiency of obtaining the chip frequency degradation rate and reduce the resource consumption of obtaining the chip frequency degradation rate. Attached Figure Description

[0028] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0029] Figure 1 This is a schematic diagram of an accelerated aging test process provided in an embodiment of this application.

[0030] Figure 2 This is a flowchart illustrating a chip aging prediction method provided in an embodiment of this application.

[0031] Figure 3 This is a schematic diagram of a lookup table provided in an embodiment of this application.

[0032] Figure 4 This is a schematic flowchart of a chip aging compensation method provided in an embodiment of this application.

[0033] Figure 5 This is a schematic diagram of the structure of a chip aging prediction device provided in an embodiment of this application.

[0034] Figure 6 This is a schematic diagram of a chip aging compensation device provided in an embodiment of this application.

[0035] Figure 7 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0036] Ensuring chip reliability is one of the core challenges in the semiconductor industry, especially in critical fields such as high-performance computing, automotive electronics, aerospace, and medical devices, where the long-term stable operation of chips is crucial. Chip aging lifetime prediction is the foundation of chip reliability management. Its core objective is to predict the degree of chip aging and estimate its remaining lifespan by monitoring and analyzing key chip parameters.

[0037] Currently, the mainstream methods for predicting chip aging include prediction based on physical failure models and extrapolation methods based on circuit performance degradation.

[0038] Among these, prediction methods based on physical failure models rely on mathematical modeling of physical degradation mechanisms such as electromigration, negative bias temperature instability, and hot carrier injection, combined with SPICE simulations for lifetime estimation. However, this method faces serious challenges at advanced process nodes (such as below 7nm), where the coupling effect of multiple failure mechanisms makes it difficult for a single model to accurately describe actual degradation behavior.

[0039] Extrapolation methods based on circuit performance degradation periodically measure key circuit parameters (such as path delay, maximum frequency, and functional test pass rate) to observe their degradation trends and extrapolate to failure thresholds. While this method is simple to implement, it typically monitors only a few critical paths or modules, resulting in limited coverage and an inability to fully reflect the overall health of the chip.

[0040] Given the shortcomings of the aforementioned chip aging prediction methods, the industry has proposed inferring chip aging patterns by recording and statistically analyzing changes in chip performance over time, and then using these patterns to predict chip aging. However, these methods simply statistically analyze the changes in chip performance over time. Since the actual application scenarios of chips vary, the accuracy of current methods in predicting chip aging is not high.

[0041] To address the aforementioned technical problems, this application proposes a novel chip aging prediction method that can more comprehensively and accurately predict the frequency degradation rate of chips, thereby achieving more accurate chip aging prediction.

[0042] This application will describe the specific implementation of the chip aging prediction method proposed in this application through various different embodiments. The methods described in each embodiment can be executed on hardware devices such as computers, servers, and smart terminals. The embodiments of this application do not limit the specific execution environment of the described methods.

[0043] The technical solutions of the embodiments of this application will be described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0044] First, a general overview of the technical concepts that may be involved in the embodiments of this application is provided. It should be noted that the technical concepts described herein may appear in any embodiment of this application, and unless otherwise stated, when these technical concepts appear in subsequent embodiments of this application, their specific meanings are consistent with those described herein.

[0045] The technical concepts and their meanings that may be involved in the embodiments of this application include:

[0046] The frequency of a chip specifically refers to its clock frequency, or it can also refer to the chip's frequency or main frequency. Chip frequency is a crucial parameter for measuring chip operating speed and performance. A higher chip frequency results in faster operation and stronger performance; conversely, a lower chip frequency leads to slower operation and weaker performance.

[0047] Chip frequency degradation refers to the decrease in chip frequency. Chip frequency degradation is used to characterize chip aging and performance degradation. In this embodiment, chip frequency degradation is positively correlated with chip aging and performance degradation; that is, the greater the frequency degradation, the higher the degree of chip aging and the more severe the performance degradation. Therefore, in this embodiment, chip frequency degradation is used to quantify the degree of chip aging and performance degradation.

[0048] The frequency degradation rate of a chip refers to the rate at which its frequency degrades compared to its initial frequency. The initial frequency can refer to the chip's original manufacturing frequency or its frequency at a specific set point. The frequency degradation rate can be calculated by taking the difference between the original and initial frequencies and then dividing that difference by the original initial frequency. The frequency degradation rate can be directly used to represent the chip's aging rate or performance degradation rate.

[0049] This application first proposes a method for performing accelerated aging tests on chips and predicting chip aging based on these tests. This method induces changes in key chip parameters within a short period, simulating the chip's aging process. During the test, the correlation between changes in key chip parameters and voltage, ambient temperature, and runtime is recorded, allowing for prediction of chip aging based on this correlation. This accelerated aging test is typically performed on batches of chips to identify general aging patterns and avoid the influence of individual chip variations on the test results. In some cases, accelerated aging tests can also be performed on individual chips to observe their aging patterns.

[0050] See Figure 1 As shown in the figure, the processing procedure of the method for performing accelerated aging tests on chips and predicting chip aging based on the accelerated aging tests provided in this embodiment includes:

[0051] S101. Perform reliability simulation on the chip to determine the test conditions for accelerated aging test.

[0052] First, static timing analysis is performed on the chip. Based on the static timing analysis data, the critical paths with the minimum setup slack in the chip's integrated functions are extracted for subsequent accelerated aging tests.

[0053] Then, based on the chip application scenario, test conditions for accelerated aging tests on the chip are formulated, such as process, voltage, temperature, etc.

[0054] Secondly, aging simulation was performed on the chip according to the established test conditions. During the simulation, the values ​​of the test conditions were controlled to change, and the changes in parameters of the chip's critical path, such as changes in settling time margin and frequency, were obtained when the values ​​of the test conditions changed.

[0055] Finally, the data recorded during the simulation were analyzed to fit the relationship between the parameter changes of the chip's critical path and the changes in time, voltage, and temperature. Based on this relationship, a reliable range of test conditions for accelerated aging tests on the chip was determined.

[0056] In particular, when conducting accelerated aging tests on chips, limiting the test conditions to the aforementioned reliable range ensures that the chips will not suffer hardware damage.

[0057] Therefore, the reliability simulation of the chip described above can determine the reliability test conditions for accelerated aging tests on the chip.

[0058] S102. Set the chip in an aging environment and conduct accelerated aging tests on the chip.

[0059] First, when conducting accelerated aging tests on batches of chips, test samples are selected from the batch of chips.

[0060] Typically, when sampling chips from a batch of chips, chips from three different corners (TT, SS, and FF) are selected to cover chips produced under typical scenarios in the manufacturing process, ensuring that the test results have statistical representativeness and reliability boundaries. Following the above rules, chips are sampled from the same or multiple batches of wafers at a predetermined ratio (≥50 chips per corner) to ensure that the samples cover different wafer locations (center / edge) to reflect manufacturing uniformity.

[0061] Next, baseline data is obtained before the aging test to ensure that the initial functions and performance of the test samples meet the requirements. For example, the basic functions of the sample chip, such as logic, memory, and interfaces, are verified to be normal, and the chip frequency is tested at high temperatures (85℃~125℃) and different voltages (0.7V~1.1V). A database is established to store all test results as baseline data for subsequent aging tests and aging analysis.

[0062] Finally, according to the reliability test conditions determined in step S101 above, the chip is subjected to accelerated aging tests. For example, the chip is placed on a high-temperature aging board, a fixed aging time is set, and stress is applied to the chip within this aging time, such as applying a voltage 1.2-1.8 times the standard voltage, and / or a high-temperature ambient temperature is set, such as 85℃~125℃, to accelerate chip aging. In addition, the aging time can be set in stages, such as setting aging for 24 hours, 48 ​​hours, 96 hours, etc.

[0063] During the aforementioned aging test, key chip parameters, such as leakage current, dielectric loss, and insulation resistance, are monitored and recorded in real time. Changes in these key parameters quantify the chip's aging process.

[0064] The aforementioned accelerated aging test can be performed during the post-silicon testing stage or during the chip usage stage. It is used to discover the correspondence between the chip's key parameters and the voltage, ambient temperature, and operating time when the chip is in operation. Alternatively, it can be used to discover the correspondence between the key parameters of a specific chip and the voltage, ambient temperature, and operating time when the chip is in operation.

[0065] When performing the accelerated aging test on a batch of chips, the test conditions for the accelerated aging test can be determined through step S101, and then step S102 can be performed to select test samples and conduct aging tests on the test samples. By performing accelerated aging tests on a batch of chips, the general laws of chip aging can be discovered, thereby more accurately revealing the correspondence between chip aging and chip voltage, ambient temperature, operating time, etc.

[0066] In some other embodiments, if the accelerated aging test conditions have been determined, step S101 can be skipped and step S102 can be executed directly.

[0067] Alternatively, in other embodiments, when the accelerated aging test object has been clearly identified, such as when it is necessary to perform accelerated aging tests on one or more chips, the operation of selecting test samples can be skipped when executing step S102. Instead, the accelerated aging test can be performed directly on the chips that need to be accelerated to discover the correspondence between the key parameters of these individual chips and chip voltage, ambient temperature, running time, etc.

[0068] Therefore, the accelerated aging test described above can be used to conduct accelerated aging tests on batches of chips or individual chips, thereby enabling the discovery of the correlation between chip aging and changes in chip voltage, ambient temperature, and runtime based on the test process data. Whenever it is necessary to determine the correlation between the aging of batches of chips or individual chips and changes in chip voltage, ambient temperature, and runtime, the above-mentioned accelerated aging test can be performed on the chips.

[0069] After determining the correspondence between the chip's key parameters and chip voltage, ambient temperature, and runtime through the accelerated aging test described above, the key parameters of the chip under any voltage, temperature environment, and runtime conditions can be predicted based on this correspondence. Furthermore, the degree of chip aging can be determined based on these key parameters, thus achieving the purpose of predicting chip aging.

[0070] The chip's voltage, ambient temperature, and runtime can refer to the voltage, ambient temperature, and runtime during the chip's use after it has been put into operation. The voltage at which the chip is in its operating state can be the voltage supplying power to the chip during its use. In some embodiments, when the chip's power supply voltage is not constant during use, the average value of the power supply voltage during operation can be taken as the chip's operating voltage. The ambient temperature at which the chip is in its operating state can be the temperature of the environment in which the chip is used. In some embodiments, when the chip's operating environment is not fixed, or when the temperature of the chip's operating environment is not constant, the average temperature of the chip's operating environment can be taken as the ambient temperature at which the chip is in its operating state. The runtime at which the chip is in its operating state refers to the runtime the chip has experienced when predicting the chip's frequency degradation rate. For example, if it is necessary to predict the aging level of the chip one year after it is put into use, then the runtime at which the chip is in its operating state is one year. In other embodiments, the runtime of the chip in the working state is the effective duration of the chip in the actual operating state. For example, suppose we want to predict the aging degree of the chip one year after it is put into use, but after one year since the chip was put into use, the total cumulative running time of the chip is 500 hours, then the runtime of the chip in the working state is 500 hours.

[0071] Alternatively, the chip's voltage, ambient temperature, and runtime can also refer to the voltage, ambient temperature, and runtime of the chip when it is in operation during post-silicon testing. In other words, it refers to the voltage supplied to the chip, the temperature of the test environment, and the duration of the test when the chip is being tested.

[0072] In another embodiment of this application, a different chip aging prediction method is provided. In this method, accelerated aging tests are conducted on the chip. During the test, the chip's voltage, ambient temperature, and operating time are adjusted, and changes in key chip parameters and frequency are monitored to determine the correlation between chip frequency degradation and chip voltage, ambient temperature, operating time, etc. Based on this correlation, the chip's frequency degradation rate can be predicted, thereby achieving the purpose of predicting chip aging or chip performance degradation.

[0073] In this embodiment, the chip is first subjected to an accelerated aging test. The specific aging test process can be referred to Figure 1 Steps S101 and S102 in the illustrated embodiment are performed. Changes in key chip parameters are recorded during the aging process.

[0074] After completing the accelerated aging of the chip, this embodiment also performs frequency testing on the accelerated-aged chip. For example, after the chip is placed on a high-temperature aging board for accelerated aging according to the processing method described in step S102 above, the accelerated-aged chip is then placed on a frequency test bench to test its frequency. The change between the measured frequency of the chip and its initial frequency is then calculated to determine the frequency degradation rate of the chip after accelerated aging. The voltage applied to the chip during frequency testing is called the test voltage.

[0075] Following the above process, accelerated aging and frequency testing are performed on the tested chips. By analyzing the monitoring data from each chip's testing process, the correlation between the chip's frequency degradation rate and its voltage, ambient temperature, and operating time can be determined. For example, during accelerated aging, keeping the ambient temperature and operating time constant while changing only the voltage, and testing the frequency degradation rate after applying different voltages, the relationship between the chip's frequency degradation rate and its voltage can be determined. Similarly, during accelerated aging, keeping the chip's voltage and operating time constant while changing only the ambient temperature, and testing the frequency degradation rate after accelerated aging at different ambient temperatures, the relationship between the chip's frequency degradation rate and its operating ambient temperature can be determined. Furthermore, during accelerated aging, keeping the chip's voltage and ambient temperature constant while changing only the operating time, and testing the frequency degradation rate after accelerated aging for different operating times, the relationship between the chip's frequency degradation rate and its operating time can be determined.

[0076] Specifically, the above processing revealed that the chip's frequency degradation rate and chip voltage satisfy a power-law relationship, as shown in Formula 1 below:

[0077] ΔRatio f =V m (Formula 1)

[0078] Where, ΔRatio f V represents the frequency degradation rate of the chip; V represents the voltage of the chip when it is in operation; m is a constant whose value may vary depending on the chip's process, performance and design. Usually, its value is a range, such as 4 to 18.

[0079] The frequency degradation rate of a chip and its runtime follow a power-law relationship, specifically as shown in Formula 2 below:

[0080] ΔRatio f =t n (Formula 2)

[0081] Where, ΔRatio f The frequency degradation rate of the chip is represented by t; the runtime is represented by n; and n is a constant whose value may vary depending on the chip's process, performance, and design. Typically, its value is within a range, such as 0.15 to 0.8.

[0082] The relationship between the chip's frequency degradation rate and the chip's ambient temperature satisfies the Arrhenius equation, specifically the relationship shown in Formula 3 below:

[0083]

[0084] Where, ΔRatio f Indicates the chip's frequency degradation rate; T represents the ambient temperature; E represents the frequency degradation rate. a This represents the activation energy of the chip, specifically the activation energy of the materials used to manufacture the chip; k is the Boltzmann constant.

[0085] Through the accelerated aging test process of the chip in this embodiment, it can be found that the frequency degradation of the chip is related to the voltage, ambient temperature and running time when the chip is in operation. Therefore, changes in these factors will lead to the frequency degradation of the chip, that is, chip aging and chip performance degradation.

[0086] Combining Formulas 1, 2, and 3 above, it can be determined that the chip's frequency degradation rate is affected by the chip's voltage, ambient temperature, and operating time. Therefore, the relationship between the chip's frequency degradation rate and these factors is shown in Formula 4.

[0087]

[0088] Based on Formula 4 above, the frequency degradation rate of the chip can be predicted. For example, after determining the voltage, ambient temperature, and operating time of the chip when it is in operation, the frequency degradation rate of the chip can be calculated according to the calculation method of Formula 4 above.

[0089] When implementing the chip aging prediction method provided in this embodiment, the accelerated aging test method described in this embodiment can be followed first. By conducting accelerated aging tests on the chip, the correlation between the chip's frequency degradation rate and the chip's voltage, ambient temperature, and operating time can be determined. This yields the correlation between the chip's frequency degradation rate and the chip's voltage, ambient temperature, and operating time shown in Formula 4 above. After obtaining the chip's voltage, ambient temperature, and operating time, the chip's frequency degradation rate can be predicted based on the correlation between the chip's frequency degradation rate and the chip's voltage, ambient temperature, and operating time shown in Formula 4. This predicts the degree of chip aging and performance degradation.

[0090] The chip's voltage, ambient temperature, and runtime can refer to the voltage, ambient temperature, and runtime during the chip's use after it has been put into operation. The voltage at which the chip is in its operating state can be the voltage supplying power to the chip during its use. In some embodiments, when the chip's power supply voltage is not constant during use, the average value of the power supply voltage during operation can be taken as the chip's operating voltage. The ambient temperature at which the chip is in its operating state can be the temperature of the environment in which the chip is used. In some embodiments, when the chip's operating environment is not fixed, or when the temperature of the chip's operating environment is not constant, the average temperature of the chip's operating environment can be taken as the ambient temperature at which the chip is in its operating state. The runtime at which the chip is in its operating state refers to the runtime the chip has experienced when predicting the chip's frequency degradation rate. For example, if it is necessary to predict the aging level of the chip one year after it is put into use, then the runtime at which the chip is in its operating state is one year. In other embodiments, the runtime of the chip in the working state is the effective duration of the chip in the actual operating state. For example, suppose we want to predict the aging degree of the chip one year after it is put into use, but after one year since the chip was put into use, the total cumulative running time of the chip is 500 hours, then the runtime of the chip in the working state is 500 hours.

[0091] Alternatively, the chip's voltage, ambient temperature, and runtime can also refer to the voltage, ambient temperature, and runtime of the chip when it is in operation during post-silicon testing. In other words, it refers to the voltage supplied to the chip, the temperature of the test environment, and the duration of the test when the chip is being tested.

[0092] The chip aging prediction method provided in this embodiment discovers the comprehensive correlation between the chip's frequency degradation rate and the chip's voltage, ambient temperature, and operating time. Based on this correlation, the chip's frequency degradation rate can be predicted comprehensively based on the chip's voltage, ambient temperature, and operating time when it is in operation, thereby achieving a more accurate prediction of chip aging.

[0093] In another embodiment, a different method for predicting chip aging is provided. This method involves conducting accelerated aging tests on the chip, adjusting the chip's voltage, ambient temperature, and operating time during the test, and monitoring changes in key chip parameters and frequency during the test to determine the correlation between chip frequency degradation and chip voltage, ambient temperature, and operating time. Based on this correlation, the chip's frequency degradation rate can be predicted, thereby achieving the purpose of predicting chip aging.

[0094] The specific implementation process of performing accelerated aging tests on the chip, monitoring changes in key chip parameters and frequency during the test, and determining the correlation between chip frequency degradation and chip voltage, ambient temperature, and runtime as described in the above embodiments can be found in the above embodiments. Furthermore, the correlation between chip frequency degradation and chip voltage, ambient temperature, and runtime obtained through the above accelerated aging tests can also be found in Formula 4 of the above embodiments. These details will not be repeated in this embodiment.

[0095] In the process of determining the correlation between chip frequency degradation and chip voltage, ambient temperature, and operating time through accelerated aging tests, the inventors of this application discovered that when testing the chip frequency, different test voltages applied to the chip result in changes in the measured chip frequency. This leads to variations in the calculated frequency degradation rate after accelerated aging based on the measured chip frequency. In other words, the test voltage applied during accelerated aging testing affects the accuracy of the measured frequency degradation rate. Therefore, when determining the correlation between chip frequency degradation rate and chip voltage, ambient temperature, and operating time through accelerated aging and testing of the accelerated-aged chip's frequency degradation rate, the influence of the test voltage must be considered to ensure a more accurate final correlation between the chip frequency degradation rate and these factors.

[0096] Based on the above findings, in the chip aging prediction method provided in this embodiment, the following processes (S201 to S203) are used to determine the influence of the test voltage at the test chip frequency on determining the correlation between the chip frequency degradation rate and chip voltage, ambient temperature, and operating time:

[0097] S201. Set the chip in an aging environment and conduct an accelerated aging test on the chip.

[0098] Specifically, before executing step S201, the test conditions for the accelerated aging test can be determined by referring to the process of step S101 in the above embodiment. Then, in step S201, the chip is subjected to an accelerated aging test according to the determined test conditions.

[0099] The processing procedure for step S201 can be found in [reference needed]. Figure 1 The processing procedure of step S102 in the illustrated embodiment. During this accelerated aging test, stress voltage, stress environment temperature, and stress running time are applied to the chip, and changes in key chip parameters are monitored during the test.

[0100] S202. After performing accelerated aging tests on the chip, different test voltages are applied to the chip to test its frequency, and the frequency degradation rate of the chip measured under different test voltages is obtained.

[0101] Specifically, after accelerated aging of the chip, it is placed on a frequency test bench, a test voltage is applied, and its frequency is measured. During this process, different test voltages are applied to the same chip, and the chip's frequency is measured at each voltage. The frequency degradation rate of the chip under different test voltages is then calculated. Thus, for the same chip, a set of statistical data on its frequency degradation rate under different test voltages can be obtained.

[0102] By performing the above operation on multiple chips, statistical data on the frequency degradation rate of each group of chips under different test voltages can be obtained.

[0103] S203. Based on the frequency degradation rate of the chip measured under different test voltages, determine the formula for calculating the frequency degradation rate trend influence factor.

[0104] Specifically, based on the frequency degradation rate of the chip measured under different test voltages obtained in step S202, the influence of the test voltage on the frequency degradation rate of the chip can be determined. This influence is equivalent to the influence of the test voltage on the relationship between the frequency degradation rate of the chip and the chip voltage, ambient temperature, and operating time.

[0105] In this embodiment, the influence of test voltage on determining the frequency degradation rate of a chip is represented by a frequency degradation rate trend influence factor. Since there is a corresponding relationship between the chip's frequency degradation rate and the chip's voltage, ambient temperature, and operating time, this frequency degradation rate trend influence factor can also represent the influence of test voltage on determining the frequency degradation rate of a chip and the corresponding relationship between chip voltage, ambient temperature, and operating time.

[0106] Assuming the frequency degradation rate trend influencing factor mentioned above is denoted as P, the impact of the frequency degradation rate trend influencing factor on the relationship between the chip's frequency degradation rate and chip voltage, ambient temperature, and operating time can be expressed as shown in Formula 5 below:

[0107]

[0108] It is understandable that when determining the frequency degradation rate of a chip by testing its frequency, the obtained frequency degradation rate is actually the frequency degradation rate after being affected by the test voltage. In other words, the chip frequency degradation rate obtained in step S202 is measured under the influence of the test voltage. Under the same accelerated aging operation (chip voltage, ambient temperature, and operating time remain constant), the change in frequency degradation rate is caused solely by the test voltage.

[0109] This embodiment obtains the frequency degradation rate of the chip measured under different test voltages through the processing described in steps S201 and S202. By statistically analyzing these data, the relationship between the frequency degradation rate trend influence factor and the test voltage can be determined. In this embodiment, the relationship between the frequency degradation rate trend influence factor and the test voltage is expressed by a formula for calculating the frequency degradation rate trend influence factor. In this formula, the test voltage used to test the chip's frequency is the independent variable, and the frequency degradation rate trend influence factor is the dependent variable. This formula can be used to calculate the frequency degradation rate trend influence factor corresponding to the test voltage when testing the chip's frequency.

[0110] In some embodiments, through the processing in step S203, the frequency degradation rate of the chip measured under different test voltages is statistically analyzed to obtain the calculation formula for the frequency degradation rate trend influence factor as shown in Formula Six:

[0111] P = exp(-αV) measure (Formula Six)

[0112] Where P represents the frequency degradation rate trend influencing factor, V measure This represents the test voltage, and α is a coefficient.

[0113] Substituting the above formula for calculating the frequency degradation rate trend influence factor into Formula 5 above, we can obtain the frequency degradation rate prediction formula. Since the frequency degradation rate prediction formula quantifies the influence of the test voltage on the correlation between the chip's frequency degradation rate and chip voltage, ambient temperature, and operating time, the correlation between the chip's frequency degradation rate and chip voltage, ambient temperature, and operating time reflected by the frequency degradation rate prediction formula is more accurate.

[0114] Therefore, based on this frequency degradation rate prediction formula, the frequency degradation rate of the chip can be calculated, which is to predict the degree of chip aging, by obtaining the voltage, ambient temperature and operating time of the chip when it is in operation.

[0115] The voltage, ambient temperature, and runtime of the chip during its operating state can refer to the voltage, ambient temperature, and runtime during its use after the chip is put into use. In this case, the voltage at which the chip is in its operating state can be the voltage supplying power to the chip during its use. In some embodiments, when the chip's power supply voltage is not constant during use, the average value of the power supply voltage during operation can be taken as the voltage at which the chip is in its operating state. The ambient temperature at which the chip is in its operating state can be the temperature of the environment in which the chip is used. In some embodiments, when the chip's operating environment is not fixed, or when the temperature of the chip's operating environment is not constant, the average value of the temperature of the chip's operating environment can be taken as the ambient temperature at which the chip is in its operating state. The runtime at which the chip is in its operating state refers to the runtime the chip has experienced when predicting the chip's frequency degradation rate. For example, assuming it is necessary to predict the aging level of the chip one year after it is put into use, then the runtime at which the chip is in its operating state is one year. In other embodiments, the runtime of the chip in the working state is the effective duration of the chip in the actual operating state. For example, suppose we want to predict the aging degree of the chip one year after it is put into use, but after one year since the chip was put into use, the total cumulative running time of the chip is 500 hours, then the runtime of the chip in the working state is 500 hours.

[0116] Alternatively, the voltage, ambient temperature, and runtime of the chip when it is in operation can also refer to the voltage, ambient temperature, and runtime of the chip when it is in operation during post-silicon testing. In other words, it refers to the voltage that supplies power to the chip, the temperature of the test environment, and the duration of the test when the chip is being tested.

[0117] Because this embodiment considers and quantifies the influence of the test voltage on the determination of the relationship between the chip frequency degradation rate and chip voltage, ambient temperature, and operating time when determining the relationship between the chip frequency degradation rate and chip voltage, ambient temperature, and operating time, the determined relationship between the chip frequency degradation rate and chip voltage, ambient temperature, and operating time is more accurate, and thus more accurate chip aging prediction can be achieved based on this relationship.

[0118] Another embodiment of this application provides a different chip aging prediction method. This method involves conducting accelerated aging tests on the chip, adjusting the chip's voltage, ambient temperature, and operating time during the test, and monitoring changes in key chip parameters during the test. For specific processing steps, please refer to the above embodiments, such as step S201 in the above embodiments. These details will not be repeated in this embodiment.

[0119] After performing the accelerated aging test on the chip as described above, this embodiment further applies different test voltages to the accelerated-aged chip to test its frequency by executing step S202 in the above embodiment, and obtains the frequency degradation rate of the chip measured under different test voltages. For a detailed description of the process, please refer to step S202 in the above embodiment.

[0120] In the process of testing the frequency degradation rate of a chip under different test voltages according to the processing method described in step S202 of the above embodiments, the inventors of this application discovered that not only changes in the test voltage cause changes in the measured chip frequency degradation rate, but also changes in the measured chip frequency when the chip manufacturing process nanometer scale changes while the test voltage remains constant. Thus, it can be seen that both the test voltage and the chip manufacturing process nanometer scale affect the frequency of the tested chip, that is, the test voltage and the chip manufacturing process nanometer scale affect the calculation of the frequency degradation rate trend influence factor.

[0121] Based on the above analysis, the chip aging prediction method provided in this embodiment includes the following steps:

[0122] S301. Multiple chips with different nanometer scales in manufacturing processes are placed in an aging environment to conduct accelerated aging tests on the chips.

[0123] Specifically, the processing in step S301 can be performed with reference to step S201 in the above embodiment, that is, according to the processing method described in step S201 in the above embodiment, accelerated aging tests are performed on multiple chips with different nanometer scales in the manufacturing process.

[0124] S302. After conducting accelerated aging tests on multiple chips with different nanometer-scale manufacturing processes, different test voltages are applied to the multiple chips with different nanometer-scale manufacturing processes to test the chip frequency, and the frequency degradation rate of the multiple chips with different nanometer-scale manufacturing processes measured under different test voltages is obtained.

[0125] Specifically, the processing in step S302 can be performed with reference to step S202 in the above embodiment. That is, for chips with different manufacturing processes and nanometer scales, the frequency degradation rate of the chips is tested under different test voltages according to the processing method described in step S202 in the above embodiment. This yields the frequency degradation rate data of chips with different manufacturing processes and nanometer scales measured under different test voltages under the same accelerated aging operation (with chip voltage, ambient temperature, and running time remaining unchanged).

[0126] S303. Based on the frequency degradation rate of multiple chips with different nanometer scales of the manufacturing process measured under different test voltages, determine the calculation formula for the frequency degradation rate trend influence factor.

[0127] Specifically, in this embodiment, the influence of test voltage and manufacturing process nanometer scale on determining the frequency degradation rate of the chip is represented by the frequency degradation rate trend influence factor. Since the frequency degradation rate of the chip has a corresponding relationship with the chip voltage, ambient temperature, and operating time, the frequency degradation rate trend influence factor can also represent the influence of test voltage and manufacturing process nanometer scale on determining the frequency degradation rate of the chip and the corresponding relationship between chip voltage, ambient temperature, and operating time.

[0128] Referring to the processing method of step S203 in the above embodiment, by statistically analyzing the frequency degradation rate data of multiple chips with different manufacturing process nanometer scales measured under different test voltages in step S302, the relationship between the above-mentioned frequency degradation rate trend influencing factor and the test voltage and manufacturing process nanometer scale can be determined.

[0129] In this embodiment, the relationship between the frequency degradation rate trend influence factor and the test voltage and the nanometer scale of the manufacturing process is represented by a formula for calculating the frequency degradation rate trend influence factor. In this formula, the test voltage used for frequency testing of the chip and the nanometer scale of the chip's manufacturing process are used as independent variables, and the frequency degradation rate trend influence factor is the dependent variable. This formula can be used to calculate the corresponding frequency degradation rate trend influence factor based on the test voltage and the nanometer scale of the chip's manufacturing process when testing the chip's frequency.

[0130] In some embodiments, through the processing in step S303, the frequency degradation rate data of multiple chips with different nanometer scales in the manufacturing process, measured under different test voltages, are statistically analyzed to obtain the calculation formula for the frequency degradation rate trend influence factor as shown in Formula 7:

[0131] P=A*exp(-αV measure (Formula 7)

[0132] Where P represents the frequency degradation rate trend influencing factor, A is used to characterize the impact of the chip manufacturing process nanometer scale on the frequency degradation rate trend influencing factor, and V... measure This represents the test voltage, and α is a coefficient.

[0133] In other embodiments, substituting the above-described formula for calculating the frequency degradation rate trend influence factor into Formula 5 yields the frequency degradation rate prediction formula shown in Formula 8 below:

[0134]

[0135] Where, ΔRatio f A represents the frequency degradation rate; A characterizes the impact of the chip's manufacturing process nanometer scale on the frequency degradation rate trend; V measure The values ​​represent the test voltage, α is a coefficient, V represents the voltage, m is a constant whose value may vary depending on the chip's process, performance, and design; typically, it falls within a range, such as 4–18; T represents the ambient temperature; E a The activation energy of the chip is represented by k, which specifically refers to the activation energy of the material used to manufacture the chip; k is the Boltzmann constant; t represents the running time; n is a constant whose value may vary depending on the chip's process, performance, and design. Typically, its value is within a range, such as 0.15 to 0.8.

[0136] Because the frequency degradation rate prediction formula quantifies the influence of the test voltage and the nanometer scale of the chip manufacturing process on the relationship between the chip frequency degradation rate and the chip voltage, ambient temperature, and operating time, the relationship between the chip frequency degradation rate and the chip voltage, ambient temperature, and operating time reflected by the frequency degradation rate prediction formula is more accurate.

[0137] Therefore, based on the frequency degradation rate prediction formula determined in this embodiment, the frequency degradation rate of the chip can be calculated, i.e., the degree of chip aging, by obtaining the voltage, ambient temperature and operating time of the chip when it is in operation.

[0138] The voltage, ambient temperature, and runtime of the chip during its operating state can refer to the voltage, ambient temperature, and runtime during its use after the chip is put into use. In this case, the voltage at which the chip is in its operating state can be the voltage supplying power to the chip during its use. In some embodiments, when the chip's power supply voltage is not constant during use, the average value of the power supply voltage during operation can be taken as the voltage at which the chip is in its operating state. The ambient temperature at which the chip is in its operating state can be the temperature of the environment in which the chip is used. In some embodiments, when the chip's operating environment is not fixed, or when the temperature of the chip's operating environment is not constant, the average value of the temperature of the chip's operating environment can be taken as the ambient temperature at which the chip is in its operating state. The runtime at which the chip is in its operating state refers to the runtime the chip has experienced when predicting the chip's frequency degradation rate. For example, assuming it is necessary to predict the aging level of the chip one year after it is put into use, then the runtime at which the chip is in its operating state is one year. In other embodiments, the runtime of the chip in the working state is the effective duration of the chip in the actual operating state. For example, suppose we want to predict the aging degree of the chip one year after it is put into use, but after one year since the chip was put into use, the total cumulative running time of the chip is 500 hours, then the runtime of the chip in the working state is 500 hours.

[0139] Alternatively, the voltage, ambient temperature, and runtime of the chip when it is in operation can also refer to the voltage, ambient temperature, and runtime of the chip when it is in operation during post-silicon testing. In other words, it refers to the voltage that supplies power to the chip, the temperature of the test environment, and the duration of the test when the chip is being tested.

[0140] Because this embodiment considers and quantifies the influence of test voltage and the nanometer scale of chip manufacturing process on the determination of the correlation between chip frequency degradation rate and chip voltage, ambient temperature and operating time when determining the correlation between chip frequency degradation rate and chip voltage, ambient temperature and operating time, the determined correlation between chip frequency degradation rate and chip voltage, ambient temperature and operating time is more accurate, and thus more accurate chip aging prediction can be achieved based on this correlation.

[0141] In some embodiments, another chip aging prediction method is provided. This method first determines the correspondence between the chip's frequency degradation rate and the voltage, ambient temperature, and operating time of the chip during operation, according to the method described in any of the above embodiments. Then, based on the correspondence between the chip's frequency degradation rate and the voltage, ambient temperature, and operating time of the chip during operation, the chip's frequency degradation rate is predicted, thereby achieving the purpose of predicting chip aging.

[0142] As a preferred embodiment, this embodiment, when determining the correspondence between the chip's frequency degradation rate and the voltage, ambient temperature, and operating time of the chip in its operating state, refers to the processing procedure described in steps S301 to S303 of the above embodiment. That is, by setting different aging conditions (setting different voltages, ambient temperatures, and operating times), accelerated aging tests are conducted on multiple chips with different manufacturing process nanometer scales. The frequencies of multiple chips with different manufacturing process nanometer scales after accelerated aging are tested under different test voltages to discover the correspondence between the chip's voltage, ambient temperature, and operating time and the chip's frequency degradation rate. At the same time, the influence of the chip's manufacturing process nanometer scale and the test voltage when testing the chip's frequency is discovered on determining the correspondence between the chip's voltage, ambient temperature, and operating time and the chip's frequency degradation rate. Finally, the frequency degradation rate prediction formula shown in Formula 8 above is obtained.

[0143] Referring to the description of the above embodiments, the frequency degradation rate prediction formula shown in Formula 8 not only quantifies the correspondence between the chip's operating voltage, ambient temperature, and operating time and the chip's frequency degradation rate, but also quantifies the influence of the test voltage when testing the chip's frequency on determining the correspondence between the chip's operating voltage, ambient temperature, and operating time and the chip's frequency degradation rate. This allows the frequency degradation rate prediction formula to more accurately quantify the correspondence between the chip's operating voltage, ambient temperature, and operating time and the chip's frequency degradation rate.

[0144] Based on the above correspondence, the chip aging prediction method proposed in this embodiment can predict the frequency degradation rate of any chip during the post-silicon testing stage or the chip usage stage, thereby determining the degree of chip aging. This method is executed after determining the correspondence between the chip's operating voltage, ambient temperature, and operating time and the chip's frequency degradation rate through the above processing. Furthermore, this method is also applicable to any of the above embodiments; that is, in any of the above embodiments, after determining the correspondence between the chip's operating voltage, ambient temperature, and operating time and the chip's frequency degradation rate, the chip's frequency degradation rate can be predicted by referring to the chip aging prediction steps provided in this embodiment.

[0145] See Figure 2 As shown, the chip aging prediction method provided in this embodiment predicts chip aging by performing the following steps S401 to S402:

[0146] S401. Obtain the voltage, ambient temperature, operating time, and frequency degradation rate trend influencing factors of the chip when it is in operation.

[0147] The voltage, ambient temperature, and runtime of the chip during its operating state can refer to the voltage, ambient temperature, and runtime during its use after the chip is put into use. In this case, the voltage at which the chip is in its operating state can be the voltage supplying power to the chip during its use. In some embodiments, when the chip's power supply voltage is not constant during use, the average value of the power supply voltage during operation can be taken as the voltage at which the chip is in its operating state. The ambient temperature at which the chip is in its operating state can be the temperature of the environment in which the chip is used. In some embodiments, when the chip's operating environment is not fixed, or when the temperature of the chip's operating environment is not constant, the average value of the temperature of the chip's operating environment can be taken as the ambient temperature at which the chip is in its operating state. The runtime at which the chip is in its operating state refers to the runtime the chip has experienced when predicting the chip's frequency degradation rate. For example, assuming it is necessary to predict the aging level of the chip one year after it is put into use, then the runtime at which the chip is in its operating state is one year. In other embodiments, the runtime of the chip in the working state is the effective duration of the chip in the actual operating state. For example, suppose we want to predict the aging degree of the chip one year after it is put into use, but after one year since the chip was put into use, the total cumulative running time of the chip is 500 hours, then the runtime of the chip in the working state is 500 hours.

[0148] Alternatively, the voltage, ambient temperature, and runtime of the chip when it is in operation can also refer to the voltage, ambient temperature, and runtime of the chip when it is in operation during post-silicon testing. In other words, it refers to the voltage that supplies power to the chip, the temperature of the test environment, and the duration of the test when the chip is being tested.

[0149] Referring to the description of the above embodiments, the aforementioned frequency degradation rate trend influence factor is obtained by quantifying the influence of the test voltage when testing the chip's frequency on the determination of the correspondence between the chip's operating voltage, ambient temperature, and operating time and the chip's frequency degradation rate. This frequency degradation rate trend influence factor is related to the test voltage obtained when testing the chip's frequency. In determining the correspondence between the chip's operating voltage, ambient temperature, and operating time and the chip's frequency degradation rate, different test voltages obtained when testing the chip's frequency result in different frequency degradation rate trend influence factors, and the resulting correspondence between the chip's operating voltage, ambient temperature, and operating time and the chip's frequency degradation rate will also differ. Referring to Formula 5 in the above embodiments, this difference in correspondence is caused by changes in the frequency degradation rate trend influence factor P.

[0150] Therefore, when predicting chip aging based on the correlation between the chip's operating voltage, ambient temperature, and operating time and the chip's frequency degradation rate, the frequency degradation rate trend influencing factor should be determined first. Then, based on the correlation between the chip's operating voltage, ambient temperature, and operating time and the chip's frequency degradation rate determined under the influence of this frequency degradation rate trend influencing factor, the chip's frequency degradation rate can be predicted.

[0151] In determining the correspondence between the chip's operating voltage, ambient temperature, and operating time and the chip's frequency degradation rate according to the above embodiments, the frequency degradation rate trend influence factor can also be determined when the test voltage for testing the chip's frequency is determined. For example, referring to the above embodiments, the frequency degradation rate trend influence factor can be calculated based on the test voltage obtained when testing the chip's frequency using the frequency degradation rate trend influence factor calculation formula shown in Formula Six or Formula Seven of the above embodiments. When calculating the frequency degradation rate trend influence factor using the formula shown in Formula Seven, it is also necessary to determine the chip's manufacturing process nanometer scale.

[0152] S402. Based on the voltage, the ambient temperature, the operating time, and the frequency degradation rate trend influencing factor, determine the frequency degradation rate of the chip.

[0153] Specifically, after obtaining the voltage, ambient temperature, operating time, and frequency degradation rate trend influencing factor of the chip in its working state, the frequency degradation rate of the chip can be determined according to the correspondence between the voltage, ambient temperature, operating time and frequency degradation rate of the chip in its working state determined under the influence of the frequency degradation rate trend influencing factor.

[0154] For example, firstly, determine the correspondence between the chip's operating voltage, ambient temperature, and operating time under the influence of the acquired frequency degradation rate trend influencing factor, and the chip's frequency degradation rate. Then, substitute the acquired chip operating voltage, ambient temperature, and operating time into this correspondence to determine the corresponding frequency degradation rate.

[0155] In some embodiments, the frequency degradation rate prediction formula shown in Formula 8 of the above embodiments is used to represent the correspondence between the chip's operating voltage, ambient temperature, operating time, and the chip's frequency degradation rate, determined under the influence of the frequency degradation rate trend influencing factor. Specifically, in Formula 8, A*exp(-αV measure This indicates the influence factor on the frequency degradation rate trend.

[0156] Based on this, the voltage, ambient temperature, running time, and frequency degradation rate trend influencing factor of the chip in operation obtained in step S401 are substituted into Formula 8 above to calculate the frequency degradation rate of the chip.

[0157] It is understood that the chip aging prediction method provided in this embodiment, when determining the correlation between the chip's frequency degradation rate and chip voltage, ambient temperature, and operating time, considers and quantifies the influence of the test voltage during chip frequency testing and the nanometer scale of the chip's manufacturing process on the determination of this correlation, and represents this influence through a frequency degradation rate trend influence factor. The introduction of this frequency degradation rate trend influence factor makes the determined correlation between the chip's frequency degradation rate and chip voltage, ambient temperature, and operating time more accurate.

[0158] Based on this, when predicting chip aging, the voltage, ambient temperature, operating time, and frequency degradation rate trend influencing factor of the chip in its working state are obtained. Then, based on the obtained voltage, ambient temperature, operating time, and frequency degradation rate trend influencing factor, and combined with the correspondence between the chip frequency degradation rate determined under the influence of the frequency degradation rate trend influencing factor and the voltage, ambient temperature, and operating time of the chip in its working state, the frequency degradation rate of the chip can be determined.

[0159] Because this method obtains the frequency degradation rate trend influence factor when predicting the chip's frequency degradation rate and uses it to predict the chip's frequency degradation rate, this method fully considers the influence of the frequency degradation rate trend influence factor on determining the chip's frequency degradation rate, thereby improving the accuracy of chip aging prediction.

[0160] Another embodiment of this application provides a different chip aging prediction method, the method comprising:

[0161] S501. By conducting accelerated aging tests on the chip, the correlation between the voltage, ambient temperature, and operating time of the chip in its working state and the frequency degradation rate of the chip is determined.

[0162] Specifically, step S501 can uncover the correlation between the voltage, ambient temperature, and operating time of the chip in its working state and the chip's frequency degradation rate. This correlation can be expressed by the frequency degradation rate calculation formula.

[0163] The processing of step S501 can be performed by referring to the process of determining the correspondence between the voltage, ambient temperature and running time of the chip in the working state and the frequency degradation rate of the chip in the chip aging prediction method described in any of the above embodiments, and will not be repeated here.

[0164] S502: Obtain the frequency degradation rate corresponding to each of the multiple chips.

[0165] Specifically, step S502 can be executed with reference to the processing procedure in the chip aging prediction method described in the above embodiments, thereby determining the frequency degradation rate of each of the multiple chips. For example, the frequency degradation rate corresponding to each of the multiple chips can be obtained according to the processing procedure shown in steps S401 and S402 in the above embodiments. That is, firstly, the voltage, ambient temperature, running time, and frequency degradation rate trend influencing factor of each of the multiple chips in their operating state are obtained. Then, for each chip, based on the voltage, ambient temperature, running time, and frequency degradation rate trend influencing factor of the chip in its operating state, the frequency degradation rate of the chip is determined according to the processing procedure shown in step S402 in the above embodiments.

[0166] S503. Based on the frequency degradation rate corresponding to each of the multiple chips, select chips from the multiple chips whose frequency degradation rate is less than the target frequency degradation rate; or, determine the frequency of each of the multiple chips based on the frequency degradation rate corresponding to each of the multiple chips, and select chips from the multiple chips whose frequency is greater than the target frequency.

[0167] Specifically, after obtaining the frequency degradation rates of multiple chips, these chips can be screened based on their respective frequency degradation rates to select qualified chips that meet the performance standards. For example, based on the frequency degradation rates of multiple chips, chips with frequency degradation rates lower than the target frequency degradation rate can be selected. As described in the previous example, the frequency degradation rate of a chip is positively correlated with chip aging and chip performance degradation. If the frequency degradation rate of a chip is lower than the target frequency degradation rate, it means that the chip's aging degree after accelerated aging testing is lower than the aging degree corresponding to the target frequency degradation rate, and its performance degradation is less. In this case, the chip's performance can be considered to meet the standards, and therefore, chips with frequency degradation rates lower than the target frequency degradation rate can be considered qualified chips.

[0168] If a chip's frequency degradation rate is not less than the target frequency degradation rate, it indicates that the chip's aging degree after accelerated aging testing is higher than the aging degree corresponding to the target frequency degradation rate, and its performance degradation is more severe. In this case, the chip's performance can be considered substandard. Therefore, chips with a frequency degradation rate not less than the target frequency degradation rate can be considered unqualified chips or chips that need to be eliminated or optimized. The aforementioned target frequency degradation rate can be set based on a chip performance threshold. For example, when the chip's frequency degradation rate reaches a certain threshold, the chip frequency is too low, causing its performance to fail to meet the performance threshold. This frequency degradation rate threshold is then determined as the target frequency degradation rate. Specifically, the target frequency degradation rate can be a specific value, such as 3%, 4%, etc.

[0169] Alternatively, after obtaining the frequency degradation rates for each of the multiple chips, the individual frequencies of the chips can be calculated based on these rates. For example, the degraded frequencies of the chips can be determined by calculating their initial frequencies and corresponding degradation rates. Then, the chips are screened based on their individual frequencies to select those that meet the performance standards. For instance, chips with frequencies higher than the target frequency can be selected. As described in the previous examples, chip frequency is positively correlated with chip performance. A chip with a frequency higher than the target frequency indicates that its performance after accelerated aging testing has reached the target performance level. In this case, the chip's performance can be considered satisfactory, and chips with frequencies higher than the target frequency can be considered qualified chips.

[0170] If a chip's frequency is not greater than the target frequency, it indicates that the chip's performance after accelerated aging testing does not reach the target performance level. In this case, the chip's performance can be considered substandard, and chips with frequencies not exceeding the target frequency can be considered unqualified or require elimination or optimization. The aforementioned target frequency can be set based on a chip performance threshold. For example, if the chip's frequency is lower than a certain frequency threshold, its performance is considered to be below that threshold, and this frequency threshold is then determined as the target frequency. This target frequency can specifically be a certain frequency value, such as 2GHz, 2.3GHz, etc.

[0171] Based on the above operations, the method provided in this embodiment can effectively perform chip quality inspection and performance screening during chip mass production. Specifically, before chips leave the factory, the frequency degradation rate of the chips is predicted over a certain period. Chips with a frequency degradation rate less than the target frequency degradation rate or a frequency greater than the target frequency are selected as qualified chips that meet performance standards and can be shipped for use. Chips with a frequency degradation rate not less than the target frequency degradation rate or a frequency not greater than the target frequency are considered unqualified chips and should be prohibited from leaving the factory. Therefore, this method can provide a basis for chip screening during chip mass production, which is beneficial for improving the yield rate of mass-produced chips.

[0172] The target frequency degradation rate mentioned above can be a pre-set frequency degradation rate, such as a frequency degradation rate set according to a set performance screening standard, such as a frequency degradation rate of 2% or 3%.

[0173] Alternatively, in some embodiments, the target frequency degradation rate can be determined based on the frequency degradation rates of multiple chips. Specifically, since chips manufactured using different processes or with different designs have varying performance and stability, different target frequency degradation rates should be used to measure the performance or quality of different chips. In this embodiment, the multiple chips are manufactured using the same process, with the same design, or from the same batch, thus making the frequency degradation rates of the multiple chips comparable. Based on this, after obtaining the frequency degradation rates of the multiple chips, a target frequency degradation rate is determined based on the frequency degradation rates of the multiple chips. For example, if the frequency degradation rates of the multiple chips are all between 2% and 5%, the target frequency degradation rate can be set to 3%; if the frequency degradation rates of the multiple chips are all between 2% and 10%, the target frequency degradation rate can be set to 4%. In addition, the target frequency degradation rate can also be determined by combining the distribution of the frequency degradation rates of the multiple chips. In this embodiment, the setting of the target frequency degradation rate varies with the chip, so that the setting of the target frequency degradation rate is consistent with the actual performance level of the chip, which can improve the rationality of chip selection.

[0174] Similarly, the target frequency mentioned above can be a pre-set frequency threshold, or it can be determined based on the individual frequencies of multiple chips. For example, after determining the frequencies of multiple chips based on their respective frequency degradation rates, if the frequencies of multiple chips are all between 2GHz and 3GHz, the target frequency can be set to 2.2GHz; if the frequencies of multiple chips are all between 2.3GHz and 3.1GHz, the target frequency can be set to 2.5GHz. Furthermore, the target frequency can be determined by combining the frequency distribution of multiple chips. In this embodiment, the target frequency setting changes with the chip, thereby ensuring that the target frequency setting matches the actual performance level of the chip and improving the rationality of chip selection.

[0175] In another embodiment of the chip aging prediction method of this application, a chip aging compensation scheme is also provided. This scheme can effectively compensate for chip aging after it is determined, thereby increasing the frequency of the aging chip and improving the performance of the aging chip.

[0176] Chip aging compensation typically refers to delaying or compensating for frequency degradation by adjusting the chip's operating state after it has been determined that the chip's frequency is degrading.

[0177] Current chip aging compensation schemes typically employ global derating or hardware redundancy. For example, when chip frequency degradation is detected, the overall operating voltage or frequency of the chip is reduced to prevent further performance degradation due to high-intensity operation. Alternatively, redundant CPU cores or memory blocks are incorporated into the chip, activating them when frequency degradation is detected. These aging compensation schemes either degrade overall chip performance, sacrificing the available computing power of certain modules, or result in high hardware costs and low resource utilization.

[0178] To address the aforementioned technical problems, this embodiment proposes a scheme for aging compensation of chips by applying a compensation voltage. This scheme is effective and accurate in compensating for chip aging, and it has low hardware cost and high resource utilization.

[0179] The chip aging compensation scheme provided in this embodiment can be implemented based on the chip aging prediction method described in any of the above embodiments.

[0180] Another chip aging prediction method provided in this embodiment includes:

[0181] S601. By conducting accelerated aging tests on the chip, the correlation between the voltage, ambient temperature, and operating time of the chip in its working state and the frequency degradation rate of the chip is determined.

[0182] Specifically, the processing of step S601 can be performed by referring to the process of determining the correspondence between the voltage, ambient temperature and running time of the chip in the working state and the frequency degradation rate of the chip in the chip aging prediction method described in any of the above embodiments, and will not be repeated here.

[0183] In particular, the processing in step S601 can discover the correspondence between the voltage, ambient temperature and operating time of the chip when it is in operation and the frequency degradation rate of the chip. This correspondence can be expressed by the frequency degradation rate calculation formula.

[0184] The chip in step S601 can be a single chip or multiple chips from a certain batch or of the same design.

[0185] S602, Obtain the frequency degradation rate of the chip.

[0186] Specifically, step S602 can be performed with reference to the processing procedure in the chip aging prediction method described in the above embodiments, thereby determining the chip's frequency degradation rate. For example, the chip's frequency degradation rate can be obtained according to the processing procedures shown in steps S401 and S402 in the above embodiments.

[0187] The chip in step S602 can be the chip described in step S601 or a chip from the same batch and with the same design as the chip described in step S601.

[0188] In other embodiments, the chips in step S602 are qualified chips selected from a batch of chips through the processing of steps S502 and S503 in the above embodiments, whose frequency degradation rate is less than the target frequency degradation rate or whose frequency is greater than the target frequency. After these chips are manufactured and put into use, their frequency degradation rate during use can be identified by the method of this embodiment, and when the frequency degradation rate of these chips reaches a certain level, voltage compensation is performed on them, thereby achieving the purpose of aging compensation for these chips. However, for unqualified chips selected from a batch of chips through the processing of steps S502 and S503 in the above embodiments, whose frequency degradation rate is not less than the target frequency degradation rate or whose frequency is not greater than the target frequency, they may be intercepted and not put into use, and therefore the voltage compensation operation of this embodiment will not be performed on these chips.

[0189] S603. When the frequency degradation rate of the chip is greater than a preset threshold, based on the correspondence between the frequency degradation rate of the chip and the compensation voltage, the target compensation voltage corresponding to the frequency degradation rate of the chip is obtained, so as to realize the aging compensation of the chip through the target compensation voltage.

[0190] The relationship between the chip's frequency degradation rate and the compensation voltage can be used to represent the frequency degradation rate of the chip or a certain type of chip (a specific batch or a specific design), and the compensation voltage required to restore the chip or type of chip from the frequency degradation rate to its initial frequency state. This compensation voltage refers to the additional voltage required to supply the chip to its original power supply voltage.

[0191] In this embodiment, the correspondence between the chip's frequency degradation rate and the compensation voltage is determined by performing a voltage compensation test on the chip after frequency degradation. In this voltage compensation test, the supply voltage to the chip is increased, thereby restoring the chip to its initial frequency state after frequency degradation. Through this voltage compensation test, for any frequency degradation rate of the chip, the compensation voltage required to restore the chip to its initial frequency state from that degradation rate can be determined, thus obtaining the correspondence between the chip's frequency degradation rate and the compensation voltage.

[0192] In this embodiment, the voltage compensation test described above can be performed on the chip after the accelerated aging test. The specific processing procedure for the accelerated aging test on the chip can be found in the accelerated aging test processing procedure described in the above embodiment.

[0193] Through the above processing, for each chip or each design and each batch of chips, this embodiment pre-obtains the correspondence between the chip's frequency degradation rate and the compensation voltage. Based on this, for each chip, when it is determined through step S602 that the chip's frequency degradation rate is greater than a preset threshold, the processing in step S603 can be referred to, and based on the chip's actual frequency degradation rate and the correspondence between the chip's frequency degradation rate and the compensation voltage, the compensation voltage corresponding to the chip's actual frequency degradation rate can be obtained as the target compensation voltage.

[0194] Based on this target compensation voltage, aging compensation can be performed on the chip. That is, by applying the target compensation voltage to the chip, the frequency and performance of the chip can be improved, thus achieving the purpose of aging compensation.

[0195] The aforementioned preset threshold is a frequency degradation rate threshold set in this application embodiment to trigger aging compensation operation on the chip. Specifically, it can be a specific frequency degradation rate value, such as 1%, 2%, etc. When the chip's frequency degradation rate exceeds the preset threshold, it indicates that the chip's frequency degradation has reached a point where voltage compensation operation is required to improve the chip's frequency and performance.

[0196] The chip aging compensation method proposed in this embodiment predetermines the correspondence between the chip's frequency degradation rate and the compensation voltage required to restore the chip to its initial frequency state.

[0197] Based on the aforementioned correspondence, when the frequency degradation rate of the chip is determined to be greater than a preset threshold, a target compensation voltage is determined based on the chip's frequency degradation rate and the aforementioned correspondence. This target compensation voltage is then used to compensate for the chip's aging. The above solution improves the chip's frequency and performance through voltage compensation, thereby achieving chip aging compensation. This solution can improve chip performance during aging and has low hardware cost and high resource utilization.

[0198] Furthermore, the solution in this embodiment pre-obtains the correspondence between the frequency degradation rate and the compensation voltage of the chip. Different chips can have their own corresponding correspondence between frequency degradation rate and compensation voltage. This allows for differentiated and personalized voltage compensation when aging compensation is performed on different chips, based on the corresponding correspondence between frequency degradation rate and compensation voltage of each chip. This enables voltage compensation to adapt to the differentiated performance requirements of different chips, improving the effectiveness and accuracy of aging compensation.

[0199] Another embodiment of this application provides a different chip aging prediction method, the method comprising:

[0200] S701. Set the chip in an aging environment and perform an accelerated aging test on the chip.

[0201] Specifically, the detailed process of performing accelerated aging tests on the chips described above can be found in the chip accelerated aging test process described in the above chip aging prediction method embodiment, and will not be repeated here.

[0202] Referring to the above description of the chip aging prediction method embodiment, step S701, which involves performing accelerated aging tests on the chip, can be used to discover the correspondence between the chip's operating voltage, ambient temperature, and operating time and the chip's frequency degradation rate. This correspondence can be expressed by the frequency degradation rate calculation formula.

[0203] The specific process of determining the correspondence between the voltage, ambient temperature, and operating time of the chip in its working state and the frequency degradation rate of the chip by performing accelerated aging tests on the chip in step S701 can be performed by referring to the process of determining the correspondence between the voltage, ambient temperature, and operating time of the chip in its working state and the frequency degradation rate of the chip in the chip aging prediction method described in any of the above embodiments, and will not be repeated here.

[0204] The chip in step S701 can be a single chip, or multiple chips from a batch or of the same design.

[0205] During the accelerated aging test described above, this embodiment also monitors the output value of the chip's aging sensor in real time. That is, during the accelerated aging test, while testing the frequency of the aged chip, the output value of the chip's aging sensor is simultaneously acquired. Here, the aging sensor refers to a sensor installed inside the chip to sense its aging process.

[0206] Through the above processing, changes in chip frequency and the output value of the chip aging sensor can be recorded simultaneously during the accelerated aging process. Based on the recorded data, the correlation between the changes in the chip aging sensor's output value and the chip's frequency degradation can be obtained. This correlation can be used to infer chip frequency degradation by observing changes in the chip aging sensor's output value.

[0207] The process in step S701 allows the chip to age rapidly, providing a basis for subsequent voltage compensation tests.

[0208] S702. After performing an accelerated aging test on the chip, a voltage compensation test is performed on the chip.

[0209] Specifically, after the chip undergoes accelerated aging test in step S701, the chip's frequency degrades, at which point the conditions are met to perform voltage compensation on the chip to increase its frequency.

[0210] In step S702, the supply voltage to the chip is increased, and the chip frequency is tested and the output value of the chip aging sensor is recorded before and after each voltage increase. The above-mentioned operation of increasing the supply voltage to the chip can be performed according to the set operation precision.

[0211] In other embodiments, during step S702, the supply voltage to the chip is increased, and the output value of the chip aging sensor is recorded before and after each voltage increase. Then, based on the correspondence between the output value change of the chip aging sensor and the chip frequency degradation determined in step S701, the corresponding chip frequency change is determined from the recorded output value change of the chip aging sensor. Therefore, each time the supply voltage to the chip is increased, the corresponding chip frequency data and the output value data of the chip aging sensor can be obtained. This method can save the step of testing the chip frequency, thereby improving test execution efficiency.

[0212] By jointly executing the above steps S701 and S702, the chip is aged to different frequency degradation rates, and a voltage compensation test is performed on the aged chip to increase the chip voltage. The changes in the chip aging sensor output value and the chip frequency are recorded throughout the process, and various monitoring data in the above process are recorded.

[0213] S703. Based on the voltage data of the chip, the output value data of the aging sensor, and the frequency data of the chip obtained during the voltage compensation test, determine the correspondence between the output value of the aging sensor, the frequency degradation rate of the chip, and the compensation voltage required to restore the chip to its initial frequency state, and construct the lookup table based on the determined correspondence.

[0214] Specifically, by analyzing the chip voltage data, aging sensor output data, and chip frequency data obtained during the aforementioned voltage compensation test, the correspondence between the aging sensor output value and the chip frequency degradation rate can be determined, as well as the correspondence between the chip frequency degradation rate and the compensation voltage required to restore the chip from that degradation rate to its initial frequency state. Based on these correspondences, a system can be established... Figure 3 The lookup table shown.

[0215] See Figure 3 As can be seen, the lookup table records the correspondence between the output value of the chip's aging sensor, the chip's frequency degradation rate, and the compensation voltage required to restore the chip to its initial frequency state.

[0216] S704, obtain the frequency degradation rate of the chip.

[0217] Specifically, the chip in step S704 can be the chip described in steps S701 and S702, or a chip from the same batch and with the same design as those described in steps S701 and S702.

[0218] Through the processing of steps S701 to S703 above, the correspondence between the frequency degradation rate and the compensation voltage of a specific chip is determined, and the correspondence is presented in the lookup table corresponding to the chip.

[0219] After a chip identical to the aforementioned specific chip has been put into use or tested for a certain period of time, the voltage, ambient temperature, operating time, and frequency degradation rate trend influencing factor of the chip in its working state are obtained. Then, based on the voltage, ambient temperature, operating time, and frequency degradation rate trend influencing factor of the chip in its working state, the frequency degradation rate of the chip is determined.

[0220] Step S704 can be executed with reference to the processing procedure in the chip aging prediction method described in the above embodiments, thereby determining the chip's frequency degradation rate. For example, the chip's frequency degradation rate can be obtained according to the processing procedures shown in steps S401 and S402 in the above embodiments.

[0221] In other embodiments, the chips in step S704 are qualified chips selected from the batch of chips through the processing of steps S502 and S503 in the above embodiments, whose frequency degradation rate is less than the target frequency degradation rate or whose frequency is greater than the target frequency. After these chips are shipped and put into use, their frequency degradation rate during use can be identified by the method of this embodiment, and when the frequency degradation rate of these chips reaches a certain level, voltage compensation is performed on them, thereby achieving the purpose of aging compensation for these chips. However, for unqualified chips selected from the batch of chips through the processing of steps S502 and S503 in the above embodiments, whose frequency degradation rate is not less than the target frequency degradation rate or whose frequency is not greater than the target frequency, they may be intercepted and not put into use, and therefore the voltage compensation operation of this embodiment will not be performed on these chips.

[0222] S705. When the frequency degradation rate of the chip is greater than a preset threshold, based on the correspondence between the frequency degradation rate of the chip and the compensation voltage, the target compensation voltage corresponding to the frequency degradation rate of the chip is obtained, so as to realize the aging compensation of the chip through the target compensation voltage.

[0223] Specifically, after determining the frequency degradation rate of the chip in step S704, and confirming that the frequency degradation rate is greater than a preset threshold, the target compensation voltage corresponding to the chip's frequency degradation rate can be obtained based on the chip's frequency degradation rate and the correspondence between the chip's frequency degradation rate and the compensation voltage obtained in step S703. For example, after determining the chip's frequency degradation rate, the compensation voltage corresponding to the chip's frequency degradation rate can be determined from the lookup table corresponding to the chip obtained in step S703; this is the target compensation voltage.

[0224] The aforementioned preset threshold is a frequency degradation rate threshold set in this application embodiment to trigger aging compensation operation on the chip. Specifically, it can be a specific frequency degradation rate value, such as 1%, 2%, etc. When the chip's frequency degradation rate exceeds the preset threshold, it indicates that the chip's frequency degradation has reached a point where voltage compensation operation is required to improve the chip's frequency and performance.

[0225] Based on this target compensation voltage, aging compensation can be performed on the chip. That is, by applying the target compensation voltage to the chip, the frequency of the chip can be increased, thus achieving the purpose of aging compensation.

[0226] In this embodiment, the correspondence between the chip's frequency degradation rate and the compensation voltage is obtained in advance, and a lookup table is generated based on this correspondence. This makes the correspondence between the chip's frequency degradation rate and the compensation voltage clearer and more understandable, thereby improving the efficiency of determining the target compensation voltage based on the correspondence between the chip's frequency degradation rate and the compensation voltage.

[0227] The aging compensation scheme in the chip aging prediction method provided in the above embodiments can also be executed independently, that is, it is not limited to executing the chip aging prediction method and then executing the above chip aging compensation scheme. For the scenario where the chip aging compensation scheme is executed independently, this application embodiment also provides a chip aging compensation method, which can be applied to the post-silicon testing stage of the chip or to the chip usage stage, for compensating the aging chip to improve chip performance.

[0228] The chip aging compensation method provided in this embodiment will be described below. For specific processing content involving chip aging prediction or chip accelerated aging test, please refer to the corresponding content of the chip aging prediction method described in the above embodiment.

[0229] See Figure 4 As shown, the chip aging compensation method provided in this embodiment includes:

[0230] S801, obtain the frequency degradation rate of the chip.

[0231] In some embodiments, the chip frequency degradation rate can be predicted and determined according to the chip aging prediction method described in any of the above embodiments. For example, according to the description in any of the above embodiments, the chip is first subjected to accelerated aging tests and the frequency of the chip after accelerated aging is tested to determine the correspondence between the voltage, ambient temperature, and operating time of the chip in its operating state and the chip frequency degradation rate. The influence of the test voltage and the nanometer scale of the chip's manufacturing process on the correspondence between the voltage, ambient temperature, and operating time of the chip in its operating state and the chip frequency degradation rate is also determined, ultimately yielding the frequency degradation rate prediction formula shown in Formula 8 of the above embodiments.

[0232] Then, by obtaining the chip's operating voltage, ambient temperature, operating time, and frequency degradation rate trend influencing factors, the chip's frequency degradation rate can be determined based on the frequency degradation rate prediction formula mentioned above.

[0233] In other embodiments, the frequency degradation rate of the chip can also be obtained in other ways, such as by testing the frequency of the chip and comparing the measured frequency with the initial frequency of the chip to determine the frequency degradation rate of the chip.

[0234] In other embodiments, the chips in step S801 are qualified chips selected from a batch of chips through the processing of steps S502 and S503 in the above embodiments, whose frequency degradation rate is less than the target frequency degradation rate or whose frequency is greater than the target frequency. After these chips are manufactured and put into use, their frequency degradation rate during use can be identified by the method of this embodiment, and when the frequency degradation rate of these chips reaches a certain level, voltage compensation is performed on them to achieve the purpose of aging compensation for these chips. However, for unqualified chips selected from a batch of chips through the processing of steps S502 and S503 in the above embodiments, whose frequency degradation rate is not less than the target frequency degradation rate or whose frequency is not greater than the target frequency, they may be intercepted and not put into use, and therefore the voltage compensation operation of this embodiment will not be performed on these chips.

[0235] S802. When the frequency degradation rate of the chip is greater than a preset threshold, based on the correspondence between the frequency degradation rate of the chip and the compensation voltage, the target compensation voltage corresponding to the frequency degradation rate of the chip is obtained, so as to realize the aging compensation of the chip through the target compensation voltage.

[0236] The relationship between the chip's frequency degradation rate and the compensation voltage can be used to represent the chip's frequency degradation rate and the compensation voltage required to restore the chip from that degradation rate to its initial frequency state. This compensation voltage refers to the additional voltage required to supply the chip to its original power supply voltage.

[0237] In this embodiment, the correspondence between the chip's frequency degradation rate and the compensation voltage is determined by performing a voltage compensation test on the chip after the chip or another chip of the same type has experienced frequency degradation. In this voltage compensation test, the supply voltage to the frequency-degraded chip is increased, thereby restoring the chip to its initial frequency state. Through this voltage compensation test, for any frequency degradation rate of the chip, the compensation voltage required to restore the chip to its initial frequency state from that degradation rate can be determined, thus obtaining the correspondence between the chip's frequency degradation rate and the compensation voltage.

[0238] In this embodiment, the voltage compensation test described above can be performed on the chip after the chip's frequency has degraded due to accelerated aging testing. The specific process for performing the accelerated aging test on the chip can be found in the accelerated aging test process described in the above embodiment.

[0239] Through the above processing, this embodiment pre-obtains the correspondence between the frequency degradation rate and the compensation voltage for each chip. Based on this, for each chip, when it is determined through step S801 that the frequency degradation rate of the chip is greater than a preset threshold, the processing in step S802 can be referred to, and the compensation voltage corresponding to the actual frequency degradation rate of the chip can be obtained according to the actual frequency degradation rate of the chip and the correspondence between the frequency degradation rate and the compensation voltage, as the target compensation voltage.

[0240] Based on this target compensation voltage, aging compensation can be performed on the chip. That is, by applying the target compensation voltage to the chip, the frequency of the chip can be increased, thus achieving the purpose of aging compensation.

[0241] The aforementioned preset threshold is a frequency degradation rate threshold set in this application embodiment to trigger aging compensation operation on the chip. Specifically, it can be a specific frequency degradation rate value, such as 1%, 2%, etc. When the chip's frequency degradation rate exceeds the preset threshold, it indicates that the chip's frequency degradation has reached a point where voltage compensation operation is required to improve the chip's frequency and performance.

[0242] The chip aging compensation method proposed in this embodiment predetermines the correspondence between the chip's frequency degradation rate and the compensation voltage required to restore the chip to its initial frequency state.

[0243] Based on the aforementioned correspondence, when the frequency degradation rate of the chip is determined to be greater than a preset threshold, a target compensation voltage is determined based on the chip's frequency degradation rate and the aforementioned correspondence. This target compensation voltage is then used to compensate for the chip's aging. The above solution increases the chip's frequency through voltage compensation, thereby achieving chip aging compensation. This solution can improve chip performance during aging and has low hardware cost and high resource utilization.

[0244] Furthermore, the solution in this embodiment pre-obtains the correspondence between the frequency degradation rate and the compensation voltage of the chip. Different chips can have their own corresponding correspondence between frequency degradation rate and compensation voltage. This allows for differentiated and personalized voltage compensation when aging compensation is performed on different chips, based on the corresponding correspondence between frequency degradation rate and compensation voltage of each chip. This enables voltage compensation to adapt to the differentiated needs of different chips, improving the effectiveness and accuracy of aging compensation.

[0245] Another embodiment of this application provides a different chip aging compensation method, the method comprising:

[0246] S901. Set the chip in an aging environment and perform an accelerated aging test on the chip.

[0247] Specifically, the detailed process of performing accelerated aging tests on the chips described above can be found in the chip accelerated aging test process described in the above chip aging prediction method embodiment, and will not be repeated here.

[0248] Referring to the above description of the chip aging prediction method embodiment, step S901, which involves performing accelerated aging tests on the chip, can be used to discover the correspondence between the chip's operating voltage, ambient temperature, and operating time and the chip's frequency degradation rate. This correspondence can be expressed by the frequency degradation rate calculation formula.

[0249] The specific process of determining the correspondence between the voltage, ambient temperature, and operating time of the chip in its working state and the frequency degradation rate of the chip by performing accelerated aging tests on the chip in step S901 can be performed by referring to the process of determining the correspondence between the voltage, ambient temperature, and operating time of the chip in its working state and the frequency degradation rate of the chip in the chip aging prediction method described in any of the above embodiments, and will not be repeated here.

[0250] Through the accelerated aging test described above, this embodiment tests the frequency of the chip after accelerated aging to determine the frequency degradation rate of the chip after aging.

[0251] Furthermore, during the accelerated aging test described above, this embodiment also monitors the output value of the chip's aging sensor in real time. That is, during the accelerated aging test, while testing the frequency of the aged chip, the output value of the chip's aging sensor is simultaneously acquired. Here, the aging sensor refers to a sensor disposed inside the chip to sense the aging of the chip.

[0252] Through the above processing, changes in chip frequency and the output value of the chip aging sensor can be recorded simultaneously during the accelerated aging process. Based on the recorded data, the correlation between the changes in the chip aging sensor's output value and the chip's frequency degradation can be obtained. This correlation can be used to infer chip frequency degradation by observing changes in the chip aging sensor's output value.

[0253] The process in step S901 allows the chip to age rapidly, providing a basis for subsequent voltage compensation tests.

[0254] S902. After performing accelerated aging tests on the chip, voltage compensation tests are performed on the chip.

[0255] Specifically, after the chip undergoes accelerated aging testing, the chip's frequency degrades, at which point the conditions become available to perform voltage compensation on the chip to increase its frequency.

[0256] In step S902, the supply voltage to the chip is increased, and the chip frequency is tested and the output value of the chip aging sensor is recorded before and after each voltage increase. The above-mentioned operation of increasing the supply voltage to the chip can be performed according to the set operation precision.

[0257] In other embodiments, during step S902, the supply voltage to the chip is increased, and the output value of the chip aging sensor is recorded before and after each voltage increase. Then, based on the correspondence between the output value change of the chip aging sensor and the chip frequency degradation determined in step S901, the corresponding chip frequency change is determined from the recorded output value change of the chip aging sensor. Therefore, each time the supply voltage to the chip is increased, the corresponding chip frequency data and the output value data of the chip aging sensor can be obtained. This method can save the step of testing the chip frequency, thereby improving test execution efficiency.

[0258] By jointly executing the above steps S901 and S902, the chip is aged to different frequency degradation rates, and a voltage compensation test is performed on the aged chip to increase the chip voltage. The changes in the chip aging sensor output value and the chip frequency are recorded throughout the process, and various monitoring data in the above process are recorded.

[0259] S903. Based on the voltage data of the chip, the output value data of the aging sensor, and the frequency data of the chip obtained during the voltage compensation test, determine the correspondence between the output value of the aging sensor, the frequency degradation rate of the chip, and the compensation voltage required to restore the chip to its initial frequency state, and construct the lookup table based on the determined correspondence.

[0260] Specifically, by analyzing the chip voltage data, aging sensor output data, and chip frequency data obtained during the aforementioned voltage compensation test, the correspondence between the aging sensor output value and the chip frequency degradation rate can be determined, as well as the correspondence between the chip frequency degradation rate and the compensation voltage required to restore the chip from that degradation rate to its initial frequency state. Based on these correspondences, a system can be established... Figure 3 The lookup table shown.

[0261] See Figure 3 As can be seen, the lookup table records the correspondence between the output value of the chip's aging sensor, the chip's frequency degradation rate, and the compensation voltage required to restore the chip to its initial frequency state.

[0262] Through the processing in steps S901 to S903, the corresponding relationship between frequency degradation rate and compensation voltage can be determined for any type, design, or batch of chip.

[0263] S904, obtain the frequency degradation rate of the chip.

[0264] Specifically, through the processing of steps S901 to S903 above, the corresponding relationship between frequency degradation rate and compensation voltage can be determined for any type, design, or batch of chip, and this relationship is presented in a lookup table corresponding to that chip. At this point, for other chips of the same type, design, or batch, aging compensation can be performed based on the relationship between frequency degradation rate and compensation voltage obtained in steps S901 to S903.

[0265] In other embodiments, the chips in step S904 are qualified chips selected from the batch of chips through the processing of steps S502 and S503 in the above embodiments, whose frequency degradation rate is less than the target frequency degradation rate or whose frequency is greater than the target frequency. After these chips are shipped and put into use, their frequency degradation rate during use can be identified by the method of this embodiment, and when the frequency degradation rate of these chips reaches a certain level, voltage compensation is performed on them, thereby achieving the purpose of aging compensation for these chips. However, for unqualified chips selected from the batch of chips through the processing of steps S502 and S503 in the above embodiments, whose frequency degradation rate is not less than the target frequency degradation rate or whose frequency is not greater than the target frequency, they may be intercepted and not put into use, and therefore the voltage compensation operation of this embodiment will not be performed on these chips.

[0266] In some embodiments, after the chip is put into use or tested for a certain period of time, the voltage, ambient temperature, operating time, and frequency degradation rate trend influencing factor of the chip in its operating state are obtained. Then, based on the chip's operating voltage, ambient temperature, operating time, and frequency degradation rate trend influencing factor, the chip's frequency degradation rate is determined. The specific process for determining the chip's frequency degradation rate can be performed in accordance with the processing procedure in the chip aging prediction method described in the above embodiments, thereby determining the chip's frequency degradation rate. For example, the chip's frequency degradation rate can be obtained according to the processing procedures shown in steps S401 and S402 of the above embodiments.

[0267] In other embodiments, after the chip has been put into use or tested for a certain period of time, the output value of the aging sensor of the chip is obtained. Then, based on the output value and the lookup table constructed in step S903, the frequency degradation rate of the chip is determined.

[0268] For details, see Figure 3 As can be seen, the lookup table constructed in step S903 records the correspondence between the output value of the chip's aging sensor, the chip's frequency degradation rate, and the compensation voltage required to restore the chip to its initial frequency state. Therefore, when obtaining the output value of the chip's aging sensor, the frequency degradation rate corresponding to that output value can be read from the lookup table, thus obtaining the chip's frequency degradation rate.

[0269] In other embodiments, after the chip has been put into use or tested for a certain period of time, the output value of the aging sensor of the chip is acquired. Then, the change in the output value of the aging sensor is determined by calculating the difference between the acquired output value and the initial output value. Finally, based on the change in the output value of the aging sensor, and the correspondence between the change in the output value of the chip's aging sensor and the frequency degradation rate of the chip obtained in step S901, the frequency degradation rate of the chip is determined.

[0270] The aforementioned initial output value refers to the output value of the chip's aging sensor when the chip is in its initial frequency state.

[0271] After a chip is put into use or tested for a certain period of time, its frequency may degrade to a certain extent. At this time, the output value of the aging sensor of the chip is obtained, and the difference between the aging sensor output value obtained at this time and the initial output value is calculated to obtain the change in the output value of the aging sensor.

[0272] Based on the change in the output value of the aging sensor, and the correspondence between the change in the output value of the chip aging sensor and the frequency degradation rate of the chip obtained through step S901, the frequency degradation rate of the chip can be determined.

[0273] S905. When the frequency degradation rate of the chip is greater than a preset threshold, based on the correspondence between the frequency degradation rate of the chip and the compensation voltage, the target compensation voltage corresponding to the frequency degradation rate of the chip is obtained, so as to realize the aging compensation of the chip through the target compensation voltage.

[0274] Specifically, after determining the frequency degradation rate of the chip in step S904, and confirming that the frequency degradation rate is greater than a preset threshold, the target compensation voltage corresponding to the chip's frequency degradation rate can be obtained based on the chip's frequency degradation rate and the correspondence between the chip's frequency degradation rate and the compensation voltage obtained in step S903. For example, after determining the chip's frequency degradation rate, the compensation voltage corresponding to the chip's frequency degradation rate can be determined from the lookup table corresponding to the chip obtained in step S903; this is the target compensation voltage.

[0275] Based on this target compensation voltage, aging compensation can be performed on the chip. That is, by applying the target compensation voltage to the chip, the frequency of the chip can be increased, thus achieving the purpose of aging compensation.

[0276] The aforementioned preset threshold is a frequency degradation rate threshold set in this application embodiment to trigger aging compensation operation on the chip. Specifically, it can be a specific frequency degradation rate value, such as 1%, 2%, etc. When the chip's frequency degradation rate exceeds the preset threshold, it indicates that the chip's frequency degradation has reached a point where voltage compensation operation is required to improve the chip's frequency and performance.

[0277] This embodiment pre-obtains the correspondence between the chip's frequency degradation rate and the compensation voltage, and generates a lookup table based on this correspondence. This makes the correspondence between the chip's frequency degradation rate and the compensation voltage clearer and more concise, thereby improving the efficiency of determining the target compensation voltage based on the correspondence between the chip's frequency degradation rate and the compensation voltage. Furthermore, this embodiment provides multiple different implementation methods for obtaining the chip's frequency degradation rate, which can improve the flexibility of the solution implementation.

[0278] This application also provides a chip aging prediction device, which is used to predict the aging of the chip during the post-silicon testing stage or the chip usage stage. See [link to documentation]. Figure 5 As shown, the device includes:

[0279] The data acquisition unit 001 is used to acquire the voltage, ambient temperature, running time, and frequency degradation rate trend influencing factor of the chip when it is in operation. The frequency degradation rate trend influencing factor is related to the test voltage acquired when testing the chip frequency.

[0280] The aging prediction unit 002 is used to determine the frequency degradation rate of the chip based on the voltage, the ambient temperature, the operating time, and the frequency degradation rate trend influence factor.

[0281] In some embodiments of this chip aging prediction device, the data acquisition unit 001 obtains the frequency degradation rate trend influence factor according to the following formula:

[0282] P = exp(-αV) measure )

[0283] Where P represents the frequency degradation rate trend influencing factor, V measure This represents the test voltage, and α is a coefficient.

[0284] In some embodiments of this chip aging prediction device, the data acquisition unit 001 obtains the frequency degradation rate trend influence factor according to the following formula:

[0285] P=A*exp(-αV measure )

[0286] Where P represents the frequency degradation rate trend influencing factor, A is used to characterize the impact of the chip's manufacturing process nanometer scale on the frequency degradation rate trend influencing factor, and V measure This represents the test voltage, and α is a coefficient.

[0287] In some embodiments of the chip aging prediction device, when the aging prediction unit 002 determines the frequency degradation rate of the chip based on the voltage, the ambient temperature, the operating time, and the frequency degradation rate trend influence factor, it calculates the frequency degradation rate of the chip according to the following frequency degradation rate calculation formula:

[0288]

[0289] Where, ΔRatio f A represents the frequency degradation rate; A characterizes the impact of the chip's manufacturing process nanometer scale on the frequency degradation rate trend; V measure The values ​​represent the test voltage, α is a coefficient, V represents the voltage, m is a constant whose value may vary depending on the chip's process, performance, and design; typically, it falls within a range, such as 4–18; T represents the ambient temperature; E a The activation energy of the chip is represented by k, which specifically refers to the activation energy of the material used to manufacture the chip; k is the Boltzmann constant; t represents the running time; n is a constant whose value may vary depending on the chip's process, performance, and design. Typically, its value is within a range, such as 0.15 to 0.8.

[0290] In some embodiments of the chip aging prediction device, the device further includes:

[0291] A preprocessing unit is used to place the chip in an aging environment and perform accelerated aging tests on the chip; after the accelerated aging test, different test voltages are applied to the chip to test its frequency, and the frequency degradation rate of the chip measured under different test voltages is obtained; based on the frequency degradation rate of the chip measured under the different test voltages, a formula for calculating the frequency degradation rate trend influence factor is determined; the formula for calculating the frequency degradation rate trend influence factor is used to calculate the frequency degradation rate trend influence factor based on the test voltage when testing the chip's frequency.

[0292] In some embodiments of the chip aging prediction device, the aging prediction unit 002 is further configured to: obtain the frequency degradation rate corresponding to each of the multiple chips; select chips with a frequency degradation rate less than a target frequency degradation rate from the multiple chips based on the frequency degradation rate corresponding to each of the multiple chips; or, determine the frequency of each of the multiple chips based on the frequency degradation rate corresponding to each of the multiple chips, and select chips with a frequency greater than a target frequency from the multiple chips.

[0293] In some embodiments of the chip aging prediction device, the device further includes a voltage compensation unit, which is used to obtain a target compensation voltage corresponding to the frequency degradation rate of the chip based on the correspondence between the frequency degradation rate of the chip and the compensation voltage when the frequency degradation rate of the chip is greater than a preset threshold, so as to realize aging compensation of the chip through the target compensation voltage.

[0294] In some embodiments of the chip aging prediction device, the correspondence between the chip's frequency degradation rate and the compensation voltage is carried out in a lookup table, which includes the correspondence between the output value of the chip's aging sensor, the chip's frequency degradation rate, and the compensation voltage required to restore the chip to its initial frequency state.

[0295] The chip's aging sensor is used to detect the chip's aging.

[0296] In some embodiments of the chip aging prediction device, the lookup table is constructed by the voltage compensation unit through the following process: the chip is placed in an aging environment and accelerated aging test is performed on the chip; after the accelerated aging test, the chip is subjected to a voltage compensation test; based on the voltage of the chip, the output value of the aging sensor, and the frequency of the chip obtained during the voltage compensation test, the correspondence between the output value of the aging sensor, the frequency degradation rate of the chip, and the compensation voltage required to restore the chip to its initial frequency state is determined, and the lookup table is constructed based on the determined correspondence.

[0297] The chip aging prediction device provided in this embodiment belongs to the same concept as the chip aging prediction method provided in the above embodiments of this application. It can execute the chip aging prediction method provided in any of the above embodiments of this application and has the corresponding functional modules and beneficial effects for executing the chip aging prediction method. Technical details not described in detail in this embodiment can be found in the specific processing content of the chip aging prediction method provided in the above embodiments of this application, and will not be repeated here.

[0298] Another embodiment of this application provides a chip aging compensation device, which is used to perform aging compensation on the chip during the post-silicon testing stage or the chip usage stage. See [link to relevant documentation] Figure 6 As shown, the device includes:

[0299] Aging determination unit 011 is used to obtain the frequency degradation rate of the chip;

[0300] The aging compensation unit 012 is used to obtain the target compensation voltage corresponding to the frequency degradation rate of the chip based on the correspondence between the frequency degradation rate of the chip and the compensation voltage when the frequency degradation rate of the chip is greater than a preset threshold, so as to realize the aging compensation of the chip through the target compensation voltage.

[0301] In some embodiments of the chip aging compensation device, the correspondence between the chip's frequency degradation rate and the compensation voltage is carried out in a lookup table, which includes the correspondence between the output value of the chip's aging sensor, the chip's frequency degradation rate, and the compensation voltage required to restore the chip to its initial frequency state.

[0302] The chip's aging sensor is used to detect the chip's aging.

[0303] In some embodiments of this chip aging compensation device, the lookup table is constructed by the aging compensation unit 012 through the following processing:

[0304] The chip was placed in an aging environment to undergo accelerated aging tests.

[0305] After the chip undergoes accelerated aging testing, a voltage compensation test is performed on the chip.

[0306] Based on the voltage of the chip, the output value of the aging sensor, and the frequency of the chip obtained during the voltage compensation test, the correspondence between the output value of the aging sensor, the frequency degradation rate of the chip, and the compensation voltage required to restore the chip to its initial frequency state is determined, and the lookup table is constructed based on the determined correspondence.

[0307] In some embodiments of the chip aging compensation device, the aging determination unit 011 acquires the frequency degradation rate of the chip by: acquiring the output value of the aging sensor of the chip; and determining the frequency degradation rate of the chip based on the output value and the lookup table.

[0308] In some embodiments of the chip aging compensation device, during the accelerated aging test of the chip, the aging compensation unit 012 also determines the correspondence between the change in the output value of the aging sensor and the frequency degradation rate of the chip based on the output value of the aging sensor and the frequency of the chip.

[0309] The aging determination unit 011 acquires the frequency degradation rate of the chip, including:

[0310] Obtain the output value of the aging sensor of the chip;

[0311] The change in the output value of the aging sensor is determined by calculating the difference between the output value and the initial output value; wherein, the initial output value is the output value of the aging sensor when the chip is in the initial frequency state;

[0312] The frequency degradation rate of the chip is determined based on the change in the output value of the aging sensor and the correspondence between the change in the output value of the aging sensor and the frequency degradation rate of the chip.

[0313] The chip aging compensation device provided in this embodiment belongs to the same concept as the chip aging compensation method provided in the above embodiments of this application. It can execute the chip aging compensation method provided in any of the above embodiments of this application and has the corresponding functional modules and beneficial effects for executing the chip aging compensation method. Technical details not described in detail in this embodiment can be found in the specific processing content of the chip aging compensation method provided in the above embodiments of this application, and will not be repeated here.

[0314] The functions implemented by each unit in the above-mentioned chip aging prediction device and / or chip aging compensation device can be implemented by the same or different processors, and this application embodiment does not limit this.

[0315] It should be understood that the units in the above chip aging prediction device and / or chip aging compensation device can be implemented by a processor calling software. For example, the device includes a processor connected to a memory containing instructions. The processor calls the instructions stored in the memory to implement any of the above methods or to implement the functions of each unit of the device. The processor can be a general-purpose processor, such as a CPU or microprocessor, and the memory can be internal or external to the device. Alternatively, the units in the device can be implemented as hardware circuits. By designing the hardware circuits, some or all of the unit functions can be implemented. The hardware circuits can be understood as one or more processors. For example, in one implementation, the hardware circuit is an ASIC, and the functions of some or all of the above units are implemented by designing the logical relationships of the components within the circuit. In another implementation, the hardware circuit can be implemented by a PLD, such as an FPGA, which can include a large number of logic gates. The connection relationships between the logic gates are configured through configuration files to implement the functions of some or all of the above units. All units of the above device can be implemented entirely by a processor calling software, entirely by hardware circuits, or partially by a processor calling software with the remaining parts implemented by hardware circuits.

[0316] In this application embodiment, a processor is a circuit with signal processing capabilities. In one implementation, the processor can be a circuit with instruction reading and execution capabilities, such as a CPU, microprocessor, GPU, or DSP. In another implementation, the processor can implement certain functions through the logical relationships of hardware circuits. These logical relationships are fixed or reconfigurable. For example, the processor may be a hardware circuit implemented as an ASIC or PLD, such as an FPGA. In a reconfigurable hardware circuit, the process of the processor loading a configuration document and configuring the hardware circuit can be understood as the processor loading instructions to implement the functions of some or all of the above units. Furthermore, it can also be a hardware circuit designed for artificial intelligence, which can be understood as an ASIC, such as an NPU, TPU, or DPU.

[0317] As can be seen, each unit in the above device can be one or more processors (or processing circuits) configured to implement the above methods, such as: CPU, GPU, NPU, TPU, DPU, microprocessor, DSP, ASIC, FPGA, or a combination of at least two of these processor forms.

[0318] Furthermore, the units in the above devices can be integrated in whole or in part, or they can be implemented independently. In one implementation, these units are integrated together and implemented in the form of a System-on-Chip (SoC). The SoC may include at least one processor for implementing any of the above methods or implementing the functions of the units in the device. The at least one processor may be of different types, such as CPU and FPGA, CPU and artificial intelligence processor, CPU and GPU, etc.

[0319] Another embodiment of this application also provides an electronic device, see [link to relevant documentation] Figure 7 As shown, the device includes:

[0320] Memory 200 and processor 210;

[0321] The memory 200 is connected to the processor 210 and is used to store programs;

[0322] The processor 210 is used to implement the chip aging prediction method or chip aging compensation method provided in any of the above embodiments by running the program stored in the memory 200.

[0323] Specifically, the aforementioned electronic device may also include: a bus, a communication interface 220, an input device 230, and an output device 240.

[0324] The processor 210, memory 200, communication interface 220, input device 230, and output device 240 are interconnected via a bus. Among them:

[0325] A bus can include a pathway for transmitting information between various components of a computer system.

[0326] The processor 210 can be a general-purpose processor, such as a general-purpose central processing unit (CPU), a microprocessor, etc., or an application-specific integrated circuit (ASIC), or one or more chips used to control the execution of the program of the present invention. It can also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), an off-the-shelf programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.

[0327] Processor 210 may include a main processor, as well as a baseband chip, modem, etc.

[0328] The memory 200 stores a program that executes the technical solution of this invention, and may also store an operating system and other key business functions. Specifically, the program may include program code, which includes computer operation instructions. More specifically, the memory 200 may include read-only memory (ROM), other types of static storage devices capable of storing static information and instructions, random access memory (RAM), other types of dynamic storage devices capable of storing information and instructions, disk storage, flash memory, etc.

[0329] Input device 230 may include a device for receiving user input data and information, such as a keyboard, mouse, camera, scanner, light pen, voice input device, touch screen, pedometer, or gravity sensor.

[0330] Output device 240 may include devices that allow information to be output to a user, such as a display screen, printer, speaker, etc.

[0331] The communication interface 220 may include a device that uses any transceiver to communicate with other devices or communication networks, such as Ethernet, Radio Access Network (RAN), Wireless Local Area Network (WLAN), etc.

[0332] The processor 210 executes the program stored in the memory 200 and calls other devices, which can be used to implement the various steps of the chip aging prediction method or chip aging compensation method provided in any of the above embodiments of this application.

[0333] In addition to the methods and devices described above, embodiments of this application may also be computer program products, which include computer program instructions that, when executed by a processor, cause the processor to perform the steps of the chip aging prediction method or chip aging compensation method described in any of the embodiments described above.

[0334] The computer program product can be written in any combination of one or more programming languages ​​to perform the operations of the embodiments of this application. The programming languages ​​include object-oriented programming languages ​​such as Java and C++, as well as conventional procedural programming languages ​​such as C or similar languages. The program code can be executed entirely on the user's computing device, partially on the user's computing device, as a standalone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0335] Furthermore, embodiments of this application may also be computer-readable storage media storing a computer program thereon, the computer program being executed by a processor of the steps in the chip aging prediction method or chip aging compensation method described in any of the above embodiments of this specification.

[0336] For the foregoing method embodiments, in order to simplify the description, they are all described as a series of actions. However, those skilled in the art should understand that this application is not limited to the described order of actions, because according to this application, some steps can be performed in other orders or simultaneously. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily essential to this application.

[0337] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For apparatus embodiments, since they are basically similar to method embodiments, the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments.

[0338] The steps in the methods of the various embodiments of this application can be adjusted, merged, or deleted in order according to actual needs, and the technical features described in each embodiment can be replaced or combined.

[0339] The modules and sub-modules in the various embodiments of the present application's devices and terminals can be merged, divided, and deleted according to actual needs.

[0340] It should be understood that the disclosed terminals, devices, and methods can be implemented in other ways, given the several embodiments provided in this application. For example, the terminal embodiments described above are merely illustrative. For instance, the division of modules or sub-modules is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple sub-modules or modules may be combined or integrated into another module, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be indirect coupling or communication connection through some interfaces, devices, or modules, and may be electrical, mechanical, or other forms.

[0341] The modules or submodules described as separate components may or may not be physically separate. The components that constitute a module or submodule may or may not be physical modules or submodules; that is, they may be located in one place or distributed across multiple network modules or submodules. Some or all of the modules or submodules can be selected to achieve the purpose of this embodiment's solution, depending on actual needs.

[0342] Furthermore, the functional modules or sub-modules in the various embodiments of this application can be integrated into one processing module, or each module or sub-module can exist physically separately, or two or more modules or sub-modules can be integrated into one module. The integrated modules or sub-modules described above can be implemented in hardware or in the form of software functional modules or sub-modules.

[0343] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0344] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein can be implemented directly by hardware, a software unit executed by a processor, or a combination of both. The software unit can be located in random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.

[0345] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0346] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A chip aging compensation method, characterized in that, The method is applied in the post-silicon testing stage or the chip usage stage, and the method includes: Obtain the frequency degradation rate of the chip; If the frequency degradation rate of the chip is greater than a preset threshold, the target compensation voltage corresponding to the frequency degradation rate of the chip is obtained based on the correspondence between the frequency degradation rate of the chip and the compensation voltage, so as to realize the aging compensation of the chip through the target compensation voltage.

2. The method according to claim 1, characterized in that, The correspondence between the chip's frequency degradation rate and the compensation voltage is contained in a lookup table, which includes the correspondence between the chip's aging sensor output value, the chip's frequency degradation rate, and the compensation voltage required to restore the chip to its initial frequency state. The chip's aging sensor is used to detect the chip's aging.

3. The method according to claim 2, characterized in that, The query table is constructed through the following process: The chip was placed in an aging environment to undergo accelerated aging tests. After the chip undergoes accelerated aging testing, a voltage compensation test is performed on the chip. Based on the voltage of the chip, the output value of the aging sensor, and the frequency of the chip obtained during the voltage compensation test, the correspondence between the output value of the aging sensor, the frequency degradation rate of the chip, and the compensation voltage required to restore the chip to its initial frequency state is determined, and the lookup table is constructed based on the determined correspondence.

4. The method according to claim 2, characterized in that, Obtaining the frequency degradation rate of the chip includes: Obtain the output value of the aging sensor of the chip; Based on the output value and the lookup table, the frequency degradation rate of the chip is determined.

5. The method according to claim 3, characterized in that, The method further includes: During the accelerated aging test of the chip, the correspondence between the change in the output value of the aging sensor and the frequency degradation rate of the chip is determined based on the output value of the aging sensor and the frequency of the chip. Obtaining the frequency degradation rate of the chip includes: Obtain the output value of the aging sensor of the chip; The change in the output value of the aging sensor is determined by calculating the difference between the output value and the initial output value; wherein, the initial output value is the output value of the aging sensor when the chip is in the initial frequency state; The frequency degradation rate of the chip is determined based on the change in the output value of the aging sensor and the correspondence between the change in the output value of the aging sensor and the frequency degradation rate of the chip.

6. A chip aging compensation device, characterized in that, The apparatus is used to perform aging compensation on the chip during the post-silicon testing stage or the chip usage stage. The apparatus includes: An aging determination unit is used to obtain the frequency degradation rate of the chip. An aging compensation unit is used to obtain a target compensation voltage corresponding to the frequency degradation rate of the chip based on the correspondence between the frequency degradation rate of the chip and the compensation voltage when the frequency degradation rate of the chip is greater than a preset threshold, so as to achieve aging compensation of the chip through the target compensation voltage.

7. The apparatus according to claim 6, characterized in that, The correspondence between the chip's frequency degradation rate and the compensation voltage is contained in a lookup table, which includes the correspondence between the chip's aging sensor output value, the chip's frequency degradation rate, and the compensation voltage required to restore the chip to its initial frequency state. The chip's aging sensor is used to detect the chip's aging.

8. The apparatus according to claim 7, characterized in that, The query table is constructed through the following process: The chip was placed in an aging environment to undergo accelerated aging tests. After the chip undergoes accelerated aging testing, a voltage compensation test is performed on the chip. Based on the voltage of the chip, the output value of the aging sensor, and the frequency of the chip obtained during the voltage compensation test, the correspondence between the output value of the aging sensor, the frequency degradation rate of the chip, and the compensation voltage required to restore the chip to its initial frequency state is determined, and the lookup table is constructed based on the determined correspondence.

9. The apparatus according to claim 7, characterized in that, The aging determination unit obtains the frequency degradation rate of the chip, including: Obtain the output value of the aging sensor of the chip; Based on the output value and the lookup table, the frequency degradation rate of the chip is determined.

10. The apparatus according to claim 8, characterized in that, During the accelerated aging test of the chip, the correspondence between the change in the output value of the aging sensor and the frequency degradation rate of the chip is determined based on the output value of the aging sensor and the frequency of the chip. The aging determination unit obtains the frequency degradation rate of the chip, including: Obtain the output value of the aging sensor of the chip; The change in the output value of the aging sensor is determined by calculating the difference between the output value and the initial output value; wherein, the initial output value is the output value of the aging sensor when the chip is in the initial frequency state; The frequency degradation rate of the chip is determined based on the change in the output value of the aging sensor and the correspondence between the change in the output value of the aging sensor and the frequency degradation rate of the chip.

11. An electronic device, characterized in that, include: Processor and memory; The memory is connected to the processor and is used to store programs; The processor is configured to implement the chip aging compensation method as described in any one of claims 1 to 5 by running a program in the memory.

12. A computer-readable storage medium, characterized in that, The method includes a computer program that, when run by a processor, causes the processor to perform the chip aging compensation method as described in any one of claims 1 to 5.

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