Decision feedback circuit for receiving end of high-speed serial circuit
By designing a half-rate predictive decision feedback circuit, the insufficient feedback loop margin and clock rate challenge of DFE in high-speed signal transmission are solved, and inter-symbol interference can be effectively eliminated and adapted to various channel environments with low power consumption.
Patent Information
- Application Number
- CN202511062879.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-31
- Publication Date
- 2025-11-18
AI Technical Summary
During high-speed signal transmission, existing decision feedback equalizers (DFEs) face challenges such as insufficient feedback loop margin and high clock rate, making it difficult to effectively eliminate inter-symbol interference and adapt to high-attenuation channels.
Design a half-rate predictive decision feedback circuit for the receiver of a high-speed serial circuit, including even-path and odd-path structures, and using components such as adders, slicers, and D flip-flops. By using half-rate and predictive structures, the clock rate requirement is reduced and the loop delay is decreased, and the feedback strength is controlled by a switch array.
It reduces the clock rate requirement, decreases loop delay, adapts to low-power, high-speed scenarios, eliminates more inter-symbol interference, and is suitable for transmission channels with various insertion loss.
Smart Images
Figure CN120979413A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The application belongs to the technical field of circuit design, and particularly relates to a decision feedback circuit for a high-speed serial circuit receiving end. BACKGROUND
[0002] After high-speed signals pass through a channel, the signals at the receiving end will have serious inter-symbol interference (ISI) due to high-frequency loss and reflection of the channel. A conventional continuous-time linear equalizer (CTLE) is a linear equalizer that compensates for high-frequency attenuation of the channel while also amplifying noise, and thus cannot cope with a channel environment with high insertion loss alone. A decision feedback equalizer (DFE) is a nonlinear equalizer that can reduce signal ISI without amplifying noise, and thus is widely used in high-channel-attenuation channels and has become one of the core technologies of high-speed serial links (SerDes) and storage interfaces (such as DDR5).
[0003] DFE dynamically offsets the ISI suffered by the current symbol by feeding back the historical information of the decided symbol in real time, thereby improving signal integrity. However, in high-speed application scenarios, the design of DFE faces challenges such as insufficient feedback loop margin and high clock rate. SUMMARY
[0004] To solve the above problems in the prior art, the application provides a decision feedback circuit for a high-speed serial circuit receiving end.
[0005] The technical problem to be solved by the application is solved by the following technical scheme: The application provides a decision feedback circuit for a high-speed serial circuit receiving end, comprising: an even path structure and an odd path structure. The even path structure and the odd path structure each comprise: an adder, a first slicer, a second slicer, a multiplexer, a first D flip-flop, a second D flip-flop, a third D flip-flop, and a fourth D flip-flop; wherein the output end of the adder is connected to the first input end of the first slicer and the second slicer, the output end of the first slicer is connected to one input end of the multiplexer, the output end of the second slicer is connected to another input end of the multiplexer, the output end of the multiplexer is connected to the input end of the first D flip-flop, the input end and the output end of the first D flip-flop, the second D flip-flop, and the third D flip-flop are connected in sequence, the output end of the first D flip-flop is also connected to the input end of the fourth D flip-flop and the first input end of the adder, the output end of the second D flip-flop is also connected to the second input end of the adder, the output end of the third D flip-flop is used to output data, and the third input end of the adder is used to access an analog input signal Input. The output of the fourth D flip-flop in the even-path structure is connected to the fourth input of the adder in the odd-path structure, and the output of the first D flip-flop in the even-path structure is also connected to the control terminal of the multiplexer in the odd-path structure; similarly, the output of the fourth D flip-flop in the odd-path structure is connected to the fourth input of the adder in the even-path structure, and the output of the first D flip-flop in the odd-path structure is also connected to the control terminal of the multiplexer in the even-path structure; the output of the third D flip-flop in the even-path structure is used to output even-path output data, and the output of the third D flip-flop in the odd-path structure is used to output odd-path output data.
[0006] Compared with the prior art, the beneficial effects of the present invention are as follows: 1) The DFE designed in this invention is a half-rate structure (i.e., the sampling clock period is 1 / 2 of the data symbol width), which reduces the requirement for clock rate. Furthermore, through the tap1 structure of the speculative DFE, the problem of insufficient tap1 loop margin in the traditional direct feedback DFE is eliminated, thereby reducing loop delay. Therefore, compared with other existing DFEs, it can be more adaptable to low-power and high-speed scenarios. 2) The DFE designed in this invention has four feedback taps (tap1~4), which can eliminate more inter-symbol interference caused by prescripts. At the same time, by controlling the feedback strength of different feedback taps through a switch array, the DFE can adapt to various transmission channels with different insertion losses.
[0007] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. Attached Figure Description
[0008] Figure 1 This is a schematic diagram of the architecture of a DFE for a high-speed serial circuit receiver provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of the circuit structure of the adder provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of the circuit structure of the slicer provided in an embodiment of the present invention; Figure 4 This is a schematic diagram illustrating the working principle of the slicer in the even path structure provided in this embodiment of the invention. Figure 5 This is a schematic diagram of the circuit structure of the D flip-flop provided in an embodiment of the present invention; Figure 6 This is a schematic diagram of the architecture of a full-rate direct feedback DFE; Figure 7 This is a schematic diagram of the architecture of a full-rate predictive DFE; Figure 8 is a structural diagram of a slicer based on a CML structure. DETAILED DESCRIPTION
[0009] The application will be described in further detail below with reference to specific embodiments, but the embodiments of the application are not limited thereto.
[0010] The application provides a DFE for a high-speed serial circuit receiving end, which comprises an even path structure and an odd path structure. Both the even path structure and the odd path structure comprise an adder, a first slicer, a second slicer, a multiplexer, a first D flip-flop, a second D flip-flop, a third D flip-flop and a fourth D flip-flop. The output end of the third D flip-flop of the even path structure is used for outputting even path output data, and the output end of the third D flip-flop of the odd path structure is used for outputting odd path output data. Exemplarily, Figure 1 is a structural diagram of a DFE for a high-speed serial circuit receiving end provided by the application. As shown in Figure 1 , both the even path structure and the odd path structure comprise an adder S, a first slicer S1, a second slicer S2, a multiplexer M, a first D flip-flop D1, a second D flip-flop D2, a third D flip-flop D3 and a fourth D flip-flop D4, wherein the output end of S is connected with the first input ends of S1 and S2, the output end of S1 is connected with one input end (i.e. 0 input end) of M, the output end of S2 is connected with the other input end (i.e. 1 input end) of M, the output end of M is connected with the input end of D1, the input end and the output end of D1, D2 and D3 are connected in sequence, and the output end of D1 is also connected with the input end of D4 and the first input end a of S (for example, the red line and the blue line where h2 in Figure 1 is located), the output end of D2 is also connected with the second input end b of S (for example, the red line and the blue line where h4 in Figure 1 is located), the output end of D3 is used for outputting data, and the third input end c of S is used for inputting an analog input signal Input. As shown in Figure 1 , the output end of D4 in the even path structure is connected with the fourth input end d of S in the odd path structure (for example, the blue line where h3 in Figure 1 is located), and the output end of D1 in the even path structure is also connected with the control end of M in the odd path structure (for example, the blue line where h1 in Figure 1 is located); in the same way, the output end of D4 in the odd path structure is connected with the fourth input end d of S in the even path structure (for example, the red line where h3 in Figure 1 is located), and the output end of D1 in the odd path structure is also connected with the control end of M in the even path structure (for example, the red line where h1 in Figure 1(The red line where h1 is located); the output of D3 in the even path structure is used to output the even path output data DATA_EVEN, and the output of D3 in the odd path structure is used to output the odd path output data DATA_ODD.
[0011] In this invention, the clock terminals of D1, D2, D3 and D4 in both the even-path structure and the odd-path structure are used to access a pair of differential clock signals, which consist of a clock signal CKI and a differential signal CKI_B of the clock signal CKI.
[0012] like Figure 1 As shown, the half-rate predictive DFE designed in this invention combines the advantages of half-rate to reduce clock rate requirements with the advantage of reducing loop delay through predictive structure. Therefore, it is more suitable for high-speed application scenarios compared to other DFE structures.
[0013] In some embodiments, the adder of the present invention includes: a main circuit and three sub-circuits with identical circuit structures, and each sub-circuit includes a current source whose input current magnitude is controlled by an external switch array, wherein a pair of output terminals (V) of the main circuit op and V on ) and a pair of output terminals (V) of each sub-circuit op and V on All of these are connected together to serve as the output terminals of the adder. The main circuit and each sub-circuit are also connected to the power supply voltage VDD and ground. The pair of input terminals (VDD, V ... ip and V in ) serves as the third input terminal (V) of the adder ip and V in The first sub-circuit's input pair serves as the first input of the adder (tap2_P and tap2_N), the second sub-circuit's input pair serves as the fourth input of the adder (tap3_P and tap3_N), and the third sub-circuit's input pair serves as the second input of the adder (tap4_P and tap4_N). The main circuit includes MOSFETs, resistors, capacitors, and amplifiers, and each sub-circuit includes a current source and multiple MOSFETs.
[0014] For example, Figure 2 This is a schematic diagram of the circuit structure of the adder provided by the present invention, as shown below. Figure 2 As shown, the main circuit consists of MOSFETs M23~M30, resistors R1~R6, capacitors C1~C2, an amplifier, and some switches. Figure 2 As shown, V ip and V in These are a pair of input terminals of the main circuit, V op and Von These are the two output terminals of the main circuit. The negative input terminal of the amplifier is used to connect to VDD / 2, and the positive input terminal is configured according to... Figure 2 The connection shown is used to connect resistors R1 to R4, and the other components are connected according to... Figure 2 Connect each other using the connection method shown. Continue to refer to [reference needed]. Figure 2 Each sub-circuit includes: MOSFET M31, MOSFET M32, MOSFET M33, MOSFET M34, current source I1, and current source I2; wherein, the current output of I1 and I2 is controlled by an external switch array; the gate of M31 is connected to the gate of M33 and serves as one of the two input terminals of this sub-circuit, tap2_P / tap3_P / tap4_P; the gate of M32 is connected to the gate of M34 and serves as the other of the two input terminals of this sub-circuit, tap2_N / tap3_N / tap4_N; the drain of M31 is connected to the drain of M33 and serves as one of the two output terminals of this sub-circuit, V. on After the drain of M32 is connected to the drain of M34, it serves as the other terminal V of the pair of output terminals of this sub-circuit. op The sources of M33 and M34 are both connected to one end of I1, and the other end of I1 is connected to the power supply voltage VDD. The sources of M31 and M32 are both connected to one end of I2, and the other end of I2 is grounded. Figure 1 and Figure 2 As shown, the adder is connected to a pair of differential input terminals V ip and V in It receives the differential input signal from the AFE (analog front end), and then from V... ip and V in The signal and the feedback signal from the DFF are added together by an adder. The adder has two paths, upper and lower, which receive feedback signals from different DFFs respectively, to obtain the output of the odd / even path adder. R5, R6 and C1, C2 are zero-adjustment resistors / capacitors, which can adjust the gain curve of the adder. R3 and R4 are gain adjustment resistors, which can adjust the output gain and change the amplitude of the output adder to meet the requirements of different PVT conditions.
[0015] In this invention, the first slicer and the second slicer are structurally identical, and their main function is to determine whether the analog signal from the adder is at a 1 or 0 level. Figure 1As shown, the outputs of the odd / even adders correspond to two slicers, whose decision thresholds can be changed by external bias voltages. The two slicers corresponding to the adders are biased by +h1 (increasing the decision threshold) and -h1 (decreasing the decision threshold), respectively. That is, the decision thresholds of both the first and second slicers are adjusted by external bias voltages. Specifically, the external bias voltage connected to the first slicer is used to increase its decision threshold, and the external bias voltage connected to the second slicer is used to decrease its decision threshold. After passing through a single-stage multiplexer (MUX), the two slicers ultimately output a single signal to the subsequent DFF. The MUX's selection of the slicer is mainly determined by the decision result of the previous clock cycle. If the previous clock data dn-1=1, to eliminate the influence of the data's postscript on dn, the MUX selects the output signal of the +h1 slicer; otherwise, it selects the output signal of the -h1 slicer. The first slicer and the second slicer each have a second input terminal, a third input terminal, and a fourth input terminal. In the even-path structure, the second input terminal of both the first and second slicers is used to connect to the clock signal CKI, the third input terminal is used to connect to the differential signal CKI_B of the clock signal CKI, and the fourth input terminal is used to connect to a pair of differential signals (i.e., the aforementioned external bias voltage). In the odd-path structure, the second input terminal of both the first and second slicers is used to connect to the differential signal CKI_B, the third input terminal is used to connect to the clock signal CKI, and the fourth input terminal is used to connect to a pair of differential signals (i.e., the aforementioned external bias voltage). In this invention, the operating modes of each slicer include: track mode and regenerate mode. Furthermore, each slicer includes a first-stage circuit and a second-stage circuit. In track mode, the first-stage circuit samples and amplifies the input; in regenerate mode, the second-stage circuit generates the output signal.
[0016] For example, Figure 3 This is a schematic diagram of the circuit structure of the slicer provided by the present invention. Figure 3 As shown, the first-stage circuit includes MOSFETs M1 to M10, and the second-stage circuit includes MOSFETs M11 to M22. The gate IN of M1... p and the gate IN of M4 n These are a pair of differential input terminals that constitute the first input terminal of the slicer; the gate TH of M3 p and the gate TH of M2 nThese are a pair of differential input terminals forming the fourth input terminal of the slicer; the gates of M7, M8, M9, and M10 are interconnected to form the second input terminal of the slicer; the gates of M5 and M6 are interconnected to form the third input terminal of the slicer; the source of M1 is connected to the drain of M5 and the source of M3 simultaneously, the source of M5 is grounded, the drain of M1 is connected to the drain of M7, the drain of M9, and the drain of M2 simultaneously, the source of M7 is used to connect to the power supply voltage VDD, the source of M9 is grounded, and the drain of M3 is connected to M8... The drains of M11, M4, and M10 are connected simultaneously. The source of M8 is connected to the power supply voltage VDD. The source of M4 is connected to the source of M2 and the drain of M6. The sources of M6 and M10 are both grounded. The gate of M11 is connected to the drains of M9 and M7. The source of M11 is grounded. The drain of M11 is connected to the drains of M13, M19, and M21. The gate of M13 is connected to the gate of M9. The source of M13 is connected to the power supply voltage VDD. The source of M19... The drain of M19 is connected to the drain of M15, the source of M15 is grounded, and the gate of M15 is used to connect to the power supply voltage VDD. The drain of M19 is connected to the gates of M20 and M22 simultaneously. The gate of M19 is connected to the gates of M21, the drains of M20 and M22 simultaneously. The source of M21 is connected to the drain of M16, the source of M16 is used to connect to the power supply voltage VDD, and the gate of M16 is grounded. The source of M20 is connected to the drain of M17, the gate of M17 is connected to the gate of M13, and the source of M17 is grounded. The source of M22 is connected to the drain of M18. The source of M18 is used to connect to the power supply voltage VDD. The gate of M18 is connected to the gate of M6. The drain of M22 is also connected to the drains of M14 and M12. The source of M14 is used to connect to the power supply voltage VDD. The gate of M14 is connected to the gate of M13. The source of M12 is grounded. The gate of M12 is connected to the drains of M10 and M8. The drains of M19 and M20 form a pair of differential output terminals for the slicer. It should be noted that when... Figure 3 When the slicer shown is the first or second slicer in an even-path structure, the gates of M5, M6, and M18 are all used to connect to the differential signal CKI_B of the clock signal CKI, and the gates of M7, M8, M9, M10, M13, M14, and M17 are all used to connect to the clock signal CKI; while when Figure 3 When the slicer shown is the first or second slicer in an odd-path structure, the opposite is true: the gates of M5, M6, and M18 are all used to connect to the clock signal CKI, and the gates of M7, M8, M9, M10, M13, M14, and M17 are all used to connect to the differential signal CKI_B of the clock signal CKI. It should be noted that the terminals connected to the CKI signal and the terminals connected to the CKI_B signal constitute the clock terminals of the slicer.
[0017] The following example, using a slicer in an even-path structure, illustrates the working principle of a slicer. Figure 4 As shown, when CKI=0 and CKI_B=1, the slicer is in the tracking stage. At this time, the tail current transistors M5 and M6 and the load transistors M7 and M8 of the first-stage circuit are turned on, and the input transistors M1~M4 amplify the differential input signal. Simultaneously, the output voltage of the first-stage circuit is transmitted to the positive feedback loop of the second-stage circuit through M11~M14, ensuring the second-stage outputs correct data. When CKI=1 and CKI_B=0, the slicer is in the regenerate stage. At this time, the tail current transistors and load transistors of the first-stage circuit are turned off, and M9 and M10 are turned on, pulling the output voltage of the first-stage circuit down to GND to isolate the influence of the first-stage circuit on the second-stage circuit. M13 and M14 are also turned off, stopping the pull-up of the output node. Meanwhile, in the positive feedback of the second-stage circuit, the tail current source transistors M17 and M18 are turned on, forming a strong positive feedback loop and giving the output strong noise immunity. Finally, the output voltage of the second-stage circuit recovers to full swing and can be directly used in subsequent digital circuits (such as flip-flops, DFFs, etc.) without the need for an additional RS latch.
[0018] In this invention, the first D flip-flop, the second D flip-flop, the third D flip-flop, and the fourth D flip-flop are D flip-flops with identical structures. In some embodiments, the D flip-flop is composed of multiple PMOS transistors and multiple NMOS transistors, and is a two-stage latch circuit connected in series. The D flip-flop has four stages of inverters, and each stage of the latch circuit includes two inverters, each inverter consisting of one PMOS transistor and one NMOS transistor. For example, Figure 5 This is a schematic diagram of a circuit structure of a D flip-flop provided by the present invention. Figure 5 As shown, the D flip-flop is composed of MOS transistors M35 to M58. M35, M36, M39, M40, M43, M45, M47, M48, M51, M52, M55, and M57 are PMOS transistors, and the rest are NMOS transistors. The upper end of the PMOS transistor is the source, and the lower end is the drain; the upper end of the NMOS transistor is the drain, and the lower end is the source. IN represents the input terminal of the D flip-flop, and OUT represents the output terminal. M35 to M58 are arranged according to… Figure 5 Connect using the connection method shown. Figure 5 In this circuit, M35~M46 form the first-stage latch circuit, M47~M58 form the second-stage latch circuit, and M36 and M37 form the first-stage inverter, M45 and M46 form the second-stage inverter, M48 and M49 form the third-stage inverter, and M57 and M58 form the fourth-stage inverter. For example... Figure 5As shown, the gates of M35, M42, M50, and M51 are all connected to the clock signal CKI, and the gates of M38, M39, M47, and M54 are all connected to the differential signal CKI_B of the clock signal CKI. The terminals connected to the CKI signal and the terminals connected to the CKI_B signal constitute the clock terminals of this D flip-flop. Figure 5 As shown, the input signal passes through a total of 4 inverters to the output signal. Meanwhile, since the inverter-based D flip-flop proposed in this invention replaces all transmission gate switches with inverter switches, the signal driving capability becomes stronger, thus greatly reducing the propagation delay of the flip-flop. This makes the architecture of the D flip-flop more suitable for high-speed DFE design.
[0019] After introducing the adder, slicer, and D flip-flop, this invention continues to explain the working principle of the designed DFE. For example... Figure 1 As shown, O+h1 is the output signal of the first slicer in the odd path structure, O-h1 is the output signal of the second slicer in the odd path structure, O is the output signal of the multiplexer in the odd path structure, O1 is the output signal of the first D flip-flop in the odd path structure, O2 is the output signal of the fourth D flip-flop in the odd path structure, and O3 is the output signal of the second D flip-flop in the odd path structure. Similarly, E+h1 is the output signal of the first slicer in the even path structure, E-h1 is the output signal of the second slicer in the even path structure, E is the output signal of the multiplexer in the even path structure, E1 is the output signal of the first D flip-flop in the even path structure, E2 is the output signal of the fourth D flip-flop in the even path structure, and E3 is the output signal of the second D flip-flop in the even path structure. Figure 1 As shown, taking the even-path structure as an example, first observe the tap1 loop. This tap1 loop adopts a predictive structure, that is, it selects the two input signals E+h1 and E-h1 of the MUX through the signal at O1 to obtain the output signal. Next, observe the tap2 loop, which adopts a direct feedback structure, that is, it feeds back the weighted output of E1 to the adder. Similarly, the feedback loops of tap3 and tap4, as well as the case of the ODD path, can be obtained.
[0020] The advantages of the DFE, adder, and slicer designed in this invention will be further illustrated by comparing them with existing DFEs, adders, and slicers.
[0021] Currently, existing DFEs include: Figure 6 The full-rate direct feedback DFE shown is Figure 7 The full-rate prediction formula DFE is shown.
[0022] The existing full-rate direct feedback DFE is called full-rate because the sampling clock period and the data symbol period are the same; the method for eliminating the preamble is to directly use the sampling result of the (n-1)th clock cycle (CLK). The weighted data is fed back to the summer, hence the name direct feedback. The key to this structure's design is meeting loop margin requirements: before the slicer samples the summer output at clock clk (n-1), the decision result at clock clk (n-1) must have already been fed back to the summer output, while allowing sufficient setup time for the slicer's decision. The delays experienced throughout the feedback path are, in order: the delay from the CK trigger edge of the flip-flop to the output, referred to as the propagation delay. The delay from input to output in summer is denoted as... Finally, the input needs to remain stable for a certain period of time before the slicer samples, i.e., the settling time. . The drawbacks of existing full-rate direct feedback DFEs are large feedback loop delay and high clock power consumption.
[0023] The difference between existing full-rate predictive DFE and existing full-rate direct feedback DFE lies in the feedback method. The predictive structure pre-determines the feedback result when the previous data is 1 and the feedback result when the previous data is 0. These two results, dn+h1 and dn-h1, are input to the MUX for selection. The MUX's control signal comes from the decision result of the previous time step; when dn-1 is 1, dn+h1 is selected, and vice versa. Using this scheme, the delay experienced by the entire feedback path is as follows: [details of the delay are missing in the original text]. The delay from the control signal to the output of the MUX circuit is denoted as... Finally, there is the trigger setup delay. While existing full-rate predictive DFEs eliminate the summer delay of analog circuits, both full-rate direct feedback DFEs and full-rate predictive DFEs employ a full-rate architecture. This architecture places higher demands on clock design, posing a bottleneck for high-speed applications. Furthermore, the power consumption resulting from high-speed clocks is another key challenge. In short, the drawbacks of existing full-rate predictive DFEs are their complex structure and high clock power consumption.
[0024] The half-rate predictive DFE proposed in this application has the advantage of reducing clock rate requirements due to its half-rate nature. Combined with the predictive structure's ability to reduce loop delay, it is more suitable for high-speed applications compared to other structures. In other words, the DFE designed in this application has the advantages of low feedback loop delay, low clock rate, and low clock power consumption.
[0025] Specifically, Figure 6 andFigure 7 The advantages and disadvantages of the DFE shown below and the DFE proposed in this application are shown in Table 1: Table 1. Advantages and disadvantages of different DFE architectures
[0026] Currently, existing slicers include: Figure 8 The slicer shown is based on the CML structure. However, the disadvantages of the CML-based slicer are: normally open tail current, high power consumption, non-full-swing output voltage, requirement for an additional RS latch, and inability to be directly used in subsequent digital circuits. In contrast, [the following text is incomplete and requires further context: "compared to..."] Figure 8 The slicer shown in this invention operates in the following modes: track and regenerate. When CLK=0, the first-stage circuit samples and amplifies the input; when CLK=1, the second-stage circuit directly regenerates the output, restoring it to full swing. This design retains the high-speed characteristics of Architecture 1, the low power consumption of Architecture 2, and also features a full-swing output.
[0027] Specifically, Figure 8 The advantages and disadvantages of the slicer shown below and the slicer proposed in this application are shown in Table 2: Table 2. Comparison of advantages and disadvantages of different slicer structures
[0028] It should be noted that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.
[0029] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Furthermore, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.
[0030] In this specification, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude multiple instances. While different embodiments may describe certain measures, this does not mean that these measures cannot be combined to produce a good effect.
[0031] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.
Claims
1. A decision feedback circuit for a high-speed serial circuit receiver, characterized in that, include: Even path structure and odd path structure; Both the even-path structure and the odd-path structure include: an adder, a first slicer, a second slicer, a multiplexer, a first D flip-flop, a second D flip-flop, a third D flip-flop, and a fourth D flip-flop; wherein, the output of the adder is connected to the first input of the first slicer and the second slicer, the output of the first slicer is connected to one input of the multiplexer, the output of the second slicer is connected to the other input of the multiplexer, the output of the multiplexer is connected to the input of the first D flip-flop, the inputs and outputs of the first D flip-flop, the second D flip-flop, and the third D flip-flop are connected sequentially, and the output of the first D flip-flop is also connected to the input of the fourth D flip-flop and the first input of the adder, the output of the second D flip-flop is also connected to the second input of the adder, the output of the third D flip-flop is used to output data, and the third input of the adder is used to receive an analog input signal. The output of the fourth D flip-flop in the even-path structure is connected to the fourth input of the adder in the odd-path structure, and the output of the first D flip-flop in the even-path structure is also connected to the control terminal of the multiplexer in the odd-path structure; similarly, the output of the fourth D flip-flop in the odd-path structure is connected to the fourth input of the adder in the even-path structure, and the output of the first D flip-flop in the odd-path structure is also connected to the control terminal of the multiplexer in the even-path structure; the output of the third D flip-flop in the even-path structure is used to output even-path output data, and the output of the third D flip-flop in the odd-path structure is used to output odd-path output data.
2. The decision feedback circuit for a high-speed serial circuit receiver according to claim 1, characterized in that, The clock terminals of the first D flip-flop, second D flip-flop, third D flip-flop, and fourth D flip-flop in the even-path structure and the odd-path structure are all used to connect to a pair of differential clock signals consisting of clock signal CKI and the differential signal CKI_B of clock signal CKI. Both the first slicer and the second slicer have a second input terminal, a third input terminal, and a fourth input terminal. In the even-path structure, the second input terminal of both the first slicer and the second slicer is used to connect to the clock signal CKI, the third input terminal is used to connect to the differential signal CKI_B of the clock signal CKI, and the fourth input terminal is used to connect to a pair of differential signals. In the odd-path structure, the second input terminal of both the first slicer and the second slicer is used to connect to the differential signal CKI_B, the third input terminal is used to connect to the clock signal CKI, and the fourth input terminal is used to connect to the pair of differential signals.
3. The decision feedback circuit for a high-speed serial circuit receiver according to claim 1, characterized in that, The decision thresholds of the first slicer and the second slicer are adjusted by an external bias voltage. The external bias voltage connected to the first slicer is used to increase the decision threshold of the first slicer, and the external bias voltage connected to the second slicer is used to decrease the decision threshold of the second slicer.
4. The decision feedback circuit for a high-speed serial circuit receiver according to claim 1, characterized in that, The adder includes a main circuit and three sub-circuits with identical circuit structures. Each sub-circuit contains a current source whose input current is controlled by an external switch array. A pair of output terminals of the main circuit are connected to a pair of output terminals of each sub-circuit to serve as the output terminals of the adder. The main circuit and each sub-circuit are also connected to a power supply voltage VDD and ground. A pair of input terminals of the main circuit serve as the third input terminal of the adder, a pair of input terminals of the first sub-circuit serve as the first input terminal of the adder, a pair of input terminals of the second sub-circuit serve as the fourth input terminal of the adder, and a pair of input terminals of the third sub-circuit serve as the second input terminal of the adder.
5. The decision feedback circuit for a high-speed serial circuit receiver according to claim 4, characterized in that, The main circuit includes: MOSFETs, resistors, capacitors, and amplifiers; each sub-circuit includes: MOSFET M31, MOSFET M32, MOSFET M33, MOSFET M34, current source I1, and current source I2; wherein, the current output of current source I1 and current source I2 is controlled by an external switch array; the gate of M31 is connected to the gate of M33 as one of a pair of input terminals, and the gate of M32 is connected to the gate of M34 as the other of a pair of input terminals; the drain of M31 is connected to the drain of M33 as one of a pair of output terminals, and the drain of M32 is connected to the drain of M34 as the other of a pair of output terminals; the source of M33 and the source of M34 are both connected to one end of I1, and the other end of I1 is connected to the power supply voltage VDD; the source of M31 and the source of M32 are both connected to one end of I2, and the other end of I2 is grounded.
6. The decision feedback circuit for a high-speed serial circuit receiver according to claim 2, characterized in that, The first slicer and the second slicer are structurally identical. The slicer has two operating modes: track mode and regenerate mode. The slicer includes a first-stage circuit and a second-stage circuit. In track mode, the first-stage circuit samples and amplifies the input. In regenerate mode, the second-stage circuit generates the output signal.
7. The decision feedback circuit for a high-speed serial circuit receiver according to claim 6, characterized in that, The first stage circuit includes: MOSFET M1, MOSFET M2, MOSFET M3, MOSFET M4, MOSFET M5, MOSFET M6, MOSFET M7, MOSFET M8, MOSFET M9, and MOSFET M10; In this circuit, the gates of M1 and M4 form a pair of differential input terminals constituting the first input terminal of the slicer; the gates of M3 and M2 form a pair of differential input terminals constituting the fourth input terminal of the slicer; the gates of M7, M8, M9, and M10 are interconnected to serve as the second input terminal of the slicer; the gates of M5 and M6 are interconnected to serve as the third input terminal of the slicer; the source of M1 is connected to the drain of M5 and the source of M3, and the source of M5 is grounded; the drain of M1 is connected to the drain of M7, the drain of M9, and the drain of M2, and the source of M7 is used to connect to the power supply voltage VDD; the source of M9 is grounded; the drain of M3 is connected to the drain of M8, the drain of M4, and the drain of M10, and the source of M8 is used to connect to the power supply voltage VDD; the source of M4 is connected to the source of M2 and the drain of M6, and the sources of M6 and M10 are both grounded.
8. The decision feedback circuit for a high-speed serial circuit receiver according to claim 7, characterized in that, The second-stage circuit includes: MOSFET M11, MOSFET M12, MOSFET M13, MOSFET M14, MOSFET M15, MOSFET M16, MOSFET M17, MOSFET M18, MOSFET M19, MOSFET M20, MOSFET M21, and MOSFET M22; In this configuration, the gate of M11 is connected to the drains of M9 and M7 simultaneously, the source of M11 is grounded, the drain of M11 is connected to the drains of M13, M19, and M21 simultaneously, the gate of M13 is connected to the gate of M9, and the source of M13 is used to connect to the power supply voltage VDD, the source of M19 is connected to the drain of M15, the source of M15 is grounded, and the gate of M15 is used to connect to the power supply voltage VDD, the drain of M19 is connected to the gates of M20 and M22 simultaneously, the gate of M19 is connected to the gate of M21, the drains of M20 and M22 simultaneously, the source of M21 is connected to the drain of M16, and the source of M16 is used to connect to the power supply voltage VDD. M16's gate is grounded; M20's source is connected to M17's drain; M17's gate is connected to M13's gate; M17's source is grounded; M22's source is connected to M18's drain; M18's source is connected to the power supply voltage VDD; M18's gate is connected to M6's gate; M22's drain is also connected to both M14 and M12's drains; M14's source is connected to the power supply voltage VDD; M14's gate is connected to M13's gate; M12's source is grounded; M12's gate is connected to both M10 and M8's drains; and M19 and M20's drains form a pair of differential output terminals for the slicer's output.
9. The decision feedback circuit for a high-speed serial circuit receiver according to claim 1, characterized in that, The first D flip-flop, the second D flip-flop, the third D flip-flop, and the fourth D flip-flop are D flip-flops with the same structure. The D flip-flop is composed of two-stage latch circuits connected in series, and the D flip-flop has four stages of inverters.
10. The decision feedback circuit for a high-speed serial circuit receiver according to claim 9, characterized in that, The D flip-flop consists of multiple PMOS transistors and multiple NMOS transistors. Each stage of the latch circuit contains two inverters, each of which consists of one PMOS transistor and one NMOS transistor.