Method for judging pinpoint-shaped defect of substrate of high-voltage device
By spin-coating a measurement layer onto the surface of high-voltage devices and combining it with optical or SEM observation, the problem of the high influence of substrate pinpoint defects on the judgment was solved, enabling precise quality control of high-voltage devices and improving device yield and production efficiency.
Patent Information
- Application Number
- CN202511141537.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-08-15
- Publication Date
- 2025-12-12
AI Technical Summary
Existing technologies lack effective quantitative methods to determine whether the height of substrate pinpoint defects affects the breakdown and reliability of high-voltage devices, making it impossible to accurately assess their impact on the performance of high-voltage devices.
A measurement layer is formed by spin-coating a fluid material. The thickness of the measurement layer is designed to be the maximum defect height that current high-voltage devices can tolerate. Combined with optical or SEM observation, it is determined whether the top of the pinhead defect on the substrate is exposed or level with it, so as to achieve accurate judgment of the defect height.
This technology enables real-time monitoring of the impact of substrate pinpoint defects on the performance of high-voltage devices, preventing substandard silicon wafers from entering subsequent processes, improving device yield, and reducing waste wafer loss.
Smart Images
Figure CN121123045A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the field of semiconductor manufacturing, in particular to a high-voltage device substrate needle-shaped defect judgment method. BACKGROUND
[0002] The semiconductor etching process is used to accurately remove ( "carve" ) thin films or substrates on the surface of a silicon wafer according to a lithographic pattern, so as to transfer the design pattern to the wafer to form transistors, interconnects and various micro-nano structures, which is one of the core steps of building chip circuits.
[0003] During the shallow trench STI and deep trench DTI etching process, due to the structural defects of the substrate itself or the etching process, a substrate needle-shaped defect will be formed. Generally, for ordinary digital ICs or low-voltage devices, this defect will not affect the performance of the device. However, for high-voltage devices and reliability testing, if the defect is exactly in the isolation structure area, because the substrate needle-shaped defect has a certain height A, it will cause the isolation medium thickness B above the substrate needle-shaped defect to be much lower than the normal isolation required isolation medium thickness C, thereby causing breakdown at the substrate needle-shaped defect position and affecting the high-voltage device BV and reliability.
[0004] When the height A of the substrate needle-shaped defect is less than a certain size, and the isolation medium thickness B meets the high-voltage isolation requirement, the substrate needle-shaped defect can be considered to have no effect, so it is very important to determine the height A of the substrate needle-shaped defect.
[0005] Substrate needle-shaped defects are ubiquitous and cannot be completely removed. Whether they have an impact depends on their location and the height A of the substrate needle-shaped defect. The former can be determined whether it exists in the high-voltage isolation area through a conventional defect detection mechanism, but the latter lacks effective quantitative means to accurately calibrate the value of A and establish a corresponding monitoring mechanism. SUMMARY
[0006] A series of simplified concepts are introduced in the summary section, which are simplifications of existing prior art in the field. This will be further described in the detailed description section. The summary section of the present application does not mean to attempt to limit the key features and necessary technical features of the claimed technical solution, nor does it attempt to determine the protection scope of the claimed technical solution.
[0007] The technical problem to be solved by the present application is to provide a high-voltage device substrate needle-shaped defect judgment method for determining whether the height of the substrate needle-shaped defect affects the BV and reliability of the high-voltage device by measuring the layer.
[0008] To solve the above technical problems, the high-voltage device substrate needle-shaped defect judgment method provided by the present application comprises the following steps:
[0009] S1, confirm the existence of substrate tip defects by defect scanning;
[0010] S2, spin coating a material with flowability which has no influence on the process to form a measurement layer, the thickness of the measurement layer is the maximum height of the substrate tip defects which can be tolerated by the current high voltage device;
[0011] S3, judge whether the wafer is qualified according to whether the top of the substrate tip defects exposes the measurement layer.
[0012] Preferably, the high voltage device substrate tip defect judging method is further improved, the thickness of the measurement layer is determined by slicing or optical measurement to reach the maximum height of the substrate tip defects which can be tolerated by the process.
[0013] Preferably, the high voltage device substrate tip defect judging method is further improved, whether the top of the substrate tip defects exposes the measurement layer is observed by optical or SEM.
[0014] Preferably, the high voltage device substrate tip defect judging method is further improved, the following steps are used to replace steps S2-S4 when implementing steps S2-S4;
[0015] S2', spin coating a material with flowability which has no influence on the process to form a measurement layer, the thickness of the measurement layer is the same as the height of the highest substrate tip defects;
[0016] S3', judge whether the wafer is qualified according to the comparison result of the thickness of the measurement layer and the maximum height of the substrate tip defects which can be tolerated by the current high voltage device.
[0017] Preferably, the high voltage device substrate tip defect judging method is further improved, the thickness of the measurement layer is determined by optical measurement to be the same as the height of the highest substrate tip defects.
[0018] Preferably, the high voltage device substrate tip defect judging method is further improved, the spin coating material is PR, BARC or SOC.
[0019] Preferably, the high voltage device substrate tip defect judging method is further improved, the position and quantity of the substrate tip defects are marked online by defect scanning.
[0020] The present application provides two solutions for judging whether the height of the substrate tip defects has influence on the BV and reliability of the high voltage device based on the thickness of the measurement layer and the height of the top of the substrate tip defects;
[0021] The first solution is to design the thickness of the measurement layer to be the maximum height of the substrate tip defects which can be tolerated by the current high voltage device; then, as long as the top of the substrate tip defects does not expose the measurement layer, the substrate must meet the design requirements.
[0022] Secondly, the thickness of the measuring layer is designed to be the same as the height of the top of the substrate needle-shaped defects, that is, to be at the same level; then, the thickness of the measuring layer is the same as the height of the highest substrate needle-shaped defects (the highest substrate needle-shaped defects are the most likely to cause breakdown), and the height of the substrate needle-shaped defects is expressed by the thickness of the measuring layer, the height of the substrate needle-shaped defects can be obtained by slicing, and then the obtained height of the substrate needle-shaped defects is compared with the maximum height of the substrate needle-shaped defects that can be tolerated by the current high-voltage device to determine whether the silicon wafer is qualified; that is, if the obtained height of the substrate needle-shaped defects is greater than the maximum height of the substrate needle-shaped defects that can be tolerated by the current high-voltage device, it is determined that the silicon wafer is unqualified, and vice versa.
[0023] In combination with the online defect scanning technology, the present application can monitor in real time whether the substrate needle-shaped defects will affect the performance of the high-voltage device, avoid the silicon wafer that cannot meet the design requirements from flowing into the subsequent process, and thus improve the device yield and reduce the loss caused by the waste wafer. BRIEF DESCRIPTION OF DRAWINGS
[0024] The drawings of the present application are intended to show the general characteristics of the methods, structures and / or materials used in the specific exemplary embodiments according to the present application, and to supplement the description in the specification. However, the drawings of the present application are schematic drawings that are not drawn to scale, and therefore may not accurately reflect the precise structure or performance characteristics of any given embodiment, and the drawings of the present application should not be interpreted as limiting or restricting the scope of values or attributes encompassed by the exemplary embodiments according to the present application. The present application will be further described in detail below in conjunction with the specific embodiments and the accompanying drawings:
[0025] Figure 1 is the height A of the substrate needle-shaped defects, Substrate tip defects The schematic diagram showing the relationship between the thickness B of the upper isolation medium and the thickness C of the isolation medium.
[0026] Figure 2 is the schematic diagram of the first embodiment of the present application.
[0027] Figure 3 is the schematic diagram of the second embodiment of the present application. DETAILED DESCRIPTION
[0028] The advantages and effects of the present application can be fully understood by those skilled in the art from the description of the specific embodiments. The present application can also be implemented or applied in different specific embodiments, and the details in the description can be applied based on different views, with various modifications or changes without departing from the general design idea of the present application. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict. The exemplary embodiments of the present application can be implemented in various forms, and should not be interpreted as being limited to the specific embodiments described herein. It should be understood that these embodiments are provided to make the disclosure of the present application complete and complete, and to fully convey the technical solutions of these exemplary embodiments to those skilled in the art. It should be understood that when an element is referred to as "connected" or "coupled" to another element, the element can be directly connected or coupled to the other element, or there can be an intermediate element. Different is that when an element is referred to as "directly connected" or "directly coupled" to another element, there is no intermediate element. In all the drawings, the same reference signs always represent the same elements. As used herein, the term "and / or" includes any combination and all combinations of one or more related listed items.
[0029] First embodiment
[0030] Reference Figure 2 As shown, the present application provides a high-voltage device substrate needle-shaped defect judgment method, comprising the following steps:
[0031] S1, confirm the existence of substrate needle-shaped defects by defect scanning;
[0032] S2, spin coating a material with fluidity that has no effect on the process to form a measurement layer, and the thickness of the measurement layer is the maximum height H of the substrate needle-shaped defect that can be tolerated by the current high-voltage device; that is, under the condition that the current isolation medium thickness C is a constant value and no breakdown occurs, the maximum height of the substrate needle-shaped defect allowed is H; then, the substrate needle-shaped defect with a height exceeding the maximum height H will inevitably cause breakdown;
[0033] Optionally, the spin-coated material is PR, BARC or SOC;
[0034] S3, determine whether the silicon wafer is qualified according to whether the top of the substrate needle-shaped defect exposes the measurement layer; if the top of the substrate needle-shaped defect exposes the measurement layer, it is determined that the silicon wafer is unqualified, otherwise it is determined that the silicon wafer is qualified;
[0035] Wherein, the thickness of the measurement layer is determined to reach the maximum height of the substrate needle-shaped defect that can be tolerated by the process through slicing or optical measurement; whether the top of the substrate needle-shaped defect exposes the measurement layer is observed by optical or SEM.
[0036] Second embodiment;
[0037] Reference Figure 3 As shown in the drawings, the present application provides a high voltage device substrate needle-like defect judgment method, comprising the following steps:
[0038] S1, confirm the existence of substrate needle-like defects through defect scanning;
[0039] S2', spin coating a material with fluidity which has no influence on the process to form a measurement layer, the thickness of the measurement layer is level with the height of the highest substrate needle-like defect; optionally, the spin coating material is PR, BARC or SOC;
[0040] S3', judge whether the silicon wafer is qualified according to the comparison result of the thickness of the measurement layer and the maximum height H of the substrate needle-like defect which can be tolerated by the current high voltage device; that is, express the height of the highest substrate needle-like defect through the thickness of the measurement layer (the highest one will not cause breakdown, then the lower substrate needle-like defect will not cause breakdown either) comparison, if the thickness of the measurement layer is greater than the maximum height of the substrate needle-like defect which can be tolerated by the current high voltage device, then judge that the silicon wafer is unqualified, otherwise, judge that the silicon wafer is qualified;
[0041] Wherein, the optical measurement determines that the thickness of the measurement layer is level with the height of the highest substrate needle-like defect, and the position and number of the substrate needle-like defects are marked online through defect scanning.
[0042] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
[0043] The present application has been described in detail by specific implementation and examples, but these do not constitute a limitation on the present application. Those skilled in the art can also make many modifications and improvements without departing from the principles of the present application, and these should also be considered as the protection scope of the present application.
Claims
1. A method for judging pinpoint defects in high-voltage device substrates, characterized in that, Includes the following steps: S1, defect scanning confirmed the presence of a needle-like defect in the substrate; S2, spin coating forms a measurement layer with a fluid material that has no impact on the process. The thickness of the measurement layer is the maximum height of the substrate pinpoint defects that current high voltage devices can tolerate. S3 determines whether the silicon wafer is qualified based on whether the top of the needle-like defect in the substrate exposes the measuring layer.
2. The method for judging pin-tip defects in high-voltage device substrates as described in claim 1, characterized in that: The thickness of the measurement layer is determined by slicing or optical measurement to reach the maximum height of the substrate pinpoint defects that the process can tolerate.
3. The method for judging pin-tip defects in high-voltage device substrates as described in claim 1, characterized in that: The measurement layer is exposed at the top of the pinpoint defect in the substrate by optical or SEM observation.
4. The method for judging pin-tip defects in high-voltage device substrates as described in claim 1, characterized in that, The following steps are used instead of steps S2-S4; S2', spin coating forms a measurement layer with a fluid material that has no impact on the process, and the thickness of the measurement layer is level with the height of the highest substrate pinpoint defect; S3' determines whether the silicon wafer is qualified based on the comparison between the thickness of the measured layer and the maximum height of the substrate pinpoint defect that the current high voltage device can tolerate.
5. The method for judging pin-tip defects in high-voltage device substrates as described in claim 4, characterized in that: Optical measurements determined that the thickness of the measurement layer was level with the height of the highest substrate pinpoint defect.
6. The method for judging pin-tip defects in high-voltage device substrates as described in claim 1 or 4, characterized in that: Spin-coating materials are PR, BARC, or SOC.
7. The method for judging pin-tip defects in high-voltage device substrates as described in claim 1 or 4, characterized in that: The location and number of needle-like defects in the substrate are marked online by defect scanning.