Electronic device

Abstract

The invention provides an electronic device which comprises a substrate, a plurality of transistors arranged on the substrate, a light-emitting unit arranged on at least one of the plurality of transistors, a first insulating layer arranged on the light-emitting unit and an optical unit. The first insulating layer has a first opening and a second opening, and the optical unit is disposed in the first opening. In a plan view direction of the electronic device, the first opening overlaps at least a portion of the light emitting unit, and the second opening overlaps at least a portion of at least one of the plurality of transistors.

Description

TECHNICAL FIELD

[0001] The present application relates to an electronic device, and in particular, to an electronic device including a hole structure. BACKGROUND

[0002] As the number or types of film layers on the circuit layer of an electronic device increase, the detection and / or repair steps of electronic elements (e.g., transistors) in the circuit layer can be affected by the film layers on the circuit layer, and can result in the problem of ineffective repair of the electronic elements. In addition, some elements (e.g., alignment elements) provided in the electronic device can be obscured by the film layers on the circuit layer and lose their functions. Therefore, how to solve the above problems is still an important issue in the art. SUMMARY

[0003] The present application aims to provide an electronic device including a hole structure, wherein the hole structure can be used to assist in the performance of a specific process or reduce the impact of film layers on the circuit layer on specific elements.

[0004] In some embodiments, the present application provides an electronic device including a substrate, a plurality of transistors disposed on the substrate, a light emitting unit disposed on at least one of the plurality of transistors, a first insulating layer disposed on the light emitting unit, and an optical unit. The first insulating layer has a first opening and a second opening, and the optical unit is disposed in the first opening. In a top-down direction of the electronic device, the first opening overlaps at least a portion of the light emitting unit, and the second opening overlaps at least a portion of at least one of the plurality of transistors. BRIEF DESCRIPTION OF DRAWINGS

[0005] Figure 1 FIG. 1 is a partial cross-sectional view of an electronic device according to a first embodiment of the present application.

[0006] Figure 2 FIG. 2 is a partial top-down view of an electronic device according to a second embodiment of the present application.

[0007] Figure 3 FIG. 3 is a cross-sectional view of a transistor of an electronic device according to the second embodiment of the present application.

[0008] Figure 4 FIG. 4 is a partial top-down view of an electronic device according to a third embodiment of the present application.

[0009] Figure 5 FIG. 5 is a partial top-down view of an electronic device according to a fourth embodiment of the present application.

[0010] Figure 6 FIG. 6 is a partial top-down view of an electronic device according to a fifth embodiment of the present application.

[0011] Figure 7Partial top view schematic diagram of an electronic device according to a sixth embodiment of the present application.

[0012] Figure 8 Partial top view schematic diagram of an electronic device according to a variant of the sixth embodiment of the present application.

[0013] Figure 9 Partial sectional view schematic diagram of an electronic device according to a seventh embodiment of the present application.

[0014] Figure 10 Partial sectional view schematic diagram of an electronic device according to an eighth embodiment of the present application.

[0015] Figure 11 Partial sectional view schematic diagram of an electronic device according to a ninth embodiment of the present application.

[0016] Figure 12 Flowchart of a manufacturing method of an electronic device according to a first embodiment of the present application.

[0017] Figure 13 Partial sectional view schematic diagram of an electronic device according to a tenth embodiment of the present application.

[0018] Figure 14 Flowchart of a manufacturing method of an electronic device according to a tenth embodiment of the present application.

[0019] Legend: A1 - first area; A2 - second area; AD - adhesive layer; AR - anti-reflective layer; BF - buffer layer; CF1 - first filter layer; CF2 - second filter layer; CF3 - third filter layer; CFL - filter layer structure; CL - circuit layer; CO - cover layer; CP1, CP2 - capacitor element; CR - channel region; CT - contact; DA - active area; DCU - dummy optical unit; DD - display device; DE, DE1, DE2, DE3 - drain electrode; DG, D3, DS, D4, DRD, D2, D1 - width; DH - depth; DI - driving circuit; DR - drain region; DW1, DW2 - spacer structure; E1, E2 - electrode; ED - electronic device; F1, F2, K1, K2 - distance; FC - functional layer; FL - fill layer; GE, G1, G2, G3 - gate electrode; H1, H2 - thickness; HL1, HL2, VL1, VL2 - virtual straight line; IN2, IN3, IN4, IN1, INS, IN5, IN6, I1, I2, INL, IN7, IN8, IN9, IN0, OIL, IL1, IL2 - insulating layer; L1 - light ray; LCU, LCU1, LCU2, LCU3 - optical unit; LEL - light emitting layer; LR1, LR2, LR3 - laser emitter; LU - light emitting unit; M1, M2, M0, M3, ML - conductive layer; M100 - manufacturing method; NDA - peripheral area; OB - object; OC - optical layer; OD - optical sensor; OF1 - first filter opening; OF2 - second filter opening; OF3 - third filter opening; OP, OPE - opening; OP1 - first opening; OP2 - second opening; OP3 - third opening; PPL - pattern layer; PX, PX1, PX2, PX3, PX4, PX5 - pixel; QD - quantum dot; RG, R1, RS, R3, RD, R2 - range; S100, S101, S102, S103, S104, S105, S106, S107, S108, S109, S110, S111, S200, S201, S202, S203, S204, S205, S206, S207, S208, S209, S210, S211, S212 - step; SB - substrate, first substrate; SB1 - second substrate; SE, S1, S2, S3 - source electrode; SL - sealing layer; SM, OL - semiconductor; SPX - sub-pixel; SR - source region; SS1 - first substrate structure; SS2 - second substrate structure; T1 - transistor; TD - driving transistor; TS - sensing transistor; TU - stylus; TW - switching transistor; V1 - via; WS - wiring structure; X, Y, Z - direction; A-A', B-B' - tangent. DETAILED DESCRIPTION

[0020] The present application can be understood more readily by reference to the following detailed description and drawings and can be learned by the practice of the application. It is noted that for purposes of the reader's understanding, the application is described in terms of particular embodiments and illustrative drawings. Those of skill in the art will appreciate that the application is not limited to the embodiments or illustrations.

[0021] In this detailed description of the application and in the claims, certain terms have specific meanings as set forth in the Glossary of Special Terms. Those of skill in the art will appreciate that electronic device manufacturers can refer to the same element by different names. The present application does not intend to distinguish between those elements that function the same but have different names.

[0022] In this detailed description of the application and in the claims, the words "comprise," "comprises" and "comprising" are to be interpreted inclusively rather than exclusively. That is, the word "comprising" and variations thereof such as "comprises" and "comprise" are to be construed to cover the various components, additives and methodologies unconditionally and do not preclude the additional existence of unsubstantiated elements or limitations.

[0023] It will be understood that when an element or film layer is referred to as being "on" or "connected to" another element or film layer, it can be directly on or connected to the other element or film layer or intervening elements or film layers can be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element or film layer, there are no intervening elements or film layers present. When an element or film layer is referred to as being "electrically connected" to another element or film layer, it can be directly electrically connected or indirectly electrically connected. The electrically connected or coupled as described in the present application can refer to direct connection or indirect connection. In the case of direct electrical connection, the terminals of the two circuit components are directly connected or connected to each other with a conductor segment, and in the case of indirect electrical connection, there can be a switch, diode, capacitor, inductor, resistor, other suitable component, or a combination of the above components between the terminals of the two circuit components, but not limited thereto.

[0024] Although the terms "first," "second," "third," etc. can be used in this disclosure to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. The terms "first," "second," "third," and so on are not necessarily used to describe a sequence or order. Thus, a first element, component, region, layer or section in the present disclosure can be a second element, component, region, layer or section in the claims.

[0025] In the present application, the measurement of thickness, length and width can be by optical microscopy, and the thickness or width can be measured from a cross-sectional image in an electron microscope, but not limited thereto.

[0026] Additionally, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and this application and will not be interpreted in an overly literal or overly formal sense unless expressly so defined herein.

[0027] Further, the phrases "between approximately and approximately" or "between substantially and substantially" or "between approximately and approximately" are generally interpreted to mean within plus or minus 10% of the given value, or within plus or minus 5%, plus or minus 3%, plus or minus 2%, plus or minus 1%, or plus or minus 0.5% of the given value.

[0028] If the first direction is perpendicular to the second direction, the angle between the first direction and the second direction can be between 80 degrees and 100 degrees; if the first direction is parallel to the second direction, the angle between the first direction and the second direction can be between 0 degrees and 10 degrees.

[0029] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and this application and will not be interpreted in an overly literal or overly formal sense unless expressly so defined herein.

[0030] It must be noted that as the following examples can be substituted, reorganized, mixed to complete other examples without departing from the spirit of the present application.

[0031] The electronic device of the present application can include a light emitting device, a display device, a sensing device, a backlight device, an antenna device, a tiled device, or other suitable electronic device, but is not limited thereto. The electronic device of the present application can be a foldable, flexible, or stretchable electronic device. The display device can include a non-self-emissive display device or a self-emissive display device. The non-self-emissive display device includes, for example, a liquid crystal display device, but is not limited thereto. The self-emissive display device includes, for example, a light emitting diode display device, but is not limited thereto. The display device can be applied, for example, to a notebook computer, a public display, a tiled display, a vehicle display, a touch display, a television, a monitor, a smartphone, a tablet, a light source module, a lighting device, or an electronic device applied to the above products, but is not limited thereto. The sensing device can include a biosensor, a touch sensor, a fingerprint sensor, other suitable sensor, or a combination of the above types of sensors. The antenna device can include, for example, a liquid crystal antenna device, but is not limited thereto. The tiled device can include, for example, a display tiled device or an antenna tiled device, but is not limited thereto. The electronic device can have a rectangular, circular, polygonal, curved edge shape, or other suitable shape. The electronic device can include an electronic unit, wherein the electronic unit can include passive elements and active elements, such as capacitors, resistors, inductors, diodes, transistors, sensors, etc. The diode can include a light emitting diode or a photodiode. The light emitting diode can include, for example, an organic light emitting diode (OLED), a quantum light-emitting diode (QLED or QDLED), or an in-organic light emitting diode, which can include, for example, a mini LED, a micro LED, or a quantum dot LED, but is not limited thereto. The electronic device can have a driving system, a control system, a light source system, or other peripheral systems to support the display device, the antenna device, a wearable device (including, for example, augmented reality or virtual reality), a vehicle-mounted device (including, for example, an automobile windshield), or a tiled device. Hereinafter, the present application will be described with the display device as an example, but the present application is not limited thereto. The electronic device of the present application can be various combinations of the above devices, such as a combination of the display device and other devices, but is not limited thereto.

[0032] Please refer to Figure 1 , Figure 1This is a partial cross-sectional schematic diagram of an electronic device according to a first embodiment of the present invention. The electronic device ED of the present invention may include a light-emitting device for emitting light. In one embodiment, the electronic device ED may include a display device DD for displaying a screen or image, but is not limited thereto. In some embodiments, the electronic device ED may include a combination of the display device DD and other types of devices. Figure 1 As shown, an electronic device ED may include a substrate SB, a circuit layer CL disposed on the substrate SB, an electronic unit (e.g., a light-emitting unit LU) disposed on the circuit layer CL, and an optical unit LCU disposed on the light-emitting unit LU, but is not limited thereto. It should be noted that the structure of the electronic device ED is not limited to this. Figure 1 The description is limited to what is shown and may include other components and / or films. The structure of each film or component of the electronic device ED is described in detail below.

[0033] A substrate SB can be used to support components and films located thereon. The substrate SB may comprise a rigid or flexible material. Rigid materials include, for example, glass, quartz, sapphire, ceramic, other suitable materials, or combinations thereof. Flexible materials include, for example, polyimide (PI), polycarbonate (PC), polyethylene terephthalate (PET), other suitable materials, or combinations thereof. In some embodiments, the substrate SB may comprise a multilayer structure, not... Figure 1 The above is the limit.

[0034] The circuit layer CL may include various wires, circuits, and electronic units applicable to an electronic device ED. The electronic units may include any suitable active and / or passive components. The circuit layer CL may include any suitable structure formed by stacking conductive and insulating layers, wherein the conductive layers can be used to form the aforementioned wires, circuits, or electronic units. According to this embodiment, the circuit layer CL may include a plurality of transistors, capacitors, nodes, and / or signal feed lines, for example... Figure 1 The transistor T1 is shown. It should be noted that... Figure 1 The structure of only one transistor T1 is shown as an example, and the structures of other transistors are not shown, but are not limited to the structure of transistor T1. In other words, the electronic device ED includes a plurality of transistors disposed on the substrate SB. The plurality of transistors in the circuit layer CL can serve as driving units, switching units, sensing driving units, or other suitable electronic units. For example, Figure 1The transistor T1 shown can be electrically connected to the light-emitting unit LU in the electronic device ED to drive the light-emitting unit LU; that is, transistor T1 can serve as a driving unit for the light-emitting unit LU, but is not limited thereto. The transistors (e.g., transistor T1) in the circuit layer CL can include, but are not limited to, thin-film transistors (TFTs). Specifically, as... Figure 1 As shown, the circuit layer CL may include a buffer layer BF, a semiconductor SM disposed on the buffer layer BF, a conductive layer M1 disposed on the semiconductor SM, and a conductive layer M2 disposed on the conductive layer M1. The conductive layer M1 may form the gate electrode GE of the transistor T1, while the conductive layer M2 may form the source electrode and drain electrode DE of the transistor T1. In one embodiment, the circuit layer CL may further include a conductive layer M0 disposed between the buffer layer BF and the substrate SB. The gate electrode GE of the transistor T1 may correspond to the channel region of the semiconductor SM, while the source electrode and drain electrode DE of the transistor T1 may be electrically connected to the source region and drain region of the semiconductor SM, respectively. It should be noted that... Figure 1 The source electrode and the channel region, source region, and drain region of the semiconductor SM are not shown; they are indicated by [label / description]. Figure 3 The conductive layers M1 and M2 may comprise any suitable conductive material, such as a metal, but are not limited thereto. The semiconductor SM may comprise any suitable semiconductor material. For example, the material of the semiconductor SM in this embodiment may comprise metal oxides (e.g., indium gallium zinc oxide (IGZO)), a-IGZO (amorphous IGZO), crystalline IGZO, spinel-type IGZO crystal structures, C-Axis Aligned Crystal IGZO hybrid films, nc-IGZO (nanocrystalline IGZO, intermediate between single-crystal IGZO and amorphous IGZO), native crystalline IGZO films (a mixed form of amorphous and nanocrystalline phases), polycrystalline spinel-type IGZO, but is not limited thereto. In other embodiments, the material of the semiconductor SM may comprise low-temperature polysilicon (LTPS) or amorphous silicon (a-Si), but is not limited thereto. In other embodiments, the semiconductor SM material of some transistors may be a metal oxide material, and the semiconductor SM material of some transistors may be low-temperature polycrystalline silicon. Although Figure 1The illustrated transistor T1 is a top gate thin film transistor, but the present embodiments are not limited thereto. In some embodiments, the transistor T1 can include a bottom gate thin film transistor, a dual gate or double gate thin film transistor, a multi-gate thin film transistor, or other types of thin film transistors. The plurality of transistors in the electronic device ED can be the same or different types of transistors. As Figure 1 illustrated, the electronic device ED can further include an insulating layer IN2 disposed between the gate electrode GE (or the conductive layer M1) and the semiconductor SM. The insulating layer IN2 can serve as a gate insulating layer in the transistor T1. Note that, although Figure 1 The illustrated insulating layer IN2 is a patterned film layer, but the present embodiments are not limited thereto. In some embodiments, the insulating layer IN2 can be a continuous film layer disposed on the semiconductor SM and the buffer layer BF. The electronic device ED can further include an insulating layer IN3 disposed between the conductive layer M1 and the conductive layer M2, and an insulating layer IN4 disposed on the conductive layer M2. The insulating layers IN2, IN3, and IN4 can include any suitable insulating material.

[0035] In some embodiments, the transistor T1 can further include a semiconductor OL disposed on the substrate SB. In other words, the transistor T1 can include two layers of semiconductors (i.e., the semiconductor SM and the semiconductor OL). The semiconductor OL can be disposed between the semiconductor SM and the substrate SB. For example, the semiconductor OL can be disposed directly on the buffer layer BF, but the present embodiments are not limited thereto. In the top-down direction (i.e., the direction Z) of the electronic device ED, the semiconductor SM can at least partially overlap the semiconductor OL. In some embodiments, the electronic device ED can further include an insulating layer IN1 disposed between the semiconductor SM and the semiconductor OL. Specifically, the insulating layer IN1 can be disposed directly on the upper surface of the semiconductor OL and directly contact the semiconductor OL. The semiconductor SM can be electrically connected to the semiconductor OL. In this case, the source electrode SE (not shown) and / or the drain electrode DE of the transistor T1 can be electrically connected to the semiconductor SM and the semiconductor OL. For example, the semiconductor SM can be electrically connected to the semiconductor OL through the conductive layer M2 or the conductive layer M1. Figure 1 Figure 1 ​For example, a conductive layer M2 may be filled with vias passing through a buffer layer BF and an insulating layer IN1 to contact the semiconductor OL, thereby electrically connecting it to the semiconductor OL, but this is not a limitation. In other embodiments, the semiconductor SM may be electrically connected to the semiconductor OL through other conductive layers. In some embodiments, the semiconductor SM may be electrically connected to the semiconductor OL through multiple conductive layers. The insulating layer IN1 may include a metal oxide material, such as aluminum oxide, but is not limited to it. The insulating layer IN1 may serve as an etching stopping layer and / or a waterproof oxygen layer, thereby protecting the semiconductor OL. The material of the semiconductor OL may include indium zinc oxide (In-Zn-O), indium gallium zinc tin oxide (In-Ga-Zn-Sn-O), indium gallium tin oxide (In-Ga-Sn-O), or indium tin zinc oxide (In-Sn-Zn-O), but is not limited to it. The crystal structure of the semiconductor OL may differ from that of the semiconductor SM. For example, the semiconductor OL may include a polycrystalline oxide material, but is not limited to it. The atomic percentage content of indium in the semiconductor OL material can be greater than that of zinc, and the atomic percentage content of zinc can be greater than that of gallium. The atomic percentage contents of indium and gallium in the semiconductor SM material can be greater than those of indium and gallium, respectively, in the semiconductor OL material. The atomic percentage content of oxides in the semiconductor OL material can be greater than that of oxides in the semiconductor SM material. In this embodiment, the carrier mobility of the semiconductor OL can be greater than that of the semiconductor SM. In this case, by including the semiconductor OL electrically connected to the semiconductor SM in the transistor T1, the overall carrier mobility of the semiconductor in the transistor T1 can be improved. For example, after providing the semiconductor OL, the carrier mobility of the transistor's semiconductor (including the semiconductor SM and the semiconductor OL) can be greater than 50 cm⁻¹. 2 / Vs, but not limited thereto. This improves the performance of transistor T1, and consequently improves the performance of electronic device ED. In this embodiment, semiconductor SM may have a thickness H1, and semiconductor OL may have a thickness H2, wherein thickness H2 may be less than thickness H1. Thicknesses H1 and H2 are indicated by... Figure 3 It was not marked as such. Figure 1The comparison of the thickness H1 of semiconductor SM and the thickness H2 of semiconductor OL can be performed on the portion where semiconductor SM and semiconductor OL overlap. Specifically, it can be first determined that semiconductor SM overlaps a portion of semiconductor OL, and the maximum thickness of that portion of semiconductor SM is defined as thickness H1. Similarly, it can be first determined that semiconductor OL overlaps a portion of semiconductor SM, and the maximum thickness of that portion of semiconductor OL is defined as thickness H2. In other embodiments, thicknesses H1 and H2 can be defined in other suitable ways and are not limited to the above. It should be noted that the feature of transistor T1 including semiconductor OL is not limited to all transistors applied to circuit layer CL. For example, in some embodiments, a portion of the transistors may include semiconductor OL, while another portion of the transistors may not include semiconductor OL.

[0036] In some embodiments, the circuit layer CL may further include a capacitor element, wherein the capacitor element may be formed from different conductive and insulating layers in the circuit layer CL. For example, as Figure 1 As shown, the circuit layer CL may include capacitor elements CP1 and CP2, which may be formed by conductive layers M1 and M2 and an insulating layer IN3 sandwiched between conductive layers M1 and M2, but are not limited thereto. In other embodiments, capacitor elements CP1 and CP2 may be formed by other conductive layers. Capacitor elements CP1 and CP2 can be used to stabilize the voltage when the electronic device ED displays the screen, thereby improving the display effect of the electronic device ED, but are not limited thereto.

[0037] In some embodiments, the circuit layer CL may further include a trace structure WS, wherein the trace structure WS may be formed by a conductive layer in the circuit layer CL. Specifically, the electronic device ED may include an active region DA and a peripheral region NDA. The active region DA may be an area in the electronic device ED that serves a primary function (such as displaying an image, emitting light, or being operable by a user). In this embodiment, the active region DA may be defined as the smallest rectangular or smallest area shape surrounded by the outer edge of the outermost light-emitting unit LU (e.g., the outer edge of the light-emitting layer LEL of the light-emitting unit LU), but is not limited thereto. In other embodiments, the shape, location, or extent of the active region DA may be defined by any suitable method. The peripheral region NDA may be defined as other areas in the electronic device ED besides the active region DA, such as non-display areas or non-light-emitting areas. Figure 1As shown, the trace structure WS can be disposed within the peripheral area NDA. In this embodiment, the trace structure WS can be formed by conductive layers M0, M1, M2, and M3. Specifically, the electronic device ED may further include conductive layer M0, wherein conductive layer M0 can be directly disposed on the surface of substrate SB and can extend on the surface of substrate SB to electrically connect to external electronic components. Figure 1 (Not shown). Conductive layer M1 can be electrically connected to conductive layer M0 through a via through buffer layer BF. Electronic device ED may also include insulating layer INS disposed between insulating layer IN3 and insulating layer IN4, and conductive layer M2 can be electrically connected to conductive layer M1 through a via through insulating layer INS and insulating layer IN3. Electronic device ED may also include conductive layer M3, wherein conductive layer M3 may be disposed on insulating layer I2 and electrically connected to conductive layer M2. Conductive layers (e.g., conductive layers M2 and M3) in wiring structure WS may extend within active region DA and / or peripheral region NDA of electronic device ED and be electrically connected to any suitable electronic component (e.g., transistor T1, but not limited thereto) of electronic device ED. In some embodiments, conductive layer M3 may be disposed at other suitable locations of electronic device ED. Thus, electronic components in electronic device ED can be electrically connected to external electronic components through wiring structure WS. The materials of conductive layer M0 and conductive layer M3 may refer to the materials of conductive layer M1 and conductive layer M2 described above. Insulating layer INS may include any suitable insulating material. It should be noted that... Figure 1 The wiring structure WS shown is merely exemplary, and the present invention is not limited thereto. In other embodiments, the conductive layers in the wiring structure WS can be connected in any manner, allowing electronic components in the electronic device ED to be electrically connected to external electronic components.

[0038] Although Figure 1 Only transistor T1, located within the active region DA, is shown; however, the circuit layer CL may include transistors located in the peripheral region NDA. That is, transistors in the circuit layer CL may be located in the active region DA and / or the peripheral region NDA of the electronic device ED. Furthermore, Figure 1 The structure of the circuit layer CL shown is merely exemplary, and the present invention is not limited thereto. The circuit layer CL may also include other suitable components or films depending on the design of the electronic device ED.

[0039] According to this embodiment, as Figure 1As shown, the electronic device ED may also include an insulating layer IN5, which may be disposed on the circuit layer CL and may cover components in the circuit layer CL, such as transistor T1, capacitor element CP1, capacitor element CP2, etc., but is not limited thereto. The upper surface of the insulating layer IN5 (or the surface away from the circuit layer CL) may be a flat surface to facilitate the placement of other components and / or film layers thereon. In this case, the insulating layer IN5 may serve as a planarization layer. The insulating layer IN5 may include any suitable insulating material.

[0040] The electronic unit may be disposed on the insulating layer IN5. In one embodiment, the electronic unit may include a light-emitting unit LU as a light source for the electronic device ED. The light-emitting unit LU may include, but is not limited to, a light-emitting diode. In this embodiment, the electronic device ED may include an organic light-emitting diode display device, and the light-emitting unit LU may include an organic light-emitting diode, but is not limited to, for example, such as Figure 1 As shown, the light-emitting unit LU may include an electrode E1, an electrode E2, and a light-emitting layer LEL disposed between the electrodes E1 and E2. Electrode E1 may be disposed on an insulating layer IN5, the light-emitting layer LEL may be disposed on electrode E1, and electrode E2 may be disposed on the light-emitting layer LEL. One of the electrodes E1 and E2 may be an anode, and the other may be a cathode. For example, electrode E1 may be an anode, and electrode E2 may be a cathode, but this is not a limitation. Electrode E1 may include any suitable conductive material, such as a metallic material or a transparent conductive material, but this is not a limitation. Electrode E2 may include any suitable conductive material, such as a transparent conductive material, but this is not a limitation. The electronic device ED may also include an insulating layer IN6 disposed on the insulating layer IN5, wherein the insulating layer IN6 may include an opening OP that partially covers the electrode E1 and exposes a portion of the electrode E1. A portion of the light-emitting layer LEL may be disposed within the opening OP of the insulating layer IN6. Specifically, a light-emitting unit LU can be composed of a portion of electrode E1 exposed by an opening OP, a portion of the light-emitting layer LEL disposed within the opening OP, and a corresponding portion of electrode E2 disposed within the opening OP. In this case, the range of a light-emitting unit LU can be defined, for example, by the range of the portion of the light-emitting layer LEL disposed within the opening OP, but is not limited thereto. Therefore, the insulating layer IN6 can serve as a pixel defining layer and include a plurality of openings OP. Although Figure 1Only one light-emitting unit LU is shown, but the electronic device ED may include a plurality of light-emitting units LU, each disposed in one of the plurality of openings OP of the insulating layer IN6. Electrode E1 may be electrically connected to transistor T1 (e.g., the drain electrode DE of transistor T1), thereby electrically connecting the light-emitting unit LU to transistor T1. In other words, the light-emitting unit LU may be disposed on at least one transistor (e.g., transistor T1) and electrically connected to that transistor. It should be noted that, although... Figure 1 Only one light-emitting unit LU is shown, but the electronic device ED may include a plurality of light-emitting units LU, each of which may be disposed on at least one transistor and electrically connected to the transistor.

[0041] In some embodiments, the electronic device ED may further include insulating layers IL1, OIL, and IL2 disposed on the light-emitting unit LU. Specifically, insulating layers IL1, OIL, and IL2 may be disposed on the electrode E2. Insulating layers IL1, OIL, and IL2 may serve as encapsulation layers for encapsulating the components, light-emitting unit LU, and film layers between themselves and the substrate SB. Furthermore, insulating layer IL2 may have a flat upper surface to facilitate the placement of other components and film layers thereon. In this embodiment, insulating layers IL1 and IL2 may comprise any suitable transparent inorganic material, while insulating layer OIL may comprise any suitable transparent organic material. In other words, the aforementioned encapsulation layer may be formed by alternating stacks of inorganic and organic insulating layers.

[0042] In some embodiments, such as Figure 1 As shown, the electronic device ED may further include an insulating layer I1 disposed between insulating layers IN5 and IL1, and an insulating layer I2 disposed on insulating layer IL2. Insulating layers I1 and I2 may comprise any suitable insulating material. Insulating layer I2 may isolate the optical unit LCU from the packaging layer (including insulating layers IL1, OIL, and IL2) and the components or films beneath it. In this case, the conductive layer M3 in the aforementioned wiring structure WS may be electrically connected to the conductive layer M2, for example, through vias passing through insulating layers I2, IL2, IL1, IN5, and IN4, but is not limited thereto.

[0043] In some embodiments, the electronic device ED can further include a dam wall structure DW1 disposed on the insulating layer IN5. The dam wall structure DW1 can be formed by patterning the insulating layer IN6. Specifically, the insulating layer IN6 after being patterned to have a protruding shape can serve as the dam wall structure DW1, which can be used to reduce the possibility of water vapor and / or oxygen from invading the interior of the electronic device ED, thereby achieving the effect of protecting the electronic elements within the electronic device ED. The electrode E1, the light emitting layer LEL, and the insulating layer IL1 can extend over the dam wall structure DW1, but the disclosure is not limited thereto. The dam wall structure DW1 can be disposed in the peripheral region NDA of the electronic device ED.

[0044] In some embodiments, a portion of the light emitting layer LEL disposed in one of the openings OP of the insulating layer IN6 can include a via V1, wherein the via V1 can expose a portion of the electrode E1, and the electrode E2 can fill the via V1 and contact the portion of the electrode E1 exposed by the via V1. In addition, the portion of the electrode E1 exposed by the via V1 can be electrically connected to the conductive layer M2 in the circuit layer CL, and electrically connected to the semiconductor SM through the conductive layer M2, and electrically connected to the semiconductor OL through the semiconductor SM, but the disclosure is not limited thereto. Through the above design, the electrode E1 and the electrode E2 can be electrically connected to a voltage source through the conductive layer M2, the semiconductor SM, and the semiconductor OL, thereby reducing the impedance of the electrodes (i.e., the electrode E1 and the electrode E2) in the light emitting unit LU, so as to improve the performance of the light emitting unit LU. It should be noted that the portion of the light emitting layer LEL including the via V1 can not serve as a light emitting region in the light emitting unit LU. In some embodiments, the portion of the electrode E1 exposed by the via V1 can be electrically connected to a voltage source by other suitable means, and is not limited to the above means.

[0045] In this embodiment, the optical unit LCU can be disposed on the insulating layer I2. The optical unit LCU can include any suitable material that can change the wavelength or color of the light passing through the optical unit LCU, or can change the light-emitting angle of the light. The optical unit LCU can include quantum dots, fluorescent, phosphorescent, scattering particles, other suitable materials, or a combination thereof. For example, the optical unit LCU of this embodiment can include quantum dots QD, but is not limited thereto. The optical unit LCU can correspond to the light-emitting unit LU. Specifically, the electronic device ED further includes an insulating layer INL disposed on the light-emitting unit LU, wherein the insulating layer INL can include a first opening OP1, and the optical unit LCU can be disposed in the first opening OP1. In other words, the optical unit LCU in this embodiment can be formed by disposing the quantum dots QD in the first opening OP1 of the insulating layer INL, but is not limited thereto. The first opening OP1 can penetrate the insulating layer INL, and can expose a film layer (such as the insulating layer I2, but is not limited thereto) located below the insulating layer INL. The insulating layer INL can include any suitable light-blocking material, such as black resin, gray resin, scattering particles, other suitable materials, or a combination thereof. The above-mentioned "the optical unit LCU corresponds to the light-emitting unit LU" can mean that, in the top-down direction of the electronic device ED, the optical unit LCU overlaps at least a portion of the light-emitting unit LU. Here, "the optical unit LCU overlaps at least a portion of the light-emitting unit LU" can mean that the optical unit LCU overlaps at least a portion of the light-emitting layer LEL of the light-emitting unit LU, but is not limited thereto. In this case, the first opening OP1 of the insulating layer INL can overlap at least a portion of the light-emitting unit LU in the top-down direction of the electronic device ED. The optical unit LCU can be used to change the wavelength or color of the light emitted by the light-emitting unit LU to which it corresponds, or to change the light-emitting angle of the light emitted by the light-emitting unit LU to which it corresponds. It should be noted that, although Figure 2 Only one optical unit LCU is shown, but the electronic device ED can include a plurality of optical units LCU, and each optical unit LCU can be disposed in a first opening OP1 of the insulating layer INL and correspond to one of the light-emitting units LU. In this case, the insulating layer INL can include a plurality of first openings OP1, and each of the plurality of first openings OP1 can overlap at least a portion of one of the light-emitting units LU in the top-down direction of the electronic device ED. The plurality of optical units LCU in the electronic device ED can change the light to have different wavelengths or colors or different light-emitting angles, but is not limited thereto. For example, as shown in FIG. 1C, the electronic device ED can include a plurality of optical units LCU, and each optical unit LCU can be disposed in a first opening OP1 of the insulating layer INL and correspond to one of the light-emitting units LU. In this case, the insulating layer INL can include a plurality of first openings OP1, and each of the plurality of first openings OP1 can overlap at least a portion of one of the light-emitting units LU in the top-down direction of the electronic device ED. The plurality of optical units LCU in the electronic device ED can change the light to have different wavelengths or colors or different light-emitting angles, but is not limited thereto. Figure 1As shown, the electronic device ED can include an optical unit LCU1, an optical unit LCU2, and an optical unit LCU3, and the light rays passing through the optical unit LCU1, the optical unit LCU2, and the optical unit LCU3 can be red light, green light, and blue light, respectively, and can be mixed to white light, but the present application is not limited thereto. Figure 1 The structure of the optical unit LCU1 disposed in the first opening OP1 is shown only exemplarily. In some embodiments, as shown in FIG. 1C, the optical unit LCU1 can be disposed in the active region DA. Figure 1 As shown, the electronic device ED can further include a dummy optical unit DCU disposed in the non-active region NDA, wherein the dummy optical unit DCU can not correspond to a light emitting unit LU. The dummy optical unit DCU can be disposed, for example, in the non-active region NDA adjacent to the active region DA, but the present application is not limited thereto.

[0046] According to the present application, the insulating layer INL can further include a second opening OP2 in addition to the first opening OP1 described above, wherein no optical unit LCU can be disposed in the second opening OP2. Specifically, the insulating layer INL can have a plurality of openings, wherein a portion of the plurality of openings can be the first opening OP1 described above in which the optical unit LCU can be disposed, and another portion of the plurality of openings can be an opening OPE in which no optical unit LCU is disposed, and the second opening OP2 can be one of the openings OPE. The second opening OP2 (or the opening OPE) can pass through the insulating layer INL and can expose a film layer located below the insulating layer INL. According to the present application, the second opening OP2 of the insulating layer INL can overlap at least a portion of at least one transistor in the circuit layer CL in the top view direction of the electronic device ED. The above-mentioned "the second opening OP2 overlaps at least a portion of the transistor" can include embodiments in which the second opening OP2 overlaps at least one of a source electrode (or source) and a drain electrode (or drain) of the transistor in the top view direction of the electronic device ED. For example, as shown in FIG. 1C, the second opening OP2 can overlap at least a portion of the source electrode S of the transistor T in the top view direction of the electronic device ED. Figure 1As shown, the insulating layer INL can include the second opening OP2 overlapping the transistor Tl, but not limited thereto. In this case, the second opening OP2 can overlap at least one of the source electrode (not shown) and the drain electrode DE of the transistor Tl in the top-down direction of the electronic device ED, or can overlap both the source electrode and the drain electrode DE of the transistor Tl. The second opening OP2 can also overlap the gate electrode GE, the semiconductor SM, and / or the semiconductor OL (if any) of the transistor Tl, but not limited thereto. In other words, the electronic device ED of the present disclosure can include a plurality of transistors disposed on the substrate SB, a light emitting unit LU disposed on at least one of the plurality of transistors (e.g., the transistor Tl), and an insulating layer INL disposed on the light emitting unit LU, wherein the insulating layer INL can include a first opening OP1 overlapping at least a portion of the light emitting unit LU and a second opening OP2 overlapping at least a portion of the at least one transistor (e.g., the transistor Tl). Note that the "opening OPE overlapping at least a portion of the transistor" described in the present disclosure can include a case where at least one of the openings OPE overlaps at least a portion of the transistor. Specifically, in some embodiments, the insulating layer INL can include a plurality of openings OPE in which the optical unit LCU is not disposed, wherein a portion of the plurality of openings OPE (e.g., the second opening OP2) can overlap at least a portion of the at least one transistor, and another portion of the plurality of openings OPE (e.g., another opening OPE shown) can not overlap the transistor. In the present embodiment, at least a portion of each transistor (i.e., at least one of the source electrode and the drain electrode) in the circuit layer CL can overlap at least one opening OPE (e.g., the second opening OP2) of the insulating layer INL in the top-down direction of the electronic device ED, but not limited thereto. In some embodiments, the opening OPE can overlap at least a portion of other electronic elements in the top-down direction of the electronic device ED, depending on the design of the electronic device ED. The range definition of the source electrode and the drain electrode in the transistor will be described in detail below. Figure 1 As shown, the insulating layer INL can include the second opening OP2 overlapping the transistor Tl, but not limited thereto. In this case, the second opening OP2 can overlap at least one of the source electrode (not shown) and the drain electrode DE of the transistor Tl in the top-down direction of the electronic device ED, or can overlap both the source electrode and the drain electrode DE of the transistor Tl. The second opening OP2 can also overlap the gate electrode GE, the semiconductor SM, and / or the semiconductor OL (if any) of the transistor Tl, but not limited thereto. In other words, the electronic device ED of the present disclosure can include a plurality of transistors disposed on the substrate SB, a light emitting unit LU disposed on at least one of the plurality of transistors (e.g., the transistor Tl), and an insulating layer INL disposed on the light emitting unit LU, wherein the insulating layer INL can include a first opening OP1 overlapping at least a portion of the light emitting unit LU and a second opening OP2 overlapping at least a portion of the at least one transistor (e.g., the transistor Tl). Note that the "opening OPE overlapping at least a portion of the transistor" described in the present disclosure can include a case where at least one of the openings OPE overlaps at least a portion of the transistor. Specifically, in some embodiments, the insulating layer INL can include a plurality of openings OPE in which the optical unit LCU is not disposed, wherein a portion of the plurality of openings OPE (e.g., the second opening OP2) can overlap at least a portion of the at least one transistor, and another portion of the plurality of openings OPE (e.g., another opening OPE shown) can not overlap the transistor. In the present embodiment, at least a portion of each transistor (i.e., at least one of the source electrode and the drain electrode) in the circuit layer CL can overlap at least one opening OPE (e.g., the second opening OP2) of the insulating layer INL in the top-down direction of the electronic device ED, but not limited thereto. In some embodiments, the opening OPE can overlap at least a portion of other electronic elements in the top-down direction of the electronic device ED, depending on the design of the electronic device ED. The range definition of the source electrode and the drain electrode in the transistor will be described in detail below.

[0047] In some embodiments, the electronic device ED can further include an insulating layer IN7, an insulating layer IN8, and an insulating layer IN9 disposed on the insulating layer INL. The insulating layer IN7, the insulating layer IN8, and the insulating layer IN9 can extend over the insulating layer INL and can fill in the second opening OP2 (or the opening OPE). In other words, a portion of the insulating layer IN7, the insulating layer IN8, and the insulating layer IN9 can be disposed in the second opening OP2 (or the opening OPE). The insulating layer IN7 and the insulating layer IN9 can be inorganic layers and include any suitable transparent inorganic material. The insulating layer IN8 can be an organic layer and include any suitable transparent organic material or a material with a relatively low refractive index. In this embodiment, the material of the insulating layer IN8 can have a lower refractive index than other organic layers in the electronic device ED (e.g., the insulating layer OIL, but not limited thereto). In this way, the light extraction efficiency of the electronic device ED can be improved and / or the interference caused by the external ambient light incident on the electronic device ED can be reduced. In some embodiments, the electronic device ED can further include a barrier structure DW2 disposed on the insulating layer IN7. The barrier structure DW2 can be formed by patterning the insulating layer IN8. Specifically, the insulating layer IN8 can have a protruding shape after being patterned and can serve as the barrier structure DW2, which can be used to reduce the possibility of moisture and / or oxygen invading the interior of the electronic device ED. The insulating layer IN9 can extend over the barrier structure DW2, but not limited thereto. The barrier structure DW2 can be disposed in the peripheral region NDA of the electronic device ED.

[0048] According to this embodiment, the electronic device ED can further include a first filter layer CF1, a second filter layer CF2, and a third filter layer CF3 disposed on the optical unit LCU (or the insulating layer INL), where the first filter layer CF1, the second filter layer CF2, and the third filter layer CF3 can respectively allow light of a specific color to pass through. The first filter layer CF1, the second filter layer CF2, and the third filter layer CF3 may, for example, include a color filter, but not limited thereto. In this embodiment, the first filter layer CF1, the second filter layer CF2, and the third filter layer CF3 can respectively allow red light, green light, and blue light to pass through, but not limited thereto. In other words, the first filter layer CF1, the second filter layer CF2, and the third filter layer CF3 can respectively include a red color filter layer, a green color filter layer, and a blue color filter layer. In this embodiment, the first filter layer CF1, the second filter layer CF2, and the third filter layer CF3 can be stacked and form a filter layer structure CFL. For example, as shown in FIG. 1, the filter layer structure CFL can include a first filter layer CF1, a second filter layer CF2, and a third filter layer CF3 stacked in this order. In this embodiment, the first filter layer CF1, the second filter layer CF2, and the third filter layer CF3 can be disposed on the optical unit LCU (or the insulating layer INL), but not limited thereto. For example, the first filter layer CF1, the second filter layer CF2, and the third filter layer CF3 can be disposed on the insulating layer INL, but not limited thereto. Figure 1As shown, a first filter layer CF1, a second filter layer CF2, and a third filter layer CF3 can be sequentially disposed on the insulating layer IN9 to form a filter layer structure CFL. The arrangement order of the first filter layer CF1, the second filter layer CF2, and the third filter layer CF3 in the filter layer structure CFL is merely exemplary and is not limited to this embodiment. The filter layer structure CFL can extend on the insulating layer INL and can fill the second opening OP2 (or opening OPE) of the insulating layer INL. Specifically, as... Figure 1 As shown, the first filter layer CF1, the second filter layer CF2, and the third filter layer CF3 can be filled into the second opening OP2 (or opening OPE) of the insulating layer INL, that is, a portion of the first filter layer CF1, the second filter layer CF2, and the third filter layer CF3 can be disposed in the second opening OP2 (or opening OPE). Furthermore, in this embodiment, the filter layer structure CFL corresponding to a portion of an optical unit LCU may only include a filter layer with the same color as the light emitted after passing through the optical unit LCU. Here, "the filter layer structure CFL corresponding to a portion of an optical unit LCU" can refer to the filter layer structure CFL overlapping a portion of the optical unit LCU in the top view direction of the electronic device ED. For example, as... Figure 1 As shown, the light passing through the optical unit LCU1 is red light, and the portion of the filter layer structure CFL corresponding to the optical unit LCU1 may only include a red color filter layer, i.e., the first filter layer CF1. Specifically, the second filter layer CF2 and the third filter layer CF3 in the portion of the filter layer structure CFL corresponding to the optical unit LCU1 can be removed (e.g., through a patterning process of the second filter layer CF2 and the third filter layer CF3) so that the optical unit LCU1 corresponds only to the first filter layer CF1 in the filter layer structure CFL. In this case, after removing a portion of the second filter layer CF2 and the third filter layer CF3, an opening corresponding to the optical unit LCU1 can be formed. In short, with Figure 1 Taking the structure shown as an example, the electronic device ED may include a first filter layer CF1, a second filter layer CF2, and a third filter layer CF3 disposed on the insulating layer INL. A portion of the first filter layer CF1, the second filter layer CF2, and the third filter layer CF3 may be disposed in the second opening OP2. In the top view of the electronic device ED, the first filter layer CF1 may overlap with the optical unit LCU1, while the second filter layer CF2 and the third filter layer CF3 may not overlap with the optical unit LCU1. Similarly, when light passes through... Figure 1 When the optical unit LCU2 emits green light, the portion of the filter layer structure CFL corresponding to the optical unit LCU2 may only include the second filter layer CF2, meaning that the first filter layer CF1 and the third filter layer CF3 do not correspond to the optical unit LCU2; however, when light passes through... Figure 1When the optical unit LCU3 emits blue light, the portion of the color filter layer structure CFL corresponding to the optical unit LCU3 can only include the third color filter layer CF3, i.e., the first color filter layer CF1 and the second color filter layer CF2 do not correspond to the optical unit LCU3. It is noted that the portion of the color filter layer structure CFL corresponding to the dummy optical unit DCU located in the non-display area NDA can include the first color filter layer CF1, the second color filter layer CF2 and the third color filter layer CF3, i.e., the color filter layers of the portion can not be removed.

[0049] According to the present embodiment, the electronic device ED can further include a protective layer disposed on the color filter layer structure CFL. The protective layer can refer to a combination of film layers located on the color filter layer structure CFL, or in other words, the protective layer can include a structure formed by a stack of film layers on the color filter layer structure CFL. As shown in Figure 1 The protective layer of the electronic device ED of the present embodiment can include an optical layer OC, an adhesive layer AD, a cover layer CO and an anti-reflection layer AR, but is not limited thereto. The optical layer OC can be disposed on the color filter layer structure CFL, and the adhesive layer AD can be disposed on the optical layer OC. The optical layer OC can include any suitable element or film layer that can improve the light emission effect of the electronic device ED. The adhesive layer AD can include any suitable transparent adhesive material. The cover layer CO can be attached to the optical layer OC through the adhesive layer AD. The cover layer CO can provide a protection effect for the film layers or elements located thereunder. The cover layer CO can include glass, for example, but is not limited thereto. The anti-reflection layer AR can be disposed on the cover layer CO to improve the light emission effect of the electronic device ED. A portion of the film layers in the protective layer can be filled into the second openings OP2 (or in other words, the openings OPE) of the insulating layer INL. For example, as shown in Figure 2 A portion of the optical layer OC in the protective layer can be filled into the second openings OP2 (or in other words, the openings OPE), for example, as shown in Figure 3 The film layers included in the protective layer shown are only exemplary, and the present application is not limited thereto. In other embodiments, the protective layer can include other suitable elements or film layers according to the design of the electronic device ED. In addition, although Figure 2 Not shown, in some embodiments, the electronic device ED can further include a touch layer, wherein the touch layer can be disposed at any suitable position in the electronic device ED.

[0050] Please refer to Figure 3 and Figure 2 , Figure 2 is a partial top view of an electronic device according to a second embodiment of the present application, Figure 2 is a cross-sectional view of a transistor of the electronic device according to the second embodiment of the present application. For simplicity of the drawings, Figure 2 only a partial structure of the insulating layer INL is shown. Specifically, Figure 1The diagram illustrates the arrangement of an optical unit LCU1, an optical unit LCU2, and an optical unit LCU3 within an opening in an insulating layer INL. As described above, the insulating layer INL can be patterned to form a plurality of openings, which can be divided into a first opening OP1 in which an optical unit LCU is disposed and an opening OPE in which no optical unit LCU is disposed. Therefore, in Figure 2 In the partial top view of the insulating layer INL shown, the insulating layer INL may include three first openings OP1, in which optical units LCU1, LCU2, and LCU3 are respectively disposed, while other openings in the insulating layer INL that do not have optical units LCU may be openings OPE. Openings OPE may include second openings OP2, and in the top view of the electronic device ED, the second opening OP2 may overlap at least a portion of the transistors in the circuit layer CL. For example, Figure 2 This illustrates the case where the second opening OP2 overlaps with the transistor T1 in a top view of the electronic device ED. In this case, Figure 2 A portion of the structure shown can correspond to Figure 3 The diagram shows a top view of the structure along the tangent A-A'. It should be noted that, although... Figure 3 As not shown, the electronic device ED may include another transistor, and another opening OPE may overlap at least a portion of the other transistor in the top view of the electronic device ED. In some embodiments, a portion of the opening OPE may not overlap the transistor. Figure 2 The pattern of the insulating layer INL shown is merely exemplary and is not intended to limit this embodiment. In other embodiments, the insulating layer INL may have any suitable pattern depending on the design of the electronic device ED (e.g., the placement of the optical unit LCU or transistors), thereby forming a first opening OP1 for placing the optical unit LCU and an opening OPE (e.g., including a second opening OP2) that may overlap at least a portion of the transistor.

[0051] Figure 3 A cross-sectional view of a transistor (e.g., transistor T1) in an electronic device ED is shown. Specifically, Figure 3 The structure shown can be Figure 3 The structure shown is a cross-sectional view along the tangent B-B'. For example... Figure 2As shown, the transistor T1 can include a semiconductor SM, a gate electrode GE, a source electrode SE, and a drain electrode DE, but the disclosure is not limited thereto. In some embodiments, the transistor T1 can further include a semiconductor OL electrically connected to the semiconductor SM. The gate electrode GE can be formed by the conductive layer M1, and the source electrode SE and the drain electrode DE can be formed by the conductive layer M2, but the disclosure is not limited thereto. In the present embodiment, the electronic device ED can further include a plurality of data lines and a plurality of scan lines (not shown in the figure), wherein one of the plurality of scan lines can be electrically connected to the gate electrode GE, or in other words, the scan line and the gate electrode GE can be formed by patterning the conductive layer M1. One of the plurality of data lines can be electrically connected to the source electrode SE, or in other words, the data line and the source electrode SE can be formed by patterning the conductive layer M2. The plurality of scan lines can extend in a direction, wherein the extension direction of the scan line can be the extension direction of the conductive layer M1 used to form the gate electrode GE of the transistor T1. For example, in the present embodiment, the extension direction of the conductive layer M1 used to form the gate electrode GE of the transistor T1 can be parallel to the direction X, i.e., the extension direction of the scan line can be parallel to the direction X, but the disclosure is not limited thereto. The plurality of data lines can extend in another direction that is not parallel to the extension direction of the scan line. According to the present embodiment, the ranges of the gate electrode GE, the source electrode SE, and the drain electrode DE in the transistor T1 can be defined in a cross-sectional view of the transistor T1. Specifically, the gate electrode GE, the source electrode SE, and the drain electrode DE of the transistor T1 can be defined in a cross-sectional view of the transistor T1 perpendicular to the extension direction of the scan line, i.e., the direction Y. The following illustrates the definition of the ranges of the gate electrode GE, the source electrode SE, and the drain electrode DE of the transistor T1 by way of example of the structure shown in the figure. Figure 2 The structure shown in the figure is used as an example to illustrate the definition of the ranges of the gate electrode GE, the source electrode SE, and the drain electrode DE of the transistor T1, wherein Figure 2 A cross-sectional view of the transistor T1 perpendicular to the extension direction of the scan line, i.e., the direction Y, is shown.

[0052] According to the present embodiment, the gate electrode GE of the transistor T1 can have a range RG in a cross-sectional view of the transistor T1, where the range RG of the gate electrode GE can be defined by a range R1 of a portion of the conductive layer M1 overlapping the semiconductor SM. Specifically, in a cross-sectional view of the transistor T1 perpendicular to the extension direction of the scan line, the range R1 of the portion of the conductive layer M1 overlapping the semiconductor SM can be first identified, and a width DG of the range R1 can be measured. The width DG can be the maximum width of the range R1 measured in a direction (i.e., the direction Y) perpendicular to the extension direction of the scan line. Then, the range RG of the gate electrode GE can be defined by extending the range R1 by 0.25 times the width (i.e., the width DG) of the range R1 on each of the left and right sides of the range R1, respectively. In other words, in the cross-sectional view of the transistor T1, the left and right sides of the range RG can protrude from the left and right sides of the range R1 by a distance of 0.25 times the width DG of the range R1, respectively. In this case, the range RG can have a width D3, where the width D3 is 1.5 times the width DG (i.e., D3 = 1.5*DG). The width D3 can be the maximum width of the range RG measured in a direction (i.e., the direction Y) perpendicular to the extension direction of the scan line. The width D3 can also be considered as the width of the gate electrode GE. The range RG of the gate electrode GE of the transistor T1 can be defined in the above-described manner.

[0053] According to the present embodiment, the source electrode SE of the transistor T1 can have a range RS in a cross-sectional view of the transistor T1, where the range RS of the source electrode SE can be defined by a range R3 of a portion of the conductive layer M2 contacting the source region SR of the semiconductor SM. Specifically, in a cross-sectional view of the transistor T1 perpendicular to the extension direction of the scan line, the range R3 of the portion of the conductive layer M2 overlapping the source region SR of the semiconductor SM can be first identified, and a width DS of the range R3 can be measured. The width DS can be the maximum width of the range R3 measured in a direction (i.e., the direction Y) perpendicular to the extension direction of the scan line. Specifically, the width DS can be the width measured on the side where the conductive layer M2 contacts the source region SR of the semiconductor SM. Then, the range RS of the source electrode SE can be defined by extending the range R3 by 0.25 times the width (i.e., the width DS) of the range R3 on each of the left and right sides of the range R3, respectively. In other words, in the cross-sectional view of the transistor T1, the left and right sides of the range RS can protrude from the left and right sides of the range R3 by a distance of 0.25 times the width DS of the range R3, respectively. In this case, the range RS can have a width D4, where the width D4 is 1.5 times the width DS (i.e., D4 = 1.5*DS). The width D4 can be the maximum width of the range RS measured in a direction (i.e., the direction Y) perpendicular to the extension direction of the scan line. The width D4 can also be considered as the width of the source electrode SE. The range RS of the source electrode SE of the transistor T1 can be defined in the above-described manner.

[0054] According to the present embodiment, the drain electrode DE of the transistor T1 can have a range RD in a cross-sectional view of the transistor T1, where the range RD of the drain electrode DE can be defined by a range R2 of the portion of the conductive layer M2 in contact with the drain region DR of the semiconductor SM. Specifically, in a cross-sectional view of the transistor T1 perpendicular to the extension direction of the scan line, the range R2 of the portion of the conductive layer M2 in contact with the drain region DR of the semiconductor SM can be first identified, and a width DRD of the range R2 can be measured. The width DRD can be the maximum width of the range R2 measured in a direction perpendicular to the extension direction of the scan line, i.e., the direction Y. Specifically, the width DRD can be the width measured on the side of the conductive layer M2 in contact with the drain region DR of the semiconductor SM. Then, the range RD of the drain electrode DE can be defined by extending the range R2 by 0.25 times the width of the range R2, i.e., the width DRD, on each of the left and right sides of the range R2. In other words, in the cross-sectional view of the transistor T1, the left and right sides of the range RD can protrude from the left and right sides of the range R2 by a distance of 0.25 times the width DRD of the range R2. In this case, the range RD can have a width D2, where the width D2 is 1.5 times the width DRD, i.e., D2 = 1.5*DRD. The width D2 can be the maximum width of the range RD measured in a direction perpendicular to the extension direction of the scan line, i.e., the direction Y. The width D2 can also be considered as the width of the drain electrode DE. The range RD of the drain electrode DE of the transistor T1 can be defined in the above-described manner.

[0055] After the ranges of the gate electrode GE, the source electrode SE, and the drain electrode DE of the transistor T1 are defined, the above-mentioned "the second opening OP2 overlaps at least one of the drain electrode DE and the source electrode SE in the transistor T1" can mean that, as viewed in the top-down direction of the electronic device ED, or in a cross-sectional view of the electronic device ED, e.g., a cross-sectional view perpendicular to the extension direction of the scan line, a projection of the second opening OP2 on the substrate SB can overlap at least one of a projection of the range RD of the drain electrode DE on the substrate SB and a projection of the range RS of the source electrode SE on the substrate SB, or in other words, a range of the projection of the second opening OP2 on the substrate SB can cover at least one of the projection of the range RD on the substrate SB and the projection of the range RS on the substrate SB. It is noted that the above-mentioned manner of defining the gate electrode GE, the source electrode SE, and the drain electrode DE of the transistor T1 can be applied to other transistors of the circuit layer CL. In the present disclosure, when describing that an opening, e.g., the opening OPE, of the insulating layer INL overlaps at least a portion of a transistor, or describing that one element overlaps another element, the definition of "overlap" can be referred to the above, and thus will not be described again.

[0056] According to the present embodiment, as Figure 2As shown, the second opening OP2 may have a width D1, where the width D1 may be the width of the second opening OP2 measured in a direction parallel to the extension direction of the scan line (i.e., parallel to direction X). That is, the extension direction of the width D1 may be perpendicular to direction X, for example, parallel to direction Y, but is not limited thereto. Specifically, in the top view of the insulating layer INL (e.g., Figure 2 In this embodiment, the width D1 can be defined as the maximum width of the second opening OP2 measured in a direction parallel to the extension direction of the scan line, but is not limited thereto. In this case, the width D1 of the second opening OP2, the width D2 of the drain electrode DE of transistor T1, the width D3 of the gate electrode GE of transistor T1, and the width D4 of the source electrode SE of transistor T1 can be the widths measured in the same direction (i.e., parallel to direction X). According to this embodiment, the width D1 of the second opening OP2 can range from 15 micrometers (μm) to 45 μm (i.e., 15 μm ≤ D1 ≤ 45 μm), but is not limited thereto. In some embodiments, the width D1 of the second opening OP2 can range from 20 μm to 40 μm (i.e., 20 μm ≤ D1 ≤ 40 μm). The definition and range of the widths of other openings OPE of the insulating layer INL can refer to the width D1 of the second opening OP2 described above. When the width D1 of the second opening OP2 is less than 15 μm, the size of the second opening OP2 may be too small, thus increasing the difficulty of overlapping with the transistor T1. When the width of the second opening OP2 is greater than 45 μm, the size of the second opening OP2 may be too large, thus reducing the light-shielding effect of the insulating layer INL.

[0057] In some embodiments, Figure 1 The second opening OP2 shown may overlap the gate electrode GE of transistor T1, and the width D1 of the second opening OP2 may be greater than the width D3 of the gate electrode GE of transistor T1 (i.e., D1>D3). In some embodiments, Figure 3 The second opening OP2 shown may overlap the source electrode SE of transistor T1, and the width D1 of the second opening OP2 may be greater than the width D4 of the source electrode SE of transistor T1 (i.e., D1>D4). In some embodiments, Figure 3The second opening OP2 can overlap the drain electrode DE of the transistor T1, and the width D1 of the second opening OP2 can be greater than the width D2 of the drain electrode DE of the transistor T1 (i.e., D1 > D2). In some embodiments, the width D1 of the second opening OP2 can be greater than the sum of the width D2, the width D3, and the width D4 (i.e., D1 > D2+D3+D4). In this case, the second opening OP2 can overlap the gate electrode GE, the source electrode SE, and the drain electrode DE of the transistor T1 at the same time, for example. Note that the above relationship between the width D1 of the second opening OP2 and the width D3 of the gate electrode GE, the width D2 of the drain electrode DE, and the width D4 of the source electrode SE of the transistor T1 overlapped by the second opening OP2 can be applied to the other openings (e.g., the opening OPE, but not limited thereto) of the insulating layer INL and the widths of the gate electrode, the drain electrode, and the source electrode of the transistor overlapped by the openings.

[0058] Referring back to Figure 4 , according to the present embodiment, the second opening OP2 of the insulating layer INL can have a depth DH, wherein the depth DH can be defined as the maximum vertical distance between the upper surface and the lower surface of the portion of the insulating layer INL adjacent to the second opening OP2, but not limited thereto. In some embodiments, the depth DH can range from 4 μm to 13 μm (i.e., 4 μm ≤ DH ≤ 13 μm). In some embodiments, the depth DH can range from 6 μm to 10 μm (i.e., 6 μm ≤ DH ≤ 10 μm).

[0059] In some embodiments, the electronic device ED can include a conductive layer ML disposed on the buffer layer BF and an insulating layer IN0 disposed on the conductive layer ML, but not limited thereto. The conductive layer ML can form a capacitive unit with the conductive layer M1 or the conductive layer M2, but not limited thereto. The insulating layer IN0 can include any suitable insulating material. In some embodiments, the electronic device ED can not include the insulating layer IN0 and the conductive layer ML. In addition, as Figure 4 shown, in the present embodiment, the semiconductor SM can be electrically connected to the semiconductor OL through a contact CT. The contact CT can be formed by any suitable conductive layer in the circuit layer CL. Figure 4 The features of the other film layers and elements shown can be referred to the above, and thus will not be described again.

[0060] Referring to Figure 4 , Figure 4 is a partial top view of an electronic device according to a third embodiment of the present application. Specifically, Figure 4For example, a top view schematic diagram of a driving circuit DI of one sub-pixel SPX is shown. In detail, in the present embodiment, one optical unit LCU, the filter layer (one of the first filter layer CF1, the second filter layer CF2 and the third filter layer CF3) corresponding to the optical unit LCU, and at least one light emitting unit LU, and the driving circuit DI (including at least one transistor) for driving the at least one light emitting unit can be regarded as one sub-pixel SPX. In this case, the above-mentioned optical unit LCU1, optical unit LCU2 and optical unit LCU3 can form a red sub-pixel SPX, a green sub-pixel SPX and a blue sub-pixel SPX, respectively, and the three sub-pixels can constitute one pixel. Figure 4 The shown driving circuit DI can be the driving circuit DI of any one of the red sub-pixel SPX, the green sub-pixel SPX and the blue sub-pixel SPX. In the present embodiment, as shown, Figure 4 The driving circuit DI of one sub-pixel SPX can include, for example, three transistors, i.e. a switching transistor TW, a driving transistor TD and a sensing transistor TS, but not limited thereto. The switching transistor TW can include a gate electrode G1, a source electrode S1 and a drain electrode DE1, the driving transistor TD can include a gate electrode G2, a source electrode S2 and a drain electrode DE2, and the sensing transistor TS can include a gate electrode G3, a source electrode S3 and a drain electrode DE3. It should be noted that, Figure 5 The number of transistors included in the shown driving circuit DI is only exemplary, and the present embodiment is not limited thereto. In other embodiments, according to the design of the driving circuit DI, the driving circuit DI can include any suitable number of transistors.

[0061] The following describes several examples of the overlapping relationship between the opening OPE of the insulating layer INL and the transistor.

[0062] In some embodiments, one opening OPE (which can be the above-mentioned second opening OP2, but not limited thereto) of the insulating layer INL can overlap at least a part of one transistor in the top view direction of the electronic device ED. For example, as shown, Figure 5 One opening OPE of the insulating layer INL can overlap the gate electrode G2, the source electrode S2 and the drain electrode DE2 of the driving transistor TD, i.e. overlap the driving transistor TD. In some embodiments, one opening OPE of the insulating layer INL can overlap at least one of the source electrode S2 and the drain electrode DE2 of the driving transistor TD. It should be noted that, Figure 5 Only a part of the insulating layer INL is shown exemplarily, and the insulating layer INL can include other openings OPE overlapping at least a part of the switching transistor TW and / or the sensing transistor TS.

[0063] In some embodiments, one opening OPE of the insulating layer INL (may be the second opening OP2 described above, but not limited thereto) can overlap at least a portion of the plurality of transistors in the plan view of the electronic device ED. For example, one opening OPE of the insulating layer INL can overlap the gate electrode G2, the source electrode S2, and the drain electrode DE2 of the drive transistor TD, the gate electrode G1, the source electrode S1, and the drain electrode DE1 of the switching transistor TW, and the gate electrode G3, the source electrode S3, and the drain electrode DE3 of the sensing transistor TS, but not limited thereto. In some embodiments, one opening OPE of the insulating layer INL can overlap at least a portion of any two of the switching transistor TW, the drive transistor TD, and the sensing transistor TS. In some embodiments, one opening OPE of the insulating layer INL can overlap a plurality of transistors in the plurality of drive circuits DI.

[0064] In some embodiments, one transistor can overlap a plurality of openings OPE in the plan view of the electronic device ED. Here, "one transistor overlaps a plurality of openings OPE" may, for example, include embodiments in which the source electrode SE (or the drain electrode DE) of the transistor overlaps a plurality of openings OPE and embodiments in which the source electrode SE and the drain electrode DE of the transistor overlap different openings OPE, respectively. For example, in the drive circuit DI, the source electrode S1 and the drain electrode DE1 of the switching transistor TW can overlap different openings OPE, the source electrode S2 and the drain electrode DE2 of the drive transistor TD can overlap different openings OPE, and the source electrode S3 and the drain electrode DE3 of the sensing transistor TS can overlap different openings OPE, but not limited thereto.

[0065] The above-described overlapping of the openings OPE of the insulating layer INL and the transistors can be applied to the embodiments and variant embodiments of the present application. Note that different openings OPE in the insulating layer INL can overlap the transistors in different ways.

[0066] Reference is made to Figure 4 , Figure 5 is a partial plan view schematically showing an electronic device according to a fourth embodiment of the present application. Figure 5 The structure shown in Figure 6 One of the main differences between the structure shown in Figure 6 The drive transistor TD, the switching transistor TW, and the sensing transistor TS each further include a semiconductor OL according to the present embodiment. According to the present embodiment, one opening OPE of the insulating layer INL can overlap the semiconductor OL in the transistor in the plan view of the electronic device ED. In some embodiments, one opening OPE of the insulating layer INL (may be the second opening OP2 described above, but not limited thereto) can overlap the semiconductor OL in one transistor in the plan view of the electronic device ED. For example, as shown in FIG. 4B, one opening OPE of the insulating layer INL can overlap the semiconductor OL in the drive transistor TD, the switching transistor TW, and the sensing transistor TS, but not limited thereto. Figure 6As shown, one opening OPE of the insulating layer INL can overlap the semiconductor OL of the driving transistor TD. In some embodiments, one opening OPE of the insulating layer INL (which can be the second opening OP2 described above, but is not limited thereto) can overlap the semiconductor OL of multiple transistors in the plan view of the electronic device ED. For example, one opening OPE of the insulating layer INL can overlap the semiconductor OL of the driving transistor TD, the semiconductor OL of the switching transistor TW, and the semiconductor OL of the sensing transistor TS. In some embodiments, one opening OPE of the insulating layer INL can overlap the semiconductor OL of multiple transistors in multiple driving circuits DI. In some embodiments, the semiconductor OL of one transistor can overlap multiple openings OPE in the plan view of the electronic device ED. For example, the semiconductor OL of the driving transistor TD, the semiconductor OL of the switching transistor TW, and the semiconductor OL of the sensing transistor TS can respectively overlap more than one opening OPE, but is not limited thereto. The above-described overlapping manner of the openings OPE of the insulating layer INL and the semiconductor OL of the transistors can be applied to various embodiments and variant embodiments of the present application. It is noted that different openings OPE can overlap the semiconductor OL in different overlapping manners.

[0067] Please refer to Figure 6 , Figure 6 is a partial plan view of an electronic device according to a fifth embodiment of the present application. Specifically, Figure 6 The arrangement of multiple pixels PX in the electronic device ED is shown. In this embodiment, each pixel PX can be composed of three sub-pixels (i.e., the sub-pixels SPX described above), and the three sub-pixels can respectively include the optical unit LCU1, the optical unit LCU2, and the optical unit LCU3, but are not limited thereto. In other embodiments, the number of sub-pixels (or optical units LCU) included in each pixel PX can be determined according to the design of the electronic device ED. In this embodiment, the range of one pixel PX can be defined in the following manner. First, in a horizontal direction (e.g., the direction X), two color-same optical units LCU that are adjacent to each other and located in two adjacent pixels PX can be identified. The "two color-same optical units LCU that are adjacent to each other" herein can mean that no other optical unit LCU is included between the two optical units LCU. For example, in the plan view of the electronic device ED, the two color-same optical units LCU that are adjacent to each other and located in two adjacent pixels PX can be identified as the two optical units LCU1 and LCU2 in the pixel PX1 and the two optical units LCU3 and LCU4 in the pixel PX2. In this embodiment, the range of one pixel PX can be defined as the range of the three sub-pixels SPX1, SPX2, and SPX3 in the pixel PX1, and the range of the three sub-pixels SPX4, SPX5, and SPX6 in the pixel PX2. Figure 7In this context, the optical unit LCU2 in pixel PX1 and the optical unit LCU2 in pixel PX2, which is adjacent to pixel PX1 and located to the left of pixel PX1, can be two adjacent optical units LCUs of the same color. Similarly, the optical unit LCU2 in pixel PX1 and the optical unit LCU2 in pixel PX3, which is adjacent to pixel PX1 and located to the right of pixel PX1, can also be two adjacent optical units LCUs of the same color. After confirming the above-mentioned "two adjacent optical units LCUs of the same color", a virtual straight line passing through the midpoint of the two optical units LCU can be defined. Specifically, taking pixel PX1 as an example, the optical unit LCU2 in pixel PX1 can define a virtual straight line VL1 with another optical unit LCU2 located to its left (i.e., the optical unit LCU2 in pixel PX2), where the virtual straight line VL1 can extend along a vertical direction (e.g., direction Y) perpendicular to the horizontal direction and pass through the midpoint of the optical units LCU2 in pixel PX1 and the optical units LCU2 in pixel PX2. In this scenario, the optical unit LCU2 in pixel PX1 and the optical unit LCU2 in pixel PX2 can have a horizontal distance F1. The distances from the virtual line VL1 to the optical unit LCU2 in pixel PX1 and from the virtual line VL1 to the optical unit LCU2 in pixel PX2 can both be half of the distance F1. Similarly, the optical unit LCU2 in pixel PX1 can also define a virtual line VL2 with another optical unit LCU2 located to its right (i.e., the optical unit LCU2 in pixel PX3). The virtual line VL2 can extend vertically and pass through the midpoint between the optical units LCU2 in pixel PX1 and the optical unit LCU2 in pixel PX3. In this scenario, the optical unit LCU2 in pixel PX1 and the optical unit LCU2 in pixel PX3 can have a horizontal distance F2, while the distances from the virtual line VL2 to the optical unit LCU2 in pixel PX1 and from the virtual line VL2 to the optical unit LCU2 in pixel PX3 can both be half of the distance F2. In other words, a pixel PX can define a virtual line with two other pixels PX located to its left and right. The distances F1 and F2 can be the same or different, and this embodiment is not limited to this. Furthermore, in the vertical direction, the two optical units LCUs with the minimum vertical distance located in two adjacent pixels PX can be identified first. For example, in Figure 8In this context, the optical unit LCU2 of pixel PX1 and the optical unit LCU3 of pixel PX4, which is adjacent to and above pixel PX1, can be optical units LCUs located in two adjacent pixels PX with minimum vertical distance. Similarly, the optical unit LCU3 of pixel PX1 and the optical unit LCU2 of pixel PX5, which is adjacent to and below pixel PX1, can also be optical units LCUs located in two adjacent pixels PX with minimum vertical distance. After confirming the above-mentioned "two optical units LCUs located in two adjacent pixels PX with minimum vertical distance", the virtual straight line passing through the midpoint of the two optical units LCU can then be defined. Specifically, taking pixel PX1 as an example, the optical unit LCU2 in pixel PX1 can define a virtual straight line HL1 with the optical unit LCU3 in pixel PX4 located above pixel PX1. The virtual straight line HL1 extends horizontally and passes through the midpoint between the optical units LCU2 and LCU3 in pixel PX1 and PX4, respectively. In this case, the optical units LCU2 and LCU3 in pixel PX1 and PX4 can have a vertical distance K1, and the distances from the virtual straight line HL1 to both LCU2 and LCU3 in pixel PX1 can be half of distance K1. Similarly, the optical unit LCU3 in pixel PX1 can also define a virtual straight line HL2 with the optical unit LCU2 in pixel PX5 located below pixel PX1. The virtual straight line HL2 extends horizontally and passes through the midpoint between LCU3 and LCU2 in pixel PX1 and PX5, respectively. In this scenario, the optical unit LCU3 in pixel PX1 and the optical unit LCU2 in pixel PX5 can have a distance K2 in the vertical direction, and the distance from the virtual line HL2 to the optical unit LCU3 in pixel PX1 and the distance from the virtual line HL2 to the optical unit LCU2 in pixel PX5 can both be half of the distance K2. In other words, a pixel PX can define a virtual line with two other pixels PX located above and below it. The distances K1 and K2 can be the same or different, and this embodiment is not limited thereto. According to this embodiment, after defining two virtual lines VL1 and VL2 and two virtual lines HL1 and HL2 based on a pixel PX, the region of the pixel PX can be defined as the region enclosed by the two virtual lines VL1 and VL2 and the two virtual lines HL1 and HL2, but is not limited thereto. For example, in Figure 7In the embodiment, the region of the pixel PX1 can be a region enclosed by the virtual straight line VL1, the virtual straight line VL2, the virtual straight line HL1 and the virtual straight line HL2. In this way, the range of the region of the pixel PX can be defined. It is noted that the above-mentioned definition of the region of the pixel PX is merely exemplary, and the present application is not limited thereto. In other embodiments, the region of the pixel PX can be defined in any suitable manner according to the arrangement of the pixel PX and / or the setting position of the optical unit LCU.

[0068] In the present embodiment, the area of one pixel PX can include a first area A1 and a second area A2, wherein the first area A1 corresponds to the optical unit LCU, and the second area A2 does not correspond to the optical unit LCU. In other words, the first area A1 can be defined as the portion of the area of one pixel PX that corresponds to the optical unit LCU, and the second area A2 can be defined as another portion of the area of one pixel PX that does not correspond to the optical unit LCU, i.e. the second area A2 can be the portion of the area of one pixel PX other than the first area A1. The first area A1 can include three portions corresponding to the optical unit LCU1, the optical unit LCU2 and the optical unit LCU3 in the pixel PX, but the disclosure is not limited thereto. According to the present embodiment, in the top-down direction of the electronic device ED, the number of transistors in the circuit layer CL overlapping the first area A1 can be less than the number of transistors overlapping the second area A2. Here, "the transistor overlapping the first area A1 (or the second area A2)" can mean that at least a portion (e.g. at least one of the source electrode and the drain electrode) of the transistor overlaps the first area A1 (or the second area A2). For example, in the top-down direction of the electronic device ED, the circuit layer CL can include X1 transistors overlapping the first area A1 of one pixel PX and Y1 transistors overlapping the second area A2 of the pixel PX, wherein X1 can be less than Y1. The above-described relationship between the number of transistors overlapping the first area A1 and the second area A2 can apply to each pixel PX. Furthermore, as described above, the insulating layer INL can include the first opening OP1 in which the optical unit LCU is disposed and the opening OPE in which the optical unit LCU is not disposed. In this case, the first opening OP1 can correspond to the first area A1, and the opening OPE can correspond to the second area A2. Specifically, the first area A1 of one pixel PX can correspond to three first openings OP1 for disposing the optical unit LCU1, the optical unit LCU2 and the optical unit LCU3, respectively. In some embodiments, the second area A2 of one pixel PX can correspond to one opening OPE. In this case, in the top-down direction of the electronic device ED, the sum of the number of transistors overlapping the three first openings OP1 corresponding to the first area A1 of one pixel PX can be less than the number of transistors overlapping the opening OPE corresponding to the second area A2 of the pixel PX. In some embodiments, the second area A2 of one pixel PX can correspond to a plurality of openings OPE. In this case, in the top-down direction of the electronic device ED, the sum of the number of transistors overlapping the three first openings OP1 corresponding to the first area A1 of one pixel PX can be less than the sum of the number of transistors overlapping the plurality of openings OPE corresponding to the second area A2 of the pixel PX.In some embodiments, the total area of the semiconductor (e.g., semiconductor SM) of the transistors overlapped by the three first openings OP1 corresponding to the first area A1 of a pixel PX can be less than the total area of the semiconductor (e.g., semiconductor SM) of the transistors overlapped by the plurality of openings OPE corresponding to the second area A2 of the pixel PX. The features of this embodiment can be applied to other embodiments and variant embodiments of the present application.

[0069] Please refer to Figure 8 and Figure 7 , Figure 8 FIG. 6A is a partial top view schematic diagram of an electronic device according to a sixth embodiment of the present application, Figure 7 FIG. 6B is a partial top view schematic diagram of an electronic device according to a variant embodiment of the sixth embodiment of the present application. Specifically, Figure 8 and Figure 4 respectively show a top view schematic diagram of a driving circuit DI of a sub-pixel SPX. Figure 5 and Figure 7 The structure of the driving circuit DI shown in FIGS. 6A and 6B can refer to the related content of Figure 7 , Figure 8 and the above, and thus will not be described again. According to this embodiment, in the driving circuit DI of a sub-pixel SPX, the number of transistors overlapped with the first opening OP1 in which the optical unit LCU is disposed can be less than the number of transistors overlapped with the opening OPE in which the optical unit LCU is not disposed. Specifically, in the top view direction of the electronic device ED, the plurality of transistors in the driving circuit DI of a sub-pixel SPX can include a first portion of transistors overlapped with the first opening OP1 and a second portion of transistors overlapped with the opening OPE, wherein the number of the first portion of transistors can be different from the number of the second portion of transistors, and in an embodiment, the number of the first portion of transistors can be less than the number of the second portion of transistors. In some embodiments, as shown in Figure 8 the different number of transistors in the driving circuit DI of a sub-pixel SPX can be overlapped with one first opening OP1 and one opening OPE, and in this case, the plurality of transistors in the driving circuit DI of the sub-pixel SPX can include a first portion of transistors overlapped with the first opening OP1 and a second portion of transistors overlapped with the opening OPE, wherein the number of the first portion of transistors is less than the number of the second portion of transistors. For example, in Figure 8In some embodiments, the first portion of the plurality of transistors can include one transistor (i.e., the sensing transistor TS) overlapping the first opening OP1, and the second portion of the plurality of transistors can include two transistors (i.e., the driving transistor TD and the switching transistor TW) overlapping the plurality of openings OPE, but the present application is not limited thereto. The opening OPE can be the second opening OP2 as described above. In other words, in the present embodiment, the first opening OP1 can overlap the first portion of the plurality of transistors, the second opening OP2 can overlap the second portion of the plurality of transistors, and the number of the first portion of the plurality of transistors can be different from the number of the second portion of the plurality of transistors. For example, the number of the first portion of the plurality of transistors can be less than the number of the second portion of the plurality of transistors. In some embodiments, as shown in FIG. 6, the first portion of the plurality of transistors can include one transistor (i.e., the sensing transistor TS) overlapping the first opening OP1, and the second portion of the plurality of transistors can include two transistors (i.e., the driving transistor TD and the switching transistor TW) overlapping the plurality of openings OPE, but the present application is not limited thereto. Figure 9 In some embodiments, as shown in FIG. 6, the first portion of the plurality of transistors can include one transistor (i.e., the sensing transistor TS) overlapping the first opening OP1, and the second portion of the plurality of transistors can include two transistors (i.e., the driving transistor TD and the switching transistor TW) overlapping the plurality of openings OPE, but the present application is not limited thereto. Figure 9 In some embodiments, as shown in FIG. 6, the first portion of the plurality of transistors can include one transistor (i.e., the sensing transistor TS) overlapping the first opening OP1, and the second portion of the plurality of transistors can include two transistors (i.e., the driving transistor TD and the switching transistor TW) overlapping the plurality of openings OPE, but the present application is not limited thereto. Figure 9 In some embodiments, as shown in FIG. 6, the first portion of the plurality of transistors can include one transistor (i.e., the sensing transistor TS) overlapping the first opening OP1, and the second portion of the plurality of transistors can include two transistors (i.e., the driving transistor TD and the switching transistor TW) overlapping the plurality of openings OPE, but the present application is not limited thereto. It is noted that the number of the plurality of transistors in the driving circuit DI of a sub-pixel SPX can be determined according to the design of the driving circuit DI, and is not limited to the above. In some embodiments, the driving circuit DI of a sub-pixel SPX can include XI transistors, which include Y1 transistors (i.e., the first portion of the plurality of transistors) overlapping the first opening OP1 and Z1 transistors (i.e., the second portion of the plurality of transistors) overlapping at least one opening OPE, wherein XI is the sum of Y1 and Z1, and Y1 can be less than Z1. The features of the present embodiment can be applied to other embodiments and variant embodiments of the present application.

[0070] Please refer to Figure 1 , Figure 9 FIG. 7 is a partial cross-sectional schematic view of an electronic device according to a seventh embodiment of the present application. Specifically, FIG. 7 shows a sub-pixel SPX of the electronic device according to the seventh embodiment of the present application. Figure 9 FIG. 7 shows a sub-pixel SPX of the electronic device according to the seventh embodiment of the present application. Figure 9A portion of the insulating layer INL and the film layer and elements thereunder are shown in the electronic device ED. In particular, Figure 9 The structure shown can be formed, for example, after the insulating layer INL and the optical unit LCU are disposed in the manufacturing process of the electronic device ED. According to the present embodiment, since the insulating layer INL includes the opening OPE in addition to the first opening OP1 where the optical unit LCU is disposed, the elements or film layer under the insulating layer INL can be subjected to a specific process through the opening OPE after the insulating layer INL and the optical unit LCU are disposed.

[0071] In some embodiments, since the opening OPE can overlap at least a portion of the transistor in the circuit layer CL in the top-down direction of the electronic device ED, the position of the specific transistor can be marked through the opening OPE after the insulating layer INL and the optical unit LCU are disposed. For example, when a defective transistor is found in the detection step of the transistor, the position of the defective transistor can be marked to facilitate the repair process of the defective transistor subsequently. In the present embodiment, the position of the transistor can be marked, for example, by means of laser dot positioning, but not limited thereto. Specifically, as shown in Figure 1 If the transistor T1 is detected as a defective transistor in the detection step of the transistor, laser can be emitted by the laser emitter LR1, where the laser can pass through the opening OP2 (or the opening OPE) overlapping the transistor T1 and leave a mark at any suitable position corresponding to the transistor T1, such as the surface of the insulating layer I2 corresponding to the transistor T1, but not limited thereto. In other embodiments, the position of the transistor can be marked by computer coordinate positioning, ink color marking positioning or other suitable means. Furthermore, after the marking step of the defective transistor, the defective transistor can be subjected to a repair process through the opening OPE. For example, as shown in Figure 9 After the position of the transistor T1 is marked in the above manner, laser can be emitted by the laser emitter LR2, where the laser can pass through the opening OP2 and be emitted to the transistor T1 to repair the transistor T1.

[0072] In some embodiments, the film layer or elements under the insulating layer INL can also be subjected to a via process through the opening OPE. For example, as shown in Figure 10 The laser emitter LR3 can emit laser, where the laser can pass through the opening OPE and form a via V1 in the light emitting layer LEL. The features of the via V1 are described above and will not be repeated. In other words, the via V1 can overlap or at least partially overlap the opening OPE of the insulating layer INL in the top-down direction of the electronic device ED. Figure 10The feature of the overlap of the via V1 on the opening OPE is also shown. Since the laser used to form the via V1 can not pass through (or in other words, pass through the material of) the insulating layer INL, the possibility of the material of the insulating layer INL being high-temperature vaporized and generating contamination by the laser irradiation can be reduced. It is noted that the opening OPE can not be limited to forming the above-mentioned via V1, but can also be used to perform other film layer opening processes. In this case, the via structure formed by the opening OPE can overlap or at least partially overlap the opening OPE in the top-down direction of the electronic device ED. In some embodiments, the electronic device ED can include a tiled display device, and a through glass via (TGV) can be formed by the opening OPE to electrically connect different electronic devices ED.

[0073] In the existing electronic device, if the position of the defective transistor is to be marked, the defective transistor is to be repaired, or a via is to be formed in the film layer under the optical unit after the optical unit is disposed, the laser used for the above-mentioned processes can be affected when passing through the barrier structure of the optical unit, for example, the laser can be blocked or absorbed by the material of the barrier structure, thereby increasing the difficulty of the above-mentioned processes. Alternatively, the barrier structure can affect the observation difficulty of the position marking of the transistor. On the other hand, since the insulating layer INL of the electronic device ED of the present application can include the opening OPE which is not disposed with the optical unit LCU, and the above-mentioned processes can be performed through the opening OPE, the influence of the material of the insulating layer INL on the above-mentioned processes can be reduced, for example, the possibility of the laser being blocked or absorbed by the material of the insulating layer INL can be reduced. In this way, the process yield of the electronic device ED can be improved. It is noted that the opening OPE can also be used to perform other suitable processes, and is not limited to the above-mentioned processes.

[0074] In addition, although Figure 10 It is not shown that, in the present embodiment, the semiconductor OL can be disposed in the peripheral region NDA and the active region DA, and the number of openings of the insulating layer INL overlapped by the semiconductor OL disposed in the peripheral region NDA is different from the number of openings of the insulating layer INL overlapped by the semiconductor OL disposed in the active region DA in the top-down direction of the electronic device ED. The openings of the insulating layer INL here can include the first opening OP1 in which the optical unit LCU is disposed and the opening OPE in which the optical unit LCU is not disposed. Specifically, the number of openings of the insulating layer INL overlapped by the semiconductor OL disposed in the peripheral region NDA can be less than the number of openings of the insulating layer INL overlapped by the semiconductor OL disposed in the active region DA, but is not limited thereto.

[0075] Please refer to Figure 10 , Figure 10This is a partial cross-sectional schematic diagram of an electronic device according to an eighth embodiment of the present invention. According to this embodiment, the electronic device ED may further include a light sensor OD, wherein the light sensor OD may be disposed between the insulating layer INL and the substrate SB. For example, as... Figure 10 As shown, the photosensitive sensor OD can be disposed on the insulating layer IN5 and between the insulating layer IN5 and the insulating layer OIL, but is not limited thereto. In other embodiments, the photosensitive sensor OD can be disposed at any suitable location between the insulating layer INL and the substrate SB. According to this embodiment, in the top view of the electronic device ED, at least a portion of the photosensitive sensor OD can overlap at least one of the openings OPE of the insulating layer INL that are not provided with optical units LCU. For example, as Figure 10 As shown, in a top view of the electronic device ED, one of the openings OPE of the insulating layer INL (e.g., the second opening OP2, but not limited thereto) may overlap at least a portion of the light sensor OD. In other embodiments, the light sensor OD may overlap a plurality of openings OPE. The light sensor OD may include any suitable light-sensing element capable of receiving visible or non-visible light. The light sensor OD of this embodiment may, for example, include an organic photodiode (OPD), but is not limited thereto. In some embodiments, the light sensor OD may be formed within the electronic device ED through the openings OPE of the insulating layer INL, for example, an organic photodiode element may be formed within the electronic device ED through the openings OPE, but is not limited thereto. In some embodiments, the light sensor OD may be formed outside the electronic device ED first, and then transferred into the electronic device ED through the openings OPE. The light sensor OD may be electrically connected to the circuit layer CL, for example, electrically connected to a transistor in the circuit layer CL, thereby driving the light sensor OD through the transistor. In this embodiment, the light sensor OD may, for example, serve as a fingerprint sensing element, but is not limited thereto. For example, as Figure 10 As shown, the light L1 emitted by the self-emissive unit LU can be reflected by an object OB (e.g., a user's finger) and received by the light sensor OD after passing through the opening OP2, thereby achieving the function of fingerprint recognition. In other embodiments, the light sensor OD may include other suitable sensing elements depending on the design of the electronic device ED.

[0076] According to this embodiment, the portions of the first filter layer CF1, the second filter layer CF2, and the third filter layer CF3 disposed within the opening OPE overlapping at least a portion of the optical sensor OD can each include a filter opening. Specifically, as... Figure 10As shown, the second opening OP2 of the insulating layer INL can overlap at least a portion of the optical sensor OD in the top-down direction of the electronic device ED, and the portion of the first filter layer CF1 disposed within the second opening OP2 can include the first filter opening OF1, the portion of the second filter layer CF2 disposed within the second opening OP2 can include the second filter opening OF2, and the portion of the third filter layer CF3 disposed within the second opening OP2 can include the third filter opening OF3. The first filter opening OF1, the second filter opening OF2, and the third filter opening OF3 can at least partially overlap each other in the top-down direction of the electronic device ED. In addition, the first filter opening OF1, the second filter opening OF2, and the third filter opening OF3 can overlap at least a portion of the optical sensor OD in the top-down direction of the electronic device ED. In short, the filter openings can be formed in the filter layers to reduce the impact of the filter layers on the functionality of the optical sensor OD. Figure 2 As an example of the structure shown, the electronic device ED can include a first filter layer CF1 and a second filter layer CF2 disposed on the insulating layer INL, a portion of the first filter layer CF1 disposed in the second opening OP2 and having the first filter opening OF1, and a portion of the second filter layer CF2 disposed in the second opening OP2 and having the second filter opening OF2, and in the top-down direction of the electronic device ED, the first filter layer CF1 can overlap the optical unit LCU1, and the second filter layer CF2 can not overlap the optical unit LCU1. The optical layer OC can fill the first filter opening OF1, the second filter opening OF2, and the third filter opening OF3, but is not limited thereto. By forming the filter openings in the filter layers as described above, the impact of the filter layers on the functionality of the optical sensor OD can be reduced. Specifically, by forming the first filter opening OF1, the second filter opening OF2, and the third filter opening OF3 in the first filter layer CF1, the second filter layer CF2, and the third filter layer CF3, respectively, that overlap at least a portion of the optical sensor OD, light rays (e.g., light ray LI) can pass through the first filter opening OF1, the second filter opening OF2, and the third filter opening OF3 into the optical sensor OD without being blocked or absorbed by the first filter layer CF1, the second filter layer CF2, and / or the third filter layer CF3. In this way, the likelihood of the optical sensor OD being unable to receive light signals and being affected in its functionality can be reduced. In some embodiments, as shown in FIG. 1C, the first filter layer CF1, the second filter layer CF2, and the third filter layer CF3 can be disposed on the insulating layer INL, and the first filter layer CF1, the second filter layer CF2, and the third filter layer CF3 can be formed of the same material. Figure 11 As shown, the insulating layer IN7, the insulating layer IN8, and the insulating layer IN9 can include an opening corresponding to the first filter opening OF1, the second filter opening OF2, and the third filter opening OF3, respectively, and the optical layer OC can fill the plurality of openings.

[0077] It is noted that the electronic device ED can also include other types of sensors that overlap the opening OPE, not limited to the above-mentioned optical sensor OD. For example, the electronic device ED can include a piezoelectric sensor, a haptic device, a sound sensing element, a charge-coupled device (CCD), an antenna element, or other suitable elements, wherein at least a portion of the elements or devices can overlap at least one of the openings OPE.

[0078] In some embodiments, one opening OPE of the insulating layer INL can overlap both the transistor and the optical sensor OD. For example, as shown in Figure 11 FIG. 2, a second opening OP2 of the insulating layer INL can overlap both the optical sensor OD and the transistor T1 in the top-down direction of the electronic device ED. In some embodiments, one opening OPE of the insulating layer INL can overlap one of the transistor and the optical sensor OD, and another opening OPE of the insulating layer INL can overlap the other of the transistor and the optical sensor OD. For example, referring back to Figure 11 FIG. 1, one of the openings OPE of the insulating layer INL (e.g., the second opening OP2) can overlap the transistor T1, and another of the openings OPE of the insulating layer INL (e.g., the third opening OP3) can overlap at least a portion of the optical sensor OD in the top-down direction of the electronic device ED.

[0079] Please refer to Figure 11 , Figure 11 FIG. 1, one of the openings OPE of the insulating layer INL (e.g., the second opening OP2) can overlap the transistor T1, and another of the openings OPE of the insulating layer INL (e.g., the third opening OP3) can overlap at least a portion of the optical sensor OD in the top-down direction of the electronic device ED. Figure 11As shown, the pattern layer PPL can be formed from conductive layers M1 and / or M2. The pattern layer PPL can be formed from one or more conductive layers. In this case, the pattern layer PPL can share materials with conductive layers M1 and / or M2 or be formed in the same process, thereby reducing manufacturing costs. In the top view of the electronic device ED, at least a portion of the pattern layer PPL can overlap at least one opening OPE of the insulating layer INL. In other words, the pattern layer PPL can be positioned corresponding to the opening OPE. In some embodiments, the pattern layer PPL can serve as an alignment element. Specifically, in the manufacturing process of the electronic device ED, the pattern layer PPL can assist in positioning the film layer or component, thereby reducing the misalignment of the film layer or component. For example, when a small area mask is used in the manufacturing process of the electronic device ED, the pattern layer PPL can assist in positioning the mask, thereby reducing the misalignment of the mask, but this is not a limitation. In some embodiments, the pattern layer PPL may include a code pattern, through which a user can obtain specific information, including but not limited to positional information on the electronic device ED. For example, as Figure 12 As shown, a user can use a stylus TU to read the pattern (i.e., pattern layer PPL) through the opening OPE, thereby obtaining the position information on the electronic device ED corresponding to the stylus TU, but this is not a limitation. Specifically, the stylus TU can emit a light signal, which can reach the pattern layer PPL through the opening OPE, thereby obtaining the pattern information of the pattern layer PPL (or pattern). Here, "the light signal of the stylus TU" can include visible light signals and non-visible light signals (e.g., infrared light signals, but is not limited to this). The electronic device ED may, for example, include a plurality of pattern layers PPLs disposed at different locations on the electronic device ED, wherein each of the plurality of pattern layers PPLs can serve as a pattern to provide information about its location, and each of the plurality of pattern layers PPLs can be superimposed on at least one opening OPE of the insulating layer INL. In some embodiments, the pattern layer PPL can simultaneously serve as a registration element and a pattern. For example, the pattern layer PPL can serve as a registration element during the manufacturing process of the electronic device ED and can serve as a pattern when the electronic device ED is used subsequently. According to this embodiment, since the pattern layer PPL can overlap with the opening OPE, the influence of the insulating layer INL on the function of the pattern layer PPL can be reduced. Specifically, when the pattern layer PPL is used as a positioning element, overlapping the pattern layer PPL with the opening OPE reduces the possibility that the position of the pattern layer PPL cannot be obtained. Alternatively, when the pattern layer PPL is used as a graphic symbol, overlapping the pattern layer PPL with the opening OPE reduces the possibility that the graphic symbol cannot be read due to the absorption of the light signal emitted by the stylus TU by the material of the insulating layer INL.

[0080] According to this embodiment, as Figure 1As shown, the portions of the first filter layer CF1, the second filter layer CF2 and the third filter layer CF3 disposed within the openings OPE overlapping at least a portion of the pattern layer PPL can be removed. In this case, the pattern layer PPL can not overlap the first filter layer CF1, the second filter layer CF2 and the third filter layer CF3 in the top-down direction of the electronic device ED. By the above design, the impact of the filter layers on the function of the pattern layer PPL can be reduced. For example, by removing the portion of the first filter layer CF1, the second filter layer CF2 and the third filter layer CF3 overlapping the pattern layer PPL, the possibility that the light signal emitted by the stylus TU is blocked or absorbed by the first filter layer CF1, the second filter layer CF2 and the third filter layer CF3, resulting in a failure to read the code, can be reduced.

[0081] It is noted that, although Figure 12 Not shown, the pattern layer PPL can be formed of other materials, and the pattern layer PPL can not be limited to being disposed in the circuit layer CL. For example, in some embodiments, the pattern layer PPL can be disposed in one of the openings OPE of the insulating layer INL, and the pattern layer PPL can include a filter material, a fluorescent material, a quantum dot material or other suitable material that can pass infrared light.

[0082] Reference is made to Figure 1 , and reference is made to Figure 1 , Figure 1 A flowchart of a manufacturing method of an electronic device according to a first embodiment of the present disclosure is shown. According to the present embodiment, the manufacturing method M100 of the electronic device ED can include the following steps:

[0083] S100: providing a substrate and disposing a circuit layer on the substrate;

[0084] S101: forming a light emitting unit on the circuit layer;

[0085] S102: forming an encapsulation layer on the light emitting unit;

[0086] S103: performing an inspection procedure;

[0087] S104: forming an insulating layer on the encapsulation layer and forming a plurality of openings in the insulating layer;

[0088] S105: disposing an optical unit in a portion of the plurality of openings of the insulating layer;

[0089] S106: performing a laser process;

[0090] S107: forming a functional layer on the insulating layer and the optical unit;

[0091] S108: forming a filter layer on the functional layer;

[0092] S109: forming an optical layer on the filter layer to form an electronic panel, and performing a cutting process;

[0093] S110: forming a cover layer on the optical layer; and

[0094] S111: forming an optical film on the cover layer.

[0095] The details of each step of the manufacturing method M100 of the electronic device ED are described below.

[0096] According to the present embodiment, the manufacturing method M100 of the electronic device ED first includes a step S100 of providing a substrate SB and disposing a circuit layer CL on the substrate SB. Specifically, after the substrate SB is provided, a structure formed by stacking a conductive layer and an insulating layer can be formed on the substrate SB to form elements in the circuit layer CL, such as transistors and the like. The detailed structure of the substrate SB and the circuit layer CL can refer to the related content above, and thus will not be described again. Figure 1

[0097] Next, the manufacturing method M100 can include a step S101 of forming a light-emitting unit LU on the circuit layer CL. For example, as shown in FIG. 1B, a packaging layer (i.e., an insulating layer IN5) can be first formed on the circuit layer CL, and then an electrode E1, a light-emitting layer LEL, and an electrode E2 can be sequentially disposed on the packaging layer to form the light-emitting unit LU, but the present embodiment is not limited thereto. It should be noted that after the electrode E1 is disposed, an insulating layer IN6 can be first disposed on the electrode E1, and then the light-emitting layer LEL is disposed, but the present embodiment is not limited thereto. Figure 1

[0098] Next, the manufacturing method M100 can include a step S102 of forming a packaging layer on the light-emitting unit LU. According to the present embodiment, the packaging layer can include a structure formed by stacking an insulating layer IL1, an insulating layer OIL, and an insulating layer IL2, as shown in FIG. 1C. For example, the packaging layer can be formed by sequentially disposing the insulating layer IL1, the insulating layer OIL, and the insulating layer IL2 on the electrode E2. Figure 1

[0099] Next, the manufacturing method M100 can include a step S103 of performing an inspection procedure. Specifically, after the packaging layer is disposed, an inspection procedure can be performed on specific elements (such as the light-emitting unit LU, transistors, and the like) in the formed structure.

[0100] Next, the manufacturing method M100 can include a step S104 of forming an insulating layer INL on the packaging layer and forming a plurality of openings in the insulating layer INL. Specifically, as shown in FIG. 1D, the insulating layer INL can be formed on the packaging layer, and a plurality of openings (including a first opening OP1 and an opening OPE) can be formed in the insulating layer INL. Figure 1

[0101] ​​​​Next, the manufacturing method M100 can include a step S105 of disposing optical units LCU in a portion of the plurality of openings of the insulating layer INL. Specifically, as shown in FIG. 1 1 A, after forming the plurality of openings of the insulating layer INL, each of the optical units LCU (including the optical unit LCU1, the optical unit LCU2, and the optical unit LCU3 described above) can be disposed in one of the openings. The openings in which the optical units LCU are disposed can be the first openings OP1 described above, and the openings in which no optical units LCU are disposed can be the openings OPE described above. Figure 13

[0102] Next, the manufacturing method M100 can include a step S106 of performing a laser process. Specifically, after disposing the optical units LCU, a laser process can be performed on the film layers or elements below the insulating layer INL through the openings OPE. In some embodiments, the laser process includes repairing a defective transistor with a laser through the openings OPE. In some embodiments, the laser process includes performing a via process on a specific film layer (e.g., the light-emitting layer LEL, but not limited thereto) with a laser through the openings OPE.

[0103] Next, the manufacturing method M100 can include a step S107 of forming a functional layer on the insulating layer and the optical units. The functional layer here can be the insulating layer IN8 shown in FIG. 1 1 B. As described above, the insulating layer IN8 can include a material having a lower refractive index than other organic layers in the electronic device ED, but not limited thereto. In some embodiments, the insulating layer IN8 can also include hollow particles filled in the organic material layer. Figure 14

[0104] Next, the manufacturing method M100 can include a step S108 of forming a filter layer on the functional layer. Specifically, after sequentially disposing the insulating layer IN7, the insulating layer IN8, and the insulating layer IN9, the first filter layer CF1, the second filter layer CF2, and the third filter layer CF3 can be disposed on the insulating layer IN9 to form a filter layer structure CFL. It should be noted that the first filter layer CF1, the second filter layer CF2, and the third filter layer CF3 can be patterned respectively, such that the portion of the filter layer structure CFL corresponding to an optical unit LCU can only include a filter layer having the same color as the light passing through the optical unit LCU.

[0105] Next, the manufacturing method M100 can include a step S109 of forming an optical layer OC on the filter layer and performing a cutting process. Specifically, after forming the filter layer structure CFL, the optical layer OC can be disposed on the filter layer structure CFL. After that, a cutting process can be performed on the formed structure to divide the formed structure into a plurality of electronic panels.

[0106] ​​Next, the manufacturing method M100 can include a step S110 of forming the cover layer CO on the optical layer OC, and a step S111 of forming the optical film on the cover layer CO. Specifically, after the optical layer OC is provided and the plurality of electronic panels are cut out, the adhesive layer AD can be provided on the optical layer OC of one electronic panel, and the cover layer CO can be provided on the adhesive layer AD to attach the cover layer CO to the electronic panel. Then, the optical film can be provided on the cover layer CO, such as the anti-reflection layer AR shown in FIG. 1, to form the electronic device ED, so as to improve the light-out effect of the electronic device ED. Figure 13 The manufacturing method M100 of the electronic device ED can also include other suitable steps, and is not limited to the above steps.

[0107] It should be noted that the manufacturing method M100 of the electronic device ED can also include other suitable steps, and is not limited to the above steps.

[0108] Please refer to Figure 14 and Figure 13 , Figure 13 FIG. 10 is a partial cross-sectional schematic view of an electronic device according to a tenth embodiment of the present application, Figure 13 FIG. 11 is a flowchart of a manufacturing method of an electronic device according to the tenth embodiment of the present application. According to the present embodiment, the manufacturing method M200 of the electronic device ED can include the following steps:

[0109] S200: providing a first substrate and providing a circuit layer on the first substrate;

[0110] S201: forming a light-emitting unit on the circuit layer;

[0111] S202: forming an encapsulation layer on the light-emitting unit;

[0112] S203: performing an inspection procedure;

[0113] S204: forming an insulating layer on the encapsulation layer and forming a plurality of openings in the insulating layer;

[0114] S205: providing an optical unit in a portion of the plurality of openings of the insulating layer;

[0115] S206: performing a laser process;

[0116] S207: providing a second substrate and providing a filter layer on the second substrate;

[0117] S208: providing a functional layer on the filter layer;

[0118] S209: forming a sealing layer and a filling layer on the first substrate;

[0119] S210: aligning and attaching the first substrate to the second substrate;

[0120] S211: performing a cutting process; and S211: performing a cutting process; and

[0121] S212: An optical film is disposed on the second substrate.

[0122] The following details each step of the manufacturing method M200 for the electronic device ED.

[0123] According to this embodiment, the manufacturing method M200 of the electronic device ED may include two substrate processes. Specifically, steps S200 to S206 in the manufacturing method M200 may be... Figure 1 The process of manufacturing the first substrate structure SS1 shown, and steps S207 to S208 in manufacturing method M200 can be: Figure 1 The process of fabricating the second substrate structure SS2 shown. After forming the first substrate structure SS1 and the second substrate structure SS2, the first substrate structure SS1 and the second substrate structure SS2 can be bonded together to form an electronic device ED.

[0124] The fabrication process of the first substrate structure SS1 may first include step S200: providing a first substrate SB and forming a circuit layer CL on the first substrate SB. Specifically, as follows: Figure 13 As shown, the first substrate SB can be Figure 13 The first substrate SB is a substrate, and the circuit layer CL can be disposed on the first substrate SB. The detailed structure of the first substrate SB and the circuit layer CL can be referred to above, so it will not be repeated here.

[0125] Next, the fabrication process of the first substrate structure SS1 may include steps S201 to S206. Details of steps S201 to S206 can be found in steps S101 to S106 described above, and will not be repeated here. After completing step S206, the first substrate structure SS1 can be formed. The structural features of the first substrate structure SS1 can be found in [reference needed]. Figure 13 The structure of the electronic device ED shown is not described in detail here.

[0126] The fabrication process of the second substrate structure SS2 may first include step S207: providing a second substrate SB1 and depositing a filter layer on the second substrate SB1. Specifically, as... Figure 1 As shown, a second substrate SB1 can be provided first, and a first filter layer CF1, a second filter layer CF2, and a third filter layer CF3 can be formed on the second substrate SB1 to form a filter layer structure CFL. It should be noted that the first filter layer CF1, the second filter layer CF2, and the third filter layer CF3 can be patterned respectively, so that after the second substrate structure SS2 is subsequently bonded to the first substrate structure SS1, the portion of the filter layer structure CFL corresponding to an optical unit LCU can include only a filter layer with the same color as the light after passing through the optical unit LCU. Figure 13For example, it is shown that the first filter layer CFL and the third filter layer CF3 correspond to a portion of the optical unit LCU being removed, while the second filter layer CF2 corresponds to the structure of the optical unit LCU. In this case, Figure 13 The shown optical unit LCU can be the optical unit LCU2.

[0127] Then, the process of the second substrate structure SS2 can comprise a step S208 of providing a functional layer FC on the filter layer. Specifically, after providing the filter layer structure CFL on the second substrate SB1, the functional layer FC can be provided on the filter layer structure CFL. The functional layer FC of the present embodiment can for example refer to the shown, but not limited to, insulating layer IN8. After providing the functional layer FC, the second substrate structure SS2 can be formed. Figure 13

[0128] It is noted that the processes of the first substrate structure SS1 and the second substrate structure SS2 can be performed in any order or can be performed simultaneously, and the present embodiment is not limited thereto. In addition, the first substrate structure SS1 and the second substrate structure SS2 can further comprise other suitable elements or film layers, and the present embodiment is not limited to the shown structure. Figure 1

[0129] After forming the first substrate structure SS1 and the second substrate structure SS2, the manufacturing method M200 of the electronic device ED can comprise a step S209 of forming a sealing layer SL and a filling layer FL on the first substrate. Specifically, as shown in ​

[0130] Then, the manufacturing method M200 of the electronic device ED can comprise a step S210 of aligning and adhering the first substrate with the second substrate. Specifically, as shown in ​

[0131] ​​​​Next, the manufacturing method M200 of the electronic device ED can include a step S211 of performing a cutting process. Specifically, after the first substrate structure SS1 and the second substrate structure SS2 are aligned and attached, a cutting process can be performed on the formed structure to divide it into a plurality of electronic panels.

[0132] Next, the manufacturing method M200 of the electronic device ED can include a step S212 of disposing an optical film on the side of the second substrate SB1 opposite the color filter layer structure CFL. Specifically, although not shown in the figures, after the electronic panels are formed by the cutting process, an optical film, such as the anti-reflection layer AR shown in FIG. 1, can be formed on the second substrate SB1 of one of the electronic panels to form the electronic device ED, thereby improving the light extraction efficiency of the electronic device ED. ​

[0133] It should be noted that the manufacturing method M200 of the electronic device ED can also include other suitable steps and is not limited to the steps described above.

[0134] In summary, the present application provides an electronic device including an insulating layer disposed on a light emitting unit, wherein the insulating layer includes a plurality of openings. A portion of the plurality of openings of the insulating layer can be disposed with optical units, while another portion of the plurality of openings can be disposed without optical units and can overlap specific elements (such as transistors, light sensors, etc.) in the electronic device in the top-down direction of the electronic device. Through the above design, specific processes can be performed on the elements or film layers under the insulating layer through the openings without optical units, thereby improving the process yield of the electronic device.

[0135] The above only describes the embodiments of the present application and is not intended to limit the present application. For those skilled in the art, the present application can have various modifications and changes. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.​

Claims

1. An electronic device, characterized by comprising: Including: a substrate; a plurality of transistors provided over the substrate; a light emitting unit provided over at least one of the plurality of transistors; a first insulating layer provided over the light emitting unit and having a first opening and a second opening; and an optical unit provided in the first opening; wherein, in a plan view of the electronic device, the first opening overlaps at least a portion of the light emitting unit, and the second opening overlaps at least a portion of the at least one of the plurality of transistors. The second opening overlaps a gate electrode of one of the at least one of the plurality of transistors, and a width of the second opening is greater than a width of the gate electrode. 2.The electronic device of claim 1, wherein, The second opening overlaps a source electrode of one of the at least one of the plurality of transistors, and a width of the second opening is greater than a width of the source electrode. 3.The electronic device of claim 1, wherein, The second opening overlaps a drain electrode of one of the at least one of the plurality of transistors, and a width of the second opening is greater than a width of the drain electrode. 4.The electronic device of claim 1, wherein, One of the at least one of the plurality of transistors includes a first semiconductor and a second semiconductor, the second semiconductor being provided between the first semiconductor and the substrate. 5.The electronic device of claim 1, wherein, Further including a second insulating layer provided between the first semiconductor and the second semiconductor, the second insulating layer directly contacting the second semiconductor. 6.The electronic device of claim 5, wherein, The second insulating layer includes a metal oxide material. 7.The electronic device of claim 6, wherein, The one of the at least one of the plurality of transistors includes a source electrode and a drain electrode, one of the source electrode and the drain electrode being electrically connected to the first semiconductor and the second semiconductor. 8.The electronic device of claim 5, wherein, A thickness of the second semiconductor is less than a thickness of the first semiconductor. 9.The electronic device of claim 5, wherein, Further including a third insulating layer provided over the first insulating layer, a portion of the third insulating layer being provided in the second opening. 10.The electronic device of claim 1, wherein, Further including a first filter layer provided over the first insulating layer, a portion of the first filter layer being provided in the second opening, and in the plan view of the electronic device, the first filter layer overlaps the optical unit. 11.The electronic device of claim 1, wherein, Further including a second filter layer provided over the first insulating layer, a portion of the second filter layer being provided in the second opening, and in the plan view of the electronic device, the second filter layer does not overlap the optical unit. 12.The electronic device of claim 11, wherein, Further including a light sensor provided between the first insulating layer and the substrate, in the plan view of the electronic device, the second opening overlaps at least a portion of the light sensor. 13.The electronic device of claim 1, wherein, Further including a first filter layer provided over the first insulating layer, a portion of the first filter layer being provided in the second opening and having a first filter opening, in the plan view of the electronic device, the first filter layer overlaps the optical unit. 14.The electronic device of claim 13, wherein, ​ 15.The electronic device of claim 14, wherein, A second filter layer is further included and disposed on the first insulating layer, a portion of the second filter layer is disposed in the second opening and has a second filter opening, and the second filter layer does not overlap the optical unit in the top-down direction of the electronic device. 16.The electronic device of claim 1, wherein, A light sensor is further included and disposed between the first insulating layer and the substrate, and the first insulating layer includes a third opening that overlaps at least a portion of the light sensor in the top-down direction of the electronic device. 17.The electronic device of claim 1, wherein, The first opening overlaps a first portion of the plurality of transistors, the second opening overlaps a second portion of the plurality of transistors, and the number of the first portion of the plurality of transistors is different from the number of the second portion of the plurality of transistors. 18.The electronic device of claim 17, wherein, The number of the first portion of the plurality of transistors is less than the number of the second portion of the plurality of transistors. The number of the first portion of the plurality of transistors is less than the number of the second portion of the plurality of transistors.

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