Vertical fin type display sensing module and preparation method thereof

Abstract

The invention relates to the technical field of intelligent integrated devices, in particular to a vertical fin type display sensing module and a preparation method thereof.The module comprises a driving backboard and an anode on the driving backboard, the anode is provided with a semiconductor fin type structure, the semiconductor fin type structure comprises an n + GaN layer and a graphical n-GaN epitaxial layer, a protruding fin part with a notch is formed, and the n + GaN layer is arranged on the n + GaN layer. A P + region and a P + + region are formed by ion implantation on the side walls of the gap and the fin part, an N + region is formed at the top, a grid electrode is arranged on the P + + region, a metal layer and a transparent conductive oxide layer are arranged on the N + region, and a light-emitting unit is bonded on the transparent conductive oxide layer; the image sensing unit is overlapped with the projection of the fin type structure and comprises a light filtering layer and a micro lens. The preparation method comprises the steps of patterning to form the fin type structure, performing selective ion implantation to realize P / N region doping, and transferring and bonding the light-emitting unit in a huge amount. High-performance driving and sensing functions are integrated on a single chip through a GaN fin type structure, the problems of low performance, complex process and high cost in the prior art are solved, and integrated fusion of display and sensing is achieved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of intelligent integrated devices, and in particular to a vertical fin type display sensing module and a preparation method thereof. BACKGROUND

[0002] With the rapid development of artificial intelligence, Internet of Things and next-generation human-computer interaction technology, the market has put forward higher requirements for the functional integration of intelligent electronic devices. Traditional display devices can only realize the single function of information output, and the interaction function needs to rely on external independent elements such as cameras and infrared sensors. This kind of separate design not only increases the volume, power consumption and cost of the system, but also constitutes a bottleneck in response speed and integration.

[0003] In recent years, the industry has proposed an integrated concept of integrating image sensing functions inside the display panel, in order to realize advanced interaction functions such as under-screen fingerprint recognition, gesture control and gaze tracking. However, the existing integration schemes mostly adopt the way of arranging the traditional planar photoelectric sensor array and display pixels side by side or in a stacked manner. These schemes have limitations: the sensing unit and the display unit are independent in physical structure and driving mode, which leads to a decrease in pixel aperture ratio, significantly affecting the display resolution and brightness; the planar sensor has low carrier mobility and slow response speed, which is difficult to meet the demand of real-time and high-speed image capture; and the manufacturing process of display and sensing functions has poor compatibility, often requiring complex integration processes, low yield and high cost. SUMMARY

[0004] The technical problem to be solved by the present application is to solve the problems of low performance, complex process and high cost of the existing integration scheme, and to provide a vertical fin type display sensing module, which solves the problem of difficult to balance performance, process and cost in the existing display sensing integration technology through vertical fin type device structure and integration process. The technical scheme adopted by the present application to solve the technical problem is: a vertical fin type display sensing module, comprising a driving backplate, wherein the driving backplate is provided with an anode, The anode is provided with a semiconductor fin structure, the semiconductor fin structure comprises an n+ GaN layer and an n- GaN epitaxial layer which are stacked in order from bottom to top, the n- GaN epitaxial layer is patterned to form at least one protruding fin portion, and the area between the fin portions constitutes a gap. The gap and the fin sidewall are formed with P+ regions and P++ heavily doped regions on the P+ regions by ion implantation, the fin top is formed with N+ regions by ion implantation, a gate is formed on the P++ heavily doped regions, a metal layer in ohmic contact with the N+ regions and a transparent conductive oxide layer covering the metal layer are arranged on the N+ regions, and a light emitting unit is bonded on the transparent conductive oxide layer; Further comprising an image sensing unit, which at least partially overlaps with the projection of the semiconductor fin structure on the driving backboard, and which comprises a light filter layer and a microlens layer.

[0005] By integrating the three-dimensional gate-controlled driving unit and the high-mobility sensing unit on the same semiconductor fin structure, the contradiction between the performance and the integration of the traditional planar structure is broken, and a foundation is provided for high-performance single-chip fusion.

[0006] According to an embodiment of the present application, the light filter layer is a composite structure of an RGB light filter layer and a QD quantum dot layer.

[0007] The color resolution and the light conversion efficiency of the image sensing unit are improved, and the defects of large light loss and low sensing performance caused by the traditional light filter are overcome.

[0008] According to an embodiment of the present application, the light emitting unit is a micro light emitting diode, which comprises, from bottom to top, a P-type bonding metal layer, a P-type GaN layer, a multi-quantum well light emitting layer, an N-type GaN layer and an N-type bonding metal layer.

[0009] The light emitting unit is a Micro-LED stacked structure, which ensures that the display function has the performance of high brightness, high contrast and low power consumption, and meets the needs of high-end display.

[0010] According to an embodiment of the present application, further comprising an interlayer dielectric layer covering the semiconductor fin structure, the doped regions and the gate; a common cathode electrically connected to the light emitting unit and the image sensing unit through electrodes on the interlayer dielectric layer is arranged on the interlayer dielectric layer, and the common cathode is covered with a thin film encapsulation layer.

[0011] The system is simplified, and the complexity and the packaging cost are reduced.

[0012] Further provided is a preparation method of the vertical fin display sensing module as described in the above-mentioned solution, comprising the following steps: S1, a driving backboard is prepared, a plurality of regularly arranged through holes are formed on the driving backboard, and a conductive material is filled in the through holes, then a plurality of anodes are formed on the upper surface of the driving backboard, and each anode covers at least one through hole; S2, growing n+ GaN layer and n- GaN epitaxial layer on the anode in turn, and patterning the n- GaN epitaxial layer to form a semiconductor fin structure with at least one protruding fin, the area between the fins constituting a gap; S3, forming P+ region in the gap and fin sidewall by ion implantation, forming P++ heavily doped region on the P+ region, and forming N+ region on the top of the fin; S4, growing a polysilicon layer on the P++ heavily doped region to form a gate; S5, depositing an interlayer dielectric layer, a metal layer and a transparent conductive oxide layer, and performing chemical mechanical polishing to form planarization; S6, using mass transfer and bonding process to bond the light emitting unit to the transparent conductive oxide layer; S7, forming a common cathode on the top surface of the light emitting unit bonded with the light emitting unit and the transparent conductive oxide layer corresponding to the image sensing unit, and growing a thin film packaging layer; S8, preparing an RGB filter layer and a microlens layer in the area corresponding to the image sensing unit on the thin film packaging layer by a photolithography process, preparing a QD quantum dot layer in the area corresponding to the light emitting unit, and packaging by a glass cover plate.

[0013] By patterning the fin structure and selective ion implantation, high-precision and high-yield preparation of the three-dimensional fin structure is realized, and selective ion implantation ensures accurate doping of P-type and N-type regions in three-dimensional space, realizing high-performance, low-leakage driving and sensing function.

[0014] According to one embodiment of the present application, the RGB filter layer in step S8 includes a red filter, a green filter and a blue filter; and the QD quantum dot layer includes a red quantum dot layer and a green quantum dot layer.

[0015] According to one embodiment of the present application, a black matrix is further included, which is arranged around the periphery of the red filter, the green filter and the blue filter, and the red quantum dot layer and the green quantum dot layer, for light shielding.

[0016] By integrating the QD quantum dot layer and the black matrix, color conversion of the display unit and light shielding protection of the sensing unit are realized simultaneously in the process, simplifying the manufacturing steps and improving the overall performance and yield.

[0017] According to one embodiment of the present application, the P+ region, the P++ heavily doped region and the N+ region in step S3 are realized by a selective ion implantation process.

[0018] In addition, a preparation method of a vertical fin display sensing module is also provided, which includes the following steps: S1', a driving backplane is prepared, a plurality of regularly arranged through holes are formed on the driving backplane, and a conductive material is filled in the through holes, and then a plurality of anodes are formed on the upper surface of the driving backplane, and each anode covers at least one through hole; S2', an n+ GaN layer and an n- GaN epitaxial layer are sequentially grown on the anode, and the n- GaN epitaxial layer is patterned to form a semiconductor structure with a gap; S3', a P+ GaN region is formed in the gap by ion implantation; S4', a polysilicon layer is deposited and patterned to form a gate, and then a metal layer is deposited and patterned to form a source, the source surrounds the gate and is isolated from the gate by an oxide layer; S5', a transparent conductive oxide layer is deposited on the source, and a chemical mechanical polishing is performed after growing an interlayer dielectric layer; S6', a large-scale transfer and bonding process is used to bond the light emitting unit to the transparent conductive oxide layer; S7', a common cathode is formed on the top surface of the light emitting unit bonded with the light emitting unit and the transparent conductive oxide layer corresponding to the image sensing unit, and a thin film encapsulation layer is grown; S8', an RGB filter layer and a microlens layer are prepared on the thin film encapsulation layer corresponding to the image sensing unit by a photolithography process, a QD quantum dot layer is prepared on the thin film encapsulation layer corresponding to the light emitting unit, and the whole is encapsulated by a glass cover plate.

[0019] By forming a planar structure in which the source surrounds the gate, a high-performance technical means compatible with standard planar processes is provided, and the use of an aluminum source reduces the contact resistance and improves the driving capability, providing diversity and flexibility for the realization of different technical routes.

[0020] According to one embodiment of the present application, the source formed in step S4' is a metal aluminum layer.

[0021] Advantages of the present application: The three-dimensional fin structure based on gallium nitride material has high electron mobility and excellent gate control capability, providing a unified high-performance single-chip platform for driving and sensing functions, realizing the simultaneous improvement of high resolution, high brightness, high contrast display and high speed, high sensitivity image sensing, and breaking the performance limitation of traditional planar structures due to low mobility and aperture ratio; By selective ion implantation, a P-type driving region and an N-type sensing region are precisely formed on a single fin structure, and combined with a large-scale transfer bonding and chemical mechanical polishing process, high-precision and high-yield monolithic integration of Micro-LED display units and photoelectric sensing units is realized, avoiding complex epitaxial growth or high-temperature and high-pressure bonding processes, and significantly reducing process complexity and manufacturing cost; The composite structure of the RGB filter and the QD quantum dot layer further optimizes light utilization efficiency and color fidelity, and the integrated design of the common cathode and the film packaging enhances the reliability and integration of the device. Not only can high resolution, high brightness, high contrast and low response time display functions be realized, but also real-time external image signals can be received, and an optimized driving circuit is matched, which provides a feasible solution for single-chip integration of man-machine interaction display. BRIEF DESCRIPTION OF DRAWINGS

[0022] The application will be further described below with reference to the drawings and examples.

[0023] Figure 1 is a structural schematic diagram of the embodiment one of the application.

[0024] Figure 2 is a schematic diagram of step 1 of the embodiment one of the application.

[0025] Figure 3 is a schematic diagram of step 2 of the embodiment one of the application.

[0026] Figure 4 is a schematic diagram of step 3 of the embodiment one of the application.

[0027] Figure 5 is a schematic diagram of step 4 of the embodiment one of the application.

[0028] Figure 6 is a schematic diagram of step 5 of the embodiment one of the application.

[0029] Figure 7 is a schematic diagram of step 6 of the embodiment one of the application.

[0030] Figure 8 is a schematic diagram of step 7 of the embodiment one of the application.

[0031] Figure 9 is a schematic diagram of step 8 of the embodiment one of the application.

[0032] Figure 10 is a current density diagram of the embodiment one of the application in operation.

[0033] Figure 11 is an electric field intensity diagram of the embodiment one of the application in operation.

[0034] Figure 12 is a structural schematic diagram of the embodiment two of the application.

[0035] Figure 13 is a schematic diagram of step 1 of the embodiment two of the application.

[0036] Figure 14 is a schematic diagram of step 2 of the embodiment two of the application.

[0037] Figure 15 is a schematic diagram of step 3 of embodiment two of the present application.

[0038] Figure 16 is a schematic diagram of step 4 of embodiment two of the present application.

[0039] Figure 17 is a schematic diagram of step 5 of embodiment two of the present application.

[0040] Figure 18 is a schematic diagram of step 6 of embodiment two of the present application.

[0041] Figure 19 is a schematic diagram of step 7 of embodiment two of the present application.

[0042] Figure 20 is a schematic diagram of step 8 of embodiment two of the present application.

[0043] Figure 21 is a current density diagram of the working of embodiment two of the present application.

[0044] Figure 22 is an electric field intensity diagram of the working of embodiment two of the present application.

[0045] Figure 23 is a driving circuit diagram of embodiment one and embodiment two of the present application.

[0046] In the figure: 1, driving back plate; 2, anode; 3, semiconductor fin structure; 31, n+ GaN layer; 32, n- GaN epitaxial layer; 33, P+ region; 34, P++ heavily doped region; 35, N+ region; 36, P+ GaN region; 37, polysilicon layer; 38, oxide layer; 39, metal aluminum layer; 4, metal layer; 5, transparent conductive oxide layer; 6, image sensing unit; 7, filter layer; 71, red filter; 72, green filter; 73, blue filter; 74, red quantum dot layer; 75, green quantum dot layer; 76, black matrix; 8, microlens layer; 9, interlayer dielectric layer; 10, common cathode; 11, thin film packaging layer; 12, light emitting unit; 121, P-type bonding metal layer; 122, P-type GaN layer; 123, multiple quantum well light emitting layer; 124, N-type GaN layer; 125, N-type bonding metal layer; 13, glass cover plate. DETAILED DESCRIPTION

[0047] The present application will now be further described in greater detail in connection with the enclosed drawings. These drawings form a part of this specification and are included to further illustrate the present application and, therefore, are to be construed along with the detailed description of the present application. The drawings are not drawn to scale since the emphasis of the drawings is on illustrating the structural features of the present application rather than providing accurate scale representations.

[0048] Embodiment one As Figure 1As shown, a vertical fin-type display sensing module includes a driving backplate 1, an anode 2 on the driving backplate 1, and a semiconductor fin structure 3 on the anode 2. The semiconductor fin structure 3 includes an n+ GaN layer 31 and an n- GaN epitaxial layer 32 stacked sequentially from bottom to top. The n- GaN epitaxial layer 32 is patterned to form at least one protruding fin. The area between the fins forms a notch. P+ regions 33 and P++ heavily doped regions 34 on the P+ regions 33 are formed by ion implantation within the notch and on the sidewalls of the fins. An N+ region 35 is formed on the top of the fin by ion implantation. A gate is formed on the P++ heavily doped region 34. A metal layer 4 in ohmic contact with the N+ region 35 and a transparent conductive oxide layer 5 covering the metal layer 4 are provided on the transparent conductive oxide layer 5. A light-emitting unit 12 is bonded on the transparent conductive oxide layer 5. The module also includes an image sensing unit 6, which at least partially overlaps with the projection of the semiconductor fin structure 3 on the driving backplate 1. The image sensing unit 6 includes a filter layer 7 and a microlens layer 8. It also includes an interlayer dielectric layer 9, which covers the semiconductor fin structure 3, the doped region and the gate; a common cathode 10 is disposed on the interlayer dielectric layer 9 and electrically connected to the light-emitting unit 12 and the image sensing unit 6 through an electrode groove thereon, and the common cathode 10 is covered with a thin film encapsulation layer 11.

[0049] The filter layer 7 is a composite structure of an RGB filter layer and a QD quantum dot layer. The RGB filter layer includes a red filter 71, a green filter 72, and a blue filter 73. The QD quantum dot layer includes a red quantum dot layer 74 and a green quantum dot layer 75. It also includes a black matrix 76, which is arranged around the red filter 71, green filter 72, blue filter 73, red quantum dot layer 74, and green quantum dot layer 75 for light blocking.

[0050] The light-emitting unit 12 is a miniature light-emitting diode, which includes, from bottom to top, a P-type bonding metal layer 121, a P-type GaN layer 122, a multi-quantum-well light-emitting layer 123, an N-type GaN layer 124, and an N-type bonding metal layer 125.

[0051] The fabrication method of the vertical fin display sensor module of Example 1 includes the following steps: Step 1: As Figure 2 As shown, a drive backplate 1 is prepared, and a number of regularly arranged vias are formed on the drive backplate 1. The vias are filled with conductive material, and then a number of anodes 2 are formed on the upper surface of the drive backplate 1, with each anode 2 covering at least one via. Step 2: As Figure 3 As shown, an n+ GaN layer 31 and an n- GaN epitaxial layer 32 are sequentially grown on the anode 2, and the n- GaN epitaxial layer 32 is patterned to form a semiconductor fin structure 3 with at least one protruding fin, and the region between the fins forms a gap. Step 3: As shown in Figure 4 , P+ region 33 is formed in the gap and the fin sidewall by ion implantation, P++ heavily doped region 34 is formed on P+ region 33, and N+ region 35 is formed on the top of the fin; Step 4: As shown in Figure 5 , a polysilicon layer 37 is grown on P++ heavily doped region 34 to form a gate; Step 5: As shown in Figure 6 , an interlayer dielectric layer 9, a metal layer 4 and a transparent conductive oxide layer 5 are deposited, and chemical mechanical polishing is performed to form planarization; Step 6: As shown in Figure 7 , a light emitting unit 12 is bonded to the transparent conductive oxide layer 5 using a mass transfer and bonding process; Step 7: As shown in Figure 8 , a common cathode 10 is formed on the top surface of the bonded light emitting unit 12 and the transparent conductive oxide layer 5 corresponding to the image sensing unit 6, and a thin film encapsulation layer 11 is grown; Step 8: As shown in Figure 9 , an RGB filter layer and a microlens layer 8 are prepared in the area corresponding to the image sensing unit 6 on the thin film encapsulation layer 11 by a photolithography process, a QD quantum dot layer is prepared in the area corresponding to the light emitting unit 12, and the module is encapsulated by a glass cover plate 13. The black arrows in the figure represent the current direction.

[0052] The P+ region 33, the P++ heavily doped region 34 and the N+ region 35 in Step 3 are realized by a selective ion implantation process.

[0053] A three-dimensional channel structure is created, providing a physical basis for subsequent excellent gate control capability and high mobility sensing, and fundamentally breaking through the performance limitations of planar devices; By forming P-type and N-type doped regions at precise positions of the three-dimensional structure, monolithic integration and electrical isolation of the driving transistor and the photodiode are realized on a single fin structure, avoiding complex subsequent bonding and interconnection. The metal layer is used to form a low-resistance ohmic contact with the N+ region; The covered ITO layer provides a stable and oxidation-resistant ideal bonding surface. The RGB filter performs primary spectral selection on incident light, and the QD quantum dot layer further absorbs and converts light, emitting light with higher color purity. The two work together to significantly improve the color resolution and sensitivity of the image sensing unit, and the black matrix effectively suppresses optical crosstalk.

[0054] The vertical fin display sensing module prepared by the above method has a current density and an electric field strength during operation as shown in Figure 10 and Figure 11As shown, the device exhibits good conduction characteristics in the on state. The electric field distribution inside the device is uniform and the peak electric field is located in the design expected region, which helps to improve the breakdown voltage and reliability of the device and achieves excellent withstand voltage performance, thus meeting the application requirements of high-performance power semiconductor devices.

[0055] Example 2 The difference from Example 1 is as follows: Figure 12 As shown, the n-GaN epitaxial layer 32 is patterned to form a notch, and a P+ GaN region 36 is formed in the notch by ion implantation. A polycrystalline silicon layer 37 is deposited on the P+ GaN region 36 in the middle. A metal aluminum layer 39 is wrapped around the polycrystalline silicon layer 37 at a certain distance. An oxide layer 38 is provided between the two. The oxide layer 38 is flush with the metal aluminum layer 39. The top of the two is covered by a transparent conductive oxide layer 5.

[0056] The method for fabricating the vertical fin display sensor module of Example 2 includes the following steps: Step 1: As Figure 13 As shown, a drive backplate 1 is prepared, and a number of regularly arranged vias are formed on the drive backplate 1. The vias are filled with conductive material, and then a number of anodes 2 are formed on the upper surface of the drive backplate 1, with each anode covering at least one via. Step 2: As Figure 14 As shown, an n+ GaN layer 31 and an n- GaN epitaxial layer 32 are sequentially grown on the anode 2, and the n- GaN epitaxial layer 32 is patterned to form a semiconductor structure with a notch; Step 3: As Figure 15 As shown, a P+ GaN region 36 is formed within the notch by ion implantation; Step 4: As Figure 16 As shown, a polysilicon layer 37 is deposited and patterned to form a gate, followed by the deposition and patterning of an aluminum metal layer 39 to form a source, the source surrounding the gate and the two being isolated by an oxide layer 38. Step 5: As Figure 17 As shown, a transparent conductive oxide layer 5 is deposited on the source electrode, and an interlayer dielectric layer 9 is grown before chemical mechanical polishing is performed. Step 6: As Figure 18 As shown, the light-emitting unit 12 is bonded to the transparent conductive oxide layer 5 using a mass transfer and bonding process; Step 7: As Figure 19 As shown, a common cathode 10 and a thin film encapsulation layer 11 are formed on the top surface of the light-emitting unit 12 and the transparent conductive oxide layer 5 corresponding to the image sensing unit 12. Step 8: As Figure 20As shown, the region corresponding to the image sensing unit 6 on the thin film packaging layer 11 is prepared with an RGB filter layer and a microlens layer 8 by a yellow light process, the region corresponding to the light emitting unit 12 is prepared with a QD quantum dot layer, and is packaged by a glass cover plate 13, and the black arrow in the figure represents the current direction.

[0057] The structure of step 4 enhances the control ability of the channel carriers by using the lateral capacitive coupling between the metal source and the polysilicon gate, is a high-efficiency planar surround gate variant, and can obtain the gate control performance of a nearly three-dimensional device on a planar process platform. The scheme provides a different technical means from embodiment one, has higher compatibility with the existing planar semiconductor manufacturing process, reduces the manufacturing difficulty, and at the same time guarantees the driving performance through the optimized structure.

[0058] The current density and electric field intensity of the vertical fin type display sensing module prepared by the above method during work are respectively as shown in Figure 21 and Figure 22 It can be seen that the device shows high current handling capability in the on state, and excellent on characteristics. The electric field intensity distribution shows that the internal electric field of the device is effectively modulated, the peak electric field is located in the expected region of the structure design, and the on performance is further improved while ensuring high breakdown voltage, significantly optimizing the power conversion efficiency and reliability, and especially suitable for power semiconductor devices integrated with electronic applications.

[0059] The driving circuit shown in Figure 23 of embodiment one and embodiment two can improve the performance and reliability of the display, has the beneficial effects of high integration, low power consumption, high speed and good stability, and has a wide range of applications.

[0060] Based on the above ideal embodiments according to the application, through the above description, relevant personnel can make various changes and modifications without deviating from the technical idea of the application. The technical scope of the application is not limited to the contents of the specification, and must be determined according to the scope of the claims.

Claims

1. A vertical fin-type display sensing module, comprising a drive backplate (1), wherein an anode (2) is provided on the drive backplate (1), characterized in that: The anode (2) is provided with a semiconductor fin structure (3), the semiconductor fin structure (3) includes an n+ GaN layer (31) and an n- GaN epitaxial layer (32) stacked sequentially from bottom to top, the n- GaN epitaxial layer (32) is patterned to form at least one protruding fin, and the area between the fins forms a gap. The notch and the sidewall of the fin are formed by ion implantation to form a P+ region (33) and a P++ heavily doped region (34) on the P+ region (33). The top of the fin is formed by ion implantation to form an N+ region (35). A gate is formed on the P++ heavily doped region (34). The N+ region (35) is provided with a metal layer (4) in ohmic contact with it and a transparent conductive oxide layer (5) covering the metal layer (4). A light-emitting unit (12) is bonded on the transparent conductive oxide layer (5). It also includes an image sensing unit (6) that at least partially overlaps with the projection of the semiconductor fin structure (3) onto the drive backplate (1), which includes a filter layer (7) and a microlens layer (8).

2. The vertical fin-type display sensor module according to claim 1, characterized in that: The filter layer (7) is a composite structure of an RGB filter layer and a QD quantum dot layer.

3. The vertical fin-type display sensor module according to claim 1, characterized in that: The light-emitting unit (12) is a micro light-emitting diode, which includes, from bottom to top, a P-type bonded metal layer (121), a P-type GaN layer (122), a multi-quantum well light-emitting layer (123), an N-type GaN layer (124), and an N-type bonded metal layer (125).

4. The vertical fin-type display sensor module according to claim 1, characterized in that: It also includes an interlayer dielectric layer (9), which covers the semiconductor fin structure (3), the doped region and the gate; a common cathode (10) is provided on the interlayer dielectric layer (9) and electrically connected to the light-emitting unit and the image sensing unit (6) through the electrode groove thereon, and the common cathode (10) is covered with a thin film encapsulation layer (11).

5. A method for manufacturing a vertical fin-type display sensing module as described in claims 1-4, characterized in that, Includes the following steps: S1. Prepare a driving backplate (1), form a number of regularly arranged vias on the driving backplate (1), fill the vias with conductive material, and then form a number of anodes (2) on the upper surface of the driving backplate (1), with each anode (2) covering at least one via. S2. An n+ GaN layer (31) and an n- GaN epitaxial layer (32) are sequentially grown on the anode (2), and the n- GaN epitaxial layer (32) is patterned to form a semiconductor fin structure with at least one protruding fin, and the region between the fins forms a gap. S3. A P+ region (33) is formed in the notch and the sidewall of the fin by ion implantation, a P++ heavily doped region (34) is formed on the P+ region (33), and an N+ region (35) is formed on the top of the fin. S4. A polysilicon layer (37) is grown on the P++ heavily doped region (34) to form a gate; S5, deposited interlayer dielectric layer (9), metal layer (4) and transparent conductive oxide layer (5), and chemical mechanical polishing to form planarization; S6. The light-emitting unit (12) is bonded to the transparent conductive oxide layer (5) using a mass transfer and bonding process; S7. A common cathode (10) and a thin film encapsulation layer (11) are formed on the top surface of the bonding light-emitting unit (12) and the transparent conductive oxide layer (5) of the corresponding image sensing unit (6). S8. An RGB filter layer and a microlens layer (8) are prepared on the thin film encapsulation layer (11) in the region corresponding to the image sensing unit (6) using a photoluminescence process. A QD quantum dot layer is prepared in the region corresponding to the light-emitting unit (12), and then encapsulated by a glass cover plate (13).

6. The method for fabricating a vertical fin-type display sensing module according to claim 5, characterized in that: The RGB filter layer in step S8 includes a red filter (71), a green filter (72) and a blue filter (73); the QD quantum dot layer includes a red quantum dot layer (74) and a green quantum dot layer (75).

7. The method for fabricating a vertical fin-type display sensing module according to claim 6, characterized in that: It also includes a black matrix (76) which is arranged around the periphery of a red filter (71), a green filter (72) and a blue filter (73) as well as a red quantum dot layer (74) and a green quantum dot layer (75) for light blocking.

8. The method for fabricating a vertical fin-type display sensing module according to claim 5, characterized in that: In step S3, the formation of the P+ region (33), the P++ heavily doped region (34), and the N+ region (35) is achieved by selective ion implantation.

9. A method for manufacturing a vertical fin-type display sensing module as described in claims 1-4, characterized in that, Includes the following steps: S1', Prepare a driving backplate (1), form a number of regularly arranged vias on the driving backplate (1), fill the vias with conductive material, and then form a number of anodes (2) on the upper surface of the driving backplate (1), with each anode (2) covering at least one via; S2', an n+ GaN layer (31) and an n- GaN epitaxial layer (32) are sequentially grown on the anode (2), and the n- GaN epitaxial layer (32) is patterned to form a semiconductor structure with a notch; S3', A P+ GaN region is formed in the notch by ion implantation (36); S4', deposit a polysilicon layer (37) and pattern it to form a gate, then deposit a metal layer and pattern it to form a source, the source surrounds the gate and the two are isolated by an oxide layer (38). S5', After depositing a transparent conductive oxide layer (5) on the source electrode and growing an interlayer dielectric layer (9), perform chemical mechanical polishing; S6' The light-emitting unit (12) is bonded to the transparent conductive oxide layer (5) using a mass transfer and bonding process; S7', A common cathode (10) and a thin film encapsulation layer (11) are formed on the top surface of the bonding light-emitting unit (12) and the transparent conductive oxide layer (5) of the corresponding image sensing unit (6). S8'. An RGB filter layer and a microlens layer (8) are prepared on the thin film encapsulation layer (11) in the region corresponding to the image sensing unit (6) using a photoluminescence process. A QD quantum dot layer is prepared in the region corresponding to the light-emitting unit (12), and then encapsulated by a glass cover plate (13).

10. The method for manufacturing a vertical fin-type display sensing module according to claim 9, characterized in that: The source layer formed in step S4' is a metallic aluminum layer (39).

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