Wiring optimization method and device for printed circuit board, equipment and medium

Abstract

The invention relates to the technical field of artificial intelligence, and discloses a wiring optimization method and device for a printed circuit board, equipment and a medium, and the method comprises the steps: recognizing the number of layers, obtained in advance, of the printed circuit board, carrying out the multi-dimensional feature analysis of the circuit wiring of each layer according to the number of layers, and obtaining the global wiring features of a circuit; performing wiring analysis on the global wiring characteristics of the circuit by using a predetermined optimization analysis algorithm to obtain a global wiring optimization path; extracting local key wiring features in the global wiring optimization path, and performing wiring analysis on the local key wiring features by using an optimization analysis algorithm to obtain a local wiring optimization path; and generating a wiring optimization scheme of the printed circuit board according to the global wiring optimization path and the local wiring optimization path. And the wiring accuracy of the printed circuit board is improved.

Description

Technical Field

[0001] This invention relates to the field of artificial intelligence technology, and in particular to a method, apparatus, device and medium for optimizing the wiring of printed circuit boards. Background Technology

[0002] With the rapid development of consumer electronics, communication equipment, industrial control and other fields, the requirements of electronic systems for integration, functional density and performance continue to rise. From traditional through-hole components to surface mount devices, and then to packaging forms such as BGA and CSP, the size of components is constantly shrinking and the number of pins is increasing significantly, resulting in extremely tight PCB wiring space. Traditional manual wiring is difficult to cope with signal connections between dense pins.

[0003] Existing PCB routing optimization techniques rely on manual routing, which leads to substandard overall performance and requires multiple trial and error tests. Details such as length control, impedance matching, and grounding strategies are easily overlooked by humans, resulting in design defects that can cause signal distortion, excessive EMI, and heat dissipation during the debugging phase. Consequently, the accuracy of PCB routing is relatively low. Summary of the Invention

[0004] This invention provides a method, apparatus, device, and medium for optimizing the wiring of printed circuit boards, in order to solve the technical problem of low accuracy in the wiring of printed circuit boards.

[0005] Firstly, a method for optimizing the routing of a printed circuit board is provided, including: Identify the number of layers of the pre-acquired printed circuit board, and perform multi-dimensional feature analysis on the circuit wiring of each layer based on the number of layers to obtain the global circuit wiring features; The global routing characteristics of the circuit are analyzed using a predetermined optimization analysis algorithm to obtain the global routing optimization path; Extract local critical routing features from the global routing optimization path, and use the optimization analysis algorithm to perform routing analysis on the local critical routing features to obtain the local routing optimization path; A routing optimization scheme for the printed circuit board is generated based on the global routing optimization path and the local routing optimization path. Secondly, a wiring optimization device for printed circuit boards is provided, comprising: The circuit routing multi-dimensional feature analysis module is used to identify the number of layers of a pre-acquired printed circuit board, and to perform multi-dimensional feature analysis on the circuit routing of each layer based on the number of layers to obtain the global circuit routing features. A global routing optimization path generation module is used to perform routing analysis on the global routing characteristics of the circuit using a pre-determined optimization analysis algorithm to obtain a global routing optimization path. The local routing optimization path generation module is used to extract local critical routing features from the global routing optimization path, and use the optimization analysis algorithm to perform routing analysis on the local critical routing features to obtain the local routing optimization path. The routing optimization scheme generation module is used to generate a routing optimization scheme for the printed circuit board based on the global routing optimization path and the local routing optimization path. Thirdly, a computer device is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps of the above-described printed circuit board wiring optimization method.

[0006] Fourthly, a computer-readable storage medium is provided, which stores a computer program that, when executed by a processor, implements the steps of the above-described printed circuit board wiring optimization method.

[0007] In this invention, by first identifying the number of printed circuit board layers and then performing multi-dimensional feature analysis on each layer, the extraction of global routing features can better align with the limitations of the actual physical layers. By using a pre-determined optimization analysis algorithm to analyze global and local features separately, the subjective bias of human experience can be reduced, and a better solution can be found through a data-driven approach. Local paths ensure the rationality of the overall layout, while local paths supplement detailed optimization. The combined routing scheme can meet electrical performance requirements. Optimized paths based on global features provide a stable foundation for framework adjustments, while locally optimized paths can quickly respond to changes in local areas, giving the routing scheme greater flexibility and adaptability to iterative upgrades in different scenarios. This solves the technical problem of low accuracy in printed circuit board routing. Attached Figure Description

[0008] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0009] Figure 1 This is a schematic diagram of an application environment for a wiring optimization method for printed circuit boards according to an embodiment of the present invention; Figure 2 This is a schematic flowchart of a wiring optimization method for a printed circuit board according to an embodiment of the present invention; Figure 3 yes Figure 2 A flowchart illustrating a specific implementation method of step S1; Figure 4 yes Figure 2A flowchart illustrating a specific implementation method of step S2; Figure 5 This is a schematic diagram of a wiring optimization device for a printed circuit board according to an embodiment of the present invention; Figure 6 This is a schematic diagram of the structure of a computer device according to an embodiment of the present invention; Figure 7 This is another structural schematic diagram of a computer device according to one embodiment of the present invention. Detailed Implementation

[0010] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0011] The printed circuit board routing optimization method provided in this embodiment of the invention can be applied to, for example, Figure 1 In this application environment, the client communicates with the server via a network. The server can identify the number of layers of a pre-acquired printed circuit board (PCB) through the client, perform multi-dimensional feature analysis on the circuit routing of each layer based on the layer number, and obtain the global routing features of the circuit. It then uses a pre-determined optimization analysis algorithm to perform routing analysis on the global routing features, obtaining a global routing optimization path. Next, it extracts local critical routing features from the global routing optimization path, performs routing analysis on these local critical routing features using the optimization analysis algorithm, and obtains a local routing optimization path. Finally, it generates a routing optimization scheme for the PCB based on the global and local routing optimization paths, and feeds the routing optimization scheme back to the client. In this invention, by first identifying the number of PCB layers and then targeting each layer... Multi-dimensional feature analysis allows for extraction of global routing features that better aligns with the limitations of the actual physical layer. Utilizing pre-defined optimization algorithms to analyze global and local features separately reduces subjective bias from human experience, enabling the discovery of optimal solutions through data-driven approaches. Local paths ensure the rationality of the overall layout, while detailed optimization is supplemented by local paths; the combined routing scheme meets electrical performance requirements. Optimized paths based on global features provide a stable foundation for framework adjustments, while locally optimized paths can quickly respond to changes in local areas, giving the routing scheme greater flexibility and adaptability to iterative upgrades in different scenarios, thus solving the technical problem of low accuracy in printed circuit board routing. The client can be, but is not limited to, various personal computers, laptops, smartphones, tablets, and portable wearable devices. The server can be implemented using a standalone server or a server cluster consisting of multiple servers. The invention will be described in detail below through specific embodiments.

[0012] Please see Figure 2 As shown, Figure 2 A schematic flowchart of a printed circuit board routing optimization method provided in an embodiment of the present invention includes the following steps: S1. Identify the number of layers of the pre-acquired printed circuit board, and perform multi-dimensional feature analysis on the circuit wiring of each layer according to the number of layers to obtain the global circuit wiring features.

[0013] In this embodiment of the invention, the number of layers of a printed circuit board refers to the number of conductive copper foil layers that constitute the PCB (Printed Circuit Board). The copper foil layers are formed by alternating and pressing insulating materials, and the layers are electrically connected through metallized vias. Common number of layers include single layer, double layer, four layers, and six layers. Complex circuits may use more than a dozen layers or even more. The more layers there are, the more wiring space there is, which is more suitable for high-density and high-frequency circuits, but the cost is also higher. The number of layers directly affects the wiring density, signal integrity, electromagnetic compatibility, and manufacturing cost of the PCB.

[0014] In this embodiment of the invention, reference is made to Figure 3 As shown, identifying the number of layers of the pre-acquired printed circuit board includes: S31. Extract key constraint parameters of the printed circuit board based on the pre-acquired circuit design data; S32. Identify the circuit signals of the printed circuit board and determine the initial layer range of the printed circuit board based on the circuit signals; S33. Correct the initial layer range according to the key constraint parameters to obtain the stack-up structure of the printed circuit board, and determine the number of layers of the stack-up structure as the number of layers of the printed circuit board.

[0015] In detail, circuit design documents include schematics, component lists, signal specifications, and mechanical dimension requirements. The key constraint parameters extracted from these documents are the core limitations that determine the number of PCB layers. These key constraint parameters include electrical constraints, physical constraints, electromagnetic compatibility constraints, and cost and process constraints. Electrical constraints include signal type and frequency, current magnitude, and impedance matching requirements; physical constraints include PCB mechanical dimensions, component packaging, and layout density; electromagnetic compatibility constraints include interference immunity requirements and radiation limits; and cost and process constraints include manufacturing costs and processing technology limitations. The type and quantity of circuit signals are the basis for determining the number of layers. Different signals have significantly different requirements for wiring resources, and signal analysis can initially define the range of layers.

[0016] Specifically, signals are categorized by function into power signals, ground signals, digital signals (low / high speed), analog signals, and radio frequency signals. The number of each type of signal is counted, such as the number of high-speed differential signals and analog signals, along with wiring complexity (e.g., whether cross-wiring is required or long-distance transmission is involved). This determines the initial layer count range. For simple circuits, such as low-speed digital circuits with a few components, containing only a few dozen signals and no high-frequency / high-current requirements, a two-layer board is usually sufficient, with an initial range of 2 layers. For medium-complexity circuits, such as those containing microprocessors, multiple sensors, and low-frequency analog signals, 4 layers may be needed, such as one power layer, one ground layer, and two signal layers, with an initial range of 4 ± 2 layers. For highly complex circuits, such as those containing high-speed FPGAs, radio frequency modules, and multiple high-current power supplies, separate signal, power, ground, and shielding layers are required, with an initial range of 6 layers or more. The initial layer count range is based solely on the number and type of signals and needs to be adjusted in conjunction with key constraint parameters to ultimately obtain the specific stack-up structure and determine the precise layer count.

[0017] Furthermore, if there are mechanical size limitations in the key constraints, such as a PCB area ≤ 5cm × 5cm, and the initial range is 4 layers, but the actual wiring density is too high to be completed in 4 layers, then it needs to be revised upwards to 6 layers; if the key constraints have strict cost limitations, and the initial range is 6 layers, but the signal requirements can be met in 4 layers through optimized wiring, then it needs to be revised downwards to 4 layers. The stack-up structure is the functional classification and sorting order of each layer. For example, the common structure of a 4-layer board is top layer (signal layer) → ground layer → power layer → bottom layer (signal layer); the common structure of a 6-layer board is top layer (signal layer) → ground layer → signal layer → power layer → signal layer → bottom layer (signal layer). The stack-up structure needs to clearly define the function of each layer (signal, power, ground, shielding, etc.) to ensure that electrical constraints (such as impedance matching, EMC) and physical constraints (such as wiring space) are met. That is, the number of layers contained in the stack-up structure is the final number of PCB layers. For example, the stack-up structure of a 6-layer board contains 6 conductive layers, so the number of layers is determined to be 6.

[0018] Furthermore, the number of PCB layers directly determines the spatial division and functional division of routing, such as signal layers, power layers, and ground layers. The routing objectives and constraints of different layers are significantly different. The routing of each layer is not independent. Layers are connected through vias. Problems such as signal interference and path conflicts may exist across layers, and cross-layer collaborative optimization needs to be achieved through global feature integration.

[0019] In this embodiment of the invention, the global circuit routing features refer to a comprehensive set of features that reflect the routing status, signal interaction, constraint rules, and potential problems of each layer within the global scope of the printed circuit board (PCB). It covers multi-dimensional information such as routing function allocation, signal type distribution, component association, interference risk, routing rules, and path shape, and is the core basis for subsequent routing optimization, signal integrity analysis, and performance verification.

[0020] In this embodiment of the invention, the step of performing multi-dimensional feature analysis on the circuit routing of each layer according to the number of layers to obtain global circuit routing features includes: Based on the number of layers, the function of each layer circuit is determined to obtain the corresponding function type of each layer circuit. Based on the functional type, the signal type of each layer of the circuit is counted, the location of key components is marked in the circuit wiring of each layer according to the signal type, and the component location is associated with the signal type; Based on the associated component locations and signal types, determine the signal interference characteristics and wiring rule characteristics between components in the circuit routing of each layer; Based on the wiring rule features, the routing path features of the circuit wiring in each layer are identified, and the signal interference features, wiring rule features, and routing path features corresponding to the circuit wiring in each layer are determined as the global circuit wiring features.

[0021] In detail, based on the PCB's layer stack-up structure, the core function of each layer is clearly defined, and functional types are categorized. These functional types include signal layers, power layers, ground layers, and shielding layers. Signal layers transmit various electrical signals and are the primary carriers for routing. Power layers provide stable power to the circuit and are typically large-area copper foils, reducing power impedance. Ground layers serve as a common reference ground for the circuit and also shield against interference. Shielding layers isolate high-frequency noise or sensitive signals. Since the signal types of different functional layers differ significantly, it is necessary to statistically analyze and associate them with component locations to clarify the start and end points of routing. This involves statistically analyzing signal types, such as high-speed signals, low-speed signals, differential signals, and single-ended signals. For critical components that significantly impact routing, such as chips, connectors, and power devices, their physical coordinates need to be marked on the corresponding layers. For example, the location of a BGA chip on the top layer and the location of a power connector on the bottom layer. The pins of these components are then mapped to the transmitted signal types, forming a location-signal mapping relationship. For example, pins 1-4 of the top-layer BGA chip transmit DDR4 signal. Differential signals are correlated with top-level high-speed differential signals, and then based on location-signal correlation, the potential interference risks between components within the layer and the routing rules that must be followed are analyzed.

[0022] Specifically, signal interference characteristics refer to the risks of electromagnetic interference and crosstalk that may occur between different signals or components, such as same-layer interference, power interference, and grounding interference. Wiring rule characteristics refer to the design rules that wiring must follow to ensure normal signal transmission and circuit reliability. These wiring rule characteristics include electrical rules, physical rules, and functional rules. Wiring rules include line width and current, i.e., selecting line width based on current (e.g., at least 0.5mm line width for 1A current, referencing IPC standards); thickening power lines and high-current paths (e.g., 2oz copper thickness can reduce line width); signal integrity (SI); impedance control: high speed. Signals (such as USB, HDMI, differential pairs) need to be impedance matched (e.g., 50Ω single-ended, 100Ω differential), which is achieved by adjusting the line width and layer stack-up; equal-length routing rules are used to process differential signals or parallel buses (such as DDR, USB, LCD) into equal-length and differential pairs (length matching within ±50mil); shorten critical paths, that is, high-speed signals (such as clock lines) should be as short as possible and layer changes should be avoided; avoid sharp angles and right angles, use 45° or rounded corners for routing to reduce impedance abrupt changes and EMI radiation, and then, under the constraints of routing rules, analyze the actual or planned routing path shape and integrate multi-dimensional characteristics into global routing characteristics.

[0023] Furthermore, routing path characteristics refer to the physical form and topological relationship of the wiring, including path length, path direction, number of vias, and inter-layer connections. This is further integrated by considering the functional type, signal type distribution, component location association, signal interference characteristics, wiring rule characteristics, and routing path characteristics of each layer to form a global feature covering the entire board. For example, the global functional distribution includes a 6-layer board with 2 signal layers, 1 power layer, 2 ground layers, and 1 shielding layer; global signal interference risk, with high-speed signals on the top layer and analog signals on the bottom layer exhibiting cross-layer radiated interference, resulting in a high risk level; global wiring rule adaptation, with all differential signals meeting the 100Ω impedance requirement, but some high-current paths having insufficient trace width; and global routing path morphology, with an average of 5 vias per signal layer and a top layer winding rate of 20%.

[0024] Furthermore, modern circuit boards, such as multi-layer PCBs, contain hundreds or thousands of components and signal paths. Manual routing makes it difficult to balance all constraints and optimization goals, such as reducing interference, shortening length, and lowering costs. However, AI algorithms can efficiently handle complex multi-dimensional problems.

[0025] S2. Using a pre-determined optimization analysis algorithm, perform routing analysis on the global routing characteristics of the circuit to obtain the global routing optimization path.

[0026] In this embodiment of the invention, the global routing optimization path refers to the optimal routing scheme obtained by algorithm optimization, which covers all layers of the entire circuit board, under the premise of meeting circuit design rules such as spacing, line width and performance requirements such as low interference and low latency. It is an improvement on the original routing path and aims to balance circuit performance, reliability and manufacturing cost.

[0027] In this embodiment of the invention, the step of performing routing analysis on the global routing characteristics of the circuit using a pre-determined optimization analysis algorithm to obtain a global routing optimization path includes: The global routing characteristics of the circuit are converted into numerical indicators; The wiring constraints of the printed circuit board are determined based on the wiring rule features in the global wiring features of the circuit. The optimization objectives corresponding to the numerical indicators are analyzed using a predetermined optimization analysis algorithm; An iterative update rule for the optimization objective is generated based on the wiring constraints, and the optimization objective is iteratively updated according to the iterative update rule to obtain the updated optimization objective. The initial routing path corresponding to the circuit routing feature is optimized according to the optimization update target to obtain the global routing optimization path.

[0028] In detail, global circuit routing characteristics, such as signal interference intensity, trace path length, and routing rule restrictions, are mostly qualitative descriptions, such as strong interference and short paths. These need to be converted into calculable numerical indicators before they can be processed by the algorithm. For example, signal interference characteristics can be quantified as interference intensity values, represented by a value from 0 to 100, with higher values ​​indicating stronger interference. Trace path characteristics can be quantified as path length, number of corners, and trace width deviation. Routing rule characteristics can be quantified as rule compliance, such as 1 indicating complete compliance and 0 indicating violation of the rule. After numericalization, the algorithm can calculate and optimize the quantified indicators through mathematical models. Routing rule characteristics are hard rules that circuit design must follow, and they need to be converted into constraints for the algorithm to ensure that the optimization results are legal and compliant. For example, the constraint that power signal lines must maintain a distance of at least 2mm from signal lines is converted into a power-signal path distance ≥ 2mm; the constraint that high-frequency signals are prohibited from right-angle corners is converted into a high-frequency path corner angle ≠ 90°. The optimization objective is the optimal result that the algorithm needs to pursue. Based on the numerical indicators, it is usually to minimize or maximize one or more indicators.

[0029] In this embodiment of the invention, the optimization objectives include minimizing the total wiring length, minimizing the signal interference intensity, and maximizing the wiring rule compliance. The optimization analysis algorithm includes, but is not limited to, genetic algorithm, simulated annealing algorithm, and particle swarm optimization algorithm. The optimization algorithm will find the optimal combination among numerical indicators based on these objectives.

[0030] In this embodiment of the invention, the step of analyzing the optimization objective corresponding to the numerical index using a predetermined optimization analysis algorithm includes: Identify the wiring attribute mapping relationship between the numerical indicators and the wiring rule features; The numerical indicators are divided into hard indicators and soft indicators; Based on the wiring attribute mapping relationship, a first optimization objective for the hard indicators and a second optimization objective for the soft indicators are determined. The first optimization objective deviation index of the first optimization objective is calculated using the multi-objective optimization function in the predetermined optimization analysis algorithm, and the second optimization objective deviation index of the second optimization objective is calculated. The optimization index of the numerical index is determined based on the first optimization target deviation index and the second optimization target deviation index.

[0031] In detail, numerical indicators such as trace width, spacing, and interference intensity have a direct correspondence with wiring rule characteristics, such as power trace width ≥ 0.5mm and high-speed signal spacing ≥ 2mm. A mapping needs to be established to clarify the optimization direction for each indicator. For example, the wiring attribute mapping relationship is that the numerical indicator power trace width corresponds to a wiring rule of power trace width ≥ 0.5mm; the numerical indicator high-speed signal spacing corresponds to a wiring rule of high-speed signal spacing ≥ 2mm. Therefore, through the wiring attribute mapping relationship, the optimization analysis algorithm can transform the rules into indicators. Constraints or optimization objectives, such as a line width ≥ 0.5mm, are transformed into minimizing the difference between the line width and 0.5mm. Numerical indicators are then divided into hard indicators and soft indicators. Hard indicators are rules that must be strictly met, and violations will lead to design failure, such as power trace line width ≥ 0.5mm and via diameter ≥ 0.3mm. Soft indicators refer to rules that are expected to be optimized but allow for certain deviations, such as differential pair length difference ≤ 50mil and crystal oscillator peripheral radiation value ≤ -58dB. Based on the mapping relationship, specific optimization objectives are set for different types of indicators.

[0032] Specifically, the first optimization objective refers to the optimization objective corresponding to the hard indicators, which is to fully comply with the rules, that is, the indicator value is equal to or better than the rule threshold. If the rule is that the power trace width is ≥0.5mm, then the optimization objective is that the trace width = 0.5mm, minimizing redundancy and saving wiring space. The second optimization objective refers to the optimization objective corresponding to the soft indicators, which is to be close to the ideal value, allowing a certain deviation range. If the rule is that the difference in length between differential pairs is ≤50mil, then the optimization objective is to minimize the length difference, with an ideal value of 0mil, but allowing a deviation of ≤50mil. Furthermore, through a multi-objective optimization function, the degree of deviation of each indicator from the target value is quantified. The deviation indicator of the first optimization objective measures the degree of violation of the hard indicators, and the deviation = max(0, target value - actual value) or deviation = max(0, actual value - target value). The deviation indicator of the second optimization objective measures the difference between the soft indicators and the ideal value, allowing a certain deviation threshold, and the deviation = (actual value - ideal value). The deviation threshold is defined as follows: when the actual value exceeds the threshold, the deviation is 0; when the actual value is within the threshold, the deviation is 0. All deviation indicators are then integrated into a single or multi-dimensional optimization indicator as the final goal of the optimization analysis algorithm. For hard indicators, a penalty function mechanism is used to severely punish violations of rules, ensuring priority is given to meeting hard rules. For soft indicators, weights are assigned according to importance and summed using a weighted average, such as a length difference weight of 0.6 and an EMI weight of 0.4. This allows for the quantification of the overall optimization level through a single indicator. The optimization analysis algorithm can directly search for the minimum value of this indicator, achieving collaborative optimization of multiple objectives.

[0033] Furthermore, the optimization process is not completed in one go, but rather gradually approaches the optimal solution through multiple iterations. The iterative update rule is to set the search direction and adjustment strategy of the optimization analysis algorithm based on the routing constraints. If the current path violates the spacing constraint, the rule may be to adjust the path away from the interference source, moving 0.5mm each time. The iterative process is that the optimization analysis algorithm starts from the initial path and gradually adjusts the path according to the iterative update rule. After each iteration, the degree of achievement of the optimization goal is calculated, such as whether the interference intensity has decreased or the length has shortened, until the goal can no longer be optimized, and the optimization update goal is obtained. When the optimization update goal converges, that is, when the index reaches the optimal state, the algorithm generates a global routing optimization path based on the specific routing scheme corresponding to the final numerical index.

[0034] In this embodiment of the invention, a forced correction strategy can be configured for hard constraint targets, such as directly thickening the line or adding parallel lines when the line width is insufficient; a fine optimization strategy can be configured for soft constraint targets, such as compensating for length differences through serpentine winding or adjusting the position of components to increase the spacing.

[0035] In this embodiment of the invention, reference is made to Figure 4As shown, the step of optimizing the initial routing path corresponding to the circuit routing feature according to the optimization update target to obtain the global routing optimization path includes: S41. Convert the optimization update target into an executable path adjustment instruction; S42. Generate the trace space, trace direction and trace width of the printed circuit board according to the executable path adjustment instruction; S43. Generate a global path planning strategy for the printed circuit board based on the trace space, the trace direction, and the trace width. S44. Optimize the initial routing path corresponding to the circuit routing feature according to the global path planning strategy to obtain the global routing optimization path.

[0036] In detail, the optimization and update objectives are phased quantifiable indicators, which need to be converted into operation instructions that the algorithm can directly execute. For each optimization objective, such as achieving hard indicators or reducing deviations in soft indicators, it is broken down into specific routing operations. If the optimization and update objective is to increase the power trace width from 0.4mm to 0.5mm, a hard indicator, it is converted into the instruction: [Adjustment object: 12V power main path; Operation: Increase trace width by 0.1mm; Range: Entire path]; If the optimization and update objective is to reduce the differential pair length difference from 55mil to 50mil, a soft indicator, it is converted into the instruction: [Adjustment object: DDR differential pair; Operation: Add 5mil serpentine winding to the short side; Constraint: The winding is an arc corner, and the distance from the main line is ≥0.2mm], then the executable path adjustment instruction includes three elements: adjustment object, operation type, and constraint conditions, to ensure that the adjustment direction is clear and does not violate the routing rules.

[0037] Specifically, based on executable path adjustment instructions, the core physical parameters of the routing, such as spatial range, direction, and line width, are determined. This clarifies the range, direction, and line width used for routing, defining the usable physical area for the routing. According to constraints in the instructions, such as avoiding power supply traces and staying away from interference sources, the boundaries of permissible routing are delineated. For example, for an instruction to shift the ADC signal path 5mm to the right, the new coordinate range of the path after the shift needs to be calculated (e.g., original path x=10-30mm → new path x=15-35mm). Simultaneously, it is ensured that there are no obstacles such as component pads or mechanical vias within this area, forming a safe routing space. For instructions on high-speed differential pair routing, routing space needs to be reserved on the short side, such as a width ≥ 0.5mm. Within a rectangular area, avoid conflicts with adjacent signals; determine the routing direction, such as horizontal, vertical, or 45° angled routing, i.e., high-speed signals should be routed in straight lines, with the direction consistent with the reference plane texture, such as horizontal texture on the ground plane → horizontal routing; power signals should follow the current flow direction, from the power interface to the load, avoiding right-angle turns and reducing impedance abrupt changes; use 45° angled routing in dense areas to reduce crossings and loops, and determine the line width according to the signal type and current magnitude, which must meet requirements such as current carrying capacity and impedance matching. In this case, power signals are allocated according to power size, and high-speed signals are allocated according to impedance matching; low-speed signals only need to meet the minimum process line width. For example, according to the instruction to increase the power trace width to 0.5mm, directly adjust the line width of the 12V power main path from 0.4mm to 0.5mm, and reduce the branch paths proportionally, such as to 0.3mm.

[0038] Furthermore, parameters such as routing space, direction, and width are integrated into a unified global path planning strategy, clarifying all constraints and priorities that must be followed during routing, ensuring that all parameters work synergistically. Space constraint rules include prohibited areas and priority areas; direction constraint rules include consistency of routing direction on the same layer and corner rules; width and spacing rules include line width matching and spacing requirements; priority rules include conflict handling and resource allocation. Based on this global path planning strategy, the optimization analysis algorithm generates a final path scheme covering all signals on the board through automatic or semi-automatic routing assistance, ensuring that every trace conforms to the rules and meets the optimization objectives. The priority in the rules, such as power signals > high-speed signals > low-speed signals, is routed in that order, with high-priority signals occupying the best resources first, such as short paths and complete reference planes. For each type of signal, the path is first planned from the starting point... The main path to the destination, such as power interface → filter capacitor → load, connector → MCU → memory, ensures that the routing conforms to the direction rules and has the shortest length. For signals that need compensation, windings are added according to the rules to ensure that the length difference meets the standard. For areas with interference risks, ground isolation strips are added according to the rules. For via layout, the number and position are controlled according to the rules. If the generated path violates the rules (such as insufficient line width or too small spacing), it is automatically fine-tuned (such as locally widening the line width or slightly detouring) until all rules are satisfied. The final output is a global routing optimization path. The global routing optimization path is a complete routing scheme containing all signals, stored in the form of coordinate point sequence, line width, via position, etc. For example, the DDR signal path: (x1,y1)→(x2,y2)→…, line width 0.2mm, 2 vias, winding segment 5mil, can be directly imported into PCB design software (such as Altium, Cadence) for implementation.

[0039] For example, power signals: the line width is calculated based on the current (1A→0.5mm), the shortest path is taken to reduce voltage drop, and the number of vias is ≤2; high-speed differential signals: space is reserved for serpentine winding to meet the length difference compensation requirements, and a complete ground plane is selected as the reference layer to ensure impedance; low-speed signals: the line width is ≥0.1mm, avoiding high-priority signal paths to reduce interference.

[0040] Furthermore, while all routing optimization paths primarily focus on the overall layout rationality, they may overlook local details, such as routing defects around core components. Therefore, it is necessary to focus on a few critical areas to avoid global optimization failure due to local issues, and also to ensure the performance of key components.

[0041] S3. Extract local critical routing features from the global routing optimization path, and use the optimization analysis algorithm to perform routing analysis on the local critical routing features to obtain the local routing optimization path.

[0042] In this embodiment of the invention, the local critical routing features are local details that play a decisive role in performance in the global routing optimization path, such as differential pair routing, power via layout, and sensitive area isolation. They focus on key areas around core components and integrate signal requirements, routing design details, and manufacturing process limitations. They are key local points that need to be controlled in the global optimization path.

[0043] In this embodiment of the invention, extracting local critical routing features from the global routing optimization path includes: Identify the signal generation type in the global wiring optimization path; The global wiring optimization path is classified according to the signal generation type to obtain the signal path region corresponding to different signal generation types; Extract the core signal features in the signal path region corresponding to different signal occurrence types; Based on the core features of the signal, the core components in the global routing optimization path are determined, and the local routing features and local manufacturability features of the core components are extracted. Based on the core signal features, the local wiring features, and the local manufacturability features, the local critical wiring features in the global wiring optimization path are determined.

[0044] In detail, the global routing optimization path includes various signal generation types, such as clock signals and RF signals in high-speed signals, control signals and power signals in low-speed signals, and analog signals and differential signals in sensitive signals. The global path is then divided according to the signal generation type, grouping signal paths with similar functions and characteristics into the same region, i.e., signal path regions. For example, all paths of high-speed clock signals will be divided into a high-speed clock signal path region, and all paths of power signals will be divided into a power signal path region, avoiding mutual interference between the characteristics of different signal types. The core characteristics of a signal refer to the key parameters that reflect the essential characteristics of that type of signal. Different signal types have different core characteristics. For example, the core characteristics of high-speed signals may include signal transmission rate, rise time, fall time, impedance matching requirements, crosstalk tolerance, etc.; the core characteristics of power signals may include current capacity, voltage ripple allowable value, and grounding method, such as single-point grounding, multi-point grounding, etc.; and the core characteristics of analog signals may include signal-to-noise ratio, bandwidth, linearity requirements, etc.

[0045] Specifically, core components refer to devices that decisively influence the core characteristics of a signal, such as clock generators and impedance matching resistors in high-speed signal paths, voltage regulators and filter capacitors in power signal paths, and operational amplifiers and sensors in analog signal paths. The performance of these components directly determines whether the signal can meet the core characteristic requirements. Routing details based on core components include the connection length between core components and surrounding components, routing angles (e.g., right-angle turns), trace spacing, number and type of vias (e.g., blind vias, buried vias), grounding / shielding design (e.g., whether to wrap with grounding copper), etc. Furthermore, from a manufacturing perspective, the manufacturability parameters of the wiring surrounding core components, such as the minimum... Whether the small line width meets the factory's processing capabilities, whether the via diameter is within the process allowable range, whether the spacing between component pads and wiring meets the soldering requirements, and whether there are heat dissipation hazards caused by dense wiring, etc., then the signal core characteristics reflecting the essential needs of the signal, the local wiring characteristics reflecting the wiring details around the core components, and the local manufacturability characteristics reflecting production feasibility are combined to finally determine the local critical wiring characteristics. For example, in the local critical wiring characteristics of a high-speed clock signal, the signal core characteristic is that the connection length between the clock generator and the load chip is ≤5cm, the local wiring characteristic is that the trace has a 45° bend and the line width is 0.2mm, and the local manufacturability characteristic is that the via diameter is ≥0.3m.

[0046] In this embodiment of the invention, the step of using the optimization analysis algorithm to perform routing analysis on the local critical routing features to obtain the local routing optimization path is the same as the step in S2 of using a predetermined optimization analysis algorithm to perform routing analysis on the global routing features of the circuit to obtain the global routing optimization path, and will not be repeated here. The local routing optimization path refers to a refined and targeted routing optimization path for a specific area, key component, or specific signal path (such as high-frequency signal, high-speed signal, sensitive signal, etc.) within the global routing framework of the printed circuit board (PCB). It focuses on the local details that need to be handled in the global routing and is a supplement and refinement to the global routing optimization path.

[0047] Furthermore, the global path ensures a reasonable overall layout, such as avoiding long-distance detours and clear functional zoning, but may overlook the detailed needs of local core areas; the local path focuses on the fine design around key components, and the combination of the two can form a solution that is reasonable at the macro level and precise at the micro level.

[0048] S4. Generate a routing optimization scheme for the printed circuit board based on the global routing optimization path and the local routing optimization path. In this embodiment of the invention, the routing optimization scheme includes the path direction and routing parameters of all signals. Its core objective is to clarify the specific implementation method of PCB routing while satisfying circuit performance, such as signal integrity, power stability, production feasibility, such as process compatibility and design efficiency, such as the shortest path.

[0049] In this embodiment of the invention, generating a routing optimization scheme for the printed circuit board based on the global routing optimization path and the local routing optimization path includes: Identify the global routing path and global routing parameters corresponding to the global routing optimization path; Identify the local routing path and local routing parameters corresponding to the local routing optimization path; The local wiring routing is integrated into the global wiring routing to obtain an optimized wiring routing scheme for the printed circuit board. The local routing parameters are integrated into the global routing parameters to obtain an optimized routing parameter scheme for the printed circuit board. The routing optimization scheme and the routing parameter optimization scheme are combined to form a routing optimization scheme for printed circuit boards.

[0050] In detail, global routing refers to the macroscopic layout direction and trend of each signal path in a printed circuit board (PCB) from an overall perspective. Examples include whether high-speed signals are laid out in straight lines to reduce delay, whether power networks use a tree-like distribution to cover all components, and whether signals from different functional modules, such as analog and digital areas, are routed in isolated zones. Global routing parameters are macroscopic parameters that affect overall routing performance, including resource allocation for routing at each layer, the baseline range of global trace widths, the upper limit of global via density, and global spacing rules for different signal types. Local routing is based on the microscopic layout of core components, such as clock chips and operational amplifiers. Path direction, such as whether the traces from the core component pins to adjacent components avoid right-angle turns, whether high-speed differential pairs maintain parallel routing, whether sensitive signals use serpentine lines, compensation length, etc.; Local routing parameters are refined parameters for the area around the core component, including local trace width, such as the trace width at the core chip pins needs to match the chip package requirements, possibly 0.15mm; local trace spacing, such as the spacing of high-speed differential pairs needs to be strictly controlled at 0.3mm to ensure impedance matching; local via type, such as using blind vias under the core component to reduce signal loss; local shielding design parameters, such as the width of the grounding copper around sensitive signals ≥1mm, etc.

[0051] Specifically, global routing is the macro framework, while local routing is the micro supplement. The integration process must ensure that local routing does not violate the global layout logic. If the global requirement is for high-speed signals to be laid out in a straight line along the PCB edge, but the pin routing of a certain core chip needs slight direction adjustments, then the adjusted local routing must ultimately revert to the global straight-line trend to avoid excessively long global signal paths due to local offsets. If the global requirement is for signal isolation between analog and digital areas, the routing of local analog chips must be strictly limited to the analog area and must not cross into the digital area. Global routing parameters are general standards, while local routing parameters are specially adjusted. During integration, the principle of prioritizing local over global routing must be followed, such as the global line width baseline. The standard trace width is 0.2mm, but a certain high-speed differential pair requires 0.18mm to match impedance. Therefore, after merging, the trace width of this differential pair is set at 0.18mm, while other ordinary signal lines remain at 0.2mm. The global via density limit is 5 per square centimeter, but due to dense pins under a certain core chip, additional vias are needed in that area. In this case, the limit needs to be relaxed, such as allowing 8 per square centimeter, while ensuring that other areas do not exceed the limit. This integrates the routing optimization scheme with the routing parameter optimization scheme to form a complete scheme that can directly guide PCB design. For example, the high-speed clock signal runs in a straight line along the right edge globally, while the local routing from core chip U1 to U2 is a 45° turn. The global trace width is 0.2mm, the local trace width at the U1 pin is 0.18mm, and the trace spacing is 0.3mm. The routing optimization scheme clarifies the path direction and trend of all signals, while the routing parameter optimization scheme clarifies the specific values ​​of trace width, spacing, and vias.

[0052] As can be seen, in the above scheme, by first identifying the number of printed circuit board layers and then performing multi-dimensional feature analysis on each layer, the extraction of global routing features can better fit the constraints of the actual physical layers. By using a pre-determined optimization analysis algorithm to analyze global and local features separately, the subjective bias of human experience can be reduced, and a better solution can be found through a data-driven approach. Local paths ensure the rationality of the overall layout, while local paths supplement detailed optimization. The combined routing scheme can meet electrical performance requirements. Optimized paths based on global features provide a stable foundation for framework adjustment, while locally optimized paths can quickly respond to changes in local areas, giving the routing scheme a stronger ability to adjust flexibly and adapt to iterative upgrades in different scenarios, thereby solving the technical problem of low accuracy in printed circuit board routing.

[0053] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0054] In one embodiment, a wiring optimization device for a printed circuit board is provided, which corresponds one-to-one with the wiring optimization method for the printed circuit board in the above embodiments. For example... Figure 5 As shown, the printed circuit board routing optimization device includes a circuit routing multi-dimensional feature analysis module 101, a global routing optimization path generation module 102, a local routing optimization path generation module 103, and a routing optimization scheme generation module 104. Detailed descriptions of each functional module are as follows: The circuit routing multi-dimensional feature analysis module 101 is used to identify the number of layers of a pre-acquired printed circuit board, and to perform multi-dimensional feature analysis on the circuit routing of each layer according to the number of layers to obtain the global circuit routing features. The global routing optimization path generation module 102 is used to perform routing analysis on the global routing characteristics of the circuit using a predetermined optimization analysis algorithm to obtain a global routing optimization path. The local routing optimization path generation module 103 is used to extract local critical routing features from the global routing optimization path, and use the optimization analysis algorithm to perform routing analysis on the local critical routing features to obtain the local routing optimization path. The routing optimization scheme generation module 104 is used to generate a routing optimization scheme for the printed circuit board based on the global routing optimization path and the local routing optimization path. In one embodiment, the circuit routing multi-dimensional feature analysis module 101, when performing the identification of the number of layers of a pre-acquired printed circuit board, is used to: Key constraint parameters of the printed circuit board are extracted based on the pre-acquired circuit design data; Identify the circuit signals of the printed circuit board and determine the initial layer range of the printed circuit board based on the circuit signals; The initial layer range is corrected based on the key constraint parameters to obtain the stack-up structure of the printed circuit board, and the number of layers in the stack-up structure is determined as the number of layers of the printed circuit board.

[0055] In one embodiment, the circuit routing multi-dimensional feature analysis module 101, when performing multi-dimensional feature analysis on the circuit routing of each layer according to the number of layers to obtain the global circuit routing features, is used to: Based on the number of layers, the function of each layer circuit is determined to obtain the corresponding function type of each layer circuit. Based on the functional type, the signal type of each layer of the circuit is counted, the location of key components is marked in the circuit wiring of each layer according to the signal type, and the component location is associated with the signal type; Based on the associated component locations and signal types, determine the signal interference characteristics and wiring rule characteristics between components in the circuit routing of each layer; Based on the wiring rule features, the routing path features of the circuit wiring in each layer are identified, and the signal interference features, wiring rule features, and routing path features corresponding to the circuit wiring in each layer are determined as the global circuit wiring features.

[0056] In one embodiment, the global routing optimization path generation module 102, when performing routing analysis on the global routing features of the circuit using a predetermined optimization analysis algorithm to obtain a global routing optimization path, is used to: The global routing characteristics of the circuit are converted into numerical indicators; The wiring constraints of the printed circuit board are determined based on the wiring rule features in the global wiring features of the circuit. The optimization objectives corresponding to the numerical indicators are analyzed using a predetermined optimization analysis algorithm; An iterative update rule for the optimization objective is generated based on the wiring constraints, and the optimization objective is iteratively updated according to the iterative update rule to obtain the updated optimization objective. The initial routing path corresponding to the circuit routing feature is optimized according to the optimization update target to obtain the global routing optimization path.

[0057] In one embodiment, the global routing optimization path generation module 102, when performing the optimization analysis using a pre-determined optimization analysis algorithm to analyze the optimization objective corresponding to the numerical index, is used to: Identify the wiring attribute mapping relationship between the numerical indicators and the wiring rule features; The numerical indicators are divided into hard indicators and soft indicators; Based on the wiring attribute mapping relationship, a first optimization objective for the hard indicators and a second optimization objective for the soft indicators are determined. The first optimization objective deviation index of the first optimization objective is calculated using the multi-objective optimization function in the predetermined optimization analysis algorithm, and the second optimization objective deviation index of the second optimization objective is calculated. The optimization index of the numerical index is determined based on the first optimization target deviation index and the second optimization target deviation index.

[0058] In one embodiment, the global routing optimization path generation module 102, when performing optimization of the initial routing path corresponding to the circuit routing feature according to the optimization update target to obtain the global routing optimization path, is used to: The optimization update target is converted into executable path adjustment instructions; The trace space, trace direction, and trace width of the printed circuit board are generated according to the executable path adjustment instructions. A global path planning strategy for the printed circuit board is generated based on the trace space, the trace direction, and the trace width. The initial routing path corresponding to the circuit routing feature is optimized according to the global path planning strategy to obtain the global routing optimization path.

[0059] In one embodiment, the local routing optimization path generation module 103, when extracting local key routing features from the global routing optimization path, is used to: Identify the signal generation type in the global wiring optimization path; The global wiring optimization path is classified according to the signal generation type to obtain the signal path region corresponding to different signal generation types; Extract the core signal features in the signal path region corresponding to different signal occurrence types; Based on the core features of the signal, the core components in the global routing optimization path are determined, and the local routing features and local manufacturability features of the core components are extracted. Based on the core signal features, the local wiring features, and the local manufacturability features, the local critical wiring features in the global wiring optimization path are determined.

[0060] This invention provides a routing optimization device for printed circuit boards (PCBs). By first identifying the number of PCB layers and then performing multi-dimensional feature analysis on each layer, the extraction of global routing features can better align with the limitations of the actual physical layers. Utilizing a pre-determined optimization analysis algorithm to analyze global and local features separately reduces subjective bias from human experience, finding a better solution through data-driven approaches. Local paths ensure the rationality of the overall layout, while local paths supplement detailed optimization; the combined routing scheme meets electrical performance requirements. Optimized paths based on global features provide a stable foundation for framework adjustments, while locally optimized paths can quickly respond to changes in local areas, giving the routing scheme greater flexibility and adaptability to iterative upgrades in different scenarios, thereby solving the technical problem of low accuracy in PCB routing.

[0061] Specific limitations regarding the routing optimization device for printed circuit boards can be found in the limitations of the routing optimization method for printed circuit boards mentioned above, and will not be repeated here. Each module in the aforementioned routing optimization device for printed circuit boards can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in or independent of the processor in a computer device in hardware form, or stored in the memory of a computer device in software form, so that the processor can call and execute the operations corresponding to each module.

[0062] In one embodiment, a computer device is provided, which may be a server, and its internal structure diagram may be as follows: Figure 6 As shown, the computer device includes a processor, memory, network interface, and database connected via a system bus. The processor provides computing and control capabilities. The memory includes non-volatile and / or volatile storage media and internal memory. The non-volatile storage media stores the operating system, computer programs, and database. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The network interface is used to communicate with external clients via a network connection. When the computer program is executed by the processor, it implements the functions or steps of a printed circuit board routing optimization method on the server side.

[0063] In one embodiment, a computer device is provided, which may be a client, and its internal structure diagram may be as follows: Figure 7 As shown, the computer device includes a processor, memory, network interface, display screen, and input devices connected via a system bus. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The network interface is used to communicate with an external server via a network connection. When the computer program is executed by the processor, it implements client-side functions or steps of a printed circuit board routing optimization method.

[0064] In one embodiment, a computer device is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to perform the following steps: Identify the number of layers of the pre-acquired printed circuit board, and perform multi-dimensional feature analysis on the circuit wiring of each layer based on the number of layers to obtain the global circuit wiring features; The global routing characteristics of the circuit are analyzed using a predetermined optimization analysis algorithm to obtain the global routing optimization path; Extract local critical routing features from the global routing optimization path, and use the optimization analysis algorithm to perform routing analysis on the local critical routing features to obtain the local routing optimization path; A routing optimization scheme for the printed circuit board is generated based on the global routing optimization path and the local routing optimization path.

[0065] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon, the computer program performing the following steps when executed by a processor: Identify the number of layers of the pre-acquired printed circuit board, and perform multi-dimensional feature analysis on the circuit wiring of each layer based on the number of layers to obtain the global circuit wiring features; The global routing characteristics of the circuit are analyzed using a predetermined optimization analysis algorithm to obtain the global routing optimization path; Extract local critical routing features from the global routing optimization path, and use the optimization analysis algorithm to perform routing analysis on the local critical routing features to obtain the local routing optimization path; A routing optimization scheme for the printed circuit board is generated based on the global routing optimization path and the local routing optimization path.

[0066] It should be noted that the functions or steps that can be implemented by the computer-readable storage medium or computer device described above can be referred to the relevant descriptions on the server side and client side in the foregoing method embodiments. To avoid repetition, they will not be described one by one here.

[0067] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments of the above methods. Any references to memory, storage, databases, or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), RAMbus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0068] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is used as an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above.

[0069] It should be noted that if any software tools or components not belonging to our company appear in the embodiments of this application, they are merely for illustrative purposes and do not represent actual use.

[0070] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention.

Claims

1. A method of routing optimization of a printed circuit board, characterized by, The method comprises the following steps: identifying the number of layers of a pre-acquired printed circuit board, performing multi-dimensional feature analysis on the circuit layout of each layer according to the number of layers to obtain circuit global layout features; performing layout analysis on the circuit global layout features by using a pre-determined optimization analysis algorithm to obtain a global layout optimization path; extracting local key layout features in the global layout optimization path, performing layout analysis on the local key layout features by using the optimization analysis algorithm to obtain a local layout optimization path; generating a layout optimization scheme for the printed circuit board according to the global layout optimization path and the local layout optimization path.

2. The printed circuit board wiring optimization method of claim 1, wherein, The step of identifying the number of layers of a pre-acquired printed circuit board comprises: extracting key constraint parameters of the printed circuit board based on pre-acquired circuit design data; identifying circuit signals of the printed circuit board, and determining an initial layer number range of the printed circuit board according to the circuit signals; correcting the initial layer number range according to the key constraint parameters to obtain a layer stacking structure of the printed circuit board, and determining the number of layers in the layer stacking structure as the number of layers of the printed circuit board.

3. The printed circuit board wiring optimization method of claim 1, wherein, The step of performing multi-dimensional feature analysis on the circuit layout of each layer according to the number of layers to obtain circuit global layout features comprises: functionally positioning each layer of circuit according to the number of layers to obtain a function type corresponding to each layer of circuit; statistically analyzing signal types of each layer of circuit according to the function type, marking key component positions in the circuit layout of each layer according to the signal types, and associating the component positions with the signal types; determining signal interference features and layout rule features between components in the circuit layout of each layer according to the associated component positions and signal types; identifying a routing path feature of the circuit layout of each layer according to the layout rule feature, and determining the signal interference features, the layout rule features and the routing path feature of the circuit layout of each layer as the circuit global layout features.

4. The printed circuit board wiring optimization method of claim 1, wherein, The step of performing layout analysis on the circuit global layout features by using a pre-determined optimization analysis algorithm to obtain a global layout optimization path comprises: converting the circuit global layout features into numerical indicators; determining layout constraint conditions of the printed circuit board based on the layout rule features in the circuit global layout features; analyzing an optimization target corresponding to the numerical indicators by using a pre-determined optimization analysis algorithm; generating an iteration update rule of the optimization target according to the layout constraint conditions, and iteratively updating the optimization target according to the iteration update rule to obtain an optimization update target; optimizing an initial layout path corresponding to the circuit layout features according to the optimization update target to obtain a global layout optimization path.

5. The printed circuit board wiring optimization method of claim 4, wherein, The step of analyzing an optimization target corresponding to the numerical indicators by using a pre-determined optimization analysis algorithm comprises: identifying a layout attribute mapping relationship between the numerical indicators and the layout rule features; dividing the numerical indicators into hard indicators and soft indicators; determining a first optimization target of the hard indicators and a second optimization target of the soft indicators according to the layout attribute mapping relationship; calculating a first optimization target deviation index of the first optimization target by using a multi-objective optimization function in a predetermined optimization analysis algorithm, and calculating a second optimization target deviation index of the second optimization target; determining an optimization index of the numerical index according to the first optimization target deviation index and the second optimization target deviation index.

6. The printed circuit board wiring optimization method of claim 4, wherein, The optimization of the initial routing path corresponding to the circuit routing feature according to the optimization update target includes: transforming the optimization update target into executable path adjustment instructions; generating a routing space, a routing direction, and a routing width of the printed circuit board according to the executable path adjustment instructions; generating a global path planning strategy of the printed circuit board according to the routing space, the routing direction, and the routing width; optimizing the initial routing path corresponding to the circuit routing feature according to the global path planning strategy to obtain a global routing optimization path.

7. The printed circuit board wiring optimization method of claim 1, wherein, The extraction of the local key routing feature in the global routing optimization path includes: identifying a signal generation type in the global routing optimization path; classifying the global routing optimization path according to the signal generation type to obtain a signal path area corresponding to different signal generation types; extracting a signal core feature in the signal path area corresponding to different signal generation types; determining a core element in the global routing optimization path according to the signal core feature, and extracting a local routing feature and a local manufacturability feature of the core element; determining a local key routing feature in the global routing optimization path according to the signal core feature, the local routing feature, and the local manufacturability feature.

8. An apparatus for optimizing wiring of a printed circuit board, characterized by comprising: It includes: a circuit routing multi-dimensional feature analysis module, configured to identify a number of layers of a printed circuit board obtained in advance, and perform multi-dimensional feature analysis on circuit routing of each layer according to the number of layers to obtain circuit global routing features; a global routing optimization path generation module, configured to perform routing analysis on the circuit global routing features by using a predetermined optimization analysis algorithm to obtain a global routing optimization path; a local routing optimization path generation module, configured to extract a local key routing feature in the global routing optimization path, and perform routing analysis on the local key routing feature by using the optimization analysis algorithm to obtain a local routing optimization path; a routing optimization scheme generation module, configured to generate a routing optimization scheme of the printed circuit board according to the global routing optimization path and the local routing optimization path.

9. A computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, The processor executes the computer program to implement the printed circuit board routing optimization method in any one of claims 1 to 7.

10. A computer-readable storage medium storing a computer program, the computer program comprising instructions that, when executed by a computer, cause the computer to perform the method of any one of claims 1 to 9. The computer program is executed by the processor to implement the printed circuit board routing optimization method in any one of claims 1 to 7.

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