Method for generating mask pattern, mask, semiconductor structure and method for manufacturing thereof

Abstract

The application provides a mask pattern generation method, a mask, a semiconductor structure and a manufacturing method thereof. The mask pattern generation method comprises: obtaining a mask pattern template comprising a scribe lane region and a reference mark pattern comprising a pattern; the reference mark pattern is divided into a plurality of reference mark regions; an outline of a part of the pattern in each reference mark region is extracted by using an auxiliary pattern to obtain a plurality of auxiliary mark patterns which are arranged in the scribe lane region; a part of the pattern in each reference mark region is cut respectively to obtain a plurality of local mark patterns which are arranged at positions of the corresponding auxiliary mark patterns in the scribe lane region to obtain a target mask pattern, so that the plurality of local mark patterns transferred to the semiconductor structure are combined into an alignment mark pattern matching the pattern in the scribe lane of the semiconductor structure. Through the embodiments of the application, the alignment accuracy in the packaging process is improved.

Description

Technical Field

[0001] The embodiments in this application relate to the field of semiconductor manufacturing technology, specifically to a method for generating a mask pattern, a mask, a semiconductor structure, and a method for manufacturing the same. Background Technology

[0002] In semiconductor manufacturing, after the chip is fabricated on the wafer surface, the wafer needs to undergo packaging processes. Specifically, packaging processes can include multiple steps such as coating, dicing, encapsulation, and testing. Coating refers to depositing a protective or functional thin film on the wafer surface to provide physical protection for the chip. Encapsulation involves dicing the semiconductor structure into multiple chips, connecting each chip with leads, mounting it to a packaging substrate, and encapsulating it with a protective shell to achieve electrical interconnection between the chips and optimize chip performance.

[0003] To improve the process quality of each step in the packaging process, alignment marks need to be set on the wafer to improve alignment accuracy. Chip target marks (CTMs) are widely used in the packaging process due to their advantages in size and symmetry.

[0004] However, researchers found in the actual packaging process that the alignment accuracy was low when using the chip target mark provided by the existing technology as the alignment reference. Summary of the Invention

[0005] In view of this, several embodiments of this application provide a method for generating a mask pattern, a mask, a semiconductor structure, and a method for manufacturing the same, to improve alignment accuracy when using chip target marks as alignment references for alignment.

[0006] In one aspect, an embodiment of this application provides a method for generating a mask pattern, applied to a mask pattern design system; the method includes: obtaining a mask pattern template and a reference mark pattern; wherein the mask pattern template includes a chip region and a dicing region surrounding the chip region; the reference mark pattern includes a graphic pattern and a background pattern; the reference mark pattern is divided into multiple non-overlapping reference mark regions; each reference mark region includes a portion of the graphic pattern and a portion of the background pattern; using auxiliary graphics to extract the outline of a portion of the graphic pattern located within each reference mark region to obtain multiple auxiliary mark patterns, and placing the multiple auxiliary mark patterns within the dicing region; wherein the number of auxiliary mark patterns is the same as the number of reference mark regions; respectively cutting out a portion of the graphic pattern located within each reference mark region to obtain multiple local mark patterns, and placing each local mark pattern at the position of the corresponding auxiliary mark pattern within the dicing region to obtain a target mask pattern, such that during the manufacturing of a semiconductor structure according to the target mask pattern, the multiple local mark patterns transferred to the semiconductor structure are combined within the dicing of the semiconductor structure to form an alignment mark pattern matching the graphic pattern.

[0007] Optionally, the auxiliary marking patterns are arranged in the dicing area, including: arranging the auxiliary marking patterns in the dicing area at the corner of the mask pattern template; wherein each auxiliary marking pattern is disposed on the side of the center line of the dicing area close to the chip area, and at least part of its boundary is attached to the center line of the dicing area.

[0008] Optionally, after laying out multiple auxiliary marker patterns within the dicing area, the method for generating the mask pattern further includes: corresponding to the multiple auxiliary marker patterns, laying out multiple protective marker patterns within the dicing area at the corner of the mask pattern template to obtain a target mask pattern; wherein each protective marker pattern is disposed on the side of the centerline of the dicing area away from the chip area, and at least covers the area defined by the following boundaries: the corner vertex of the mask pattern template, the first boundary of the auxiliary marker pattern, and the extension line formed by extending the second boundary of the auxiliary marker pattern in the opposite direction to the normal of the centerline of the dicing area; the first boundary of the auxiliary marker pattern is a portion of the auxiliary marker pattern that fits the centerline of the dicing area; the second boundary of the auxiliary marker pattern is a portion of the auxiliary marker pattern that extends along the normal of the centerline of the dicing area.

[0009] Optionally, in the target mask pattern, the transmittance of the protective marking pattern and the local marking pattern are different; wherein, the transmittance of the protective marking pattern is 0.

[0010] Optionally, the graphic pattern includes a first sub-graphic pattern and a second sub-graphic pattern with the same outline shape; the first sub-graphic pattern and the second sub-graphic pattern both extend along a first direction and a second direction that are perpendicular to each other; wherein, the length of the first sub-graphic pattern extending along the first direction is less than the length of the second sub-graphic pattern extending along the first direction, and the length of the first sub-graphic pattern extending along the second direction is less than the length of the second sub-graphic pattern extending along the second direction.

[0011] Optionally, the outline of a portion of the graphic pattern located within each of the reference mark regions is extracted using auxiliary graphics to obtain multiple auxiliary mark patterns, including: extracting the outline of a portion of the second sub-graphic pattern located within each of the reference mark regions using at least two mutually adjacent auxiliary graphics to obtain multiple auxiliary mark patterns; wherein, the auxiliary graphics are rectangles.

[0012] Optionally, a portion of the graphic pattern located within each of the reference mark regions is cropped to obtain multiple local mark patterns, and each local mark pattern is positioned at the location of a corresponding auxiliary mark pattern within the dicing area to obtain a target mask pattern. This includes: cropping a portion of the first sub-graphic pattern located within each of the reference mark regions to obtain multiple first sub-graphic local mark patterns, and positioning each first sub-graphic local mark pattern at the location of a corresponding auxiliary mark pattern within the dicing area to obtain a first target mask pattern; cropping a portion of the second sub-graphic pattern located within each of the reference mark regions to obtain multiple second sub-graphic local mark patterns, and positioning each second sub-graphic local mark pattern at the location of a corresponding auxiliary mark pattern within the dicing area to obtain a second target mask pattern; during the manufacturing of a semiconductor structure based on the target mask pattern, the first target mask pattern and the second target mask pattern are respectively transferred to different material layers of the semiconductor structure.

[0013] In another aspect, one embodiment of this application provides a mask manufactured based on a target mask pattern generated by the mask pattern generation method described in the above embodiments; during the manufacturing of a semiconductor structure according to the mask, a plurality of the local marking patterns transferred to the semiconductor structure are combined in the dicing channels of the semiconductor structure to form an alignment marking pattern that matches the graphic pattern.

[0014] In another aspect, one embodiment of this application provides a semiconductor structure manufactured according to a target mask pattern generated by the mask pattern generation method described in the above embodiments, or manufactured according to the mask manufacturing method described in the above embodiments; a plurality of the local marking patterns transferred to the semiconductor structure are combined in the dicing channels of the semiconductor structure to form an alignment marking pattern that matches the graphic pattern.

[0015] In another aspect, one embodiment of this application provides a method for manufacturing a semiconductor structure, wherein the semiconductor structure is manufactured according to a target mask pattern generated by the mask pattern generation method described in the above embodiments, or, the semiconductor structure is manufactured according to a mask as described in the above embodiments; the method for manufacturing a semiconductor structure includes: using a multiple exposure process to transfer a plurality of the local marking patterns to the dicing channels of the semiconductor structure, such that the plurality of the local marking patterns are combined in the dicing channels of the semiconductor structure to form an alignment marking pattern that matches the graphic pattern.

[0016] In several embodiments of this application, a mask pattern template including a chip region and a dicing region is obtained, along with a reference mark pattern divided into multiple reference mark regions, each of which contains a partial graphic pattern and a partial background pattern. Then, an auxiliary graphic pattern is used to extract the outline of the partial graphic pattern within each reference mark region, resulting in multiple auxiliary mark patterns. These auxiliary mark patterns are then placed within the dicing region. Next, a partial graphic pattern within each reference mark region is cropped to obtain multiple local mark patterns. Each local mark pattern is placed at the corresponding position of the auxiliary mark pattern within the dicing region to obtain the target mask pattern. This allows the multiple local mark patterns transferred to the semiconductor structure to combine within the dicing region of the semiconductor structure to form an alignment mark pattern that matches the graphic pattern during the semiconductor structure fabrication process based on the target mask pattern. Unexpected effects include: since the auxiliary mark patterns are obtained by extracting the outline of the graphic pattern, and the local mark patterns are obtained by cropping the graphic pattern, the partial transfer and recombination of the graphic pattern can be achieved without splitting the complete graphic data of the reference mark pattern. This results in the combined alignment mark pattern possessing the complete graphic features of the reference mark pattern, thereby improving the alignment accuracy during the packaging process. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in describing the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 A schematic diagram of a first chip target marking pattern provided for related technologies.

[0019] Figure 2 A schematic diagram of a second chip target marking pattern provided for related technologies.

[0020] Figure 3 A schematic diagram showing that the size of the chip target marking pattern is larger than the size of the segmentation channel region, which is provided for related technologies.

[0021] Figure 4 A schematic diagram illustrating the splitting of a chip target marking pattern for related technologies.

[0022] Figure 5 This is a schematic diagram illustrating the setting of a split chip target marking pattern in the segmentation channel area, provided for related technologies.

[0023] Figure 6 This is a schematic flowchart illustrating a method for generating a mask pattern according to an embodiment of this application.

[0024] Figure 7 A schematic diagram of a reference mark pattern provided for one embodiment of this application.

[0025] Figure 8 This is a schematic diagram illustrating the extraction of partial graphic pattern outlines using auxiliary graphics, as provided in one embodiment of this application.

[0026] Figure 9 This is a schematic diagram showing the arrangement of multiple auxiliary marking patterns in a cutting area, as provided in one embodiment of this application.

[0027] Figure 10 This is a schematic diagram showing the arrangement of multiple protective marking patterns in a cutting area, as provided in one embodiment of this application.

[0028] Figure 11 This is a schematic diagram showing the partial cutout of the first sub-graphic pattern provided in one embodiment of this application.

[0029] Figure 12 A schematic diagram of a first sub-graphic partial marker pattern provided for an embodiment of this application.

[0030] Figure 13 This is a schematic diagram showing the partial cutout of the second sub-graphic pattern provided in one embodiment of this application.

[0031] Figure 14 A schematic diagram of a second sub-graphic partial marker pattern provided for one embodiment of this application.

[0032] Figure 15This is a schematic diagram showing how multiple protective marking patterns are arranged in the cutting area at the corner of a mask pattern template, corresponding to multiple first sub-graphic local marking patterns, as provided in one embodiment of this application.

[0033] Figure 16 This is a schematic diagram showing the position of each first local marker pattern within the cutting channel area, corresponding to multiple second sub-graphic local marker patterns provided in one embodiment of this application.

[0034] Figure 17 This is a schematic diagram showing how multiple local marking patterns are combined into an alignment marking pattern within a dicing channel of a semiconductor structure, according to one embodiment of this application.

[0035] Structural designation explanation

[0036] 100. First chip target marking pattern; 100a. Second chip target marking pattern; 101. First top metal layer marking pattern; 102. First passivation protection layer marking pattern; 101a. Second top metal layer marking pattern; 102a. Second passivation protection layer marking pattern; 110. First splitting marking pattern; 120. Second splitting marking pattern; 130. Third splitting marking pattern; 200. Mask pattern template; 210. Chip area; 211. Chip pattern; 212. Dividing channel area; 220. Cutting channel area; 221. Centerline of cutting channel area; 300. Reference marking pattern; 301. First sub-pattern pattern; 302. Two sub-patterns; 310, First reference mark area; 320, Second reference mark area; 330, Third reference mark area; 340, Fourth reference mark area; 400, Auxiliary mark pattern; 410, First auxiliary pattern; 420, Second auxiliary pattern; 500, Protective mark pattern; 600, Partial mark pattern of the first sub-pattern; 610, First extension; 620, Second extension; 700, Partial mark pattern of the second sub-pattern; 710, Third extension; 720, Fourth extension; 800, Alignment mark pattern; 801, First sub-alignment mark pattern; 802, Second sub-alignment mark pattern; 900, Cutting channel of semiconductor structure. Detailed Implementation

[0037] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0038] The accompanying drawings provided in this application are only schematic illustrations of the basic concept of this application. The drawings only show the components related to this application and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the shape, quantity and proportion of each component may be changed, and the layout of the components may also be more complex.

[0039] In the description of the embodiments of this application, it should be understood that the terms "upper," "lower," "left," "right," "vertical," "horizontal," "inner," "outer," "center," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application, and do not indicate or imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined with "first" and "second" may explicitly or implicitly include one or more of the stated features.

[0040] To achieve high-density integration of semiconductor devices, the requirements for alignment accuracy in each stage of semiconductor device production are constantly increasing. Chip target marks, due to their large size and symmetrical arrangement in all directions, are widely used in packaging processes to improve the speed and accuracy of mark recognition systems in identifying alignment marks. To determine the alignment reference during processes such as coating and packaging in the packaging process, related technologies require, for each single exposure coverage area (Shot) on the semiconductor structure surface, to create a chip target mark on the exposed top metal (TM) layer before performing the coating process, and then to create a chip target mark on the passivation (PV) protective layer formed based on the coating process after the coating process is completed.

[0041] Chip target marks can be fabricated based on chip target mark patterns in a mask pattern. To improve alignment accuracy between different material layers, the chip target marks formed on the top metal layer differ in size and / or shape from those formed on the passivation protection layer. Accordingly, in the chip target mark patterns provided by related technologies, the mark patterns corresponding to the chip target marks of different material layers are different.

[0042] Please see Figure 1 and Figure 2Taking the first chip target marking pattern 100 and the second chip target marking pattern 100a provided by related technologies as examples. In the first chip target marking pattern 100, the first top metal layer marking pattern 101 and the first passivation protection layer marking pattern 102 have the same shape but different sizes; that is, the size of the first top metal layer marking pattern 101 is smaller than the size of the first passivation protection layer marking pattern 102. In the second chip target marking pattern 100a, the second top metal layer marking pattern 101a and the second passivation protection layer marking pattern 102a have different sizes and shapes; that is, the size of the second top metal layer marking pattern 101a is smaller than the size of the second passivation protection layer marking pattern 102a, and compared to the second passivation protection layer marking pattern 102a, the second top metal layer marking pattern 101a has multiple triangles added to improve alignment accuracy.

[0043] Please refer to the following: Figures 1 to 3 A mask pattern containing chip target marking patterns can be fabricated based on a mask pattern template 200. Specifically, the mask pattern template 200 may include a chip region 210 and a dicing channel region 220 surrounding the chip region 210. Within the chip region 210, a dicing channel region 212 is formed between adjacent chip patterns 211. To reduce the reduction in alignment accuracy caused by damage to the chip target markings during chip dicing, in related technologies, when designing the mask pattern template 200 based on the chip target marking patterns, researchers typically place the entire chip target marking pattern within the dicing channel region 212 to maintain the integrity of the chip target marking pattern structure. However, in the actual design process of the mask pattern template 200, researchers have found that the chip target marking patterns cannot be placed within the dicing channel region 212. The specific reasons are analyzed below.

[0044] The chip target marking pattern has mutually perpendicular length and width directions. Since the overall size of the chip target marking pattern is calculated based on its maximum length X along the length direction and its maximum width Y along the width direction, taking the first chip target marking pattern 100 and the second chip target marking pattern 100a as examples, the size of both chip target marking patterns is X. Y. However, in the mask pattern template 200, the size of the segmentation area 212 is X1 along the length direction, and X1 < X; the size of the segmentation area 212 is Y1 along the width direction, and Y1 < Y.

[0045] At this point, if the entire chip target mark pattern is directly set on the partition channel region 212, the chip target mark pattern will overlap with the chip pattern 211. If chip manufacturing is performed based on the mask pattern template 200 where the chip target mark pattern and chip pattern 211 partially overlap, it may cause damage to the chip region 210, affecting chip function and production yield. Alternatively, it may result in incomplete chip target mark morphology and reduced alignment accuracy. If the layout of the original chip pattern 211 on the mask pattern template 200 is modified to maintain the integrity of the chip target mark pattern, it may increase the area occupied by the partition channel region 212, thereby reducing the number of chips that can be accommodated on the semiconductor structure and reducing production efficiency.

[0046] To address the overlap between the chip target marking pattern and the chip pattern, researchers attempted to split the design file of the chip target marking pattern, specifically the GDS (Geometric Design System) format file. The specific splitting process is as follows.

[0047] Please refer to the following: Figure 1 , Figure 4 and Figure 5 Taking the first chip target marking pattern 100 as an example, in the first chip target marking pattern 100, the first top metal layer marking pattern 101 and the first passivation protection layer marking pattern 102 are both formed by the overlapping intersection of two rectangles extending along the length direction and the width direction, respectively. Based on the shape characteristics of the first chip target marking pattern 100, researchers divided the corresponding GDS file of the first chip target marking pattern 100 into three parts, forming a first split marking pattern 110, a second split marking pattern 120, and a third split marking pattern 130. Specifically, along the length direction, the dimensions of the first split marking pattern 110 and the third split marking pattern 130 are smaller than the dimension X1 of the segmentation channel region 212; along the width direction, the dimension of the second split marking pattern 120 is smaller than the dimension Y1 of the segmentation channel region 212. Subsequently, the researchers placed the first splitting mark pattern 110, the second splitting mark pattern 120, and the third splitting mark pattern 130 in the segmentation channel region 212 according to the shape of the chip target mark pattern, so that the three splitting mark patterns could be spliced ​​together to form the shape of the complete chip target mark pattern, thereby solving the problem of overlap between the complete chip target mark pattern and the chip pattern.

[0048] Furthermore, during the process of transferring the complete chip target marking pattern to different material layers on the semiconductor structure surface, researchers can determine the coordinates of the complete chip target marking pattern based on the mask pattern template coordinate system, so that the chip target marking pattern is formed at predetermined positions on each material layer of the semiconductor structure surface. The mask pattern template coordinate system has its origin at the center of the mask pattern template 200.

[0049] After setting the complete chip target mark pattern on the segmentation channel area 212 through the above splitting and splicing process, a mask is manufactured according to the obtained output mask pattern template. After applying the mask to the actual photolithography process, the researchers found that the alignment accuracy was low during the alignment process based on the chip target mark pattern manufactured by splitting and splicing, which was difficult to meet the alignment accuracy requirements of high-precision process nodes.

[0050] Further investigation reveals that the low alignment accuracy of the chip target mark caused by the above splitting and splicing process is due to the disruption of the graphic continuity at the splicing boundary in the chip target mark pattern formed by splicing. Furthermore, each split mark pattern experiences slight positional shifts and deformation accumulation during photolithography transfer, resulting in a deviation between the actual chip target mark pattern formed in the split channel region 212 and the designed chip target mark pattern, making it impossible to achieve sub-micron level alignment accuracy.

[0051] Therefore, it is necessary to provide a method for generating a mask pattern that can form a complete chip target mark pattern within a mask pattern template without splitting the GDS file of the chip target mark pattern, and the chip target mark pattern does not overlap with the chip pattern.

[0052] Please see Figure 6 One embodiment of this application provides a method for generating a mask pattern. This method can be applied to a mask pattern design system. Specifically, the mask pattern design system can be a computer-aided design platform used to generate mask pattern data required for the photolithography process. For example, the mask pattern design system may include a design data input and management module, a design pattern editing module, a design rule checking and verification module, and a design data integration and output module, etc. The method for generating the mask pattern may include steps S110, S120, and S130.

[0053] S110: Obtain the mask pattern template and reference mark pattern.

[0054] To reduce the risk of decreased alignment accuracy caused by splitting the reference mark pattern GDS file without overlapping the reference mark pattern and chip pattern, the design pattern editing module of the mask pattern design system can be used to first divide the reference mark pattern in the pattern editing window, and then process the reference mark pattern data of each part obtained from the division.

[0055] Please continue reading. Figure 5In this embodiment, the mask pattern template (Frame) 200 can be a basic graphic structure defining the mask pattern layout framework. Specifically, the mask pattern template 200 provided in this application embodiment is similar to the mask pattern template 200 provided in related technologies. The mask pattern template 200 can be stored in GDSII or OASIS format. The mask pattern template 200 can include a chip region 210 and a dicing region 220. The chip region 210 can be used to form the functional circuit of a semiconductor device. The chip region 210 can include multiple spaced chip patterns 211 and dicing regions 212 between adjacent chip patterns 211. The chip patterns 211 can include design patterns for manufacturing circuit structures such as transistors, interconnects, and contact holes. The dicing regions 212 can be blank areas where no circuit structure is formed. The mask pattern template 200 can define information such as the arrangement of multiple chip patterns 211, the size parameters of the chip patterns 211, the width parameters of the dicing regions 212, and the overall size parameters of the chip region 210. The dicing area 220 can be a blank area surrounding the chip area 210 without any circuit structure formed. It can be used to set up process monitoring structures, alignment marks, and dicing slots, and after chip manufacturing is completed, it is used to determine the position of the diced semiconductor structure to separate the individual chips. The mask pattern template 200 can define information such as the width parameters of the dicing area 220.

[0056] Please see Figure 7 In this embodiment, the reference mark pattern 300 can be a design pattern for alignment marks. Specifically, the reference mark pattern 300 can be a chip target mark pattern. For example, similar to the packaging process in related technologies, after the functional circuit of the semiconductor device on the surface of the semiconductor structure is fabricated, alignment marks are formed by transferring the graphic pattern in the reference mark pattern 300 to the exposed top metal layer and the passivation protection layer deposited on the top metal layer, serving as alignment references for performing processes such as coating and packaging.

[0057] In this embodiment, the reference mark pattern 300 may include a graphic pattern and a background pattern. The graphic pattern can be used to form alignment marks. Specifically, the graphic pattern may include a first sub-graphic pattern 301 and a second sub-graphic pattern 302 with the same outline shape. The first sub-graphic pattern 301 may correspond to an alignment mark formed on the top metal layer, and the second sub-graphic pattern 302 may correspond to an alignment mark formed on the passivation protective layer.

[0058] To reduce alignment difficulty, in this embodiment, the first sub-graphic pattern 301 and the second sub-graphic pattern 302 can be symmetrical along the first direction A and along the second direction B perpendicular to the first direction A. Specifically, both the first sub-graphic pattern 301 and the second sub-graphic pattern 302 can be "cross-shaped," that is, both the first sub-graphic pattern 301 and the second sub-graphic pattern 302 can be formed by the overlapping of two rectangles extending along the first direction A and the second direction B, respectively. Since the passivation protective layer covers the top metal layer, to improve the overlay accuracy during the packaging process, the length of the first sub-graphic pattern 301 extending along the first direction A is less than the length of the second sub-graphic pattern 302 extending along the first direction A, and the length of the first sub-graphic pattern 301 extending along the second direction B is less than the length of the second sub-graphic pattern 302 extending along the second direction B; that is, the size of the first sub-graphic pattern 301 is smaller than the size of the second sub-graphic pattern 302. The background pattern can be a portion of the reference mark pattern 300 other than the graphic pattern. Specifically, the background pattern can be a monochrome filled area. For example, the fill color can be white.

[0059] In this embodiment, to obtain the mask pattern template and reference mark pattern, the design data of the mask pattern template 200 and the design data of the reference mark pattern 300, which are provided by the mask pattern designer and stored in GDS format, can be imported into the design data input and management module of the mask pattern design system. The design data input and management module is used to convert the format of the two design data so that the two design data can be presented as images in the pattern editing window of the design pattern editing module of the mask pattern design system. Various pattern editing operations on the mask pattern template 200 and the reference mark pattern 300 can be completed in the pattern editing window.

[0060] To remove the background pattern in the reference marker pattern 300, only the graphic pattern is transferred to the mask pattern template 200 to reduce the overlap between the reference marker pattern 300 and the chip pattern 211 in the chip region 210. In this embodiment, the reference marker pattern 300 can be divided into multiple non-overlapping reference marker regions. Specifically, the pattern division (Monitor) operation can be performed using the design pattern editing module of the mask pattern design system to divide the reference marker pattern 300 presented in the pattern editing window into multiple reference marker regions, so that each reference marker region contains part of the graphic pattern and part of the background pattern without affecting the GDS file of the reference marker pattern 300. For example, the reference marker pattern 300 can be divided into four reference marker regions—a first reference marker region 310, a second reference marker region 320, a third reference marker region 330, and a fourth reference marker region 340—along the center line of the reference marker pattern 300 in the first direction A and the center line of the reference marker pattern 300 in the second direction B.

[0061] S120: Use auxiliary graphics to extract the outline of a partial graphic pattern located in each reference mark area to obtain multiple auxiliary mark patterns, and lay out the multiple auxiliary mark patterns in the cutting channel area.

[0062] To ensure that the graphic pattern can be completely transferred to the semiconductor structure surface, for each reference mark area obtained by dividing the reference mark pattern, a partial graphic pattern outline can be extracted using auxiliary graphics. The extracted partial graphic pattern is then used to occupy the cutting area of ​​the mask pattern template, thereby providing a positional reference for the subsequent layout of local mark patterns in the mask pattern template.

[0063] In this embodiment, the auxiliary graphic can be used to define the range of the pattern outline to be extracted. Specifically, to retain the actual outline of the portion of the graphic pattern located in each reference mark area while removing the background pattern, the auxiliary graphic can be a rectangle.

[0064] Please refer to the following: Figure 5 , Figure 7 and Figure 8 Since the size of the first sub-graphic pattern 301 is smaller than the size of the second sub-graphic pattern 302, the size of the portion of the first sub-graphic pattern 301 located within each reference mark area is smaller than the size of the portion of the second sub-graphic pattern 302 located within each reference mark area. To ensure that the position of the auxiliary mark pattern 400 in the mask pattern template 200 is suitable for extracting local mark patterns obtained from different sub-graphic patterns, in this embodiment, the outline of the portion of the graphic pattern located within each reference mark area is extracted using auxiliary graphics to obtain multiple auxiliary mark patterns. This can include: using at least two adjacent auxiliary graphics to extract the outline of the portion of the second sub-graphic pattern located within each reference mark area to obtain multiple auxiliary mark patterns. Specifically, in the pattern editing window, the boundaries of the auxiliary mark pattern can be defined by comparing the outline of the portion of the second sub-graphic pattern located within each reference mark area using auxiliary graphics to obtain the auxiliary mark pattern.

[0065] As can be seen from the formation process of the auxiliary marker pattern 400, in this embodiment, the number of auxiliary marker patterns 400 is the same as the number of reference marker areas. For example, when there are 4 reference marker areas, the number of auxiliary marker patterns 400 is also 4. Specifically, the auxiliary marker pattern 400 can correspond to the reference marker areas. Among them, the auxiliary marker pattern 400 corresponding to the first reference marker area 310 and the auxiliary marker pattern 400 corresponding to the second reference marker area 320 are symmetrical about the center line of the reference marker pattern 300 in the first direction A; the auxiliary marker pattern 400 corresponding to the first reference marker area 310 and the auxiliary marker pattern 400 corresponding to the fourth reference marker area 340 are symmetrical about the center line of the reference marker pattern 300 in the second direction B; and the auxiliary marker pattern 400 corresponding to the first reference marker area 310 and the auxiliary marker pattern 400 corresponding to the third reference marker area 330 are diagonally symmetrical.

[0066] Please refer to the following: Figure 7 and Figure 8 Taking the auxiliary marker pattern 400 corresponding to the second reference marker region 320, i.e., the auxiliary marker pattern 400 obtained by extracting the outline of a portion of the second sub-graphic pattern 302 located within the second reference marker region 320, as an example, the auxiliary marker pattern 400 can be composed of a first auxiliary graphic 410 and a second auxiliary graphic 420 that are adjacent to each other. Both the first auxiliary graphic 410 and the second auxiliary graphic 420 are rectangles. In order to make the outline of the auxiliary marker pattern 400 match the outline of the portion of the second sub-graphic pattern 302 located within each reference marker region, the sizes of the first auxiliary graphic 410 and the second auxiliary graphic 420 can be different. Specifically, the short side of the first auxiliary graphic 410 can be set adjacent to the long side of the second auxiliary graphic 420, and the length of the long side of the first auxiliary graphic 410 can be less than the length of the long side of the second auxiliary graphic 420.

[0067] Please refer to the following: Figures 7 to 9To enable multiple local marker patterns to combine on the semiconductor structure surface to form a complete alignment marker pattern that matches the pattern, and to ensure that the complete alignment marker pattern is formed at the center of the dicing channel on the semiconductor structure surface, thereby reducing alignment difficulty and improving alignment accuracy, in this embodiment, multiple auxiliary marker patterns are arranged within the dicing channel area. This may include arranging multiple auxiliary marker patterns within the dicing channel area at the corner of the mask pattern template. Each auxiliary marker pattern 400 may be positioned on the side of the dicing channel centerline 221 near the chip region 210, with at least a portion of its boundary adhering to the dicing channel centerline 221. Specifically, to improve the alignment accuracy during the process of combining multiple local marker patterns to form the alignment marker pattern, the auxiliary marker pattern 400 may be positioned with a portion of its boundary along the dividing line of the multiple reference marker regions adhering to the dicing channel centerline 221.

[0068] During the actual formation of the auxiliary marker pattern 400, researchers discovered that due to extraction operation errors and other reasons, the outline of the auxiliary marker pattern 400 may deviate from the outline of some of the second sub-graphic patterns 302. In this case, if the auxiliary marker pattern 400 is set at the corner of the mask pattern template 200 according to the degree of shape matching—for example, setting the auxiliary marker pattern 400 corresponding to the second reference marker area 320 at the lower left corner of the mask pattern template 200—this deviation may be inherited during the process of combining and forming the alignment marker pattern, reducing the alignment accuracy of each local marker pattern and resulting in a decrease in the shape matching degree between the final combined alignment marker pattern and the graphic pattern.

[0069] To further improve the alignment accuracy during the process of combining multiple local marker patterns to form a alignment marker pattern, auxiliary marker patterns 400 corresponding to each reference marker region can be placed at corresponding corners of the mask pattern template 200 based on the relative positional relationship between each reference marker region and the reference marker pattern 300, as well as the relative positional relationship between each corner of the mask pattern template 200 and the mask pattern template 200. For example, the auxiliary marker pattern 400 corresponding to the second reference marker region 320 can be placed at the upper right corner of the mask pattern template 200. To reduce the overlap between the auxiliary marker pattern 400 and the chip pattern 211 within the chip region 210, after extracting the pattern outline to obtain the auxiliary marker pattern 400, the auxiliary marker pattern 400 can be rotated at least once counterclockwise by 90° to match the shape of the auxiliary marker pattern 400 with the shape of the corresponding corner in the mask pattern template 200. For example, the auxiliary marker pattern 400 corresponding to the second reference marker region 320 can be rotated twice counterclockwise by 90° before being placed at the upper right corner of the mask pattern template 200.

[0070] Since the size of the mask pattern template 200 corresponds to the single exposure coverage area in the photolithography process, after the local marking patterns are placed at the positions of the auxiliary marking patterns 400 to obtain the target mask pattern, if a single exposure is performed based on the target mask pattern, the local marking patterns transferred to the semiconductor structure surface will be distributed in various corners of the single exposure coverage area on the semiconductor structure surface, and cannot be combined to form an alignment marking pattern. Therefore, multiple exposures are required sequentially to allow the local marking patterns in the corners of adjacent single exposure coverage areas to combine. For example, in the case where four local marking patterns are combined to form an alignment marking pattern, the alignment marking pattern can be formed by combining the local marking patterns located in the corners of 2×2 adjacent single exposure coverage areas. However, in the process of performing multiple exposures sequentially, the subsequent exposure process may damage the local marking patterns that have been transferred to the semiconductor structure surface by the previous exposure process.

[0071] Please see Figure 10 To protect local marking patterns formed on the surface of a semiconductor structure during multiple exposure processes, in some embodiments, after arranging multiple auxiliary marking patterns within the dicing area, the mask pattern generation method may further include: corresponding to the multiple auxiliary marking patterns, arranging multiple protective marking patterns within the dicing area at the corner of the mask pattern template. Thus, during the sequential multiple exposure process, the protective marking patterns 500 can block at least a portion of the light from subsequent exposure processes from illuminating the local marking patterns formed on the surface of the semiconductor structure. Specifically, to expand the protection range of the protective marking patterns 500, each protective marking pattern 500 may be disposed on the side of the centerline 221 of the dicing area away from the chip area 210, and at least cover the area defined by the following boundaries: the corner vertex of the mask pattern template 200, the first boundary of the auxiliary marking pattern, and the extension line formed by extending the second boundary of the auxiliary marking pattern in the opposite direction to the normal direction of the centerline 221 of the dicing area. The first boundary of the auxiliary marking pattern is a portion of the auxiliary marking pattern that adheres to the centerline 221 of the dicing area. The second boundary of the auxiliary marking pattern is a portion of the boundary of the auxiliary marking pattern extending along the normal direction of the center line 221 of the cutting channel region.

[0072] In this embodiment, similar to the auxiliary marking pattern, the protective marking pattern 500 can be composed of two adjacent rectangles. The shorter side of the rectangle forming the protective marking pattern 500 is longer than both the shorter side of the first auxiliary pattern 410 and the shorter side of the second auxiliary pattern 420.

[0073] Since the protective marking pattern 500 needs to block light, while the partial marking pattern needs to transmit light to transfer the pattern, in this embodiment, the transmittance of the protective marking pattern 500 and the partial marking pattern are different in the target mask pattern manufactured based on the mask pattern template on which the protective marking pattern is formed. Specifically, the transmittance of the protective marking pattern 500 can be 0.

[0074] S130: Extract a portion of the graphic pattern located in each reference mark area to obtain multiple local mark patterns, and place each local mark pattern at the position of the corresponding auxiliary mark pattern in the dicing area to obtain the target mask pattern, so that during the process of manufacturing the semiconductor structure according to the target mask pattern, the multiple local mark patterns transferred to the semiconductor structure are combined in the dicing area of ​​the semiconductor structure to form an alignment mark pattern that matches the graphic pattern.

[0075] To improve the matching degree between the alignment mark pattern and the graphic pattern formed on the semiconductor structure surface, after using the auxiliary mark pattern to occupy the cutting area of ​​the mask pattern template, a portion of the graphic pattern located in each reference mark area can be cut out to obtain multiple local mark patterns. The cut local mark patterns are then placed in the occupancy positions of the auxiliary mark pattern to obtain the target mask pattern. Thus, during the photolithography process based on the target mask pattern, the alignment mark pattern can be formed by combining multiple local mark patterns, realizing the transfer of the complete graphic pattern to the semiconductor structure surface without splitting the GDS file of the reference mark pattern.

[0076] In this embodiment, the local marker pattern can be obtained by directly cropping the graphic pattern located within each reference marker area in the pattern editing window. Therefore, the local marker pattern can correspond to the reference marker area. Similarly, there is a correspondence between the auxiliary marker pattern and the reference marker area; therefore, the local marker pattern corresponds to the auxiliary marker pattern. For example, the local marker pattern obtained by cropping a portion of the graphic pattern within the first reference marker area corresponds to the auxiliary marker pattern obtained by extracting the outline of the portion of the graphic pattern within the first reference marker area. Based on this, in this embodiment, arranging each local marker pattern at the position of the corresponding auxiliary marker pattern in the dicing area can include: setting the local marker pattern on the side of the center line 221 of the dicing area close to the chip area 210, and the local marker pattern adhering to a portion of the boundary of the dividing lines of the multiple reference marker areas along the center line 221 of the dicing area.

[0077] To ensure that the alignment mark patterns formed on different material layers on the surface of the semiconductor structure match the first sub-pattern pattern and the second sub-pattern pattern respectively, in this embodiment, a portion of the pattern pattern located in each reference mark region is extracted to obtain multiple local mark patterns, and each local mark pattern is placed at the position of the corresponding auxiliary mark pattern in the dicing region to obtain the target mask pattern. This may include: extracting a portion of the first sub-pattern pattern located in each reference mark region to obtain multiple first sub-pattern local mark patterns, and placing each first sub-pattern local mark pattern at the position of the corresponding auxiliary mark pattern in the dicing region to obtain the first target mask pattern; extracting a portion of the second sub-pattern pattern located in each reference mark region to obtain multiple second sub-pattern local mark patterns, and placing each second sub-pattern local mark pattern at the position of the corresponding auxiliary mark pattern in the dicing region to obtain the second target mask pattern.

[0078] Please see Figure 11 and Figure 12 In this embodiment, the first sub-graphic partial marker pattern can be a portion of the graphic pattern located within each reference marker region, extracted from the first sub-graphic pattern. Specifically, similar to the auxiliary marker pattern, the first sub-graphic partial marker pattern can be composed of two adjacent rectangles of different sizes. Taking the first sub-graphic partial marker pattern 600 obtained by extracting a portion of the first sub-graphic pattern located within the second reference marker region 320 as an example, the first sub-graphic partial marker pattern 600 can include a first extension 610 and a second extension 620.

[0079] It should be noted that although the outline of the first sub-graphic local marker pattern 600 is the same as or very similar to that of the auxiliary marker pattern, "extracting the outline of a part of the graphic pattern located in each reference marker area using the auxiliary graphic in the pattern editing window" and "cropping a part of the graphic pattern located in each reference marker area in the pattern editing window" are two different pattern editing operation methods. That is, extracting the outline of a part of the graphic pattern is similar to the "framing" operation, the auxiliary marker pattern actually only contains the outline information of a part of the graphic pattern, while cropping a part of the graphic pattern is similar to the "screenshot" operation, and the first sub-graphic local marker pattern 600 contains all the information of the part of the graphic pattern.

[0080] Please see Figure 13 and Figure 14In this embodiment, the second sub-graphic partial marker pattern can be a portion of the graphic pattern located within each reference marker region, extracted from the second sub-graphic pattern. Specifically, similar to the auxiliary marker pattern, the second sub-graphic partial marker pattern can be composed of two adjacent rectangles of different sizes. Taking the second sub-graphic partial marker pattern 700 obtained by extracting a portion of the second sub-graphic pattern located within the second reference marker region 320 as an example, the second sub-graphic partial marker pattern 700 can include a third extension 710 and a fourth extension 720. The information contained in the second sub-graphic partial marker pattern and the process of extracting the second sub-graphic partial marker pattern are similar to the information contained in the first sub-graphic partial marker pattern and the process of extracting the first sub-graphic partial marker pattern, and will not be described again here.

[0081] In this embodiment, during the fabrication of the semiconductor structure based on the target mask pattern, the first target mask pattern and the second target mask pattern are respectively transferred to different material layers of the semiconductor structure. Specifically, in order to match the alignment mark pattern formed on the top metal layer of the semiconductor structure surface with the first sub-pattern pattern in the reference mark pattern, the first target mask pattern can be transferred to the top metal layer of the semiconductor structure surface. Furthermore, in order to match the alignment mark pattern formed on the passivation protection layer of the semiconductor structure surface with the second sub-pattern pattern in the reference mark pattern, the second target mask pattern can be transferred to the passivation protection layer of the semiconductor structure surface.

[0082] Please see Figure 15 and Figure 16 Since the target mask pattern is formed by placing local marker patterns at the positions of auxiliary marker patterns in the dicing region, in this embodiment, a protective marker pattern 500 is formed on the side of the dicing region away from the chip region along the centerline of the dicing region of the target mask pattern. Specifically, in the first target mask pattern, the protective marker pattern 500 and the first extension 610 and the second extension 620 of the first sub-pattern local marker pattern are respectively formed on both sides of the centerline 221 of the dicing region. In the second target mask pattern, the protective marker pattern 500 and the third extension 710 and the fourth extension 720 of the second sub-pattern local marker pattern are respectively formed on both sides of the centerline 221 of the dicing region. In both the first and second target mask patterns, the size and position of the protective marker pattern on the target mask pattern can be the same.

[0083] Another embodiment of this application provides a mask. This mask can be manufactured based on a target mask pattern generated by the mask pattern generation method described in the above embodiments. During the manufacturing of a semiconductor structure according to this mask, multiple local marker patterns transferred to the semiconductor structure can be combined within the dicing channels of the semiconductor structure to form an alignment marker pattern that matches the patterned pattern.

[0084] Please see Figure 17 Another embodiment of this application provides a semiconductor structure that can be manufactured according to a target mask pattern generated by the mask pattern generation method described in the above embodiments, or according to a mask fabrication method described in the above embodiments. Multiple local marker patterns transferred to the semiconductor structure can be combined within the dicing channel 900 of the semiconductor structure to form an alignment marker pattern 800 that matches a patterned pattern. Specifically, in the alignment marker pattern 800 formed within the dicing channel 900 of the semiconductor structure, a first sub-alignment marker pattern 801 can be formed on the top metal layer and matches a first sub-patterned pattern. A second sub-alignment marker pattern 802 can be formed on a passivation protection layer and matches a second sub-patterned pattern.

[0085] Another embodiment of this application provides a method for manufacturing a semiconductor structure. This method manufactures the semiconductor structure using a target mask pattern generated according to the mask pattern generation method described in the above embodiments, or using a mask as described in the above embodiments. The method may include: using a multiple exposure process to transfer multiple local marking patterns into the dicing channels of the semiconductor structure, such that the multiple local marking patterns combine within the dicing channels of the semiconductor structure to form an alignment marking pattern that matches the patterned pattern.

[0086] The technical effects of the mask, semiconductor structure, and semiconductor structure manufacturing method described in the above embodiments can be explained by comparison with other embodiments of this application, and will not be repeated here.

[0087] In this embodiment, a mask pattern template including a chip region and a dicing region is obtained, along with a reference marker pattern divided into multiple reference marker regions. Each reference marker region contains a partial graphic pattern and a partial background pattern. Then, the outline of the partial graphic pattern within each reference marker region is extracted using auxiliary graphics to obtain multiple auxiliary marker patterns. These auxiliary marker patterns are then placed within the dicing region. Next, the partial graphic pattern within each reference marker region is extracted to obtain multiple local marker patterns. Each local marker pattern is then placed at the corresponding position of the auxiliary marker pattern within the dicing region to obtain the target mask pattern. This allows the target mask pattern to be transferred to the semiconductor fabrication process during the fabrication of the semiconductor structure based on the target mask pattern. Multiple local marking patterns of the bulk structure are combined within the dicing channel of the semiconductor structure to form an alignment marking pattern that matches the graphic pattern. Unexpected effects achieved include: since the auxiliary marking pattern is obtained by extracting the outline of a portion of the graphic pattern, and the local marking pattern is obtained by cropping a portion of the graphic pattern, after the auxiliary marking pattern occupies a position in the mask pattern template, the local marking pattern replaces the auxiliary marking pattern. Thus, without splitting the GDS file of the reference marking pattern, the local transfer and recombination of the graphic pattern can be achieved. This makes the combined alignment marking pattern have the complete graphic features of the reference marking pattern, thereby reducing the pattern deviation of the chip target marking pattern formed by splitting and splicing, and improving the alignment accuracy in the packaging process.

[0088] It is understood that the specific examples in this application are only intended to help those skilled in the art better understand the embodiments of this application, and are not intended to limit the scope of this application.

[0089] It is understood that in the various embodiments of this application, the sequence number of each process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not limit the implementation process of the embodiments of this application in any way.

[0090] It is understood that the various embodiments described in this application can be implemented individually or in combination, and the embodiments of this application are not limited in this respect.

[0091] Unless otherwise stated, all technical and scientific terms used in the embodiments of this application have the same meaning as commonly understood by one of ordinary skill in the art. The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. The term "and / or" as used in this application includes any and all combinations of one or more of the associated listed items. The singular forms "a," "the," and "the" as used in the embodiments of this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0092] As will be understood from the embodiments provided in this application, the disclosed mask and semiconductor structures can be implemented in other ways. For example, the embodiments of the mask and semiconductor structures described above are merely illustrative.

[0093] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for generating a mask pattern, characterized in that, Applied to a mask pattern design system; the method for generating the mask pattern includes: A mask pattern template and a reference mark pattern are obtained; wherein the mask pattern template includes a chip region and a dicing area surrounding the chip region; the reference mark pattern includes a graphic pattern and a background pattern; the graphic pattern includes a first sub-graphic pattern and a second sub-graphic pattern with the same outline shape; the first sub-graphic pattern and the second sub-graphic pattern extend along a first direction and a second direction that are perpendicular to each other; wherein the length of the first sub-graphic pattern extending along the first direction is less than the length of the second sub-graphic pattern extending along the first direction, and the length of the first sub-graphic pattern extending along the second direction is less than the length of the second sub-graphic pattern extending along the second direction; the reference mark pattern is divided into multiple non-overlapping reference mark regions; each reference mark region contains a portion of the graphic pattern and a portion of the background pattern; The method involves extracting the outline of a portion of the graphic pattern located within each of the reference marker regions using auxiliary graphics to obtain multiple auxiliary marker patterns. This includes: extracting the outline of a portion of the second sub-graphic pattern located within each of the reference marker regions using at least two adjacent auxiliary graphics to obtain multiple auxiliary marker patterns; wherein the auxiliary graphics are rectangles; and arranging the multiple auxiliary marker patterns within the cutting channel region; wherein the number of auxiliary marker patterns is the same as the number of reference marker regions. A portion of the graphic pattern located within each of the reference marking regions is extracted to obtain multiple local marking patterns. Each local marking pattern is then positioned within the corresponding auxiliary marking pattern in the dicing area to obtain a target mask pattern. This results in the multiple local marking patterns transferred to the semiconductor structure during the fabrication of the semiconductor structure based on the target mask pattern being combined within the dicing area of ​​the semiconductor structure to form an alignment marking pattern that matches the graphic pattern.

2. The method for generating a mask pattern according to claim 1, characterized in that, Arranging multiple auxiliary marking patterns within the cutting area includes: Multiple auxiliary marker patterns are arranged in the dicing area at the corner of the mask pattern template; wherein each auxiliary marker pattern is located on the side of the dicing area close to the chip area, and at least part of its boundary is attached to the center line of the dicing area.

3. The method for generating a mask pattern according to claim 2, characterized in that, After laying out multiple auxiliary marker patterns within the cutting area, the method for generating the mask pattern further includes: Corresponding to multiple auxiliary marker patterns, multiple protective marker patterns are arranged in the cutting channel area at the corner of the mask pattern template to obtain a target mask pattern; wherein, each of the protective marker patterns is disposed on the side of the center line of the cutting channel area away from the chip area, and at least covers the area defined by the following boundaries: the corner vertex of the mask pattern template, the first boundary of the auxiliary marker pattern, and the extension line formed by the second boundary of the auxiliary marker pattern extending in the opposite direction to the normal of the center line of the cutting channel area; the first boundary of the auxiliary marker pattern is the partial boundary of the auxiliary marker pattern that fits the center line of the cutting channel area; the second boundary of the auxiliary marker pattern is the partial boundary of the auxiliary marker pattern that extends in the normal direction of the center line of the cutting channel area.

4. The method for generating a mask pattern according to claim 3, characterized in that, In the target mask pattern, the transmittance of the protective marking pattern and the local marking pattern are different; wherein, the transmittance of the protective marking pattern is 0.

5. The method for generating a mask pattern according to claim 1, characterized in that, A portion of the graphic pattern located within each of the reference marker regions is extracted to obtain multiple local marker patterns. Each local marker pattern is then positioned within the corresponding auxiliary marker pattern within the cutting channel region to obtain a target mask pattern, including: A portion of the first sub-graphic pattern located within each of the reference marker areas is extracted to obtain multiple first sub-graphic partial marker patterns. Each first sub-graphic partial marker pattern is then placed at the position of the corresponding auxiliary marker pattern within the cutting channel area to obtain a first target mask pattern. A portion of the second sub-graphic pattern located within each of the reference mark regions is extracted to obtain multiple second sub-graphic partial mark patterns. Each second sub-graphic partial mark pattern is then placed at the position of the corresponding auxiliary mark pattern within the cutting channel region to obtain a second target mask pattern. During the manufacturing of the semiconductor structure based on the target mask pattern, the first target mask pattern and the second target mask pattern are respectively transferred to different material layers of the semiconductor structure.

6. A mask, characterized in that, The mask is manufactured based on a target mask pattern generated by the mask pattern generation method as described in any one of claims 1 to 5; during the manufacturing of a semiconductor structure according to the mask, a plurality of the local marking patterns transferred to the semiconductor structure are combined in the dicing channels of the semiconductor structure to form an alignment marking pattern that matches the graphic pattern.

7. A semiconductor structure, characterized in that, The semiconductor structure is manufactured according to a target mask pattern generated by the mask pattern generation method according to any one of claims 1 to 5, or according to the mask manufacturing method according to claim 6. The plurality of local marking patterns transferred to the semiconductor structure are combined within the dicing channel of the semiconductor structure to form an alignment marking pattern that matches the graphic pattern.

8. A method for manufacturing a semiconductor structure, characterized in that, The semiconductor structure manufacturing method manufactures a semiconductor structure according to a target mask pattern generated by the mask pattern generation method according to any one of claims 1 to 5, or manufactures a semiconductor structure according to a mask as described in claim 6. The method for manufacturing the semiconductor structure includes: Using a multiple exposure process, multiple local marking patterns are transferred to the dicing channel of the semiconductor structure, so that the multiple local marking patterns are combined in the dicing channel of the semiconductor structure to form an alignment marking pattern that matches the graphic pattern.

Images