Standard cell type selection method for simultaneously sensing congestion line length based on double-sided transistor

Abstract

The invention discloses a standard cell model selection method based on simultaneous congestion and line length sensing of a double-sided transistor, which is characterized in that optimization modeling is carried out for model selection of a standard cell with double-sided input pins, an optimization target simultaneously comprises a line length and a congestion index, and an optimization variable is the model selection of the standard cell; the method comprises the following steps: constructing an approximate optimization model by introducing a line network planning variable, and solving by adopting line network planning and standard unit model selection driven by a line network planning drive. According to the invention, congestion and wire length are optimized at the same time, a better wire length can be obtained, the coupling condition between metal wires is reduced, and the time sequence and power consumption performance of a chip are improved; according to the invention, the wiring capability of the chip is improved, the condition of design rule default after wiring of the chip is reduced, the design convergence of the chip is accelerated, and the yield of the chip is further improved; and the area of the chip can be reduced more potentially, so that the design cost of the double-sided chip can be reduced.

Description

Technical Field

[0001] This invention belongs to the field of chip design technology, and relates to transistor standard cell selection technology, and particularly to a standard cell selection method based on simultaneous perception of congestion line length of double-sided transistors. Background Technology

[0002] In the field of chip design technology, bifacial transistors have shown enormous design potential compared to traditional single-sided transistors. Standard cells built based on bifacial transistors have pins on both sides of the chip and support modular designs with bifacial interconnects. This poses a significant challenge to back-end design algorithms, requiring the remodeling of mathematical optimization problems and the design of suitable algorithms to fully utilize the design potential of chips based on bifacial transistors.

[0003] Existing chip standard cell selection methods include two techniques: First, utilizing the interconnection relationships of the standard cell's input pins, clustering related pins using a clustering algorithm, and then evenly distributing them on both sides of the chip according to their pin count. Second, determining the final standard cell selection scheme based on the even distribution of standard cell pins on both sides of the chip according to their pin count.

[0004] Both of the above schemes aim to evenly distribute pins when selecting standard cells, but they have the following shortcomings: Existing solutions lack a direct target for trace length optimization. Using uniform pin allocation as a target to guide standard cell selection can, to some extent, distribute routing resource requirements across both sides of the chip. However, uniform pin allocation does not directly optimize trace length in double-sided chip designs. Therefore, a large number of double-sided nets (where drive pins are not entirely on the same side of the chip within a net) may still exist, leading to poor trace length results for double-sided chips. Since trace length is a key metric for optimizing performance, power consumption, and area (PPA) in back-end design, the current lack of trace length optimization is highly detrimental to PPA.

[0005] Existing solutions lack direct congestion optimization targets and cannot effectively detect congestion on different sides of the double-sided chip. This reduces the chip's routeability and increases the risk of backend process failures. Furthermore, due to the parasitic coupling capacitance between adjacent metal lines, congestion can further exacerbate coupling issues, impairing the final power-to-applicability (PPA) of the chip design.

[0006] In summary, existing standard chip cell selection techniques cannot simultaneously optimize for both congestion and pin length. Both pin length and congestion are critical optimization objectives in chip design, and methods focused on uniform pin distribution cannot jointly optimize both objectives, leading to poor power performance area (PPA) in the final chip design. Summary of the Invention

[0007] To overcome the shortcomings of the prior art, this invention provides a standard cell selection method based on congestion line length sensing using double-sided transistors. This invention is based on a double-sided transistor architecture, which has pins on both the front and back sides of the chip, ensuring interconnection on both sides. By jointly optimizing both line length and congestion, this invention improves the final PPA of the chip design and reduces the design cost of double-sided chips.

[0008] The standard cell selection problem in double-sided transistor-based chip design has a significant impact on the final power performance (PPA) of the chip. This invention considers two key aspects of back-end design: congestion and trace length optimization, improving the chip's PPA and overcoming the shortcomings of existing technologies that lack optimization for trace length and congestion. This invention provides a complete mathematical model of the standard cell selection problem for double-sided input pins, with the optimization objective including both trace length and congestion indicators, and the optimization variable being standard cell selection. The original optimization problem is approximated by introducing auxiliary netting variables for easier solution. For the approximate optimization problem, a two-step decomposition is used to solve it: netting planning and netting planning-driven standard cell selection. Netting planning utilizes the results of dual analysis to design an algorithm for solving the problem. Netting planning-driven standard cell selection, based on the results of netting planning, employs a combination of global and local search methods for solution.

[0009] The technical solution provided by this invention is: A standard cell selection method based on congestion line length simultaneous sensing using double-sided transistors is proposed. This method optimizes the selection of standard cells with double-sided input pins, with the optimization objective including both line length and congestion index, and the optimization variable being the standard cell selection. An approximate optimization model is constructed by introducing wire mesh planning variables, and the model is solved using wire mesh planning and wire mesh planning-driven standard cell selection. The method includes the following steps: Step 1: Divide the double-sided transistor chip into multiple grid points according to a mesh pattern. Each grid point records the congestion status of the front and back sides of the chip's nets. Based on the standard cell selection of the double-sided transistor chip, calculate the bus length of all front and back nets. Optimize the standard cell selection problem for double-sided transistor chips with double-sided input pins using a modeling approach. Step 2: By introducing network planning variables, an approximate optimization model is constructed and solved to obtain network planning variables for congestion optimization, and further obtains network planning results for congestion optimization of double-sided chip design. The optimization objective includes both line length and congestion indicators, and the degree of optimization for line length and congestion is controlled by the objective function and constraints; the optimization variable is the selection of standard cells; the objective function and constraints for constructing the approximate optimization model are expressed as follows: in, A set of all standard unit selection variables; This is the worst-case congestion scenario. Represents the bus length on the front and back sides of each wire e, where α and β are parameters used to control congestion and the degree of optimization of wire length, respectively. A collection of wire meshes; The actual congestion value of the corresponding wire network e at different grid points; subscript Represents a grid point; z e For network planning variables; Refers to the total width of the chip layout. This refers to the total height of the chip layout.

[0010] Sort the grid points according to their total congestion value before allocation, and execute the process sequentially; for each grid point, according to... The net is evenly distributed across both sides of the chip, and the net planning result z is solved. e We obtain optimized network planning results for congestion in double-sided chip designs. Step 3: Design initialization and iterative standard element selection functions based on network planning to achieve network planning-driven standard element selection. The initialization function for standard cell selection is used to enable pin selection on the standard cell (v,e). In this case, the pin positions and net planning variables are the same; the initial selection results of standard cells are obtained by initializing the standard cell selection function; The initialization standard unit selection function is defined as follows: Where WL(e) is the half-circumference length of each wire mesh; This refers to the set of different standard element selections corresponding to the standard element v in the netlist in the standard element library; It is the collection of all nets in the netlist that are connected to the input pins of the standard cell v; This refers to the pin positions on the standard unit (v,e) when type l is selected; This represents the initial selection result for the standard unit v; The standard cell selection optimization result is obtained by further optimizing the line length using the pin positions of the double-sided net using an iterative standard cell selection function. The iterative standard cell selection function requires that the function value is minimized in the k-th round of standard cell selection. Here, the k-th round represents any round of the iterative standard cell selection.

[0011] The corresponding iterative standard unit selection function is defined as follows: in, It is the increment of the bus length DWL(e) of the net when a pin (v,e) of the net changes position; It is the initial position of pin (v,e) in the k-th round. This represents the selection optimization result of the standard unit v in the kth round.

[0012] Through the above steps, standard cell selection based on simultaneous congestion line length sensing using double-sided transistors can be achieved.

[0013] Compared with the prior art, the beneficial effects of the present invention are: This invention provides a standard cell selection method based on simultaneous congestion line length sensing of double-sided transistors. It constructs a novel optimization model for the standard cell selection problem in double-sided chip design, and uses auxiliary wire planning variables to approximate and decompose the problem. Finally, it uses wire planning algorithm and standard cell selection algorithm to obtain the final standard cell selection result.

[0014] The selection of standard cells in double-sided chip design has a significant impact on the final power-to-appearance (PPA) of the chip. It requires optimization considering both congestion and trace length, making it a challenging back-end design problem for integrated circuits. This invention constructs a standard cell selection optimization model with double-sided input pins; derives and solves an approximate optimization problem to obtain the netlist planning results; and then performs standard cell selection. The technical solution of this invention has the following advantages: This invention optimizes both congestion and line length. Compared to a design with uniformly distributed pins, it achieves a better line length, reduces coupling between metal lines, and improves the chip's timing and power consumption performance.

[0015] This invention improves the wiredability of chips, significantly reduces design rule violations after chip wiring, accelerates chip design convergence, and further helps to improve chip yield.

[0016] This invention improves chip wiring flexibility and has the potential to reduce chip area, thus helping to reduce the design cost of double-sided chips. Attached Figure Description

[0017] Figure 1 This is a flowchart of the method of the present invention. Detailed Implementation

[0018] The present invention will be further described below with reference to the accompanying drawings and embodiments, but the scope of the invention is not limited in any way.

[0019] This invention provides a standard cell selection method based on congestion line length simultaneous sensing using double-sided transistors. It performs a complete optimization problem mathematical modeling for the standard cell selection problem with double-sided input pins. The optimization objective includes both line length and congestion index, and the optimization variable is standard cell selection. The original optimization problem is constructed by introducing auxiliary net planning variables and adding new objective terms to the objective function to control the optimization degree of line length and congestion, thus creating an approximate optimization problem for easier solution. For the approximate optimization problem, a two-step decomposition is used to solve it: net planning and net planning-driven standard cell selection. The congestion-driven net planning uses an algorithm designed based on the results of dual analysis. The net planning-driven standard cell selection, based on the results of net planning, uses a combination of global and local search methods. This yields the standard cell selection. This invention determines the pin positions through standard cell selection, reducing line length and congestion during the subsequent signal transfer cell (STC) insertion and routing stage.

[0020] Taking a standard cell based on a double-sided transistor as an example, its input pins are distributed on the front and back of the chip according to different design requirements. This invention selects standard cells for the results of layout in digital circuits. The input is the chip's netlist and layout results, where each standard cell comes from a standard cell library based on double-sided transistors. This invention models a mathematical optimization problem for standard cell selection that simultaneously considers line length and congestion. After introducing auxiliary net planning variables and objective terms to control the optimization degree of line length and congestion, an approximate optimization problem is obtained. Net planning and net planning-driven standard cell selection are used to solve the problem. The specific implementation includes the following steps: Step 1: Divide the double-sided transistor chip into multiple grid points according to a grid pattern. Each grid point records the congestion status of the front and back sides of the chip's nets. Based on the standard cell selection of the double-sided transistor chip, calculate the bus length of all front and back nets. Perform optimization modeling for the standard cell selection problem of double-sided transistor chips with double-sided input pins: The objective function of the standard cell selection optimization model with double-sided input pins constructed in this invention includes two parts: congestion and wire length. Depending on the different results of the standard cell selection, a single net defined in the netlist may simultaneously contain pins on both the front and back sides; that is, the physical implementation of a net includes a front part (front net) and a back part (back net). Congestion is modeled using a rectangular uniform wire density (RUDY) type, requiring the chip to be divided into W x H grid points according to a grid pattern. Each grid point records the congestion situation on the front and back sides of the net, which is accumulated based on the net's coverage of the grid points. Wire length is calculated based on the results of the standard cell selection, determining the bus length of all front and back nets. This wire length model is based on the half-perimeter wire length (HPWL). This step proposes a mathematical optimization model for standard cell selection with double-sided input pins, whose objective function and constraints are expressed as follows: in, This is the worst-case congestion scenario. This represents the bus length of each wire e (front + back). α and β are parameters used to control the degree of congestion and wire length optimization, respectively. A collection of wire meshes. Refers to the total width of the chip layout. This refers to the total height of the chip layout. It refers to a specific location (i.e., a grid point) within the total width. This refers to a specific location (grid point) within the total height. The first two lines of the constraint section ensure that the worst-case congestion scenario in the objective function is realistic. and These represent the congestion levels at each grid point, specifically the front and back sides. The function. This refers to the collection of different standard cell types corresponding to the standard cell v in the standard cell library in the netlist. It is a set A standard unit type in [the context of the text]. It is a 0-1 variable used to determine whether the standard cell v selects the corresponding standard cell type. . The constraint ensures that each standard cell can only select one standard cell type. This is the set of all standard unit selection variables. It is a set of standard cells in the netlist.

[0021] Step two involves deriving the solution to the approximate optimization problem to obtain the network planning variables for congestion optimization. Furthermore, we obtained the optimized network planning results for congestion in double-sided chip designs; As shown in the modeling of the original problem, the only optimization variable in this problem is the standard cell selection variable x. v,l To facilitate the solution of the problem, we introduce the network planning variable z. e , representing the planned position (front or back) of a wire mesh e before actual selection, is a 0-1 variable. In this step, it is assumed that all wire meshes can be completely enclosed by z. e The variable determines whether any net will be placed entirely on the front or back side of the chip. Ignoring the specific standard cell selection might prevent nets from being placed entirely on either side. By ignoring the specific standard cell selection, an approximate optimization problem can be proposed. This helps reduce the size of the optimization variables, the complexity of the constraints, and the complexity of the objective function, quickly providing a net planning result.

[0022] The objective function and constraints of the approximate optimization model are expressed as follows: in, This corresponds to the actual congestion value at different grid points for each wire network e, which is calculated using the RUDY function. subscript This represents a grid point (coordinates) used to indicate that for net e, net e is considered valid only if the grid point is inside the bounding box of the net (the smallest rectangle covering all pins of the net). The congestion value contributes to the problem. In this problem, the approximate optimization model transforms the complex congestion function into a linear superposition function. The complex standard element selection variables in the original problem are replaced by wire network planning variables, which have simpler constraints and can be solved faster than the original problem.

[0023] The specific algorithm for wire network planning is to allocate the wire network to both sides of the chip according to its actual location and congestion situation, with the goal of reducing the worst-case congestion situation.

[0024] Since the netting assumes all driver pins are on the same side of the chip, variations in wire length do not need to be considered during netting planning. According to the constraints, the constraints of the netting optimization problem exist at every grid point. Therefore, using dual analysis, we can identify which grid points are most critical for congestion optimization. Analysis shows that the grid point with the most severe total congestion on both the front and back sides is the most critical for optimization. This invention sorts the grid points from largest to smallest according to their total congestion value when unassigned, and executes the optimization sequentially. For each grid point, according to... The net is evenly distributed across both sides of the chip, and the net planning result z is solved.e This yielded a network planning result optimized for congestion in a double-sided chip design.

[0025] Step 3: Design a standard element selection function based on network planning to achieve network planning-driven standard element selection. After obtaining the results of the net layout in step two, this step will determine the final standard cell selection based on the net layout results. The main goal is to make the pins of the standard cell conform as closely as possible to the net layout results to which the pins are connected. .

[0026] This step designs two standard element selection functions based on wire network planning (initialization standard element selection function and iterative standard element selection function), and uses the following two steps to determine the final standard element selection.

[0027] The first step is to design and utilize the initialization standard cell selection function to obtain the initial selection results of the standard cells; The corresponding initialization standard unit selection function is defined as follows: In this step, WL(e) is the half-circumference wire length HPWL of each wire mesh, and this value cannot be negative. This refers to the set of different standard element selections corresponding to the standard element v in the standard element library in the netlist. It is the set of all wire nets in the netlist that are connected to the input pins of the standard cell v. The pin selection on the standard unit (v,e) The pin position (front or back) should be considered in different scenarios. In the standard cell selection initialization function, the pin position should be optimized as much as possible. and network planning variables same. Based on the initial selection result of standard cell v, an initial type is selected for all standard cells. Therefore, all standard cell pins also obtain corresponding positions, which can be denoted as... It is used for iterative standard unit selection.

[0028] The second step is to design and utilize an iterative standard element selection function to obtain the standard element selection optimization results.

[0029] The corresponding iterative standard unit selection function is defined as follows: Based on the pin positions of the initial selection results The results will still contain double-sided meshes. Therefore, this step continues with iterative selection of standard elements to further optimize the line length. It is the increment of the bus length DWL(e) of the net when a pin (v,e) of the net changes position (from the front to the back, or from the back to the front). (A positive value indicates that changing the pin position is a bad choice, and a negative value indicates that it is a good choice.) It is the initial position of pin (v,e) in the k-th round. This represents the optimization result of the standard cell v in the k-th round. The iterative standard cell selection function requires that the standard cell selection in the k-th round minimizes the function value. Here, the k-th round represents any round in the iterative standard cell selection process. During the selection process, the increment of the pin (v,e) of the standard cell selection in the k-th round corresponds to the length of the wire bus. When positive, the initial position of the pin should be as similar as possible to that of the pin in the k-th round; while... When the value is negative, it should be as opposite as possible to the initial pin position of the k-th round. Therefore, the iterative standard cell selection function can be used to further optimize the bus length of the design based on the specific pin positions (front or back) of the double-sided net. When the optimized bus length of two adjacent rounds is less than a small constant (e.g., 1x10), the optimization can be further optimized. -3 If the condition is met, the iterative optimization process will be terminated.

[0030] This invention determines the pin positions through standard cell selection, reducing wire length and congestion during the subsequent signal transfer cell (STC) insertion and wiring stage. This method is applicable to different congestion estimation models and wire length estimation models.

[0031] It should be noted that the purpose of disclosing the embodiments is to help further understand the present invention. However, those skilled in the art will understand that various substitutions and modifications are possible without departing from the scope of the present invention and the appended claims. Therefore, the present invention should not be limited to the content disclosed in the embodiments, and the scope of protection of the present invention is defined by the scope of the claims.

Claims

1. A standard cell selection method based on dual-face transistor-based congestion line length simultaneous awareness, characterized by, The optimization modeling is performed for the standard cell selection with double-sided input pins, the optimization target includes the line length and congestion index, and the optimization variable is the standard cell selection; the line net planning variable is introduced to construct an approximate optimization model, and the line net planning and the standard cell selection driven by the line net planning are used for solving; the steps include: Step one, the optimization modeling is performed for the standard cell selection of the double-sided transistor chip with double-sided input pins; Step two, the line net planning variable is introduced to construct an approximate optimization model and solve, the line net planning variable for the congestion optimization is obtained, and the line net planning result for the congestion optimization of the double-sided chip design is further obtained; The optimization target includes the line length and congestion index, and the optimization degree of the line length and congestion is controlled through the objective function and constraint; The optimization variable is the standard cell selection; Sort the grid points according to the total congestion value when not allocated, and execute in turn; for each grid point, according to the actual congestion value of each line network e at different grid points Uniformly allocate the line network to the two sides of the chip, and solve the line network planning variable z e , to obtain the line network planning result optimized for the congestion condition of the double-sided chip design; the subscript is the grid point coordinate, representing the grid point; Step three, the initialization and iterative standard cell selection function based on the line net planning is designed to realize the standard cell selection driven by the line net planning: The initialization standard cell selection function is used to make the pin position of the standard cell same as the line net planning variable under a certain selection; the initial selection result of the standard cell is obtained through the initialization standard cell selection function; The iterative standard cell selection function is used to further optimize the line length by using the pin position of the double-sided line net, and the standard cell selection optimization result is obtained; the iterative standard cell selection function requires that when the increment of the total line length of the line net is positive, the pin selected in the kth round is the same as the initial position of the pin in the kth round; when the increment of the total line length of the line net is negative, the pin selected in the kth round is opposite to the initial position of the pin in the kth round.

2. The standard cell selection method based on dual-face transistor for simultaneous congestion and wire length awareness as claimed in claim 1, wherein, In step one, the double-sided transistor chip is divided into multiple grid points according to the grid mode, each grid point records the congestion of the front and back of the chip line net, and the total line length of the front and back line net of the double-sided transistor chip standard cell selection is counted.

3. The standard cell selection method based on dual-face transistor for simultaneous congestion and wire length awareness as claimed in claim 1, wherein, In step two, the objective function and constraint of the approximate optimization model are expressed as: where, is the set of all standard cell type selection variables; is the worst congestion case, represents the total wire length of the front and back of each wire net e, and are the optimization degree parameters for controlling congestion and wire length, respectively; is the set of wire nets; is the actual congestion value of wire net e at different grid points; subscript represents the grid point; z e is the wire net planning variable; refers to the total width of the chip layout, refers to the total height of the chip layout.

4. The standard cell selection method based on dual-face transistor for simultaneous congestion and wire length awareness as claimed in claim 3, wherein, In step three, the initialization standard cell selection function is defined as: Where WL(e) is the half-circumference length of each wire mesh; This refers to the set of different standard element selections corresponding to the standard element v in the netlist in the standard element library; It is the collection of all nets in the netlist that are connected to the input pins of the standard cell v; The pins on the standard unit (v,e) are selected as The pin location in the following case; This represents the initial selection result for the standard unit v.

5. The standard cell selection method based on dual-face transistor for simultaneous congestion and wire length awareness as claimed in claim 4, wherein, The corresponding iterative standard cell selection function is defined as: wherein, is the increment of the total wire length DWL(e) of the wire net after a pin (v, e) changes its position; is the initial position of the pin (v, e) in the kth round, is the selection optimization result of the standard cell v in the kth round.

6. The standard cell selection method based on dual-face transistor for simultaneous congestion and wire length awareness as claimed in claim 5, wherein, When the total bus length optimization for two adjacent passes is less than 1x10 -3 the optimization process of the iterative standard cell selection is aborted.

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