Control system and control method for brake controller of unmanned aerial vehicle

Abstract

The invention relates to the technical field of safety devices, in particular to an unmanned aerial vehicle brake controller control system and control method.The control system is characterized in that a first processing unit and an external host form a communication channel through a first transceiving unit, and a second processing unit and the host form another communication channel through a second transceiving unit; the two communication channels work at the same time, and the first processing unit and the second processing unit can communicate with a host; the authorization management unit is respectively connected with each processing unit through a special interface; each processing unit is used for monitoring the braking state of the unmanned aerial vehicle in real time; the first processing unit and the second processing unit correctly receive instructions and attached data sent by the host and then independently communicate with the authorization management unit through the special interface, and the processing unit which correctly transmits the instructions and the attached data to the authorization management unit and uniquely obtains authorization sends reply information to the host. According to the method, the high-reliability fault-tolerant capability can be provided while the braking response real-time performance is ensured.

Description

Technical Field

[0001] This invention relates to the field of safety device technology, specifically to a control system and control method for a drone brake controller. Background Technology

[0002] With the booming development of the drone industry, the reliability requirements for drone brake controllers are becoming increasingly stringent to ensure flight safety. Currently, more and more drone brake controllers are using bus control. To improve reliability, redundancy design and related control methods have become crucial. Common redundancy solutions include cold backup and hot backup, but both of these solutions have certain shortcomings.

[0003] In cold backup solutions, typically only one system is operational by default, while the other remains idle as a backup after power failure. The backup system is only activated when the operational system malfunctions. However, this approach has significant drawbacks during the switchover process. Since the backup system requires time to boot up and become fully operational after a power outage, brief communication interruptions can occur during this period. For drone braking control, which demands extremely high real-time performance, even a brief communication interruption can prevent braking commands from being transmitted in a timely manner, affecting braking effectiveness and potentially causing safety accidents. Furthermore, the monitoring mechanisms in cold backup solutions are often quite limited, typically monitoring only certain aspects of critical components. If other components, such as bus transceivers or communication interfaces, malfunction, preventing the operational system from receiving or executing host commands, the system may not detect this in time to trigger redundancy switching. This significantly diminishes the effectiveness of the redundancy design and fails to effectively guarantee the reliability of the braking control system.

[0004] In the hot backup scheme, both the default and backup communication links remain powered on. The host first attempts to send commands through the default link and waits for a response. If the default link fails, causing a timeout or receiving fault feedback, it then switches to the backup link. While this scheme addresses the issue of limited monitoring range in cold backup schemes, which hinders timely switching and enhances system redundancy, the redundancy switching process is cumbersome. The host must first go through a series of steps, including sending commands through the default link, waiting for a response, and fault diagnosis, before switching to the backup link. This entire switching process is time-consuming. In scenarios like UAV braking control, where response speed is extremely critical, the long switching time may not meet the demands of rapid braking, increasing flight risks. Further optimization and improvement are still possible. Summary of the Invention

[0005] The purpose of this invention is to provide a control system and method for a drone brake controller in order to solve at least one of the above-mentioned technical problems, thereby solving the problems of short-term communication interruption and weak redundancy in the cold backup scheme of the drone brake controller, as well as the problem of long redundancy switching time in the traditional hot backup scheme.

[0006] The present invention achieves the above objectives through the following technical solutions: A drone braking controller control system includes: a first transceiver unit, a second transceiver unit, a first processing unit, a second processing unit, and an authorization management unit; The first processing unit forms a communication channel with an external host through the first transceiver unit, and the second processing unit forms another communication channel with the host through the second transceiver unit; the two communication channels work simultaneously, and both the first processing unit and the second processing unit can communicate with the host. The authorization management unit is connected to the first processing unit and the second processing unit through dedicated interfaces, respectively. The first processing unit and the second processing unit are used to monitor the braking status of the drone in real time; After the first processing unit and the second processing unit correctly receive the instructions and accompanying data issued by the host, they communicate independently with the authorization management unit through a dedicated interface. The processing unit that correctly transmits the instructions and accompanying data to the authorization management unit and is the only one authorized sends a reply message to the host.

[0007] Furthermore, the first processing unit and the second processing unit are connected to the host via a bus; The authorization management unit includes a first SPI interface and a second SPI interface. The first SPI interface is used to connect to the first processing unit, and the second SPI interface is used to connect to the second processing unit.

[0008] Furthermore, the first processing unit and the second processing unit are microcontrollers; the authorization management unit uses a complex programmable logic device with higher reliability than a microcontroller.

[0009] Furthermore, the authorization management unit is configured with a dedicated interface for each processing unit, and a corresponding independent buffer is set.

[0010] A method for controlling a drone brake controller, employing any of the above-described drone brake controller control systems, the control method comprising: The target processing unit sends or forwards verified instructions and data to the authorization management unit and reads the response result from the authorization management unit; wherein, the target processing unit is either a first processing unit or a second processing unit that correctly receives instructions and data sent by the host; both the first processing unit and the second processing unit can receive instructions and data sent by the host; If the target processing unit receives a correct response, it requests authorization from the authorization management unit through the corresponding interface and reads the authorization result; if the target processing unit does not receive a correct response, it terminates the current response. If the target processing unit is authorized, it sends a reply to the host within a preset authorized time; if the target processing unit is not authorized, it terminates the response.

[0011] Furthermore, the authorization management unit responds to the processing unit that correctly transmits instructions and data.

[0012] Furthermore, the authorization management unit issues authorization to the processing unit that has transmitted the correct instructions and data and is the first to apply for authorization. The authorization management unit issues authorization to at most one processing unit at any given time.

[0013] Furthermore, after issuing authorization, the authorization management unit accepts instructions and data transmitted by the authorized processing unit for output control.

[0014] Furthermore, the preset authorization time is less than the time interval between two adjacent instructions from the host.

[0015] Furthermore, the control method also includes: when the authorization management unit issues authorization to the target processing unit, closing the authorization application of another authorization unit within a preset authorization time; When the authorization time for the target processing unit reaches the preset authorization time, the authorization for the target processing unit is revoked, and the authorization management unit reopens the authorization application.

[0016] Furthermore, the response information sent to the host includes: brake pressure, wheel speed, working status, and command execution status.

[0017] An electronic device includes a processor, a memory, and a processor program stored in the memory and executable on the processor, wherein the processor program, when executed by the processor, implements the unmanned aerial vehicle (UAV) braking controller control method as described above.

[0018] The beneficial effects of this invention are as follows: This invention employs an improved hot-backup redundancy scheme to construct a dual communication link system. When any component, such as the bus transceiver, microcontroller, or SPI interface, malfunctions, the system can automatically and seamlessly switch over—the functional communication link quickly responds to the host command, and the faster-responding microcontroller completes the subsequent processing and feeds back the results via the bus. This design not only completely avoids the communication interruption problem caused by switching in traditional redundant architectures but also eliminates the additional time loss caused by redundant switching. Through the dual-link parallel working mechanism, the system can maintain continuous operation under any single point of failure, providing dual protection for UAV flight safety. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of the structure of a drone braking controller control system according to one embodiment of the present invention; Figure 2 This is a schematic diagram of the control system principle of a drone braking controller according to one embodiment of the present invention; Figure 3 This is a flowchart of a UAV braking controller control method according to one embodiment of the present invention; Figure 4 This is a flowchart of a drone braking controller control method according to another embodiment of the present invention. Detailed Implementation

[0020] The invention will now be discussed with reference to exemplary embodiments. It should be understood that the described embodiments are merely intended to enable those skilled in the art to better understand and thus implement the invention, and are not intended to imply any limitation on the scope of the invention.

[0021] As used herein, the term "comprising" and its variations are to be interpreted as open-ended terms meaning "including but not limited to". The term "based on" is to be interpreted as "at least partially based on". The terms "one embodiment" and "an embodiment" are to be interpreted as "at least one embodiment".

[0022] Example 1 Figure 1 This is a schematic diagram of the control system structure of a drone braking controller according to one embodiment of the present invention. Figure 1 As shown, according to one embodiment of the present invention, a drone braking controller control system includes: a first transceiver unit, a second transceiver unit, a first processing unit, a second processing unit, and an authorization management unit. The first processing unit forms a communication channel with the external host through the first transceiver unit, and the second processing unit forms another communication channel with the host through the second transceiver unit; the two communication channels work simultaneously, and both the first processing unit and the second processing unit can communicate with the host. The authorization management unit is connected to the first processing unit and the second processing unit through dedicated interfaces, respectively. The first and second processing units are used to monitor the braking status of the drone in real time (including but not limited to braking pressure and wheel speed). After the first processing unit and the second processing unit correctly receive the instructions and accompanying data from the host, they communicate independently with the authorization management unit through a dedicated interface. The processing unit that correctly transmits the instructions and accompanying data to the authorization management unit and is the only one authorized sends a reply message to the host.

[0023] In this embodiment, the UAV braking controller control system adopts a dual communication link structure: the first communication link consists of the host, the first transceiver unit, the first processing unit, and the authorization management unit; the second communication link consists of the host, the second transceiver unit, the second processing unit, and the authorization management unit. Both communication links are always powered on and listen in parallel. A braking command broadcast by the host is simultaneously received by both communication links. After the two processing units complete their verification, they submit the "command" and "parameters attached to the command," such as the "braking command" and the "braking PWM duty cycle," to the authorization management unit. The authorization management unit is implemented using a CPLD (Complex Programmable Logic Device). Internally, it sets up an independent receive buffer for each SPI interface, performs data integrity verification first, and then sends back an ACK. The receiving party immediately requests authorization. The authorization management unit locks the authorization flag on a "first-come, first-served" basis and, within a preset authorization window, only converts the data in that buffer into PWM or digital level output to the braking actuator, while simultaneously blocking authorization requests from the other side, ensuring that only one control signal is active at any given time. After the authorization window ends, the flag is automatically released, and the dual links re-enter a contention state. If any transceiver unit, processing unit, or SPI interface fails, the faulty side will automatically go silent because it cannot pass the verification or obtain authorization, and the healthy side will seamlessly take over, realizing redundancy switching; the output stage signal type (PWM duty cycle, high and low level) is executed and output by the authorization management unit according to the instruction, thereby providing highly reliable fault tolerance capability while ensuring the real-time braking response.

[0024] This invention adopts a "dual hot chain + authorized arbitration" architecture, which can ensure that only one control signal is effective at any given time, realize automatic silencing on the fault side and seamless takeover and redundant switching on the healthy side, and provide high reliability fault tolerance while ensuring real-time braking response.

[0025] According to one embodiment of the present invention, the first processing unit and the second processing unit are connected to the host via a bus; The authorization management unit includes a first SPI interface and a second SPI interface. The first SPI interface is used to connect to the first processing unit, and the second SPI interface is used to connect to the second processing unit.

[0026] In this embodiment, a "shared bus + dual independent SPI" structure is adopted: the first and second transceiver units are connected in parallel on the same bus; after the instruction issued by the host is received by both transceiver units simultaneously, each is sent to its corresponding processing unit. After the two processing units independently complete the verification, they submit the "instruction" and "instruction parameters" to the authorization management unit through independent first and second SPI interfaces, respectively. The authorization management unit sets up an independent receive buffer for each SPI interface, performs verification first, and then sends back ACK; any processing unit that receives ACK immediately requests authorization, and the authorization management unit only issues authorization to the processing unit that has transmitted the correct instruction data and first requested authorization; finally, the only authorized processing unit encapsulates the data on that side (including brake pressure, wheel speed, working status, and instruction execution flag) in the authorization window and sends it back to the host through the same shared bus; the authorization request of the other processing unit is automatically blocked, and it automatically exits the current processing process, thereby avoiding packet conflicts. If any link fails, the faulty side will automatically terminate the packet return due to verification failure or failure to receive ACK, while the healthy side will still respond normally through the shared bus, realizing "single bus dual redundancy" brake control.

[0027] The present invention uses a shared bus structure, in which the healthy side seamlessly takes over when any communication link fails, achieving "single bus dual redundancy" braking control.

[0028] According to one embodiment of the present invention, the first processing unit and the second processing unit adopt a microcontroller (also known as a microprocessor, microcontroller, MCU); the authorization management unit adopts a complex programmable logic device with higher reliability than a microcontroller.

[0029] Preferably, the authorization management unit is configured with a dedicated interface for each processing unit, and a corresponding independent buffer is set.

[0030] In this embodiment, the first and second processing units are microcontrollers, responsible for collecting UAV status monitoring signals such as brake pressure and wheel speed. The authorization management unit uses a more reliable CPLD, which internally provides independent receive buffers for two SPI interfaces, physically isolated for storage. The CPLD can clear the receive buffers of SPI interface A and SPI interface B at appropriate times. For example, when the authorization management unit has received instructions and data from a certain SPI interface, but has not received an authorization request or new instructions and data from that SPI interface for a certain period of time, it can clear that SPI receive buffer.

[0031] This invention uses a microcontroller as the processing unit to collect data and verify instructions, uses a high-reliability CPLD as the authorization management unit and sets up an independent receiving buffer, and has strong redundancy capabilities, resulting in high reliability of braking control.

[0032] As an alternative to this embodiment, during the interaction between the processing unit and the authorization management unit, other communication methods are used, such as: The first processing unit and the second processing unit send a communication test command to the authorization management unit and obtain a response signal from the authorization management unit; if no correct response is received, the response is terminated; if a correct response is received, a formal command and accompanying data are sent, and the authorization result is read; if no authorization is received, the response is terminated; if authorization is received, a reply message is sent to the host; the authorization management unit responds to the communication test command and authorizes the processing unit that first transmits the correct formal command and accompanying data, and other details are consistent with the existing embodiments.

[0033] Example 2 Figure 2 This is a schematic diagram illustrating the principle of a drone braking controller control system according to one embodiment of the present invention. Figure 2 As shown, according to one embodiment of the present invention, a UAV braking controller control system adopts an improved hot backup scheme, that is, all unit modules are in a powered-on state; ignoring internal power supply, the control system mainly consists of bus transceiver A, bus transceiver B, microcontroller A, microcontroller B, and an authorization management unit. Wherein: In addition to performing authorization management functions, the authorization management unit is also the final signal output unit. The host is an external device that controls the UAV's brake controller.

[0034] The authorization management unit connects to microcontroller A and microcontroller B via two independent SPI interfaces: SPI interface A connects to microcontroller A, and SPI interface B connects to microcontroller B. Microcontroller A connects to bus transceiver A, enabling bus communication between microcontroller A and the external host. Microcontroller B connects to bus transceiver B, enabling bus communication between microcontroller B and the external host. The bus interfaces of bus transceivers A and B are connected in parallel, allowing commands issued by the host to be received by both microcontrollers A and B simultaneously. This enables microcontrollers A and B to send commands and data to the authorization management unit and read responses, as well as to request authorization from the authorization management unit and read authorization results.

[0035] After the UAV braking controller is connected to the host via the bus, two communication links are formed: Communication Link A (host – bus transceiver A – microcontroller A – SPI interface A – authorization management unit) and Communication Link B (host – bus transceiver B – microcontroller B – SPI interface B – authorization management unit).

[0036] Under normal conditions, commands issued by the host can be simultaneously received by microcontrollers A and B. After receiving the command, both microcontrollers A and B send the command and data with verification to the authorization management unit and read the response. If a correct response is received, they then request authorization from the authorization management unit; if a correct response is not received, the corresponding microcontroller terminates the response directly.

[0037] The authorization management unit receives verification instructions and data from two microcontrollers. When the verification of the instructions and data is correct, it responds to the corresponding microcontroller (the two microcontrollers respond independently). The authorization management unit opens authorization requests by default. When the authorization management unit receives an authorization request from any microcontroller, after confirming that the instructions and data are correct, it issues an authorization to that microcontroller and accepts the content transmitted by it for output. At the same time, it closes the authorization request of the other microcontroller within a limited time (referred to as the authorization time in this invention).

[0038] Finally, the sole authorized microcontroller completes the subsequent processing within the authorized time and replies to the host via the bus. Unauthorized microcontrollers immediately terminate their response. After the authorized time expires, any existing authorizations are automatically revoked, and the authorization management unit reopens authorization requests.

[0039] Example 3 Figure 3 This is a flowchart of a drone braking controller control method according to one embodiment of the present invention. Figure 3 As shown, according to one embodiment of the present invention, a drone brake controller control method is provided, employing any drone brake controller control system of the present invention. The control method includes: In step S102, the target processing unit sends or forwards the verified instructions and data to the authorization management unit and reads the response result from the authorization management unit; wherein, the target processing unit is either the first processing unit or the second processing unit that correctly receives the instructions and data sent by the host; both the first processing unit and the second processing unit can receive the instructions and data sent by the host. Step S104: If the target processing unit receives a correct response, the target processing unit requests authorization from the authorization management unit through the corresponding interface and reads the authorization result; if the target processing unit does not receive a correct response, the target processing unit terminates this response. Step S106: If the target processing unit is authorized, it sends a reply message to the host within a preset authorization time; if the target processing unit is not authorized, it terminates the response.

[0040] Preferably, the authorization management unit responds to the processing unit that correctly transmits instructions and data.

[0041] Preferably, the authorization management unit issues authorization to the processing unit that has transmitted the correct instructions and data and is the first to apply for authorization. The authorization management unit issues authorization to at most one processing unit at any given time.

[0042] Preferably, the response information sent to the host includes: brake pressure, wheel speed, working status, and command execution status.

[0043] This embodiment proposes a control method for a UAV braking controller, which is based on "parallel reception, contention for authorization, and single-path activation": All units are powered on and operational. After the host broadcasts a command on the shared bus, the first and second processing units simultaneously receive the command and add their own verifications. They then send the command and its accompanying parameters to the authorization management unit via independent SPI interfaces. The authorization management unit allocates an independent buffer for each SPI path, completes verification, and sends back an ACK. The processing unit receiving the ACK sends an authorization request to the authorization management unit. The authorization management unit locks a unique authorization on a "first-come, first-served" basis, issues the authorization to the processing unit, loads the buffer instructions and data to make it effective, starts an authorization timer, and closes the authorization request of another processing unit within the authorization time. If any link verification fails, the authorization request lags behind, or the authorization timer expires, the corresponding processing unit forcibly terminates its response via hardware. After issuing the authorization, the authorization management unit accepts the instructions and data transmitted by the authorized processing unit for output control, such as braking control. The only authorized microcontroller sends the following response information to the host: brake pressure, wheel speed, working status, and instruction execution status. The host receives the complete response information before the next instruction cycle.

[0044] This invention achieves hot backup braking control through a "parallel reception, contention for authorization, and single-path activation" mechanism.

[0045] According to one embodiment of the present invention, the preset authorization time is less than the time interval between two adjacent instructions from the host.

[0046] Preferably, the control method further includes: when the authorization management unit issues authorization to the target processing unit, closing the authorization application of another authorization unit within a preset authorization time; When the authorization time for the current target processing unit reaches the preset authorization time, the authorization for the target processing unit is revoked, and the authorization management unit reopens the authorization application.

[0047] In this embodiment, the "preset authorization time" is rigidly constrained to be less than the time interval between two adjacent instructions from the host: once the authorization management unit grants authorization to a processing unit, it immediately starts a countdown; once the countdown ends, the authorization is automatically released and competition is reopened. Because the authorization time is less than the instruction interval, it can be ensured that the authorized processing unit can complete its subsequent processing work within this time and reply to the host via the bus.

[0048] This invention eliminates dual-unit drive conflicts by closing the application on the other side during authorization; it sets the preset authorization time to be less than the interval between adjacent instructions from the host to prevent abnormal access by the processing unit and ensure that the authorized processing unit can complete subsequent processing work within this time and reply to the host via the bus.

[0049] Example 4 Figure 4 This is a flowchart of a drone braking controller control method according to another embodiment of the present invention. Figure 4 As shown, according to one embodiment of the present invention, a drone brake controller control method is provided, employing any drone brake controller control system of the present invention; the control method includes the following steps: Microcontroller A and microcontroller B continuously monitor brake pressure and wheel speed signals.

[0050] When microcontroller A receives a command from the host: Microcontroller A sends a verification command and accompanying data (such as the control of PWM output duty cycle, output level status, or virtual command for host query) to the authorization management unit via SPI interface A, and reads the response from the authorization management unit; if the response is incorrect, the response ends directly; if the response is correct, microcontroller A continues to request authorization from the authorization management unit via SPI interface A and reads the authorization result; if authorization acquisition fails, the response ends directly; if authorization is successfully acquired, microcontroller A needs to complete the subsequent processing within the authorized time and reply to the host via the bus (the reply may include brake pressure, wheel speed, working status, command execution status, etc.).

[0051] When microcontroller B receives an instruction from the host, it executes the same process as microcontroller A.

[0052] The authorization management unit employs devices with higher reliability than microcontrollers (such as CPLDs—Complex Programmable Logic Devices). Specifically, it includes: designing independent SPI modules for SPI interfaces A and B, each with its own independent receive buffer, initially containing invalid data; when the authorization management unit receives instructions and data from microcontroller A via SPI interface A and passes verification, it responds to microcontroller A through SPI interface A; when the authorization management unit receives instructions and data from microcontroller B via SPI interface B and passes verification, it responds to microcontroller B through SPI interface B; the authorization management unit defaults to opening authorization requests. When the authorization management unit receives an authorization request from any microcontroller (microcontroller A or microcontroller B), and the instructions and data in the corresponding SPI receive buffer pass verification, it issues authorization to the requesting microcontroller and loads the corresponding buffer instructions and data to make it effective. Simultaneously, it starts an authorization timer and closes the authorization request from another microcontroller within the authorization time; when the authorization timer expires, the generated authorization is automatically released, and the authorization management unit reopens authorization requests; at any given time, the authorization management unit issues authorization to at most one microcontroller.

[0053] The authorization time should be shorter than the interval between the host sending instructions, and it should be able to ensure that the authorized microcontroller can complete the subsequent processing work within this time and reply to the host through the bus. When the authorization management unit receives authorization requests from two microcontrollers at the same time, and the instructions and data in the two SPI receive buffers can pass the verification, only one microcontroller can be designated to successfully obtain authorization. This can be done according to priority or randomly.

[0054] Preferably, to avoid receiving authorization requests from two microcontrollers simultaneously, a small delay can be added during the response process of any microcontroller receiving the instruction. This will ensure that there is a clear order in which the two microcontrollers request authorization from the authorization management unit, thus clarifying the primary and backup priorities of the two microcontrollers in their responses, which will facilitate product testing and operational status analysis.

[0055] To improve reliability, the authorization management unit may clear the receive buffers of SPI interface A and SPI interface B when appropriate. For example, when the authorization management unit has received instructions and data from a certain SPI interface, but has not received an authorization request or new instructions and data from that SPI interface for a certain period of time, the SPI receive buffer may be cleared.

[0056] The UAV brake controller control system of this invention has strong redundancy capabilities: If bus transceiver A malfunctions, or microcontroller A malfunctions while all other components function normally, microcontroller A will be unable to receive or execute instructions from the host, nor will it request authorization from the authorization management unit. However, instructions can still be delivered to the authorization management unit via communication link B, and the authorization management unit will authorize microcontroller B to complete subsequent processing and reply to the host via the bus.

[0057] If SPI interface A malfunctions (including transmission and reception errors), while other interfaces function normally, microcontroller A, upon receiving an instruction, will send a verified instruction and data to the authorization management unit via SPI interface A. However, it will not receive a correct response from the authorization management unit and will automatically terminate the current response, ceasing further authorization requests. Nevertheless, the instruction can still be delivered to the authorization management unit via communication link B, and the authorization management unit will authorize microcontroller B to complete subsequent processing and reply to the host via the bus.

[0058] Similarly, if one or more of the components in communication link B, such as bus transceiver B, microcontroller B, or SPI interface B, malfunction while the others function normally, the same redundancy effect can be achieved.

[0059] This invention employs an improved hot backup redundancy scheme, which transmits commands issued by the host through two communication links. The microcontroller in the functional and fast-responding communication link performs subsequent processing and replies to the host via the bus. This avoids communication interruptions during redundancy switching and the additional time consumption of redundancy switching, while possessing strong redundancy capabilities to ensure the reliability of braking control.

[0060] Example 5 According to one embodiment of the present invention, an electronic device includes a processor, a memory, and a processor program stored in the memory and executable on the processor. When the processor program is executed by the processor, it implements any of the UAV brake controller control methods of the present invention.

[0061] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working process of the device described above can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0062] The above description is merely a preferred embodiment of this application and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of the invention involved in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the inventive concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features with similar functions disclosed in this application.

[0063] It should be understood that the sequence number of each step in the invention and embodiments of the present invention does not absolutely imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

Claims

1. A drone brake controller control system, characterized in that, include: First transceiver unit, second transceiver unit, first processing unit, second processing unit, authorization management unit; The first processing unit forms a communication channel with an external host through the first transceiver unit, and the second processing unit forms another communication channel with the host through the second transceiver unit; the two communication channels work simultaneously, and both the first processing unit and the second processing unit can communicate with the host. The authorization management unit is connected to the first processing unit and the second processing unit through dedicated interfaces, respectively. The first processing unit and the second processing unit are used to monitor the braking status of the drone in real time; After the first processing unit and the second processing unit correctly receive the instructions and accompanying data issued by the host, they communicate independently with the authorization management unit through a dedicated interface. The processing unit that correctly transmits the instructions and accompanying data to the authorization management unit and is the only one authorized sends a reply message to the host.

2. The UAV brake controller control system of claim 1, wherein: The first processing unit and the second processing unit are connected to the host via a bus; The authorization management unit includes a first SPI interface and a second SPI interface. The first SPI interface is used to connect to the first processing unit, and the second SPI interface is used to connect to the second processing unit.

3. The UAV brake controller control system of claim 1, wherein: The first processing unit and the second processing unit are microcontrollers; the authorization management unit uses a complex programmable logic device with higher reliability than a microcontroller.

4. The UAV brake controller control system of claim 3, wherein: The authorization management unit is configured with a dedicated interface for each processing unit, and a corresponding independent buffer is set.

5. A method for controlling a UAV brake controller, using the UAV brake controller control system according to any one of claims 1-4, characterized in that, The control method includes: The target processing unit sends or forwards verified instructions and data to the authorization management unit and reads the response result from the authorization management unit; wherein, the target processing unit is either a first processing unit or a second processing unit that correctly receives instructions and data sent by the host; both the first processing unit and the second processing unit can receive instructions and data sent by the host; If the target processing unit receives a correct response, it requests authorization from the authorization management unit through the corresponding interface and reads the authorization result; if the target processing unit does not receive a correct response, it terminates the current response. If the target processing unit is authorized, it sends a reply to the host within a preset authorized time; if the target processing unit is not authorized, it terminates the response.

6. The method of claim 5, wherein: The authorization management unit responds to the processing unit that correctly transmits instructions and data.

7. The method of claim 5, wherein: The authorization management unit issues authorization to the processing unit that has transmitted the correct instructions and data and is the first to apply for authorization. The authorization management unit issues authorization to at most one processing unit at any given time.

8. The method of claim 5, wherein: After issuing authorization, the authorization management unit receives instructions and data transmitted by the authorized processing unit for output control.

9. The method of claim 5, wherein: The preset authorization time is less than the time interval between two adjacent instructions from the host.

10. The method of claim 5, wherein, The control method further comprises: when the authorization management unit issues an authorization to a target processing unit, closing the authorization application of another authorization unit within a preset authorization time; When the authorization time for the current target processing unit reaches the preset authorization time, the authorization of the target processing unit is released, and the authorization application is reopened by the authorization management unit.

11. The method of claim 5, wherein, The reply information sent to the host computer includes brake pressure, wheel speed, working state, and instruction execution status.

12. An electronic device, comprising: The unmanned aerial vehicle brake controller comprises a processor, a memory, and a processor program stored on the memory and executable on the processor, and the processor program is executed by the processor to realize the control method of the unmanned aerial vehicle brake controller according to claim 5.

Images