Protection circuit, integrated circuit and protection method
By designing a protection circuit and utilizing a clock output module and an encoding judgment unit, the safety of the chip calibration process is ensured, the chip abnormality problem caused by misoperation of calibration pins is solved, and the stability and reliability of chip calibration are achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-30
- Publication Date
- 2026-03-27
AI Technical Summary
During chip calibration, human error in receiving an unexpected clock signal on the calibration pin may cause the calibration bit state to be incorrectly rewritten, leading to chip malfunction or failure to operate normally.
Design a protection circuit, including a clock output module, a calibration protection module, and a calibration storage module. By generating a fixed reference waveform and an encoding judgment mechanism, ensure that chip calibration is only initiated when a preset encoded signal is received, thus preventing misoperation.
This effectively prevents the chip from entering calibration mode due to misoperation, improves the stability and reliability of chip calibration, and ensures the chip works normally.
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Figure CN121742591A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of electronic circuits, and in particular to a protection circuit, an integrated circuit, and a protection method. BACKGROUND
[0002] With the evolution of semiconductor technology to deep sub-micron and nanometer level, transistor size is continuously shrinking, and process fluctuations have a more significant impact on chip performance. For example, the frequency deviation of an RC oscillator can exceed ±20%, and the offset voltage of an ADC (Analog-to-Digital Converter) can cause a decrease in signal acquisition accuracy. Chip calibration (Trim) technology, which precisely adjusts circuit parameters, controls deviations within an acceptable range, is an indispensable part of the chip production process. Chip calibration ultimately affects the normal operation of the chip. If the calibration pin of the chip receives an unexpected clock signal due to human error during chip calibration, the state of the calibration bit may be incorrectly rewritten, ultimately causing the chip to malfunction or even enter an inoperable state. Therefore, there is an urgent need for a protection circuit, an integrated circuit, and a protection method to protect the chip calibration process. SUMMARY
[0003] To solve the problems involved in the background art, the present application provides the following technical solutions:
[0004] In a first aspect, a protection circuit is provided, comprising: a clock output module, a calibration protection module, and a calibration storage module.
[0005] The clock output module is connected to the calibration protection module, and the calibration protection module is connected to the calibration storage module.
[0006] The clock output module is configured to provide a clock signal of a preset frequency to the calibration protection module.
[0007] The calibration protection module is configured to receive an encoded signal and an encoded clock signal, wherein the encoded signal is used to start calibration of a subsequent circuit connected to the protection circuit at a preset encoding time, and the encoded clock signal is used to indicate a calibration bit of the subsequent circuit.
[0008] The calibration storage module is configured to store verification information.
[0009] Further, the clock output module has a signal output port.
[0010] The calibration protection module has a calibration protection first port, a calibration protection second port, and a calibration protection third port.
[0011] The calibration storage module has a calibration storage receiving port.
[0012] The signal output port is connected to the first calibration protection port, and the third calibration protection port is connected to the calibration storage receiving port.
[0013] The calibration protection port 1 is used to receive the clock signal generated by the clock output module.
[0014] The calibration protection port 2 is used to receive the encoded signal and the encoded clock signal.
[0015] Furthermore, the calibration protection module includes: a waveform generation unit, a clock division unit, an encoding judgment unit, and an output control unit.
[0016] The waveform generation unit has: a first waveform generation port, a second waveform generation port, and a third waveform generation port.
[0017] The clock divider unit has: a first clock divider port, a second clock divider port, a third clock divider port, a fourth clock divider port, a fifth clock divider port, and a sixth clock divider port.
[0018] The encoding judgment unit has: a first encoding judgment port, a second encoding judgment port, and a third encoding judgment port.
[0019] The output control unit has: an output control first port, an output control second port, an output control third port, an output control fourth port, and an output control fifth port.
[0020] The waveform generation port 1 is connected to the clock frequency divider port 3 and the output control port 3. The waveform generation port 2 is connected to the clock frequency divider port 4 and the output control port 1. The waveform generation port 3 is connected to the clock frequency divider port 2. The clock frequency divider port 1 serves as the calibration protection port 1. The clock frequency divider port 5 is connected to the output control port 2. The clock frequency divider port 6 is connected to the encoding judgment port 1. The encoding judgment port 2 serves as the calibration protection port 2. The encoding judgment port 3 is connected to the output control port 4. The output control port 5 serves as the calibration protection port 3.
[0021] Furthermore, the waveform generation unit includes a first inverter and a first XOR gate.
[0022] The input terminal of the first inverter serves as the first port for waveform generation. The output terminal of the first inverter is connected to one input terminal of the first XOR gate. The other input terminal of the first XOR gate serves as the second port for waveform generation. The output terminal of the first XOR gate serves as the third port for waveform generation.
[0023] Furthermore, the clock divider unit includes: a first flip-flop, a second flip-flop, and a third flip-flop.
[0024] The data input terminal of the first flip-flop serves as the second port for clock division. The clock input terminal of the first flip-flop is connected to the clock input terminals of the second and third flip-flops, which together serve as the first port for clock division. The truth output terminal of the first flip-flop is connected to the data input terminal of the second flip-flop, which together serve as the fourth port for clock division. The truth output terminal of the second flip-flop is connected to the data input terminal of the third flip-flop, which together serve as the fifth and sixth ports for clock division. The truth output terminal of the third flip-flop serves as the third port for clock division.
[0025] Furthermore, the first flip-flop, the second flip-flop, and the third flip-flop are D flip-flops.
[0026] Furthermore, the encoding judgment unit includes a second XOR gate and a second inverter.
[0027] One input of the second XOR gate serves as the first port for encoding judgment, and the other input of the second XOR gate serves as the second port for encoding judgment. The output of the second XOR gate is connected to the input of the second inverter, and the output of the second inverter serves as the third port for encoding judgment.
[0028] Furthermore, the output control unit includes: NOR gates and NAND gates.
[0029] One input of the NOR gate is used as the first output control port, the other input of the NOR gate is used as the second output control port, the output of the NOR gate is connected to one input of the NAND gate, the other input of the NAND gate is used as the third output control port, another input of the NAND gate is used as the fourth output control port, and the output of the NAND gate is used as the fifth output control port.
[0030] In a second aspect, an integrated circuit is provided, including the protection circuit described in the first aspect.
[0031] Thirdly, a protection method is provided, applied to the protection circuit described in the first aspect, comprising:
[0032] The second port of the protection circuit receives the encoded signal under calibration protection.
[0033] The clock signal output by the clock output module in the protection circuit is used to determine whether the encoded signal is the preset code.
[0034] If the encoded signal is a preset code, then the calibration of the downstream circuit connected to the protection circuit is initiated.
[0035] The coded clock signal is received by the calibration protection second port of the protection circuit, and the check bit for the subsequent circuit is determined according to the number of clock signals.
[0036] Obtain the verification information and adjust the verification bits accordingly.
[0037] By implementing the protection circuit, integrated circuit, and protection method described in the embodiments of this application, the calibration start behavior can be encrypted and coded before the chip is calibrated using a clock signal with a fixed number of cycles. When the coded signal conforms to the preset code, the chip calibration action is initiated, reducing the probability of the chip mistakenly entering the calibration mode; thus ensuring the stability and reliability of chip calibration. Attached Figure Description
[0038] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0039] Figure 1 This is a schematic diagram of a protection circuit module provided in an embodiment of this application;
[0040] Figure 2 This is a schematic diagram of the calibration protection module structure provided in an embodiment of this application;
[0041] Figure 3 This is a schematic diagram of the waveform generation unit circuit provided in an embodiment of this application;
[0042] Figure 4 This is a schematic diagram of the clock divider unit circuit provided in the embodiments of this application;
[0043] Figure 5 This is a schematic diagram of the encoding judgment unit circuit provided in an embodiment of this application;
[0044] Figure 6 This is a schematic diagram of the output control unit circuit provided in an embodiment of this application;
[0045] Figure 7 This is a schematic diagram of the calibration protection module circuit provided in an embodiment of this application;
[0046] Figure 8 This is a schematic diagram of encoding generation provided in an embodiment of this application;
[0047] Figure 9 This is a schematic diagram of the protection method provided in the embodiments of this application. Detailed Implementation
[0048] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.
[0049] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The numbers in the accompanying drawings are only used to distinguish individual functional parts or modules and do not indicate logical relationships between parts or modules. The terms “comprising,” “including,” or “including,” and similar terms mean that the element or object preceding the term encompasses the element or object listed following the term and its equivalents, without excluding other elements or objects. The terms “connected,” “linked,” and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. “Above,” “below,” “left,” “right,” etc., are used only to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.
[0050] The various embodiments according to this disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that in the drawings, the same reference numerals are assigned to components having substantially the same or similar structure and function, and repeated descriptions of them will be omitted.
[0051] Chip calibration technology involves precisely adjusting circuit parameters to control deviations within an acceptable range, ensuring the chip functions correctly. It is an indispensable step in chip mass production, greatly guaranteeing chip reliability. Based on the implementation logic and circuit structure, chip calibration can be implemented in three ways: digital calibration code-based, non-volatile memory-based, and analog feedback adjustment-based. Each method is suitable for different application scenarios and performance requirements.
[0052] Chip calibration circuits based on digital calibration codes generate binary calibration codes and adjust analog parameters by combining digital-to-analog converters or switching networks. They have dynamic adjustment capabilities and are suitable for scenarios that require multiple calibrations or real-time compensation.
[0053] The chip calibration circuit based on non-volatile memory can save the calibration code in a non-volatile manner through one-time or multiple programming. The calibration parameters are automatically loaded after the chip is powered on. It is suitable for scenarios that require permanent storage of calibration results or on-site calibration.
[0054] Chip calibration circuits based on analog feedback regulation do not require digital calibration codes. They dynamically adjust parameters through the feedback mechanism of analog circuits, resulting in fast response speeds and suitability for scenarios with high real-time requirements.
[0055] The embodiments described in this application pertain to a chip that receives a fixed number of clock signals via a calibration pin to perform calibration operations on a target calibration bit. Specifically, when the calibration pin detects a preset number of clock pulses (e.g., 3 clock signals), it can precisely trigger the corresponding calibration bit (the 3rd bit) to go high, thereby initiating the subsequent programming process. The core advantage of this method lies in its simple circuit structure and convenient operation, requiring no complex digital logic or external interface support; however, it also has significant limitations: if the calibration pin receives an unexpected clock signal due to human error, the calibration bit state may be incorrectly rewritten, ultimately causing the chip to malfunction or even enter a failure state where it cannot operate normally.
[0056] To address the issue of accidental initiation during chip calibration, this application provides the following technical solution:
[0057] In some embodiments, such as Figure 1 As shown, a protection circuit includes: a clock output module 100, a calibration protection module 200, and a calibration storage module 300.
[0058] The clock output module 100 is connected to the calibration protection module 200, and the calibration protection module 200 is connected to the calibration storage module 300.
[0059] The clock output module 100 is used to provide a clock signal of a preset frequency to the verification and protection module 200.
[0060] The calibration protection module 200 is used to receive the encoded signal and the encoded clock signal. When the encoded signal is a preset code, the calibration of the downstream circuit connected to the protection circuit is started. The encoded clock signal is used to indicate the calibration bit of the downstream circuit.
[0061] The calibration storage module 300 is used to store calibration information.
[0062] The clock output module 100 has a signal output port 100a.
[0063] The calibration protection module 200 has: a calibration protection first port 200a, a calibration protection second port 200b, and a calibration protection third port 200c.
[0064] The calibration storage module 300 has a calibration storage receiving port 300a.
[0065] Signal output port 100a is connected to calibration protection first port 200a, and calibration protection third port 200c is connected to calibration storage receiving port 300a.
[0066] The calibration protection first port 200a is used to receive the clock signal generated by the clock output module 100.
[0067] The calibration protection port 200b is used to receive the encoded signal and the encoded clock signal.
[0068] like Figure 2 As shown, the calibration protection module 200 includes: a waveform generation unit 210, a clock division unit 220, an encoding judgment unit 230, and an output control unit 240.
[0069] The waveform generation unit 210 has: a first waveform generation port 210a, a second waveform generation port 210b, and a third waveform generation port 210c.
[0070] The clock divider unit 220 has: a first clock divider port 220a, a second clock divider port 220b, a third clock divider port 220c, a fourth clock divider port 220d, a fifth clock divider port 220e, and a sixth clock divider port 220f.
[0071] The encoding judgment unit 230 has: a first encoding judgment port 230a, a second encoding judgment port 230b, and a third encoding judgment port 230c.
[0072] The output control unit 240 has: an output control first port 240a, an output control second port 240b, an output control third port 240c, an output control fourth port 240d, and an output control fifth port 240e.
[0073] The waveform generation first port 210a is connected to the clock frequency divider third port 220c and the output control third port 240c. The waveform generation second port 210b is connected to the clock frequency divider fourth port 220d and the output control first port 240a. The waveform generation third port 210c is connected to the clock frequency divider second port 220b. The clock frequency divider first port 220a serves as the calibration protection first port 200a. The clock frequency divider fifth port 220e is connected to the output control second port 240b. The clock frequency divider sixth port 220f is connected to the encoding judgment first port 230a. The encoding judgment second port 230b serves as the calibration protection second port 200b. The encoding judgment third port 230c is connected to the output control fourth port 240d. The output control fifth port 240e serves as the calibration protection third port 200c.
[0074] like Figure 3 As shown, the waveform generation unit 210 includes a first inverter 211 and a first XOR gate 212.
[0075] The input terminal of the first inverter 211 serves as the first waveform generation port 210a. The output terminal of the first inverter 211 is connected to one input terminal of the first XOR gate 212. The other input terminal of the first XOR gate 212 serves as the second waveform generation port 210b. The output terminal of the first XOR gate 212 serves as the third waveform generation port 210c.
[0076] By logically combining the original clock signal and its delayed signal, a frequency divide-by-two and frequency divide-by-four mode of fixed reference waveform for encoding and discrimination is generated.
[0077] like Figure 4 As shown, the clock divider unit 220 includes: a first flip-flop 221, a second flip-flop 222, and a third flip-flop 223.
[0078] The data input terminal of the first flip-flop 221 serves as the second clock divider port 220b. The clock input terminal of the first flip-flop 221 is connected to the clock input terminals of the second flip-flop 222 and the third flip-flop 223, which together serve as the first clock divider port 220a. The truth output terminal of the first flip-flop 221 is connected to the data input terminal of the second flip-flop 222, which together serve as the fourth clock divider port 220d. The truth output terminal of the second flip-flop 222 is connected to the data input terminal of the third flip-flop 223, which together serve as the fifth clock divider port 220e and the sixth clock divider port 220f. The truth output terminal of the third flip-flop 223 serves as the third clock divider port 220c.
[0079] Preferably, the first flip-flop 221, the second flip-flop 222, and the third flip-flop 223 are D flip-flops.
[0080] The first flip-flop 221, the second flip-flop 222, and the third flip-flop 223 form a shift register to store the data.
[0081] The first flip-flop 221 acquires the signal for calibrating and protecting the first port 200a. The output of the second flip-flop 222 is delayed by one cycle compared to the output of the first flip-flop 221, and the output of the third flip-flop 223 is delayed by two cycles compared to the output of the first flip-flop 221. This structure is used to generate clock references with different phases (such as the basis for divide-by-two and divide-by-four waveforms).
[0082] like Figure 5 As shown, the encoding judgment unit 230 includes: a second XOR gate 231 and a second inverter 232.
[0083] One input of the second XOR gate 231 is used as the first encoding judgment port 230a, and the other input of the second XOR gate 231 is used as the second encoding judgment port 230b. The output of the second XOR gate 231 is connected to the input of the second inverter 232, and the output of the second inverter 232 is used as the third encoding judgment port 230c.
[0084] It compares the encoded signal with the internal timing state to determine whether the encoded signal conforms to the preset encoding.
[0085] like Figure 6 As shown, the output control unit 240 includes a NOR gate 241 and a NAND gate 242.
[0086] One input of NOR gate 241 is used as the first output control port 240a, the other input of NOR gate 241 is used as the second output control port 240b, the output of NOR gate 241 is connected to one input of NAND gate 242, the other input of NAND gate 242 is used as the third output control port 240c, another input of NAND gate 242 is used as the fourth output control port 240d, and the output of NAND gate 242 is used as the fifth output control port 240e.
[0087] NAND gate 242 receives the judgment result from the third port 230c of the encoding judgment and performs the final logic judgment.
[0088] NOR gate 241 generates a reset or lock signal based on the system status (such as successful verification, failure, or timeout) and feeds it back to the trigger to prevent repeated false triggering or maintain a safe state.
[0089] This module ensures that the circuit can be correctly reset or locked after a Trim operation.
[0090] Figure 7 The circuit diagram of the calibration protection module 200 is shown, and its working principle is explained below:
[0091] In the protection circuit described in this application, calibration protection first port 200a, calibration protection second port 200b, and calibration protection third port 200c are three key signal nodes. Calibration protection first port 200a receives a clock signal of a preset frequency; calibration protection second port 200b receives an encoded signal; and calibration protection third port 200c outputs the encoded signal to verify the result. First flip-flop 221, second flip-flop 222, and third flip-flop 223 form a shift register to store the data.
[0092] The third flip-flop 223, combined with the first inverter 211 and the first XOR gate 212, generates a waveform divided by two and divided by four. Taking the clock signal received by the first clock divider port 200a as an example (low level 0, high level 1), the divided-by-two signal is "01", and the divided-by-four signal is "0110". The second flip-flop 222 is delayed by one clock cycle compared to the first flip-flop 221, therefore the second flip-flop 222 will count one more "0" than the first flip-flop 221. Therefore, when the signal received by the calibration protection second port 200b is "0010110", the second XOR gate 231 is set to a high level after passing through the second inverter 232, thus opening the NAND gate 242. At this time, it means that the encoded signal conforms to the preset encoding, and subsequent chip calibration operations can continue. In this way, protection is achieved for the chip calibration process.
[0093] This protection circuit uses time delay difference as its core identification logic to distinguish between the two encoding states of "0" and "1". Specifically, the calibration protection first port 200a receives a clock signal with a preset duty cycle; schematically, the single-cycle duty cycle of this clock signal is 5 microseconds (μs). Simultaneously, the calibration protection second port 200b receives an encoded signal, which is the signal to be verified. When the trigger time of the signal at the calibration protection second port 200b precedes the signal at the calibration protection first port 200a by 5 microseconds, and the single-cycle duty cycle of the encoded signal received by the calibration protection second port 200b is less than 10 μs, the protection circuit determines the current encoding to be "0"; if the single-cycle duty cycle of the encoded signal received by the calibration protection second port 200b is greater than 10 μs, the current encoding is determined to be "1". Furthermore, the circuit also uses an edge detection mechanism to assist in encoding identification, such as... Figure 8 As shown: When the clock signal of the first calibration protection port 200a generates a rising edge, the second calibration protection port 200b is synchronously detected to see if a waveform is received. If no waveform is detected, the code is determined to be "0"; if a waveform is detected to be received by the second calibration protection port 200b, the code is determined to be "1".
[0094] By adding protection to the chip calibration process before it begins, the chip will only enter an operable chip calibration mode and allow subsequent programming procedures if the input to the second port 200b of the calibration protection conforms to a preset code (e.g., a specific sequence of instruction codes or keys) and passes verification. This avoids chip malfunctions caused by misoperation of the chip calibration pins. This protection mechanism constructs an access control barrier for the chip calibration function; only through verification of the coded signal can the operational restrictions on chip verification be lifted, ensuring the security and reliability of the chip verification process.
[0095] In other embodiments, an integrated circuit includes the protection circuit described above.
[0096] The protection circuit can be packaged independently. When in use, the packaged protection circuit is connected to the front stage of the calibration pin in the chip to be calibrated and used in conjunction with the calibration integrated circuit. Alternatively, the protection circuit and the chip to be calibrated can be packaged in the same integrated circuit, so that the integrated circuit has the function of calibration protection.
[0097] In other embodiments, such as Figure 9 As shown, a protection method is applied to the protection circuit described above. The method includes:
[0098] S100: The second port of the protection circuit receives the encoded signal by calibration protection.
[0099] S200: Determine whether the encoded signal is the preset code based on the clock signal output by the clock output module in the protection circuit. The preset code is used to indicate the start of calibration of the subsequent circuit connected to the protection circuit.
[0100] S300: In response to the encoded signal being a preset code, calibration of the downstream circuit connected to the protection circuit is initiated.
[0101] S400: The calibration protection second port of the protection circuit receives the encoded clock signal and determines the check bit for the subsequent circuit based on the number of clock signals.
[0102] S500: Obtain verification information and adjust the verification bits according to the verification information.
[0103] Preferably, before receiving the encoded signal from the calibration protection second port of the protection circuit, the method further includes:
[0104] The power-on signal is obtained from the calibration protection second port of the protection circuit, which enables the clock output module in the protection circuit to start working.
[0105] By implementing the protection circuit, integrated circuit, and protection method described in the embodiments of this application, the calibration start behavior can be encrypted and coded before the chip is calibrated using a clock signal with a fixed number of cycles. When the coded signal conforms to the preset code, the chip calibration action is initiated, reducing the probability of the chip mistakenly entering the calibration mode; thus ensuring the stability and reliability of chip calibration.
[0106] All of the above-mentioned optional technical solutions can be combined in any way to form the optional embodiments of this application, and will not be described in detail here.
[0107] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments. Many other equivalent embodiments may be included without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims
1. A protection circuit, characterized in that, include: Clock output module (100), calibration protection module (200), and calibration storage module (300); The clock output module (100) is connected to the calibration protection module (200), and the calibration protection module (200) is connected to the calibration storage module (300). The clock output module (100) is used to provide a clock signal of a preset frequency to the verification and protection module (200); The calibration protection module (200) is used to receive an encoded signal and an encoded clock signal. When the encoded signal is a preset code, the calibration of the downstream circuit connected to the protection circuit is started. The encoded clock signal is used to indicate the calibration bit of the downstream circuit. The calibration storage module (300) is used to store calibration information.
2. The protection circuit according to claim 1, characterized in that, The clock output module (100) has a signal output port (100a); The calibration protection module (200) has: a calibration protection first port (200a), a calibration protection second port (200b), and a calibration protection third port (200c); The calibration storage module (300) has a calibration storage receiving port (300a); The signal output port (100a) is connected to the calibration protection first port (200a), and the calibration protection third port (200c) is connected to the calibration storage receiving port (300a). The calibration protection first port (200a) is used to receive the clock signal generated by the clock output module (100); The calibration protection second port (200b) is used to receive the encoded signal and the encoded clock signal.
3. The protection circuit according to claim 2, characterized in that, The calibration protection module (200) includes: a waveform generation unit (210), a clock division unit (220), an encoding judgment unit (230), and an output control unit (240); The waveform generation unit (210) has: a waveform generation first port (210a), a waveform generation second port (210b), and a waveform generation third port (210c); The clock divider unit (220) has: a first clock divider port (220a), a second clock divider port (220b), a third clock divider port (220c), a fourth clock divider port (220d), a fifth clock divider port (220e), and a sixth clock divider port (220f); The encoding judgment unit (230) has: an encoding judgment first port (230a), an encoding judgment second port (230b), and an encoding judgment third port (230c); The output control unit (240) has: an output control first port (240a), an output control second port (240b), an output control third port (240c), an output control fourth port (240d), and an output control fifth port (240e); The waveform generation first port (210a) is connected to the clock division third port (220c) and the output control third port (240c). The waveform generation second port (210b) is connected to the clock division fourth port (220d) and the output control first port (240a). The waveform generation third port (210c) is connected to the clock division second port (220b). The clock division first port (220a) serves as the calibration protection first port (200a). The fifth port (220e) of the clock divider is connected to the second port (240b) of the output control, the sixth port (220f) of the clock divider is connected to the first port (230a) of the encoding judgment, the second port (230b) of the encoding judgment serves as the second port (200b) of the calibration protection, the third port (230c) of the encoding judgment is connected to the fourth port (240d) of the output control, and the fifth port (240e) of the output control serves as the third port (200c) of the calibration protection.
4. The protection circuit according to claim 3, characterized in that, The waveform generation unit (210) includes: a first inverter (211) and a first XOR gate (212); The input terminal of the first inverter (211) serves as the first port (210a) for waveform generation, the output terminal of the first inverter (211) is connected to one input terminal of the first XOR gate (212), the other input terminal of the first XOR gate (212) serves as the second port (210b) for waveform generation, and the output terminal of the first XOR gate (212) serves as the third port (210c) for waveform generation.
5. The protection circuit according to claim 3, characterized in that, The clock divider unit (220) includes: a first flip-flop (221), a second flip-flop (222), and a third flip-flop (223); The data input terminal of the first flip-flop (221) serves as the second port (220b) of the clock division. The clock input terminal of the first flip-flop (221) is connected to the clock input terminal of the second flip-flop (222) and the clock input terminal of the third flip-flop (223) to serve as the first port (220a) of the clock division. The truth output terminal of the first flip-flop (221) is connected to the data input terminal of the second flip-flop (222) to serve as the fourth port (220d) of the clock division. The truth output terminal of the second flip-flop (222) is connected to the data input terminal of the third flip-flop (223) to serve as the fifth port (220e) and the sixth port (220f) of the clock division. The truth output terminal of the third flip-flop (223) serves as the third port (220c) of the clock division.
6. The protection circuit according to claim 5, characterized in that, The first flip-flop (221), the second flip-flop (222), and the third flip-flop (223) are D flip-flops.
7. The protection circuit according to claim 3, characterized in that, The encoding judgment unit (230) includes: a second XOR gate (231) and a second inverter (232); One input of the second XOR gate (231) serves as the first encoding judgment port (230a), the other input of the second XOR gate (231) serves as the second encoding judgment port (230b), the output of the second XOR gate (231) is connected to the input of the second inverter (232), and the output of the second inverter (232) serves as the third encoding judgment port (230c).
8. The protection circuit according to claim 3, characterized in that, The output control unit (240) includes: a NOR gate (241) and a NAND gate (242); One input of the NOR gate (241) serves as the first output control port (240a), the other input of the NOR gate (241) serves as the second output control port (240b), the output of the NOR gate (241) is connected to one input of the NAND gate (242), the other input of the NAND gate (242) serves as the third output control port (240c), another input of the NAND gate (242) serves as the fourth output control port (240d), and the output of the NAND gate (242) serves as the fifth output control port (240e).
9. An integrated circuit, characterized in that, Includes the protection circuit described in any one of claims 1-8.
10. A protection method, characterized in that, The protection circuit applied to any one of claims 1-8 includes: The coded signal is received by the calibration protection second port of the protection circuit; The clock signal output by the clock output module in the protection circuit is used to determine whether the encoded signal is a preset code. In response to the encoded signal being a preset code, calibration of the downstream circuit connected to the protection circuit is initiated. The coded clock signal is received by the calibration protection second port of the protection circuit, and the check bit for the subsequent circuit is determined according to the number of clock signals. Obtain verification information and adjust the verification bit according to the verification information.