Data transmission method, electronic equipment and computer readable medium
By creating a descriptor queue by the processor and triggering the direct memory access controller to transfer data, the problem of large logic code volume in FPGA-dominated DMA transfer is solved, thus improving work efficiency.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-06
- Publication Date
- 2026-03-31
AI Technical Summary
In scenarios where Field Programmable Gate Arrays (FPGAs) dominate Direct Memory Access (DMA) transfers, existing solutions require staff to write a large amount of logic code, resulting in a significant workload.
The processor of the electronic device creates a descriptor queue, and when it receives a transfer instruction from the programmable logic device, it transfers the descriptor queue to the direct memory access controller, triggering the direct memory access controller to perform data transfer, thereby reducing the amount of logic code to be written on the programmable logic device side.
It greatly reduces the workload of staff, improves work efficiency, and simplifies the FPGA-led DMA transfer process.
Smart Images
Figure CN121764837A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of data transmission technology, and more specifically, to a data transmission method, electronic device, and computer-readable medium. Background Technology
[0002] Currently, the Direct Memory Access (DMA) technology of the common Peripheral Component Interconnect Express (PCIE) is generally initiated by the central processing unit (CPU) of the host computer. However, in the actual application scenarios of Field-Programmable Gate Array (FPGA), there are often scenarios where the FPGA leads the DMA transfer. Existing solutions that lead the DMA transfer through the FPGA have a large workload. Summary of the Invention
[0003] This application proposes a data transmission method, an electronic device, and a computer-readable medium to overcome the aforementioned deficiencies.
[0004] In a first aspect, this application provides a data transmission method applied to a processor of an electronic device, the processor being connected to a programmable logic device (PLD). The method includes: obtaining a first address in the PLD, the storage space corresponding to the first address being used to store target data, the target data being data to be sent or data to be received; determining a second address of a cache space in the electronic device based on the data volume of the target data; creating a descriptor queue based on the first address of the target data and the second address of the cache space; and, if a transmission instruction is received from the PLD, transmitting the descriptor queue to a direct memory access controller (DMC), the DMC being used to transmit the target data between the cache space and the PLD based on the descriptor queue.
[0005] Optionally, in one possible implementation, the target data consists of multiple data to be sent, and the descriptor queue includes a first descriptor corresponding to each data to be sent. Each first descriptor includes a first starting address, a first destination address, and a data length corresponding to the data to be sent. The first starting address is contained in the second address, and the first destination address is contained in the first address. If a transmission instruction from the programmable logic device is received, the descriptor queue is transmitted to the direct memory access controller, including: writing the data to be sent corresponding to each first descriptor into the cache space; if a transmission instruction from the programmable logic device is received, setting the state of each first descriptor to a state of pending transmission; transmitting the descriptor queue to the direct memory access controller, triggering the direct memory access controller to obtain the corresponding data to be sent based on the first starting address and data length in each first descriptor, and writing the obtained data to be sent into the storage space corresponding to the first destination address, and returning a first preset reply information corresponding to the first descriptor after successful writing; and modifying the state of the first descriptor corresponding to the received first preset reply information to a state of sent.
[0006] Optionally, in one possible implementation, after modifying the state of the first descriptor corresponding to the received first preset reply information to the sent state, the method further includes: if the state of each first descriptor is the sent state, then clearing or releasing the cache space.
[0007] Optionally, in one possible implementation, the target data consists of multiple data to be received, and the descriptor queue includes a second descriptor corresponding to each data to be received. Each second descriptor includes a second starting address, a second destination address, and a data length corresponding to the data to be received. The second starting address is contained in the first address, and the second destination address is contained in the second address. If a transmission instruction from the programmable logic device is received, the descriptor queue is transmitted to the direct memory access controller, including: clearing the cache space; if a transmission instruction from the programmable logic device is received, setting the state of each second descriptor to a pending state; transmitting the descriptor queue to the direct memory access controller, triggering the direct memory access controller to obtain the corresponding data to be received based on the second starting address and data length in each second descriptor, and writing the obtained data to be received into the storage space corresponding to the second destination address, and returning a second preset reply information corresponding to the second descriptor after successful writing; and modifying the state of the second descriptor corresponding to the received second preset reply information to a received state.
[0008] Optionally, in one possible implementation, after modifying the state of the second descriptor corresponding to the received second preset reply information to the received state, the method further includes: transferring the data to be received corresponding to the second descriptor stored in the cache space and in the received state to the preset storage space; and clearing the cache space.
[0009] Optionally, in one possible implementation, after clearing the cache space, the method further includes: determining whether the state of each second descriptor is a received state; if there is a second descriptor whose state is not a received state, then returning to the step of modifying the state of the second descriptor corresponding to the received second preset reply information to a received state and subsequent steps, until the state of each second descriptor is a received state.
[0010] Optionally, in one possible implementation, the direct memory access controller is located in the electronic device and connected to the processor.
[0011] Secondly, this application also provides an electronic device for connection to a programmable logic device, comprising: one or more processors; a memory; and one or more application programs, wherein the one or more application programs are stored in the memory, the one or more application programs are configured to be executed by the one or more processors, and the one or more application programs are configured to perform the methods as described above.
[0012] Thirdly, this application also provides an electronic device, comprising: a programmable logic device; one or more processors connected to the programmable logic device; a memory; and one or more application programs, wherein the one or more application programs are stored in the memory, the one or more application programs are configured to be executed by the one or more processors, and the one or more application programs are configured to perform the methods as described above.
[0013] The solution provided in this application firstly obtains a first address in the programmable logic device and determines a second address of the cache space in the electronic device based on the amount of the target data; secondly, a descriptor queue is created according to the first address of the target data and the second address of the cache space; if a transmission instruction is received from the programmable logic device, the descriptor queue is transmitted to a direct memory access controller, which is used to transmit the target data between the cache space and the programmable logic device based on the descriptor queue.
[0014] In scenarios where programmable logic devices (PLDs) drive DMA data transfer, existing solutions involve creating descriptor queues using PLDs, which requires developers to write a significant amount of logic code, resulting in a substantial workload. This application, however, creates descriptor queues based on the processor of the electronic device. Upon receiving a transfer instruction from the PLD, the descriptor queue is transmitted to the Direct Memory Access Controller (DMI), triggering the DMI to transfer the target data according to the descriptor queue. This approach avoids writing extensive logic code on the PLD side, significantly reducing workload and improving efficiency.
[0015] Other features and advantages of this application will be set forth in the following description and will be apparent in part from the description or may be learned by practicing the application. The objectives and other advantages of this application may be realized and obtained by means of the structures particularly pointed out in the written description, claims, and drawings. Attached Figure Description
[0016] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0017] Figure 1 A flowchart of the data transmission method provided in an embodiment of this application is shown; Figure 2 A flowchart of a data transmission method according to another embodiment of this application is shown; Figure 3 A flowchart of a data transmission method according to another embodiment of this application is shown; Figure 4 A flowchart of a data transmission method according to another embodiment of this application is shown; Figure 5 A flowchart of a data transmission method according to another embodiment of this application is shown; Figure 6 A flowchart of a data transmission method according to another embodiment of this application is shown; Figure 7 A structural block diagram of the electronic device provided in an embodiment of this application is shown; Figure 8 A structural block diagram of an electronic device provided in another embodiment of this application is shown; Figure 9 A structural block diagram of a computer-readable storage medium provided in an embodiment of this application is shown. Detailed Implementation
[0018] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present application, and not all of them. The components of the embodiments of the present application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely represents selected embodiments of the present application. All other embodiments obtained by those skilled in the art based on the embodiments of the present application without inventive effort are within the scope of protection of the present application.
[0019] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, in the description of this application, terms such as "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.
[0020] It should be noted that in PCIe's DM technology, or Direct Memory Access, data transfer is not handled by the CPU, but by a special processor DMA controller, thus consuming very little CPU resources.
[0021] In a PCIe system, the host computer typically contains a root complex (RC), which is the master controller of the PCIe bus, responsible for managing and controlling the entire PCIe system. Endpoint (EP) devices are the slave devices. Generally, the host computer's CPU initiates DMA transfers, sending read / write requests to the EP devices via the RC. The EP devices respond to these requests and perform the corresponding data read / write operations. In certain specific application scenarios, such as when an FPGA acts as an EP device, the FPGA can also initiate DMA transfers, actively initiating data transfer requests to the host computer. After the host computer's RC agrees, data transfer begins.
[0022] Currently, the Direct Memory Access (DMA) technology of the common Peripheral Component Interconnect Express (PCIe) is generally initiated by the central processing unit (CPU) of the host computer. However, in the actual application scenarios of Field-Programmable Gate Array (FPGA), there are often scenarios where the FPGA leads the DMA transfer. Existing solutions that lead the DMA transfer through the FPGA require the FPGA to generate descriptors, and the logic code that needs to be written by the staff is relatively complex and the workload is large.
[0023] Therefore, this application provides a data transmission method, an electronic device, and a computer-readable medium to solve or partially solve the above-mentioned problems.
[0024] Please see Figure 1 The diagram illustrates a data transmission method according to an embodiment of this application. The method is applied to a processor of an electronic device, which is connected to a programmable logic device, and specifically includes steps S101 to S104.
[0025] It should be noted that the programmable logic device refers to a programmable logic device, which can be an FPGA or a Complex Programmable Logic Device (CPLD), etc.
[0026] In one implementation scenario, the electronic device includes a processor and a programmable logic device, and the processor and the programmable logic device are connected.
[0027] In another implementation scenario, the electronic device includes a processor, which is connected to a programmable logic device. For example, the programmable logic device can be connected to the processor in a hot-swappable manner or in a pluggable manner. No specific limitation is made on the specific connection method here.
[0028] Step S101: Obtain the first address in the programmable logic device. The storage space corresponding to the first address is used to store target data, which is data to be sent or data to be received.
[0029] It is understandable that if the target data is data to be sent, it means that the processor is sending data to the programmable logic device; if the target data is data to be received, it means that the processor is receiving data transmitted by the programmable logic device.
[0030] Taking a programmable logic device (FPGA) as an example, if the FPGA-driven DMA data transfer means that the transfer request is initiated by the FPGA side, this application establishes a descriptor on the CPU side. For this purpose, the CPU side needs to know the source address and destination address of the data to be transferred. For the CPU side, it needs to know the address in the FPGA where the target data is stored, that is, to obtain the first address in the programmable logic device. The storage space corresponding to the first address is used to store the target data.
[0031] As we know, when a programmable logic device (PLD) needs to lead a DMA data transfer, it sends the transfer request (including the first address in the PLD) to the CPU. In this way, the CPU can obtain the first address in the PLD.
[0032] It should be noted that the first address represents the address range corresponding to the target data. For example, the first address is from 0x0000 to 0x000F.
[0033] In one implementation scenario, the target data is data to be sent, and a first address in the programmable logic device is obtained, the corresponding storage space of which is used to store the data to be sent.
[0034] In another implementation scenario, the target data is the data to be received. A first address in the programmable logic device is obtained, and the corresponding storage space is used to store the data to be received.
[0035] Step S102: Determine the second address of the cache space in the electronic device based on the amount of data in the target data.
[0036] Understandably, the first address is the set of addresses corresponding to each piece of data in the target data. For example, for a 16-byte target data set, the corresponding first address is from 0x0000 to 0x000F, with each byte corresponding to one address. As another example, for a 4KB target data set, the corresponding first address is from 0x0000 to 0x0FFF.
[0037] Therefore, the amount of target data can be determined based on the first address, and the second address of the cache space can be determined based on the amount of target data, where the second address is an address range.
[0038] For example, if the target data is data to be sent and the data size of the target data is 4KB, then the cache space is determined based on the data size of the target data. The capacity of the cache space is at least 4KB. Then, the second address of the cache space is determined to be 0x0000 to 0x0FFF in the electronic device.
[0039] Since the processed data can be cleaned up during the data reception process, the capacity of the cache space can be smaller than the capacity of the target data when receiving data. The second address of the cache space can be determined based on user needs.
[0040] In one example, the target data is the data to be received, and the data size of the target data is 4KB. The user's requirement is to clear the cache space every time it reaches 1KB. Therefore, the capacity of the cache space can be determined to be 1KB.
[0041] Step S103: Create a descriptor queue based on the first address of the target data and the second address of the cache space.
[0042] It should be noted that to transfer data via DMA, it is necessary to specify where the target data is read from and where it is written. Therefore, the source address and target address of the target data need to be clearly defined. In this application, the first address is the storage address of the target data in the programmable logic device, and the second address represents the storage address of the target data in the electronic device. Therefore, this application creates a descriptor queue based on the first address of the target data and the second address in the cache space.
[0043] In one optional embodiment, the target data consists of multiple data to be transmitted, and the descriptor queue includes a descriptor corresponding to each data to be transmitted. Each descriptor includes the starting address (source address), the destination address, and the data length of the corresponding data to be transmitted.
[0044] In one example, the data to be transmitted is the data to be sent, the target data consists of multiple data to be sent, and the descriptor queue includes a first descriptor corresponding to each data to be sent. Each first descriptor includes the first starting address, the first destination address, and the data length of the corresponding data to be sent.
[0045] In one example, the data to be transmitted is the data to be received, the target data consists of multiple data to be received, and the descriptor queue includes a second descriptor corresponding to each data to be received. Each second descriptor includes the second starting address, the second destination address, and the data length of the corresponding data to be received.
[0046] Step S104: If a transmission instruction is received from the programmable logic device, the descriptor queue is transmitted to the direct memory access controller, which is used to transmit the target data between the cache space and the programmable logic device based on the descriptor queue.
[0047] Understandably, the descriptor queue created on the CPU side needs to be managed by the programmable logic device (PLD) for DMA transfer. Therefore, after the CPU establishes the descriptor queue, it does not directly transfer data but waits for the transfer instruction from the PLD side. If the PLD receives the transfer instruction, it means that the descriptor queue needs to be transferred to the direct memory access controller (DMC), triggering the DMC to transfer the target data between the cache space and the PLD based on the descriptor queue.
[0048] For example, the transmission command may be a user event, such as an interrupt signal.
[0049] In one optional embodiment, a first address in the programmable logic device is obtained, and a second address of the cache space in the electronic device is determined based on the amount of the target data; a descriptor queue is created according to the first address of the target data and the second address of the cache space; if a transmission instruction is received from the programmable logic device, the descriptor queue is transmitted to a direct memory access controller, which is used to transmit the target data between the cache space and the programmable logic device based on the descriptor queue.
[0050] In scenarios where programmable logic devices (PLDs) drive DMA data transfer, existing solutions involve creating descriptor queues using PLDs, which requires developers to write a significant amount of logic code, resulting in a substantial workload. This application, however, creates descriptor queues based on the processor of the electronic device. Upon receiving a transfer instruction from the PLD, the descriptor queue is transmitted to the Direct Memory Access Controller (DMI), triggering the DMI to transfer the target data according to the descriptor queue. This approach avoids writing extensive logic code on the PLD side, significantly reducing workload and improving efficiency.
[0051] In one alternative embodiment, a direct memory access controller is disposed in the electronic device and is connected to both the processor and the programmable logic device.
[0052] In one alternative embodiment, a direct memory access controller is located in the programmable logic device and is connected to the processor.
[0053] Please see Figure 2 The diagram illustrates a data transmission method according to an embodiment of this application. The method is applied to a processor of an electronic device, which is connected to a programmable logic device, and specifically includes steps S201 to S207.
[0054] Step S201: Obtain the first address in the programmable logic device. The storage space corresponding to the first address is used to store target data, which is data to be sent or data to be received.
[0055] Step S202: Determine the second address of the cache space in the electronic device based on the amount of data in the target data.
[0056] Step S203: Create a descriptor queue based on the first address of the target data and the second address of the cache space.
[0057] It should be noted that the target data consists of multiple data to be sent, and the descriptor queue includes a first descriptor corresponding to each data to be sent. Each first descriptor includes a first starting address, a first destination address, and a data length of the corresponding data to be sent. The first starting address is contained in the second address, and the first destination address is contained in the first address.
[0058] The first starting address represents the storage address of the data to be sent in the cache space, and the first destination address represents the storage address of the data to be sent in the programmable logic device. The direct memory access controller can read the data to be sent from the cache space based on the first starting address and the data length, and then write the data to be sent into the storage space corresponding to the first destination address.
[0059] Step S204: Write the data to be sent corresponding to each of the first descriptors into the cache space.
[0060] Understandably, since the first descriptor includes the first starting address, the first destination address, and the data length of the corresponding data to be sent, the corresponding data to be sent can be written into the buffer space based on each first descriptor in the descriptor queue, that is, all the data to be sent can be written into the buffer space to prepare the data for data transmission.
[0061] Step S205: If a transmission instruction from the programmable logic device is received, the state of each of the first descriptors is set to the state to be sent.
[0062] If the processor receives a transmission instruction from the programmable logic device, it sets the state of each first descriptor to the "ready to transmit" state. It should be noted that the state of each first descriptor includes both a "ready to transmit" state and a "transmitted" state; the state of the first descriptor is used to subsequently determine whether data transmission is complete.
[0063] Step S206: The descriptor queue is transmitted to the direct memory access controller, which triggers the direct memory access controller to obtain the corresponding data to be sent based on the first starting address and data length in each first descriptor, and writes the obtained data to be sent into the storage space corresponding to the first target address, and returns the first preset reply information corresponding to the first descriptor after successful writing.
[0064] The descriptor queue is transmitted to the direct memory access controller. The direct memory access controller first obtains the corresponding data to be sent based on the first starting address and data length in each first descriptor, then writes the obtained data to be sent into the storage space corresponding to the first target address, and returns the first preset reply information corresponding to the first descriptor after successful writing.
[0065] Step S207: Modify the status of the first descriptor corresponding to the received first preset reply information to the sent status.
[0066] It should be noted that the direct memory access controller can read a preset number of data to be sent each time and write them into the corresponding storage space. After a successful write, it returns the corresponding first preset reply information. The processor modifies the status of the first descriptor corresponding to the received first preset reply information to the sent status.
[0067] In one example, the direct memory access controller reads five pieces of data to be sent based on five first descriptors, writes them to five storage spaces corresponding to five first target addresses, and returns first preset reply information corresponding to the five first descriptors after successful writing. The processor then modifies the status of the five first descriptors corresponding to the received first preset reply information to the "sent" status. This process can be used to transmit each piece of data to be sent, and then modify the status of each first descriptor to the "sent" status based on the first preset reply information.
[0068] In this embodiment, in a scenario where the programmable logic device (PLD) dominates DMA transfer, a descriptor queue is constructed by the processor, and the data to be sent corresponding to each first descriptor is written into the cache space. If a transfer instruction is received from the PLD, the state of each first descriptor is set to a pending transfer state. The descriptor queue is transmitted to a direct memory access controller (DMC), which triggers the DMC to obtain the corresponding data to be sent based on the first starting address and data length in each first descriptor, and writes the obtained data to be sent into the storage space corresponding to the first target address. After successful writing, a first preset reply information corresponding to the first descriptor is returned. The state of the first descriptor corresponding to the received first preset reply information is changed to a sent state. The data transmission method of this application does not require writing a large amount of logic code on the PLD side, greatly reducing the workload of staff and improving work efficiency.
[0069] In one optional embodiment, after modifying the state of the first descriptor corresponding to the received first preset reply information to the sent state, the method further includes: if the state of each first descriptor is the sent state, then clearing or releasing the cache space.
[0070] It should be noted that if the status of each first descriptor is "sent", it means that each piece of data to be sent has been transmitted to the storage space corresponding to the first address of the programmable logic device, and the cache space is cleared or released.
[0071] As an example, if the state of each of the first descriptors is "sent", then the cache space is cleared, and the cache space can be used to store other data, thereby improving the utilization of the cache space.
[0072] Another example is that if the state of each of the first descriptors is "sent", then the cache space is released, which can reduce the resource occupancy of the electronic device.
[0073] Please see Figure 3 The diagram illustrates a data transmission method according to an embodiment of this application. The method is applied to a processor of an electronic device, which is connected to a programmable logic device, and specifically includes steps S301 to S307.
[0074] Step S301: Obtain the first address in the programmable logic device. The storage space corresponding to the first address is used to store target data, which is data to be sent or data to be received.
[0075] Step S302: Determine the second address of the cache space in the electronic device based on the amount of data in the target data.
[0076] Step S303: Create a descriptor queue based on the first address of the target data and the second address of the cache space.
[0077] It should be noted that the target data consists of multiple data to be received, and the descriptor queue includes a second descriptor corresponding to each data to be received. Each second descriptor includes a second starting address, a second target address, and a data length for the corresponding data to be received. The second starting address is contained in the first address, and the second target address is contained in the second address.
[0078] The second starting address represents the storage address of the data to be received in the cache space, and the second target address represents the storage address of the data to be sent in the programmable logic device. The direct memory access controller can read the data to be received from the programmable logic device based on the second starting address and the data length, and then write the data to be received into the storage space corresponding to the second target address.
[0079] Step S304: Clear the cache space.
[0080] Understandably, the target data consists of multiple data to be received, indicating that data needs to be transferred from the storage space of the programmable logic device to the cache space of the electronic device. To do this, the cache space needs to be cleared to provide storage space for the data to be received.
[0081] Step S305: If a transmission instruction from the programmable logic device is received, the state of each second descriptor is set to the receive state.
[0082] It should be noted that the state of the second descriptor includes a pending state and a received state. The pending state indicates that the data to be received corresponding to the second descriptor has not yet been transmitted to the cache space, and the received state indicates that the data to be received corresponding to the second descriptor has not yet been transmitted to the cache space.
[0083] If a transmission instruction is received from a programmable logic device, the state of each second descriptor is set to the "ready to receive" state, which makes it easier to determine later whether the data to be received has been transmitted.
[0084] Step S306: The descriptor queue is transmitted to the direct memory access controller, which triggers the direct memory access controller to obtain the corresponding data to be received based on the second starting address and data length in each second descriptor, and writes the obtained data to be received into the storage space corresponding to the second target address. After successful writing, the controller returns the second preset reply information corresponding to the second descriptor.
[0085] Understandably, the descriptor queue is transmitted to the direct memory access controller. The direct memory access controller first obtains the corresponding data to be received based on the second starting address and data length in each second descriptor, then writes the obtained data to be received into the storage space corresponding to the second target address, and returns the second preset reply information corresponding to the second descriptor after successful writing.
[0086] Step S307: Modify the status of the second descriptor corresponding to the received second preset reply information to the received status.
[0087] It should be noted that the direct memory access controller can read a preset number of data to be received each time and write them into the corresponding storage space. After a successful write, it returns the corresponding second preset reply information. The processor modifies the status of the second descriptor corresponding to the received second preset reply information to the received status.
[0088] In one example, a direct memory access controller reads six data items to be received from the memory space of a programmable logic device based on a second descriptor and writes them to the corresponding cache space in the electronic device. After successful writing, it returns the corresponding second preset reply information. The processor then modifies the status of the six second descriptors corresponding to the received second preset reply information to a received state. This process can be used to transmit each data item to be received and then modify the status of each second descriptor to a received state.
[0089] In this embodiment, in a scenario where the programmable logic device (PLD) dominates DMA transfer, a descriptor queue is constructed by the processor, and the cache space is cleared. If a transfer instruction from the PLD is received, the state of each second descriptor is set to a pending state. The descriptor queue is transmitted to a direct memory access controller (DMC), triggering the DMC to obtain the corresponding pending data based on the second starting address and data length in each second descriptor. The obtained pending data is written into the storage space corresponding to the second target address, and after successful writing, a second preset reply information corresponding to the second descriptor is returned. The state of the second descriptor corresponding to the received second preset reply information is then changed to a received state. This data transfer method eliminates the need to write a large amount of logic code on the PLD side, significantly reducing the workload of staff and improving work efficiency.
[0090] Please see Figure 4 The document illustrates a flowchart of a data transmission method provided in an embodiment of this application. The method is applied to a processor of an electronic device, which is connected to a programmable logic device, and specifically includes steps S401 to S411.
[0091] Step S401: Obtain the first address in the programmable logic device. The storage space corresponding to the first address is used to store target data, which is data to be sent or data to be received.
[0092] Step S402: Determine the second address of the cache space in the electronic device based on the amount of data in the target data.
[0093] Step S403: Create a descriptor queue based on the first address of the target data and the second address of the cache space.
[0094] Step S404: Clear the cache space.
[0095] Step S405: If a transmission instruction from the programmable logic device is received, the state of each second descriptor is set to the receive state.
[0096] Step S406: The descriptor queue is transmitted to the direct memory access controller, which triggers the direct memory access controller to obtain the corresponding data to be received based on the second starting address and data length in each second descriptor, and writes the obtained data to be received into the storage space corresponding to the second target address. After successful writing, the controller returns the second preset reply information corresponding to the second descriptor.
[0097] Step S407: Modify the status of the second descriptor corresponding to the received second preset reply information to the received status.
[0098] Step S408: Transfer the data to be received corresponding to the second descriptor stored in the cache space and whose status is "received" to the preset storage space.
[0099] Step S409: Clear the cache space.
[0100] It should be noted that after transmitting the data to be received corresponding to the second descriptor in the cache space and whose status is "received" to the preset storage space, clearing the cache space can provide more storage space for subsequent storage of the data to be received.
[0101] In one optional embodiment, after the received data is written to the cache space, the data in the cache space can be processed and detected directly, and then the cache space can be cleared after the processing is completed.
[0102] Step S410: Determine whether the status of each second descriptor is "received".
[0103] If the status of each second descriptor is "received", it means that all data to be received has been transmitted to the buffer space. Therefore, it is necessary to determine whether the status of each second descriptor is "received".
[0104] Step S411: If there is a second descriptor whose state is not a received state, then return to the step of modifying the state of the second descriptor corresponding to the received second preset reply information to a received state and the subsequent steps, until the state of each second descriptor is a received state.
[0105] If the state of the second descriptor is not "received", it means that the data to be received in the target data has not been completely transmitted. In this case, it is necessary to return to modify the state of the second descriptor corresponding to the received second preset reply information to "received" and perform subsequent operations until the state of each second descriptor is "received", which means that the data to be received in the target data has been transmitted.
[0106] In one optional embodiment, the host computer first initializes the data buffer and descriptor queue. Then, it waits for user interrupts (events) initiated by the user logic. If a data transmission interrupt is received from the user logic, the data transmission process is initiated, the descriptor corresponding to the target data is written to the DMA controller, and the descriptor queue is updated simultaneously. Next, it waits for the transmission to complete. After the transmission is complete, it waits for the next transmission event.
[0107] Please see Figure 5 The diagram illustrates a data transmission method according to an embodiment of this application. This method is applied to a processor in an electronic device connected to a programmable logic device. The embodiment describes the transmission of data from the processor to the programmable logic device. Specifically, it includes steps S501 to S507.
[0108] Step S501: Initialize the descriptor queue.
[0109] The host computer initializes the descriptor queue, including allocating data cache and creating the descriptor queue. Specifically, the host computer's processor obtains a first address from the programmable logic device, determines a second address of the cache space in the electronic device based on the amount of the target data, and creates the descriptor queue according to the first address of the target data and the second address of the cache space.
[0110] Step S502: Write the data to be sent.
[0111] The target data consists of multiple data to be sent, and each data to be sent is written to the cache space of the electronic device based on a descriptor queue.
[0112] Step S503: Determine whether user_event has been received.
[0113] It should be noted that `user_event` represents a transmission command sent by the FPGA side, which can be a user event. The processor determines whether it has received `user_event`. If it has not received `user_event`, it continues to wait for the user logic (EP) to send a user event to start data transmission. If it has received `user_event`, it updates the status of the descriptor appendix.
[0114] Step S504: Update the descriptor queue state.
[0115] The descriptor queue includes a first descriptor corresponding to each piece of data to be sent. Each first descriptor includes a first starting address, a first destination address, and a data length for the corresponding data to be sent. Updating the descriptor queue status means setting the status of each first descriptor to a pending-send status.
[0116] Step S505: Initiate DMA transfer.
[0117] The specific method for initiating DMA transfer is as follows: the descriptor queue is transferred to the direct memory access controller, which triggers the direct memory access controller to obtain the corresponding data to be sent based on the first starting address and data length in each first descriptor, and writes the obtained data to be sent into the storage space corresponding to the first target address. After successful writing, the controller returns the first preset reply information corresponding to the first descriptor.
[0118] Step S506: Determine whether the transmission is complete.
[0119] The specific operation to determine whether the transmission is complete is as follows: the processor determines whether it has received the first preset reply information. If the first preset reply information is received, it means that the data to be sent corresponding to the first preset reply information has been completed.
[0120] Step S507: Update the descriptor queue state.
[0121] Updating the descriptor queue status means changing the status of the first descriptor corresponding to the completed data to be sent to the "sent" status. The status of the first descriptor determines whether all data to be sent has been transmitted. If some data has not been completely transmitted, the DMA continues transmitting data until the status of each first descriptor is "sent." Then, the process can proceed to transmit the next target data.
[0122] The embodiments of this application can realize a scenario where the client user logic dominates DMA transfer without adding logic code to establish a descriptor queue.
[0123] Please see Figure 6The diagram illustrates a data transmission method according to an embodiment of this application. This method is applied to a processor in an electronic device connected to a programmable logic device. In this embodiment, the processor receives data transmitted by the programmable logic device. Specifically, it includes steps S601 to S609.
[0124] Step S601: Initialize the descriptor queue.
[0125] The host computer initializes the descriptor queue, including allocating data cache and creating the descriptor queue. Specifically, it obtains the first address in the programmable logic device, determines the second address of the cache space in the electronic device based on the amount of target data, and creates the descriptor queue according to the first address of the target data and the second address of the cache space.
[0126] Step S602: Clear the cache space.
[0127] Clear the cache space to prepare for the processor to receive data.
[0128] Step S603: Determine whether user_event has been received.
[0129] The processor determines whether it has received a user_event. If it has not received one, it continues to wait for the user logic (EP) to send a user event to start transmitting data. If it has received a user_event, it updates the status of the descriptor appendix.
[0130] Step S604: Update the descriptor queue state.
[0131] The descriptor queue includes a second descriptor corresponding to each piece of data to be received. Each second descriptor includes a second starting address, a second destination address, and a data length for the corresponding data to be received. Updating the descriptor queue state means setting the state of each second descriptor to a state of being ready to receive.
[0132] Step S605: Initiate DMA transfer.
[0133] The specific method for initiating DMA transfer is as follows: the descriptor queue is transferred to the direct memory access controller, which triggers the direct memory access controller to obtain the corresponding data to be received based on the second starting address and data length in each second descriptor, and writes the obtained data to be received into the storage space corresponding to the second target address. After successful writing, the controller returns the second preset reply information corresponding to the second descriptor.
[0134] Step S606: Determine whether the transmission is complete.
[0135] The specific operation to determine whether the transmission is complete is to determine whether the second preset reply information has been received. If the second preset reply information is received, it means that the data to be received corresponding to the second preset reply information has been transmitted.
[0136] Step S607: Update the descriptor queue state.
[0137] Updating the descriptor queue state means changing the state of the second descriptor corresponding to the completed data to be received to the received state. The state of the second descriptor determines whether all data to be received has been transmitted. If some data has not been completely transmitted, the DMA continues transmitting data until the state of each second descriptor is in the received state.
[0138] Step S608: Send the read data.
[0139] Step S609: Clear the cache space.
[0140] If the cache space is a fixed cache, the cache space is cleared after all the data to be received corresponding to the second descriptor in the cache space that is in the received state is reported. If the cache space is a non-fixed cache, the cache area is released directly after all the data to be received corresponding to the second descriptor in the cache space that is in the received state is reported.
[0141] The embodiments of this application can realize a scenario where the client user logic dominates DMA transfer without adding logic code to establish a descriptor queue.
[0142] Please refer to Figure 7 This document illustrates a structural block diagram of an electronic device 700 provided in an embodiment of this application. The electronic device 700 can be a communication system. The electronic device 700 in this application is used to connect to a programmable logic device and may include one or more components such as a processor 711, a memory 712, and one or more application programs, wherein the processor 711 is electrically connected to the memory 712, and the one or more programs are configured to execute the methods described in the foregoing embodiments of the test methods.
[0143] Processor 711 may include one or more processing cores. Processor 711 connects to various parts within the electronic device 700 using various interfaces and lines, and performs various functions and processes data of the electronic device 700 by running or executing instructions, programs, code sets, or instruction sets stored in memory 712, and by calling data stored in memory 712. Optionally, processor 711 may be implemented using at least one hardware form of Digital Signal Processing (DSP), Field-Programmable Gate Array (FPGA), or Programmable Logic Array (PLA). Processor 711 may integrate one or more of a Central Processing Unit (CPU), Graphics Processing Unit (GPU), and modem. The CPU primarily handles the operating system, user interface, and computer programs; the GPU is responsible for rendering and drawing the displayed content; and the modem handles wireless communication. It is understood that the modem may also not be integrated into processor 711 and may be implemented separately through a communication chip. Specifically, the methods described in the foregoing embodiments can be executed by one or more processors 711.
[0144] In some implementations, memory 712 may include random access memory (RAM) or read-only memory (ROM). Memory 712 can be used to store instructions, programs, code, code sets, or instruction sets. Memory 712 may include a program storage area and a data storage area, wherein the program storage area may store instructions for implementing an operating system, instructions for implementing at least one function, instructions for implementing the various method embodiments described below, etc. The data storage area may also store data created by the electronic device 700 during use.
[0145] Please refer to Figure 8 This document illustrates a structural block diagram of an electronic device 800 provided in an embodiment of this application. The electronic device 800 includes: a programmable logic device 811; one or more processors 812 connected to the programmable logic device 811; a memory 813; and one or more application programs, wherein the one or more application programs are stored in the memory 813, and are configured to be executed by the one or more processors, and are configured to perform the methods described above.
[0146] Please refer to Figure 9 This diagram illustrates a structural block diagram of a computer-readable medium provided in an embodiment of this application. The computer-readable storage medium 900 stores program code that can be called by a processor to execute the methods described in the above method embodiments.
[0147] The computer-readable storage medium 900 may be an electronic memory such as flash memory, EEPROM (Electrically Erasable Programmable Read-Only Memory), EPROM, hard disk, or ROM. Optionally, the computer-readable storage medium 900 includes a non-transitory computer-readable storage medium. The computer-readable storage medium 900 has storage space for program code 910 that performs any of the method steps described above. This program code can be read from or written to one or more computer program products. The program code 910 may, for example, be compressed in a suitable form.
[0148] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.
Claims
1. A data transmission method, characterized by, A processor applied to an electronic device, the processor being connected with a programmable logic device, the method comprising: obtaining a first address in the programmable logic device, the storage space corresponding to the first address being used for storing target data, the target data being to-be-sent data or to-be-received data; determining a second address of a cache space in the electronic device based on a data amount of the target data; creating a descriptor queue according to the first address of the target data and the second address of the cache space; if a transmission instruction of the programmable logic device is received, transmitting the descriptor queue to a direct memory access controller, the direct memory access controller being used for transmitting the target data between the cache space and the programmable logic device based on the descriptor queue.
2. The method of claim 1, wherein, The target data is composed of a plurality of to-be-sent data, the descriptor queue includes a first descriptor corresponding to each to-be-sent data, each first descriptor includes a first start address, a first target address and a data length of the corresponding to-be-sent data, the first start address is included in the second address, the first target address is included in the first address, and if the transmission instruction of the programmable logic device is received, the descriptor queue is transmitted to the direct memory access controller, which includes: writing the to-be-sent data corresponding to each first descriptor into the cache space; if the transmission instruction of the programmable logic device is received, setting the state of each first descriptor to a to-be-sent state; transmitting the descriptor queue to the direct memory access controller, triggering the direct memory access controller to obtain the to-be-sent data based on the first start address and the data length in each first descriptor, and write the obtained to-be-sent data into the storage space corresponding to the first target address, and return the first preset reply information corresponding to the first descriptor after successful writing; modifying the state of the first descriptor corresponding to the received first preset reply information to a sent state.
3. The method of claim 2, wherein, After the state of the first descriptor corresponding to the received first preset reply information is modified to the sent state, it further includes: if the state of each first descriptor is the sent state, clearing or releasing the cache space.
4. The method of claim 1, wherein, The target data is composed of a plurality of to-be-received data, the descriptor queue includes a second descriptor corresponding to each to-be-received data, each second descriptor includes a second start address, a second target address and a data length of the corresponding to-be-received data, the second start address is included in the first address, the second target address is included in the second address, and if the transmission instruction of the programmable logic device is received, the descriptor queue is transmitted to the direct memory access controller, which includes: emptying the cache space; if the transmission instruction of the programmable logic device is received, setting the state of each second descriptor to a to-be-received state; transmitting the descriptor queue to a direct memory access controller, triggering the direct memory access controller to acquire corresponding to-be-received data based on the second start address and the data length in each second descriptor, and write the acquired to-be-received data into a storage space corresponding to the second target address, and return second preset reply information corresponding to the second descriptor after successful writing; modifying a state of the second descriptor corresponding to the received second preset reply information to a received state.
5. The method of claim 4, wherein, After the state of the second descriptor corresponding to the received second preset reply information is modified to the received state, the method further includes: transmitting to-be-received data corresponding to the second descriptor stored in the cache space and in the received state to a preset storage space; emptying the cache space.
6. The method of claim 5, wherein, After the cache space is emptied, the method further includes: determining whether the state of each second descriptor is in the received state; if the state of the second descriptor is not in the received state, returning to execute the step of modifying the state of the second descriptor corresponding to the received second preset reply information to the received state and subsequent steps until the state of each second descriptor is in the received state.
7. The method of claim 1, wherein, The direct memory access controller is arranged in the electronic device and is connected with the processor.
8. An electronic device, comprising: For connection with a programmable logic device, comprising: one or more processors; a memory; one or more application programs, wherein the one or more application programs are stored in the memory, the one or more application programs are configured to be executed by the one or more processors, and the one or more application programs are configured to execute the method according to any one of claims 1-7.
9. An electronic device, comprising: comprising: a programmable logic device; one or more processors connected with the programmable logic device; a memory; one or more application programs, wherein the one or more application programs are stored in the memory, the one or more application programs are configured to be executed by the one or more processors, and the one or more application programs are configured to execute the method according to any one of claims 1-7.
10. A computer-readable storage medium, characterized in that, The computer readable storage medium stores program codes, and the program codes can be called and executed by the processor to execute the method according to any one of claims 1-7.