Oscillation signal generating circuit and oscillation signal generating method

Abstract

The invention provides an oscillation signal generating circuit and an oscillation signal generating method. The oscillation signal generating circuit comprises a first circuit and a second circuit. The first circuit is used for generating an output signal according to a reference clock signal and a feedback clock signal. The first circuit includes a voltage-controlled oscillator. The voltage-controlled oscillator is used for outputting an output signal, and the frequency of the output signal is controlled by the control voltage. The second circuit includes a voltage compensation circuit and a maximum phase difference detector. When the maximum phase difference detector detects the maximum phase difference, the maximum phase difference detector controls the voltage compensation circuit to compensate the control voltage to the target voltage.

Description

Technical Field

[0001] This invention relates to an oscillation signal generation circuit and an oscillation signal generation method, and more particularly to an oscillation signal generation circuit and an oscillation signal generation method that can be quickly locked. Background Technology

[0002] Radar sensors based on stepped-frequency continuous wave (SFCW) have a limited time to transmit signals across the entire operating frequency range. To ensure accurate extraction of target information, a phase-locked loop (PLL) circuit capable of rapid locking becomes a critical requirement.

[0003] To address the aforementioned issues, known techniques often involve increasing the operating bandwidth of the phase-locked loop (PLL) circuit. However, using increased PLL bandwidth to achieve fast locking can result in excessive phase noise in the signal. Therefore, balancing locking speed and noise performance is an important challenge for those skilled in the art. Summary of the Invention

[0004] This invention provides an oscillation signal generation circuit and an oscillation signal generation method, which can quickly complete the frequency and / or phase locking of the output signal.

[0005] The oscillation signal generation circuit of the present invention includes a first circuit and a second circuit. The first circuit is used to generate an output signal based on a reference clock signal and a feedback clock signal. The first circuit includes a voltage-controlled oscillator (VCO). The VCO outputs an output signal, and the frequency of the output signal is controlled by a control voltage. The second circuit is coupled to the first circuit. The second circuit includes a voltage compensation circuit and a maximum phase difference detector. The maximum phase difference detector is coupled to the voltage compensation circuit. When the maximum phase difference detector detects a maximum phase difference, it controls the voltage compensation circuit to compensate the control voltage to a target voltage.

[0006] The oscillation signal generation method of the present invention includes: generating an output signal based on a reference clock signal and a feedback clock signal; controlling the frequency of the output signal by a voltage-controlled oscillator according to a control voltage and outputting an output signal; detecting a maximum phase difference; and, when the maximum phase difference is detected, compensating the control voltage to a target voltage.

[0007] Based on the above, the oscillation signal generation circuit of the present invention uses a maximum phase difference detector to detect the maximum phase difference, and when the maximum phase difference is detected, compensates the control voltage of the voltage-controlled oscillator to a target value. In this way, the oscillation signal generation circuit can quickly complete the frequency and / or phase locking operation of the output signal, improving the operating performance of the oscillation signal generation circuit. Attached Figure Description

[0008] Figure 1 A schematic diagram of an oscillation signal generation circuit according to an embodiment of the present invention is shown.

[0009] Figure 2 A schematic diagram of an oscillation signal generation circuit according to another embodiment of the present invention is shown.

[0010] Figure 3 A schematic diagram of an oscillation signal generation circuit according to another embodiment of the present invention is shown.

[0011] Figure 4A A flowchart illustrating the operation of the oscillation signal generation circuit according to an embodiment of the present invention is shown.

[0012] Figures 4B to 4D A waveform diagram illustrating the operation flow of the oscillation signal generation circuit according to an embodiment of the present invention is shown.

[0013] Figures 5A to 5C A schematic diagram illustrating the maximum phase difference detection operation of an embodiment of the present invention is shown.

[0014] Figure 6 A schematic diagram illustrating an embodiment of the maximum phase difference detector of the present invention is shown.

[0015] Figure 7 A schematic diagram illustrating an embodiment of the charge pump in the oscillation signal generation circuit of the present invention is shown.

[0016] Figure 8 A schematic diagram of an oscillation signal generation circuit according to another embodiment of the present invention is shown.

[0017] Figure 9 A flowchart illustrating an embodiment of the present invention for generating an oscillation signal is shown.

[0018] Symbol explanation:

[0019] 100, 200, 300, 800: Oscillation signal generation circuit

[0020] 110, 210, 310, 810: First circuit

[0021] 111, 211, 311, 811: Voltage-controlled oscillators

[0022] 120, 220, 320, 820: Second circuit

[0023] 121, 221, 321, 600, 821: Maximum phase difference detector

[0024] 122, 222, 322, 822: Voltage compensation circuits

[0025] 212, 312, 812: Loop filters

[0026] 213, 313, 813: Charge pump (CP)

[0027] 214, 314, 814: Phase Frequency Detector (PFD)

[0028] 215, 315, 815: Frequency dividers

[0029] 216, 316: Phase compensation circuit

[0030] 2161, 8161, 8162: Switching circuits

[0031] 2162: Phase Adjuster

[0032] 411, 412, 421, 422, 431, 432, 510, 520: Curves

[0033] 610: Digital Logic Circuits

[0034] 620: Time-Domain Voltage Conversion Circuit

[0035] 630: Comparator

[0036] 700: Charge Pump

[0037] C1, C2: Capacitors

[0038] DIV, DIV': Feedback clock signal

[0039] DS: DC signal

[0040] FLK: Locked Frequency

[0041] FST: Start Frequency

[0042] IS1, IS2: Current source

[0043] MG: Locked Zone

[0044] N: divisor

[0045] OUT: Output signal

[0046] PM: Maximum phase difference

[0047] R1: Resistor

[0048] REF, REF': Reference clock signal

[0049] REFI: Reference signal input terminal

[0050] RST: Reset signal

[0051] S1~S6: Sampling points

[0052] S410~S440, S910~S940: Steps

[0053] Spc: Phase compensation signal

[0054] Svc: Voltage compensation signal

[0055] SW1, SW2: Switches

[0056] tp1~tp3: Time interval

[0057] TV1~TV6: Voltage

[0058] Tx: Time point

[0059] UP, DN: Signals

[0060] Vc: Capacitor voltage

[0061] Vctrl: Control voltage

[0062] VLK: Target Voltage

[0063] VS1~VS3, VD1: Reference voltage

[0064] VST: Starting voltage Detailed Implementation

[0065] Please refer to Figure 1 , Figure 1 A schematic diagram of an oscillation signal generation circuit according to an embodiment of the present invention is shown. The oscillation signal generation circuit 100 includes a first circuit 110 and a second circuit 120. The first circuit 110 and the second circuit 120 are coupled to each other. The first circuit 110 generates an output signal OUT based on a reference clock signal REF and a feedback clock signal DIV. The first circuit 110 includes a voltage-controlled oscillator 111, wherein the voltage-controlled oscillator 111 receives a control voltage Vctrl and generates the output signal OUT according to the control voltage Vctrl. The voltage-controlled oscillator 111 can control the frequency of the output signal OUT according to the voltage value of the control voltage Vctrl. In this embodiment, the feedback clock signal DIV can be generated by dividing the output signal OUT by a certain frequency. In some embodiments of the present invention, the feedback clock signal DIV can also be generated by directly feeding back the output signal OUT. In one embodiment, the oscillation signal generation circuit 100 can be applied to a radar sensor with a stepped frequency continuous wave. The waveform of the output signal OUT includes a stepped frequency continuous wave, and its target frequency is a locked frequency. The radar sensor may further include a transmitting circuit, a receiving circuit, and an antenna. The transmitting circuit / receiving circuit transmits / receives wireless signals via the antenna according to the output signal OUT generated by the oscillation signal generation circuit 100, so as to detect the spatial information of external objects.

[0066] The second circuit 120 includes a maximum phase difference detector 121 and a voltage compensation circuit 122. The maximum phase difference detector 121 is coupled to the voltage compensation circuit 122. The maximum phase difference detector 121 can receive a feedback clock signal DIV and a reference clock signal REF, and perform maximum phase difference detection based on the feedback clock signal DIV and the reference clock signal REF. Specifically, the maximum phase difference detector 121 detects the maximum phase difference by detecting whether the phase difference between the feedback clock signal DIV and the reference clock signal REF is the maximum value. For example, the maximum phase difference detector 121 can use multiple phase differences between the feedback clock signal DIV and the reference clock signal REF measured for multiple cycles to form multiple discrete signals, which are then processed to obtain the aforementioned maximum phase difference. Further operational instructions can be found in the following description. Figures 5A to 5C The description is as follows: When the maximum phase difference is detected, the maximum phase difference detector 121 controls the voltage compensation circuit 122 to compensate the control voltage Vctrl to a target voltage. Furthermore, the maximum phase difference detector 121 can correspondingly generate a voltage compensation signal Svc, and can control the voltage compensation circuit 122 by providing the voltage compensation signal Svc to the voltage compensation circuit 122. The voltage compensation signal Svc can be considered as a signal to activate the voltage compensation circuit 122, causing the voltage compensation circuit 122 to provide the control voltage Vctrl, wherein the control voltage Vctrl at this time is compensated to the target voltage.

[0067] In this embodiment, when the maximum phase difference detector 121 detects the aforementioned maximum phase difference state, it can be determined that the frequency of the output signal OUT has initially reached a target locking frequency. Therefore, when the maximum phase difference is detected by the maximum phase difference detector 121, the oscillation signal generation circuit 100 of this embodiment can quickly complete the frequency locking action of the output signal OUT by directly compensating the control voltage Vctrl to the target voltage.

[0068] Please refer to Figure 2 , Figure 2A schematic diagram of an oscillation signal generation circuit according to another embodiment of the present invention is shown. The oscillation signal generation circuit 200 includes a first circuit 210 and a second circuit 220 coupled to each other. The first circuit 210 includes a voltage-controlled oscillator 211, a loop filter 212, a charge pump (CP) 213, a phase frequency detector (PFD) 214, and a frequency divider 215. The voltage-controlled oscillator 211, the loop filter 212, the charge pump 213, the phase frequency detector 214, and the frequency divider 215 form a phase-locked loop (PLL) circuit. The voltage-controlled oscillator 211 can generate a periodic output signal OUT according to the control voltage Vctrl on the loop filter 212. The frequency divider 215 is coupled between the voltage-controlled oscillator 211 and the phase frequency detector 214. The frequency divider 215 can perform a divisor N operation on the frequency of the output signal OUT, thereby generating a feedback clock signal DIV.

[0069] Phase frequency detector 214 is coupled to voltage-controlled oscillator 211 and receives a reference clock signal REF or REF' and a feedback clock signal DIV. It generates signals UP and DN by detecting the frequency and phase differences between the reference clock signal REF or REF' and the feedback clock signal DIV. Signals UP and DN indicate whether the frequency of the detected reference clock signal (REF or REF') is leading or lagging behind the feedback clock signal DIV. Phase frequency detector 214 also receives a reset signal RST and resets its phase frequency detection operation according to the reset signal RST. Charge pump 213 is coupled to voltage-controlled oscillator 211 and receives signals UP and DN. Under normal circumstances, for example, when the maximum phase difference detector 221 does not detect the maximum phase difference, charge pump 213 performs a charge pump boost / buck operation according to signals UP and DN to generate a control voltage Vctrl. The frequency and phase of the output signal OUT are controlled by adjusting the voltage value of the control voltage Vctrl.

[0070] A loop filter 212 is coupled to a voltage-controlled oscillator 211 and a voltage compensation circuit 222. The input terminal of the loop filter 212 has a control voltage Vctrl. The loop filter 212 includes capacitors C1 and C2 and a resistor R1. Capacitor C2 and resistor R1 are connected in series between the control voltage Vctrl and a reference voltage VS1. Capacitor C1 is coupled between the control voltage Vctrl and a reference voltage VS2. The terminals of capacitor C2 and resistor R1 are mutually coupled and receive a capacitor voltage Vc. In this embodiment, the reference voltages VS1 and VS2 may be the same or different. The loop filter 212 in this embodiment can be a low-pass filter.

[0071] The second circuit 220 includes a maximum phase difference detector 221, a phase compensation circuit 216, and a voltage compensation circuit 222. The maximum phase difference detector 221 receives signals UP, DN, a feedback clock signal DIV, a reference clock signal REF, and a reset signal RST. The maximum phase difference detector 221 can detect whether a maximum phase difference occurs between the feedback clock signal DIV and the reference clock signal REF based on the signals UP, DN, DIV, and REF, and generate a voltage compensation signal Svc and a phase compensation signal Spc accordingly. It should be noted that the reset signal RST, in addition to controlling the reset operation of the phase frequency detector 214 as described above, is also provided to the maximum phase difference detector 221 as a reference clock for the operation timing of the comparator in the maximum phase difference detector 221, which will be used in conjunction with... Figure 6 Please provide an explanation.

[0072] In this embodiment, the phase compensation circuit 216 includes a switching circuit 2161 and a phase adjuster 2162. The phase compensation circuit 216 is coupled to the phase frequency detector 214 and the maximum phase difference detector 221, and is coupled between the reference signal input terminal REFI and the phase frequency detector 214. The reference clock signal REF comes from the reference signal input terminal REFI. The phase compensation circuit 216 can receive the reference clock signal REF and provide the reference clock signal REF or a phase-adjusted reference clock signal REF' to the phase frequency detector 214. In addition, the phase compensation circuit 216 is used to adjust the reference clock signal REF; specifically, the phase adjuster 2162 of the phase compensation circuit 216 is used to adjust the phase of the reference clock signal REF to generate the reference clock signal REF'. The switching circuit 2161 receives the phase compensation signal Spc and determines whether to output the reference clock signal REF or REF' to the phase frequency detector 214 based on the phase compensation signal Spc. Before the maximum phase is detected, the switching circuit 2161 can output a reference clock signal REF to the phase frequency detector 214; when the maximum phase is detected, the switching circuit 2161 can output a reference clock signal REF' to the phase frequency detector 214. That is, when the maximum phase difference detector 221 detects the maximum phase difference, the phase compensation circuit 216 compensates the phase of the reference clock signal REF to form a phase-adjusted reference clock signal REF', thereby making the phase of the reference clock signal REF' approximately consistent with the phase of the feedback clock signal DIV, thus completing the phase compensation operation.

[0073] Furthermore, when the maximum phase difference is detected, the maximum phase difference detector 221 can generate a corresponding phase compensation signal Spc, so that the phase compensation circuit 216 outputs an adjusted reference clock signal REF' to the phase frequency detector 214. The reference clock signal REF' is generated by offsetting the reference clock signal REF by a phase compensation amount, so that the phase of the reference clock signal REF' and the feedback clock signal DIV can be nearly synchronized. The phase compensation amount is, for example, in the form of a signal waveform period, such as 0.1 signal waveform periods, 0.3 signal waveform periods, or 0.5 signal waveform periods, etc. The phase compensation amount can be recorded in a lookup table, which can be set in the phase adjuster 2162 in the form of a memory or a temporary register. In this embodiment, the phase adjuster 2162 can delay the phase of the reference clock signal REF to generate the reference clock signal REF'. In other embodiments, the phase adjuster 2162 can also advance the phase of the reference clock signal REF to generate the reference clock signal REF'.

[0074] The voltage compensation circuit 222 receives a voltage compensation signal Svc, a control voltage Vctrl, and a reference clock signal REF. The voltage compensation circuit 222 can generate a target voltage based on the control voltage Vctrl and provide the target voltage to generate a new control voltage Vctrl, thus completing the voltage compensation operation. Furthermore, when the maximum phase difference detector 221 detects a maximum phase difference, it outputs a voltage compensation signal Svc to the voltage compensation circuit 222. The voltage compensation circuit 222 compensates the control voltage Vctrl to the target voltage and provides it to the loop filter 212. At this time, the loop between the charge pump 213 and the loop filter 212 is temporarily disconnected. Specifically, when the maximum phase difference is detected, the voltage compensation circuit 222 can calculate the sampled voltages at multiple sampling time points corresponding to the control voltage Vctrl based on the voltage compensation signal Svc, and calculate the average value of these sampled voltages to generate the target voltage. The voltage compensation circuit 222 can generate the aforementioned multiple sampling time points based on the reference clock signal REF. Next, the voltage compensation circuit 222 can output the obtained target voltage through a voltage buffer to serve as the new control voltage Vctrl and capacitor voltage Vc of the loop filter 212, thereby enhancing the locking action of the output signal OUT. In another embodiment, a normally closed bypass switch (not shown) can be connected in parallel across the resistor R1. When the voltage compensation circuit 222 outputs the new control voltage Vctrl, the bypass switch can be briefly turned on, for example, by the maximum phase difference detector 221, so that the capacitor voltage Vc becomes equal to the new control voltage Vctrl more quickly. In this architecture, the voltage compensation circuit 222 can achieve voltage compensation operation by outputting either the control voltage Vctrl or the capacitor voltage Vc to the loop filter 212 through a single output terminal.

[0075] In the above description, the generation of the sampling voltage and the calculation of the average value can be implemented using sample and hold (S / H) circuits and voltage average value generation circuits (such as average voltage filters) that are well known to those skilled in the art, without any fixed limitations.

[0076] Please refer to the following: Figure 3 , Figure 3 A schematic diagram of an oscillation signal generation circuit according to another embodiment of the present invention is shown. The oscillation signal generation circuit 300 includes a first circuit 310 and a second circuit 320 coupled to each other. The first circuit 310 includes a voltage-controlled oscillator 311, a loop filter 312, a charge pump 313, a phase-frequency detector 314, and a frequency divider 315. The second circuit 320 includes a phase compensation circuit 316, a maximum phase difference detector 321, and a voltage compensation circuit 322.

[0077] Unlike the oscillation signal generation circuit 200 of the previous embodiment, the phase compensation circuit 316 of this embodiment is coupled in the path from the frequency divider 315 to the phase frequency detector 314. In detail, the phase compensation circuit 316 is used to perform phase adjustment on the feedback clock signal DIV generated by the frequency divider 315, thereby generating an adjusted feedback clock signal DIV'. In this embodiment, the phase compensation circuit 316 can shift the phase of the feedback clock signal DIV by a phase compensation amount, thereby generating the feedback clock signal DIV'. As mentioned above, the phase compensation amount is, for example, in the form of the signal waveform period. Furthermore, when the maximum phase difference detector 321 detects the maximum phase difference, the phase compensation circuit 316 compensates for the phase of the feedback clock signal DIV to form the phase-adjusted feedback clock signal DIV', thereby making the phase of the reference clock signal REF nearly coincide with the phase of the feedback clock signal DIV'. In this embodiment, the phase adjuster 316 can lead the phase of the feedback clock signal DIV to generate the feedback clock signal DIV'. In other embodiments, the phase adjuster 316 can also delay the phase of the feedback clock signal DIV to generate the feedback clock signal DIV'.

[0078] Furthermore, the phase compensation circuit 316 can determine the phase compensation amount of the feedback clock signal DIV by interpolating elements.

[0079] Incidentally, in the oscillation signal generation circuit 300 of this embodiment and the oscillation signal generation circuit 200 of the aforementioned embodiment, the voltage-controlled oscillator 311, 211, loop filter 312, 212, charge pump 313, 213, phase frequency detector 314, 214, frequency divider 315, 215 can all be implemented using relevant circuit architectures well known to those skilled in the art, without any specific limitations.

[0080] Furthermore, the maximum phase difference detector 321 and the voltage compensation circuit 322 in this embodiment can be respectively connected to... Figure 2 The maximum phase difference detector 221 and voltage compensation circuit 222 in the embodiment have the same circuit architecture and operation method, which will not be described in detail here.

[0081] Please refer to the following: Figure 4A as well as Figures 4B to 4D ,in Figure 4A A flowchart illustrating the operation of the oscillation signal generation circuit according to an embodiment of the present invention is provided. Figures 4B to 4D A waveform diagram illustrating the operation flow of the oscillation signal generation circuit according to an embodiment of the present invention is shown. Figure 4B This is a graph showing the relationship between the frequency and time of the output signal; Figure 4C This is a graph showing the relationship between the phase difference and time between the corresponding reference clock signal REF and the feedback clock signal DIV. Figure 4DThis is a graph showing the relationship between capacitor voltage Vc and time.

[0082] exist Figure 4A In step S410, the maximum phase difference detector in the oscillation signal generation circuit can perform the detection action of the maximum phase difference, and when the maximum phase difference state is detected, proceed to step S420. Figure 4B In the diagram, curve 412 represents the frequency change curve of the output signal from the oscillation signal generation circuit without the application of this embodiment, while curve 411 represents the frequency change curve of the output signal from the oscillation signal generation circuit of this embodiment. Specifically, between time point 0 and time point tx, the frequency of the output signal in curves 411 and 412 can rise from the initial frequency FST to the locking frequency FLK and enter the locking interval MG.

[0083] exist Figure 4C In the diagram, curve 422 represents the phase difference change curve between the corresponding reference clock signal REF and the feedback clock signal DIV in the oscillation signal generation circuit without the application of this embodiment, while curve 421 represents the phase difference change curve between the corresponding feedback clock signal DIV and the reference clock signal REF in the oscillation signal generation circuit of this embodiment. Specifically, between time point 0 and time point tx, the phase difference between the corresponding reference clock signal REF and the feedback clock signal DIV in curves 421 and 422 can both increase from an initial phase difference of 0 to a maximum phase difference PM.

[0084] exist Figure 4D In the diagram, curve 432 represents the change curve of the capacitor voltage Vc in the oscillation signal generation circuit without the application of this embodiment, while curve 431 represents the change curve of the capacitor voltage Vc in the oscillation signal generation circuit of this embodiment. Specifically, between time point 0 and time point tx, in curves 431 and 432, the capacitor voltage Vc can rise from the initial voltage VST to a voltage value lower than the target voltage VLK.

[0085] Next, in step S420, the oscillation signal generation circuit removes the phase difference between the reference clock signal and the feedback clock signal. Step S420 can be executed in conjunction with step S430, where the phase compensation circuit in the oscillation signal generation circuit removes the phase difference between the reference clock signal and the feedback clock signal by adjusting the phase of either the reference clock signal or the feedback clock signal. Furthermore, in step S440, the oscillation signal generation circuit sets the control voltage to equal the target voltage. In this embodiment, "removing the phase difference" does not necessarily mean "completely removing the phase difference," but can also mean "removing the phase difference to an appropriate error range"; for example, it could mean "removing the phase difference to within 10% of the original phase difference."

[0086] Corresponding to Figures 4B to 4D ,exist Figure 4C In curve 421, the phase difference between the reference clock signal and the feedback clock signal is removed at time point tx. That is, at time point tx, the phase difference between the reference clock signal and the feedback clock signal decreases, for example, to zero. Figure 4D In curve 431, at time point tx, the capacitor voltage Vc is directly set to be equal to the target voltage VLK. That is, at time point tx, the capacitor voltage Vc is increased to the target voltage VLK. Correspondingly, at... Figure 4B At time point tx, in curve 411, the frequency of the output signal can be quickly locked in the locking interval MG corresponding to the locking frequency FLK.

[0087] For details regarding the operation of the maximum phase difference detector in this embodiment of the invention, please refer to... Figures 5A to 5C A schematic diagram illustrating the maximum phase difference detection operation of an embodiment of the present invention. Figures 5A to 5C The multiple steps of the maximum phase difference detection operation are illustrated separately. Among them, in Figure 5A In the diagram, curve 510 represents the phase difference variation curve. In the first step, the maximum phase difference detector can set multiple sampling points on the phase curve 510 and generate phase differences for each of the multiple sampling points S1 to S6.

[0088] Next, in the second step, in Figure 5B In this process, the maximum phase difference detector can distinguish multiple sampling points S1 to S6 into multiple odd sampling points S1, S3, S5 and multiple even sampling points S2, S4, S6.

[0089] In the third step, Figure 5C In the process, the maximum phase difference detector can perform time-voltage conversion on the phase difference of multiple sampling points S1 to S6, and obtain voltages TV1 to TV6 corresponding to multiple sampling points S1 to S6 and distributed on curve 520, where voltages TV1, TV3, and TV5 are odd voltages, and voltages TV2, TV4, and TV6 are even voltages.

[0090] Furthermore, the maximum phase difference detector can calculate the trend of voltage change from TV1 to V6, i.e., the polarity of the slope, by comparing voltages TV1, TV3, and TV5 with voltages TV2, TV4, and TV6, respectively. In this embodiment, the slope is positive during the time interval tp1 between voltages TV1 and TV2; positive during the time interval tp2 between voltages TV3 and TV4; and negative during the time interval tp3 between voltages TV5 and TV6.

[0091] By changing the slope from positive to negative, the maximum phase difference detector can detect the occurrence of the maximum phase difference between time intervals tp2 and tp3. In other words, when the magnitude change trends of the first two voltages TV1 to TV6 are opposite to the magnitude change trends of the latter two voltages TV1 to TV6, the maximum phase difference detector determines that the maximum phase difference has been detected.

[0092] It is worth noting that the implementation details of the maximum phase difference detector can be found in the following references. Figure 6 The illustration shows a schematic diagram of an embodiment of the maximum phase difference detector of the present invention. The maximum phase difference detector 600 includes a digital logic circuit 610, a time-domain voltage conversion circuit 620, and a comparator 630. The digital logic circuit 610 can sequentially record the phase difference at least four time points based on a reference clock signal REF and a feedback clock signal DIV. In this embodiment, for example, it records the phase difference at six time points, generating multiple sampling points S1 to S6 with phase differences. The digital logic circuit 610 then distinguishes the sampling points S1 to S6 into multiple odd-numbered sampling points S1, S3, and S5, and multiple even-numbered sampling points S2, S4, and S6. The time-domain voltage conversion circuit 620 can be used to obtain voltages TV1, TV3, and TV5 corresponding to each odd-numbered sampling point S1, S3, and S5, and voltages TV2, TV4, and TV6 corresponding to each even-numbered sampling point S2, S4, and S6.

[0093] Comparator 630 can be used to sequentially compare voltages TV1 and TV2; compare voltages TV3 and TV4; and then compare voltages TV5 and TV6 to generate multiple change slopes. Furthermore, comparator 630 can receive a reset signal RST and can use the reset signal RST to control the timing of the above comparison operations; for example, when the phase frequency detector (PFD) 214 resets its phase frequency detection operation according to the reset signal RST to obtain a new set of phase differences between the reference clock signal REF and the feedback clock signal DIV, comparator 630 also compares the voltages converted from the above phase differences according to the reset signal RST. In this embodiment, taking voltages TV1 and TV2 as an example, when voltage TV1 is not greater than voltage TV2, the corresponding change slope is positive; when voltage TV1 is greater than voltage TV2, the corresponding change slope is negative. The maximum phase difference detector can obtain the time interval in which the maximum phase difference is generated by determining the state where the change slope changes from positive to negative polarity.

[0094] In the above description, the circuit architectures of the time-domain voltage conversion circuit 620 and the comparator 630 in the maximum phase difference detector 600 are well known to those skilled in the art and will not be described in detail here. The digital logic circuit 610 can be obtained using digital circuit design methods well known to those skilled in the art (such as hardware description languages ​​or gate-level design), without any particular limitations. Furthermore, the maximum phase difference detector 600 can be applied to... Figure 2 The maximum phase difference detector 221 in the oscillation signal generation circuit 200 and Figure 3 The maximum phase difference detector 321 in the oscillation signal generation circuit 300.

[0095] Please refer to Figure 7 , Figure 7 A schematic diagram illustrating an embodiment of the charge pump in the oscillation signal generation circuit of the present invention is shown. The charge pump 700 includes current sources IS1 and IS2, and switches SW1 and SW2. Current sources IS1, SW1, and SW2 are sequentially coupled between reference voltage terminals VD1 and VS3. Switches SW1 and SW2 are controlled by signals UP and DN, respectively. The mutual coupling terminals of switches SW1 and SW2 provide a control voltage Vctrl.

[0096] Switch SW1 is turned on or off according to the voltage level of signal UP, and switch SW2 is turned on or off according to the voltage level of signal DN. When switch SW1 is on and switch SW2 is off, the control voltage Vctrl can be pulled high; when switch SW2 is on and switch SW1 is off, the control voltage Vctrl can be pulled low. The charge pump 700 can be applied to... Figure 2 The charge pump 213 in the oscillation signal generation circuit 200 and Figure 3 The charge pump 313 in the oscillation signal generation circuit 300, and the reference Figure 7 , Figure 2 and Figure 3 When the maximum phase difference detector 221 / 321 detects the maximum phase difference, the voltages of the signals UP and DN received by the charge pump 213 / 313 / 700 are both the first voltage, which can be a 0-volt voltage or a low voltage, and the switches SW1 and SW2 are simultaneously turned off. After the phase compensation operation and voltage compensation operation are completed, the signals UP and DN return to pulse signals to dynamically correct the control voltage Vctrl.

[0097] Please refer to the following: Figure 8 , Figure 8A schematic diagram of an oscillation signal generation circuit according to another embodiment of the present invention is shown. The oscillation signal generation circuit 800 includes a first circuit 810 and a second circuit 820 coupled to each other. The first circuit 810 includes a voltage-controlled oscillator 811, a loop filter 812, a charge pump 813, a phase-frequency detector 814, and a frequency divider 815. The second circuit 820 includes a maximum phase difference detector 821 and a voltage compensation circuit 822.

[0098] and Figure 2 The implementation examples are different. Figure 8 The oscillation signal generation circuit 800 does not include a phase compensation circuit, and the first circuit 810 of the oscillation signal generation circuit 800 further includes a switching circuit 8161 and a switching circuit 8162. The phase frequency detector 814 is coupled to the voltage-controlled oscillator 811, and the frequency divider 815 is coupled between the voltage-controlled oscillator 811 and the phase frequency detector 814. The switching circuit 8162 is coupled between the frequency divider 815, the phase frequency detector 814, and the maximum phase difference detector 821. That is, the switching circuit 8162 is coupled in the path from the frequency divider 815 to the phase frequency detector 814. The switching circuit 8161 is coupled to the phase frequency detector 814 and the maximum phase difference detector 821; that is, the switching circuit 8161 is coupled in the path where the phase frequency detector 814 receives the reference clock signal REF provided by the reference signal input terminal REFI. Switching circuit 8161 outputs a DC signal DS to one input terminal of phase frequency detector 814 when maximum phase difference detector 821 detects maximum phase difference. Switching circuit 8162 also outputs a DC signal DS to the other input terminal of phase frequency detector 814 when maximum phase difference detector 821 detects maximum phase difference. The DC signal DS can be a 0-volt voltage, or it can be a low voltage, so that the voltage of signals UP and DN output by phase frequency detector 814 is 0 volts or a low voltage, thereby making the output terminal of charge pump 813 high impedance, and the loop between charge pump 813 and loop filter 812 is disconnected.

[0099] It should be noted that, Figure 8 The oscillation signal generation circuit 800 only performs frequency locking operation and not phase locking operation. In this way, the oscillation signal generation circuit 800 only performs voltage compensation operation and not phase compensation operation. Figure 7 The charge pump 700 can also be applied to Figure 8 The charge pump 813 in the oscillation signal generation circuit 800, but its operation is similar to that applied to Figure 2 , Figure 3 The charge pumps 213 and 313 in the embodiments are not entirely the same. Furthermore, while referring to... Figure 7 and Figure 8Under normal circumstances, for example, when the maximum phase difference detector 821 does not detect the maximum phase difference, the voltage-controlled oscillator 811 changes the frequency of its output signal, and the charge pump 813 operates. At this time, the signals UP and DN received by the charge pump 813 are pulse signals, and the loop of the first circuit 810 is conducting. When the maximum phase difference detector 821 detects the maximum phase difference, the voltages of the signals UP and DN received by the charge pump 813 are both the first voltage, which can be a 0-volt voltage or a low voltage, causing switches SW1 and SW2 to be turned off, and the loop of the first circuit 810 to be disconnected, achieving frequency locking operation. Here, the control voltage Vctrl at this time is provided by a fixed voltage from the voltage compensation circuit 822, that is, the control voltage Vctrl is fixed.

[0100] Please refer to Figure 9 , Figure 9 A flowchart illustrating an embodiment of the oscillation signal generation method of the present invention is shown. In step S910, an output signal can be generated based on a reference clock signal and a feedback clock signal. In step S920, a voltage-controlled oscillator can control the frequency of the output signal according to a control voltage and output an output signal. In step S930, the maximum phase difference is detected. In step S940, when the maximum phase difference is detected, the control voltage is compensated to the target voltage.

[0101] The implementation details of the above steps have been described in detail in the aforementioned embodiments and implementation methods, and will not be repeated here.

[0102] In summary, the oscillation signal generation circuit of the present invention detects the occurrence of the maximum phase difference through a maximum phase difference detector, and sets the control voltage of the oscillator to the target voltage when the maximum phase difference occurs, so that the output signal generated by the oscillation signal generation circuit can quickly lock and improve its working efficiency.

Claims

1. An oscillating signal generating circuit, characterized by, The first circuit is used to generate an output signal according to a reference clock signal and a feedback clock signal, and the first circuit comprises: a voltage-controlled oscillator used to output the output signal, and the frequency of the output signal is controlled by a control voltage; and a second circuit coupled to the first circuit, and the second circuit comprises: a voltage compensation circuit; and a maximum phase difference detector coupled to the voltage compensation circuit; wherein when the maximum phase difference detector detects a maximum phase difference, the maximum phase difference detector controls the voltage compensation circuit to compensate the control voltage to a target voltage. When the maximum phase difference detector detects the maximum phase difference, it is determined that the frequency of the output signal has reached a target locking frequency for the first time.

2. The oscillating signal generating circuit according to claim 1, characterized in that, When the maximum phase difference detector detects the maximum phase difference, it is determined that the reference clock signal and the feedback clock signal have the maximum phase difference.

3. The oscillating signal generation circuit of claim 1, wherein, The second circuit further comprises a phase compensation circuit, and the phase compensation circuit is used to adjust one of the reference clock signal and the feedback clock signal.

4. The oscillating signal generation circuit of claim 1, wherein, The first circuit further comprises a phase frequency detector and a frequency divider, wherein the phase frequency detector is coupled to the voltage-controlled oscillator and used to receive the reference clock signal and the feedback clock signal, the frequency divider is coupled between the voltage-controlled oscillator and the phase frequency detector and used to output the feedback clock signal, the phase compensation circuit is coupled to the phase frequency detector and the maximum phase difference detector, and when the maximum phase difference detector detects the maximum phase difference, the maximum phase difference detector controls the phase compensation circuit to make the phase of the reference clock signal and the phase of the feedback clock signal approach consistent.

5. The oscillating signal generating circuit according to claim 4, characterized in that, The phase compensation circuit is coupled between a reference signal input end and the phase frequency detector, the reference clock signal comes from the reference signal input end, and when the maximum phase difference detector detects the maximum phase difference, the phase compensation circuit compensates the phase of the reference clock signal to make the phase of the reference clock signal and the phase of the feedback clock signal approach consistent.

6. The oscillating signal generating circuit according to claim 5, characterized in that The phase compensation circuit determines the phase compensation amount of the reference clock signal through a lookup table.

7. The oscillating signal generating circuit according to claim 6, characterized in that The phase compensation circuit is coupled between the frequency divider and the phase frequency detector, and when the maximum phase difference detector detects the maximum phase difference, the phase compensation circuit compensates the phase of the feedback clock signal to make the phase of the reference clock signal and the phase of the feedback clock signal approach consistent.

8. The oscillating signal generating circuit according to claim 5, characterized in that, The phase compensation circuit determines the phase compensation amount of the feedback clock signal through an interpolation element.

9. The oscillating signal generating circuit according to claim 8, characterized in that, The first circuit further comprises a charge pump, the charge pump is coupled to the voltage-controlled oscillator and used to receive a first signal and a second signal, and when the maximum phase difference detector detects the maximum phase difference, the voltages of the first signal and the second signal received by the charge pump are both first voltages.

10. The oscillating signal generation circuit of claim 1, wherein, ​ 11. The oscillating signal generation circuit of claim 1, wherein, The first circuit further comprises a phase frequency detector, a frequency divider, a first switch circuit and a second switch circuit, wherein the phase frequency detector is coupled to the voltage controlled oscillator, the frequency divider is coupled between the voltage controlled oscillator and the phase frequency detector, the first switch circuit is coupled to the frequency divider, the phase frequency detector and the maximum phase difference detector, the second switch circuit is coupled to the phase frequency detector and the maximum phase difference detector, when the maximum phase difference detector detects the maximum phase difference, the maximum phase difference detector controls the first switch circuit and the second switch circuit to output a direct current signal to the phase frequency detector.

12. The oscillating signal generation circuit of claim 1, wherein, The maximum phase difference detector comprises a digital logic circuit, a time domain voltage conversion circuit and a comparator, the digital logic circuit is used to record at least four phase differences of time points as a plurality of phase differences, the time domain voltage conversion circuit is used to convert the plurality of phase differences into a plurality of voltages, and the comparator is used to compare the size relationship of the plurality of voltages, when the size change trend of the first two of the plurality of voltages is opposite to the size change trend of the last two of the plurality of voltages, it is judged that the maximum phase difference detector detects the maximum phase difference.

13. The oscillating signal generation circuit of claim 1, wherein, The first circuit further comprises a loop filter, the loop filter is coupled to the voltage controlled oscillator and the voltage compensation circuit, and an input end of the loop filter has the control voltage, the loop filter comprises a resistor and a capacitor, a first end of the resistor is coupled to the input end of the loop filter, a second end of the resistor is coupled to a first end of the capacitor, a second end of the capacitor is coupled to a reference voltage end, the first end of the capacitor has a capacitor voltage, when the maximum phase difference detector detects the maximum phase difference, the maximum phase difference detector controls the voltage compensation circuit to compensate the capacitor voltage to the target voltage.

14. An oscillating signal generating method characterized by comprising: Comprise: generating an output signal according to a reference clock signal and a feedback clock signal; controlling a voltage controlled oscillator according to a control voltage to control the frequency of the output signal and output the output signal; detecting a maximum phase difference; and compensating the control voltage to a target voltage when the maximum phase difference is detected.

15. The oscillating signal generating method according to claim 14, wherein Further comprise: when the maximum phase difference is detected, it is judged that the frequency of the output signal has reached a target locking frequency for the first time.

16. The oscillating signal generating method of claim 14, wherein, Further comprise: when the maximum phase difference is detected, the phase compensation amount of the reference clock signal is determined through a lookup table, and the phase of the reference clock signal is compensated to make the phase of the reference clock signal and the phase of the feedback clock signal tend to be consistent.

17. The oscillating signal generating method of claim 14, wherein, Further comprise: when the maximum phase difference is detected, the phase compensation amount of the feedback clock signal is determined through an interpolation element, and the phase of the feedback clock signal is compensated to make the phase of the reference clock signal and the phase of the feedback clock signal tend to be consistent.

18. The oscillating signal generating method of claim 14, wherein, Further comprise: a charge pump is provided to receive a first signal and a second signal; and When the maximum phase difference is detected, voltages of the first signal and the second signal are both first voltages.

19. The oscillating signal generating method of claim 14, wherein, Further comprising: sequentially recording phase differences at four time points as a plurality of phase differences; converting the plurality of phase differences into a plurality of voltages respectively; comparing size relationships of the plurality of voltages; and when size change trends of the first two of the plurality of voltages are opposite to a size change trend of the last two of the plurality of voltages, it is determined that the maximum phase difference is detected.

20. The oscillating signal generating method of claim 14, wherein, Further comprising: providing a loop filter coupled to the voltage-controlled oscillator; and when the maximum phase difference is detected, a capacitor voltage on a first end of a capacitor coupled to a resistance in the loop filter is compensated to the target voltage.

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