Transistor and manufacturing method of transistor

Abstract

The invention provides a transistor and a manufacturing method of the transistor. The transistor includes: a gate electrode; a semiconductor layer positioned on the gate electrode; a gate insulating layer positioned between the gate electrode and the semiconductor layer; an electrode layer including a source electrode and a drain electrode spaced apart from each other on the semiconductor layer; and an intermediate layer positioned between the semiconductor layer and the electrode layer, and including interlayer patterns overlapping the source electrode and the drain electrode, respectively.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to and all benefits derived therefrom of Korean Patent Application No. 10-2024-0133050, filed on September 30, 2024, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] This disclosure relates to display devices. Specifically, this disclosure relates to transistors included in display devices, methods of manufacturing transistors, and electronic devices including transistors. Background Technology

[0004] Recently, with the increasing interest in information display, research and development of display devices have been continuously carried out.

[0005] The foregoing content is intended only to help understand the background technology of the present disclosure and therefore should not be construed as corresponding to the prior art known to those skilled in the art. Summary of the Invention

[0006] The purpose of this disclosure is to provide a transistor with improved electron mobility.

[0007] The purpose of this disclosure is to provide a display device including transistors with improved electron mobility.

[0008] The purpose of this disclosure is to provide a method for manufacturing a transistor with improved electron mobility.

[0009] The purpose of this disclosure is not limited to the above-described purposes, and other technical purposes not described will be clearly understood by those skilled in the art from the following description.

[0010] According to embodiments of the present disclosure, a transistor includes: a gate electrode; a semiconductor layer disposed on the gate electrode; a gate insulating layer disposed between the gate electrode and the semiconductor layer; an electrode layer including a source electrode and a drain electrode spaced apart from each other on the semiconductor layer; and an intermediate layer disposed between the semiconductor layer and the electrode layer, and including interlayer patterns overlapping the source electrode and the drain electrode, respectively.

[0011] In an embodiment, each of the semiconductor layer and the intermediate layer may include a material having a layered structure.

[0012] In an embodiment, each of the semiconductor layer and the intermediate layer may include a transition metal dichalcogenide (TMDC).

[0013] In one embodiment, the semiconductor layer may include molybdenum disulfide (MoS2).

[0014] In one embodiment, the semiconductor layer may include a layer of molybdenum disulfide.

[0015] In an embodiment, the intermediate layer may include titanium disulfide (TiS2).

[0016] In an embodiment, the thickness of the intermediate layer can be between about 9 nanometers and about 11 nanometers.

[0017] In some embodiments, the electrode layer may include metal.

[0018] According to embodiments of the present disclosure, a display device may include: a substrate; a pixel circuit layer disposed on the substrate and including transistors; and a display element layer disposed on the pixel circuit layer and including light-emitting elements, wherein the transistors may include: a gate electrode; a semiconductor layer disposed on the gate electrode; a gate insulating layer disposed between the gate electrode and the semiconductor layer; an electrode layer including source electrodes and drain electrodes spaced apart from each other on the semiconductor layer; and an intermediate layer disposed between the semiconductor layer and the electrode layer, and including interlayer patterns overlapping the source electrodes and drain electrodes respectively.

[0019] In an embodiment, each of the semiconductor layer and the intermediate layer may include a material having a layered structure.

[0020] In an embodiment, each of the semiconductor layer and the intermediate layer may include a transition metal dichalcogenide (TMDC).

[0021] According to embodiments of the present disclosure, a method for manufacturing a transistor may include: forming a gate electrode; forming a gate insulating layer on the gate electrode; forming a semiconductor layer on the gate insulating layer; and forming an intermediate layer and an electrode layer on the semiconductor layer, wherein the intermediate layer includes interlayer patterns spaced apart from each other, and the electrode layer includes source electrodes and drain electrodes spaced apart from each other and respectively overlapping the interlayer patterns.

[0022] In an embodiment, the method of manufacturing the transistor may further include: forming a photoresist pattern on the semiconductor layer after forming the semiconductor layer and before forming the intermediate layer.

[0023] In this embodiment, the formation of the intermediate layer can be performed using an atomic layer deposition (ALD) process.

[0024] In an embodiment, forming an intermediate layer may include: injecting a precursor into the surface of each of the semiconductor layer and the photoresist pattern; removing the precursor that is not adsorbed onto the surface of each of the semiconductor layer and the photoresist pattern; injecting a reactant into the surface of each of the semiconductor layer and the photoresist pattern; and removing any remaining reactant.

[0025] In an embodiment, the precursor may include tetra(dimethylamino)titanium (TDMAT).

[0026] In the embodiments, the reactants may include hydrogen sulfide (H2S).

[0027] In an embodiment, the method of manufacturing the transistor may further include: after forming an electrode layer, removing a photoresist pattern, and in removing the photoresist pattern, removing a portion of each of the electrode layer and the intermediate layer that overlaps with the photoresist pattern to form an interlayer pattern spaced apart from each other and a source electrode and a drain electrode spaced apart from each other.

[0028] In one embodiment, the semiconductor layer may include molybdenum disulfide.

[0029] In some embodiments, the electrode layer may include metal.

[0030] The electronic device includes: a processor for providing input image data; and a display device for displaying an image based on the input image data, wherein the display device includes: a gate electrode; a semiconductor layer disposed on the gate electrode; a gate insulating layer disposed between the gate electrode and the semiconductor layer; an electrode layer including source electrodes and drain electrodes spaced apart from each other on the semiconductor layer; and an intermediate layer disposed between the semiconductor layer and the electrode layer, and including interlayer patterns overlapping the source electrodes and drain electrodes, respectively.

[0031] Specific details of other embodiments are included in the detailed description and accompanying drawings.

[0032] According to the above embodiments, by configuring an intermediate layer in contact with the semiconductor layer using titanium disulfide and forming the intermediate layer through an atomic layer deposition process, metal-induced gap states (MIGS) and defect-induced gap states (DIGS) of the semiconductor layer can be suppressed. Therefore, Fermi level depinning can occur, and the contact resistance between the semiconductor layer and the intermediate layer can be reduced. Due to the reduced contact resistance, the electron mobility of the transistor can be improved.

[0033] Since each of the semiconductor layer and the intermediate layer comprises a material with a layered structure and includes a transition metal dichalcogenide (TMDC), the semiconductor layer and the intermediate layer can comprise materials from the same family. That is, due to the high compatibility of the material properties of titanium disulfide and molybdenum disulfide, process compatibility between titanium disulfide and molybdenum disulfide can be ensured. Therefore, since the intermediate layer can be easily formed on the semiconductor layer, process efficiency can be improved.

[0034] The effects of the embodiments are not limited to the examples above, and many more different effects are included in this specification. Attached Figure Description

[0035] The above and other features of this disclosure will become more apparent from the accompanying drawings, which describe embodiments of the present disclosure in a further detailed manner:

[0036] Figure 1 This is a block diagram illustrating an embodiment of the display device;

[0037] Figure 2 It is a diagram. Figure 1 A block diagram of an embodiment of one of a plurality of sub-pixels;

[0038] Figure 3 It is a diagram. Figure 1 A plan view of an embodiment of the display panel;

[0039] Figure 4 It is a diagram. Figure 3 A cross-sectional view of an embodiment of the display panel;

[0040] Figure 5 It is a diagram. Figure 3 A cross-sectional view of another embodiment of the display panel;

[0041] Figure 6 The illustration includes Figure 4 or Figure 5 A cross-sectional view of an embodiment of transistors in the pixel circuit layer;

[0042] Figure 7 yes Figure 6 An enlarged cross-sectional view of a portion of the semiconductor layer and intermediate layer;

[0043] Figure 8 It is a diagram. Figure 6 The graph shows the transfer curve of the transistor;

[0044] Figure 9 It is a diagram. Figure 6 The graph shows the transfer curve of the transistor;

[0045] Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 , Figure 15 , Figure 16 , Figure 17 , Figure 18 and Figure 19 It is a diagram. Figure 6 A diagram illustrating an embodiment of a method for manufacturing a transistor;

[0046] Figure 20 This is a block diagram of an electronic device according to an embodiment; and

[0047] Figure 21Schematic diagrams of various embodiments of the electronic device are shown. Detailed Implementation

[0048] This disclosure can be modified in various ways and has various forms. Therefore, specific embodiments will be illustrated in the accompanying drawings and described in detail in the specification. However, it should be understood that this disclosure is not intended to be limited to the specific forms disclosed, and this disclosure includes all modifications, equivalents, and substitutions within the spirit and technical scope of this disclosure.

[0049] In describing each drawing, similar reference numerals are used for similar parts. In the drawings, for clarity of this disclosure, the dimensions of the structures are shown as enlarged from actual dimensions. Terms such as "first," "second," etc., may be used to describe various parts, but parts should not be limited by the terms. The terms are used only for the purpose of distinguishing one part from another. For example, without departing from the scope of this disclosure, a first part may be referred to as a second part, and similarly, a second part may be referred to as a first part.

[0050] It should be understood that, in the application, terms such as "comprising" and "having" are used to specify the presence of features, numbers, steps, operations, components, parts, or combinations thereof described in the specification, without pre-excluding the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof. The phrase "on" another part refers not only to the case where a part is "directly" on another part, but also to the case where there is another part between the two parts. In this specification, when a part of a layer, region, plate, etc., is formed on another part, the forming direction is not limited to the upward direction, but includes forming a part on a side surface or in the downward direction. Conversely, the phrase "below" another part refers not only to the case where a part is "directly" below another part, but also to the case where there is another part between the two parts.

[0051] In the following description, preferred embodiments of the present disclosure and other embodiments necessary for those skilled in the art to understand the present disclosure will be described with reference to the accompanying drawings. In the following description, singular expressions include plural expressions unless the context clearly requires otherwise.

[0052] Figure 1 This is a block diagram illustrating an embodiment of the display device.

[0053] refer to Figure 1 The display device DD may include a display panel DP, a gate driver 120, a data driver 130, a voltage generator 140, and a controller 150.

[0054] The display panel DP includes sub-pixels SP. Sub-pixels SP can be connected to gate driver 120 via first gate line GL1 to m-th gate line GLm. Sub-pixels SP can be connected to data driver 130 via first data line DL1 to n-th data line DLn, where m and n are integers greater than 0.

[0055] Subpixels (SPs) can generate light of two or more colors. For example, each of multiple subpixels (SPs) can generate light such as red, green, blue, cyan, magenta, or yellow.

[0056] Two or more sub-pixels SP can constitute a pixel PXL. For example, as shown in the image. Figure 1 As shown, pixel PXL may include three sub-pixels SP. As described above, pixel PXL can emit light of various colors and brightnesses based on the combination of light emitted from the sub-pixels SP included in pixel PXL.

[0057] Gate driver 120 is connected to a plurality of sub-pixels SP arranged in the row direction via first gate lines GL1 to m-th gate lines GLm. Gate driver 120 may output gate signals to first gate lines GL1 to m-th gate lines GLm in response to gate control signal GCS. In an embodiment, gate control signal GCS may include a start signal indicating the start of each frame, a horizontal synchronization signal, etc.

[0058] The gate driver 120 may be positioned on one side of the display panel DP. However, embodiments are not limited thereto. For example, the gate driver 120 may include two or more physically and / or logically separated drivers, and these drivers may be positioned on one side of the display panel DP and on the opposite side of the display panel DP. As described above, the gate driver 120 may be positioned in various shapes around the display panel DP according to embodiments.

[0059] Data driver 130 is connected to a plurality of sub-pixels SP arranged in the column direction via first data lines DL1 to nth data lines DLn. Data driver 130 receives image data DATA and data control signal DCS from controller 150. Data driver 130 operates in response to data control signal DCS. In an embodiment, data control signal DCS may include source start signal, source shift clock, source output enable signal, etc.

[0060] Data driver 130 can receive voltage from voltage generator 140. Data driver 130 can use the received voltage to apply a data signal having a grayscale voltage corresponding to image data DATA to first data lines DL1 through nth data lines DLn. When a gate signal is applied to each of the first gate lines GL1 through mth gate lines GLm, a data signal corresponding to image data DATA can be applied to the first data lines DL1 through nth data lines DLn. Therefore, sub-pixels SP can generate light corresponding to the data signal, and display panel DP can display an image.

[0061] In one embodiment, gate driver 120 and data driver 130 may include complementary metal-oxide-semiconductor (CMOS) circuit elements.

[0062] Voltage generator 140 can operate in response to a voltage control signal VCS from controller 150. Voltage generator 140 is configured to generate multiple voltages and provide the generated voltages to components of the display device DD, such as gate driver 120, data driver 130, and controller 150. Voltage generator 140 can generate multiple voltages by receiving an input voltage from outside the display device DD and adjusting the received input voltage.

[0063] Voltage generator 140 can generate a first electrical voltage and a second electrical voltage. The generated first and second electrical voltages can be provided to the sub-pixel SP via the power line PL. In another embodiment, at least one of the first and second electrical voltages can be provided from outside the display device DD.

[0064] Additionally, voltage generator 140 can provide various voltages and / or signals. For example, voltage generator 140 can provide one or more initialization voltages applied to sub-pixel SP. For example, during sensing operations for sensing the electrical characteristics of the transistors and / or light-emitting elements of sub-pixel SP, a predetermined reference voltage can be applied to first data lines DL1 to nth data lines DLn, and voltage generator 140 can generate the reference voltage and transmit it to data driver 130. For example, during display operations for displaying an image on display panel DP, a common pixel control signal can be applied to sub-pixel SP, and voltage generator 140 can generate the pixel control signal. In an embodiment, voltage generator 140 can provide the pixel control signal to sub-pixel SP via pixel control line PXCL. Figure 1 In this embodiment, the pixel control line PXCL is connected between the voltage generator 140 and the display panel DP, but the embodiment is not limited to this. For example, the pixel control line PXCL may be connected between the gate driver 120 and the display panel DP. In this case, the pixel control signal can be transmitted from the voltage generator 140 to the pixel control line PXCL through the gate driver 120.

[0065] The controller 150 controls the overall operation of the display device DD. The controller 150 receives input image data IMG and the corresponding control signal CTRL from an external source. The controller 150 can provide a gate control signal GCS, a data control signal DCS, and a voltage control signal VCS in response to the control signal CTRL.

[0066] The controller 150 can convert input image data IMG such that the input image data IMG is suitable for a display device DD or a display panel DP, and output image data DATA. In an embodiment, the controller 150 can output image data DATA by aligning the input image data IMG so that the aligned input image data IMG is suitable for the sub-pixels SP of the row unit.

[0067] Two or more of the components—data driver 130, voltage generator 140, and controller 150—can be mounted on a single integrated circuit. For example... Figure 1 As shown, the data driver 130, voltage generator 140, and controller 150 may be included in a driver integrated circuit (DIC). In this case, the data driver 130, voltage generator 140, and controller 150 may be functionally separated components within a single driver integrated circuit (DIC). In another embodiment, at least one of the data driver 130, voltage generator 140, and controller 150 may be provided as a component separate from the driver integrated circuit (DIC).

[0068] Figure 2 It is a diagram. Figure 1 A block diagram of an embodiment of one of a plurality of sub-pixels. Figure 2 In Figure 1 Among the multiple sub-pixels SP, the sub-pixel SPij arranged in the i-th row (i is an integer greater than or equal to 1 and less than or equal to m) and the j-th column (j is an integer greater than or equal to 1 and less than or equal to n) is shown as an example.

[0069] refer to Figure 2 Subpixel SPij may include subpixel circuit SPC and light-emitting element LD.

[0070] The light-emitting element (LD) is connected between the first power voltage node VDDN and the second power voltage node VSSN. The first power voltage node VDDN is connected to... Figure 1 It is one of multiple power lines PL and receives the first power voltage. The second power voltage node VSSN is connected to Figure 1 It is one of multiple power lines PL and receives a second power voltage. The first power voltage may have a higher voltage level than the second power voltage.

[0071] The light-emitting element LD is connected between the anode electrode AE ​​and the cathode electrode CE. The anode electrode AE ​​can be connected to the first power voltage node VDDN via a sub-pixel circuit SPC. For example, the anode electrode AE ​​can be connected to the first power voltage node VDDN via one or more transistors included in the sub-pixel circuit SPC. The cathode electrode CE can be connected to a second power voltage node VSSN. The light-emitting element LD is configured to emit light according to the current flowing from the anode electrode AE ​​to the cathode electrode CE.

[0072] Sub-pixel circuit SPC can be connected to Figure 1 The i-th gate line GL1 to the m-th gate line GLm and Figure 1 The first data line DL1 to the nth data line DLn, specifically the j-th data line DLj. In response to a gate signal received via the i-th gate line GL1, the sub-pixel circuit SPC controls the light-emitting element LD to emit light according to the data signal received via the j-th data line DLj. In an embodiment, the sub-pixel circuit SPC may also be connected to... Figure 1 The pixel control line PXCL. In this case, the sub-pixel circuit SPC can further control the light-emitting element LD in response to the pixel control signal received through the pixel control line PXCL.

[0073] For this operation, the sub-pixel circuit (SPC) may include pixel circuitry, such as transistors and one or more capacitors.

[0074] The transistors in the sub-pixel circuit SPC may include P-type transistors and / or N-type transistors. In an embodiment, the transistors in the sub-pixel circuit SPC may include metal-oxide-semiconductor field-effect transistors (MOSFETs). In an embodiment, the transistors in the sub-pixel circuit SPC may include amorphous silicon semiconductors, monocrystalline silicon semiconductors, polycrystalline silicon semiconductors, oxide semiconductors, etc.

[0075] Figure 3 It is a diagram. Figure 1 A plan view of an embodiment of the display panel.

[0076] refer to Figure 3 The display panel DP may include a display area DA and a non-display area NDA. The display panel DP displays the image through the display area DA. The non-display area NDA is positioned around the display area DA.

[0077] The display panel DP includes sub-pixels SP in the display area DA. Multiple sub-pixels SP can be arranged along a first direction DR1 and a second direction DR2 intersecting the first direction DR1. For example, multiple sub-pixels SP can be arranged in a matrix along the first direction DR1 and the second direction DR2. As another example, multiple sub-pixels SP can be arranged in a zigzag pattern along the first direction DR1 and the second direction DR2. The arrangement of the sub-pixels SP can vary depending on the embodiment. The first direction DR1 can be a row direction, and the second direction DR2 can be a column direction.

[0078] Two or more sub-pixels SP can constitute a pixel PXL. Figure 3 In this embodiment, pixel PXL includes three sub-pixels SP (i.e., first sub-pixel SP1, second sub-pixel SP2, and third sub-pixel SP3), but the embodiment is not limited thereto. For example, pixel PXL may include two sub-pixels SP. In the following description, for convenience, it is assumed that pixel PXL includes first sub-pixel SP1, second sub-pixel SP2, and third sub-pixel SP3.

[0079] Each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 can generate light of one of various colors, such as red, green, blue, cyan, magenta, and yellow. In the following description, for clarity and conciseness, it is assumed that the first sub-pixel SP1 is configured to generate red light, the second sub-pixel SP2 is configured to generate green light, and the third sub-pixel SP3 is configured to generate blue light.

[0080] Each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may include at least one light-emitting element configured to generate light. In one embodiment, the light-emitting elements of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may generate light of the same color. For example, the light-emitting elements of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may generate blue light. In other embodiments, the light-emitting elements of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may generate light of different colors. For example, the light-emitting elements of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may generate red light, green light, and blue light, respectively.

[0081] Display panels capable of self-emission (such as LED display panels that use micron- or nano-sized light-emitting diodes as light-emitting elements, or OLED display panels that use organic light-emitting diodes as light-emitting elements) can be used as display panels DP.

[0082] The components used to control the sub-pixel SP can be positioned in the non-display area NDA. Lines connected to the sub-pixel SP (e.g., Figure 1 The first gate line GL1 to the m-th gate line GLm, the first data line DL1 to the n-th data line DLn, the power line PL, and the pixel control line PXCL can be located in the non-display area NDA.

[0083] Figure 1 At least one of the gate driver 120, data driver 130, voltage generator 140, and controller 150 may be located in the non-display area NDA of the display panel DP. In an embodiment, the gate driver 120 may be located in the non-display area NDA. In this case, the data driver 130, voltage generator 140, and controller 150 may be implemented separately from the display panel DP. Figure 1 The driver integrated circuit DIC is connected to a line located in the non-display area NDA. In other embodiments, the gate driver 120 may be implemented together with the data driver 130, voltage generator 140, and controller 150 as a single integrated circuit separate from the display panel DP.

[0084] In this embodiment, the display area DA can have various shapes. The display area DA can have a closed-loop shape with sides including straight lines and / or curves. For example, the display area DA can have a polygonal, circular, semi-circular, elliptical, or other shapes.

[0085] In one embodiment, the display panel DP may have a flat display surface. In other embodiments, the display panel DP may have a display surface that is at least partially rounded. In another embodiment, the display panel DP may be flexible, foldable, or rollable. In this case, the display panel DP and / or the substrate of the display panel DP may include a material with flexible properties.

[0086] Figure 4 It is a diagram. Figure 3 A cross-sectional view of an embodiment of the display panel.

[0087] refer to Figure 4 The display panel DP may include a substrate SUB and a pixel circuit layer PCL, a display element layer DPL, and an optical function layer LFL sequentially stacked on the substrate SUB on a third direction DR3 that intersects the first direction DR1 and the second direction DR2.

[0088] The substrate SUB may comprise an insulating material such as glass or resin. For example, the substrate SUB may comprise a glass substrate. As another example, the substrate SUB may comprise a polyimide (PI) substrate. As yet another example, the substrate SUB may comprise a silicon wafer substrate formed using semiconductor processes.

[0089] In embodiments, the substrate SUB may comprise a flexible material that is bendable or foldable, and may have a single-layer or multi-layer structure. For example, the flexible material may comprise at least one of polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, cellulose triacetate, and cellulose acetate propionate. However, embodiments are not limited thereto.

[0090] The pixel circuit layer (PCL) is positioned on the substrate (SUB). The PCL may include multiple insulating layers and semiconductor and conductive electrodes positioned between these insulating layers. The conductive electrodes of the PCL can be used as circuit elements, lines, etc.

[0091] The circuit elements of the pixel circuit layer PCL may include Figure 3 Subpixel circuit SPC for each of the multiple subpixels SP (reference) Figure 2 In other words, the circuit elements of the pixel circuit layer PCL can be provided as the transistor TR of the sub-pixel circuit SPC (reference). Figure 6 ) and one or more capacitors.

[0092] The lines in the pixel circuit layer (PCL) may include lines connected to the sub-pixels (SP). The lines in the pixel circuit layer (PCL) may also include various signal lines and / or voltage lines required to drive the display element layer (DPL).

[0093] The display element layer (DPL) is positioned on the pixel circuit layer (PCL). The display element layer (DPL) may include the light-emitting elements of the sub-pixels (SP).

[0094] The light functional layer (LFL) may be positioned on the display element layer (DPL). The LFL may include a light conversion pattern with color-converting particles and / or scattering particles. For example, the color-converting particles may include quantum dots. Quantum dots can change the wavelength (or color) of light emitted from the display element layer (DPL). The LFL may also include a light scattering pattern with scattering particles. In embodiments, the light conversion pattern and light scattering pattern may be omitted.

[0095] The optical functional layer (LFL) may include a color filter layer containing color filters. The color filters selectively transmit light of a specific wavelength (or specific color). In some embodiments, the color filter layer may be omitted.

[0096] A window for protecting the exposed surface (or top surface) of the display panel (DP) can be provided on the light functional layer (LFL). The window protects the display panel (DP) from external impacts. The window can be attached to the light functional layer (LFL) using an optically transparent adhesive (or bonding agent) component. The window can have a multilayer structure selected from glass substrates, plastic films, and plastic substrates. The multilayer structure can be formed through a continuous process or an adhesive process using adhesive layers. The window can be entirely or partially flexible.

[0097] Figure 5 It is a diagram. Figure 3 A cross-sectional view of another embodiment of the display panel.

[0098] refer to Figure 5 The display panel DP' may include a substrate SUB, a pixel circuit layer PCL, a display element layer DPL, an input sensing layer ISL, and a light functional layer LFL. The substrate SUB, pixel circuit layer PCL, display element layer DPL, and light functional layer LFL are respectively configured to interact with a reference... Figure 4 The substrate (SUB), pixel circuit layer (PCL), display element layer (DPL), and optical functional layer (LFL) described are similar. Repeated descriptions will be omitted below.

[0099] The input sensing layer (ISL) can sense user input on the upper surface (or display surface) of the display panel (DP'). The input sensing layer (ISL) may include components suitable for sensing external objects, such as the user's hand or pen. For example, the input sensing layer (ISL) may include touch electrodes.

[0100] Figure 6 The illustration includes Figure 4 or Figure 5 A cross-sectional view of an embodiment of transistors in the pixel circuit layer.

[0101] refer to Figure 6 A transistor TR may include a gate electrode GE, a gate insulating layer GI, a semiconductor layer SCL, an intermediate layer ITL, and an electrode layer ETL.

[0102] The gate electrode GE can be positioned at Figure 5 The gate insulating layer GI is located on the substrate SUB. It can cover the gate electrode GE while being positioned on the gate electrode GE.

[0103] The semiconductor layer SCL can be positioned on the gate insulating layer GI. The semiconductor layer SCL can overlap with the gate electrode GE on the gate insulating layer GI.

[0104] In this embodiment, the semiconductor layer SCL may comprise a material having a layered structure. The semiconductor layer SCL may comprise a transition metal dichalcogenide (TMDC). For example, the semiconductor layer SCL may comprise molybdenum disulfide (MoS2).

[0105] The semiconductor layer SCL can be configured as a layer of molybdenum disulfide. Because the semiconductor layer SCL is configured as a layer of molybdenum disulfide, the electron mobility of the semiconductor layer SCL can be improved, and the on / off current ratio can be increased.

[0106] The intermediate layer (ITL) can be positioned on the semiconductor layer (SCL). The intermediate layer (ITL) can be in direct contact with the semiconductor layer (SCL). The intermediate layer (ITL) can include multiple interlayer patterns (ITPs) spaced apart from each other.

[0107] In embodiments, the intermediate layer ITL may comprise a material having a layered structure similar to that of the semiconductor layer SCL. Alternatively, the intermediate layer ITL may comprise a transition metal dichalcogenide (TMDC). For example, the intermediate layer ITL may comprise titanium disulfide (TiS2). However, embodiments are not limited thereto, and in another embodiment, the intermediate layer ITL may comprise bismuth (Bi).

[0108] The thickness t of the intermediate ITL layer can range from approximately 9 nanometers to approximately 11 nanometers. (See later for reference.) Figure 9 Describe it.

[0109] The electrode layer ETL can be positioned on the intermediate layer ITL. The electrode layer ETL may include source electrodes SE and drain electrodes DE spaced apart from each other. The source electrodes SE and drain electrodes DE may overlap with the interlayer pattern ITP, respectively.

[0110] In this embodiment, the electrode layer ETL may comprise a metal. For example, the electrode layer ETL may comprise at least one of gold (Au), silver (Ag), and titanium (Ti).

[0111] Figure 7 yes Figure 6 An enlarged cross-sectional view of a portion of the semiconductor layer and intermediate layer.

[0112] refer to Figure 7 The semiconductor layer SCL and the intermediate layer ITL can be in direct contact with each other. The semiconductor layer SCL may include molybdenum disulfide, and the intermediate layer ITL may include titanium disulfide. Alternatively, the semiconductor layer SCL may be configured as a single layer of molybdenum disulfide, and the intermediate layer ITL may be configured as multiple layers of titanium disulfide, and may have a thickness of about 9 nanometers to about 11 nanometers.

[0113] By arranging a titanium disulfide intermediate layer (ITL) in contact with the semiconductor layer SCL, the metal-induced gap states (MIGS) of the semiconductor layer SCL can be suppressed. Therefore, Fermi level depinning can occur, and the contact resistance between the semiconductor layer SCL and the intermediate layer ITL can be reduced. Due to the reduced contact resistance, the electron mobility of the transistor TR can be improved.

[0114] Furthermore, since each of the semiconductor layer SCL and the intermediate layer ITL includes a material with a layered structure and includes a transition metal dichalcogenide, the semiconductor layer SCL and the intermediate layer ITL can include materials from the same family. Additionally, the titanium disulfide used to configure the intermediate layer ITL can be a material having a work function similar to the lowest energy state of the conduction band of the molybdenum disulfide used to configure the semiconductor layer SCL. Therefore, due to the high compatibility of the material properties of titanium disulfide and molybdenum disulfide, process compatibility between titanium disulfide and molybdenum disulfide can be ensured. Thus, since the intermediate layer ITL is easily formed on the semiconductor layer SCL, process efficiency can be improved.

[0115] Figure 8 It is a diagram. Figure 6 The graph shows the transfer curve of the transistor. Figure 8 In the diagram, the x-axis represents the gate voltage, and the y-axis represents the drain current.

[0116] Except for the intermediate layer, the transistors are fabricated under the same conditions. In each of the comparative example (Ref), the first embodiment (Ex1), and the second embodiment (Ex2), the semiconductor layer comprises molybdenum disulfide, and the electrode layer comprises gold. Additionally, the distance between the two interlayer patterns included in the intermediate layer is approximately 4 micrometers, and the length of the semiconductor layer in each of the two interlayer patterns in the longitudinal direction is approximately 300 micrometers.

[0117] The comparative example (Ref) is an example in which no intermediate layer is formed, the first embodiment (Ex1) is an example in which the intermediate layer includes titanium disulfide with a thickness of about 10 nanometers, and the second embodiment (Ex2) is an example in which the intermediate layer includes bismuth with a thickness of about 20 nanometers.

[0118] The characteristics of the transistors according to the comparative example (Ref), the first embodiment (Ex1), and the second embodiment (Ex2) are shown in Table 1 below.

[0119] [Table 1]

[0120]

[0121] Referring to Table 1, under the conditions described above, the threshold voltage (V) was measured for each of the comparative example (Ref), the first embodiment (Ex1), and the second embodiment (Ex2). th ), Off current, On / off ratio, electron mobility, and swirl (SS) equal to or less than the threshold voltage.

[0122] refer to Figure 8According to Table 1, it can be confirmed that the threshold voltage of the transistor in each of the first embodiment (Ex1) and the second embodiment (Ex2) is less than the threshold voltage of the transistor in the comparison example (Ref).

[0123] It can be confirmed that the ratio of the on / off current of the transistor in each of the first embodiment (Ex1) and the second embodiment (Ex2) is greater than the ratio of the on / off current of the transistor in the comparative example (Ref). Furthermore, it can be confirmed that the ratio of the on / off current of the transistor in the first embodiment (Ex1) is greater than the ratio of the on / off current of the transistor in the second embodiment (Ex2).

[0124] It can be confirmed that the electron mobility of the transistors according to each of the first embodiment (Ex1) and the second embodiment (Ex2) is greater than the electron mobility of the transistor according to the comparative example (Ref). Furthermore, it can be confirmed that the electron mobility of the transistor according to the first embodiment (Ex1) is greater than the electron mobility of the transistor according to the second embodiment (Ex2).

[0125] It can be confirmed that the swing value of the threshold voltage of the transistor according to each of the first embodiment (Ex1) and the second embodiment (Ex2) is smaller than the swing value of the threshold voltage of the transistor according to the comparative example (Ref). Furthermore, it can be confirmed that the swing value of the threshold voltage of the transistor according to the first embodiment (Ex1) is smaller than the swing value of the threshold voltage of the transistor according to the second embodiment (Ex2).

[0126] Therefore, it can be confirmed that the performance of the transistor according to each of the first embodiment (Ex1) and the second embodiment (Ex2) is superior to that of the transistor according to the comparative example (Ref). Among the first embodiment (Ex1), the second embodiment (Ex2), and the comparative example (Ref), it can be confirmed that the transistor according to the first embodiment (Ex1), which includes titanium disulfide, has the best performance. Therefore, it is understood that arranging an intermediate layer between the semiconductor layer and the electrode layer in a transistor improves the performance of the transistor, and in particular, it can be confirmed that the transistor performance is optimal when the intermediate layer is a transition metal dichalcogenide (e.g., titanium disulfide).

[0127] Figure 9 It is a diagram. Figure 6 The graph shows the transfer curve of the transistor. Figure 9 In the diagram, the x-axis represents the gate voltage, and the y-axis represents the drain current.

[0128] and Figure 8Similarly, the transistor is manufactured under the same conditions, except for the intermediate layer. The third embodiment (Ex3) is an embodiment in which the intermediate layer comprises titanium disulfide with a thickness of about 5 nanometers, and the fourth embodiment (Ex4) is an embodiment in which the intermediate layer comprises titanium disulfide with a thickness of about 2 nanometers.

[0129] The characteristics of the transistors in each of the comparative examples (Ref), the first embodiment (Ex1), the third embodiment (Ex3), and the fourth embodiment (Ex4) are shown in Table 2 below.

[0130] [Table 2]

[0131]

[0132] Referring to Table 2, under the conditions described above, the threshold voltage (V) was measured for each of the comparative example (Ref), the first embodiment (Ex1), the third embodiment (Ex3), and the fourth embodiment (Ex4). th ), Off current, On / off ratio, electron mobility, and swirl (SS) equal to or less than the threshold voltage.

[0133] refer to Figure 9 According to Table 2, it can be confirmed that among the first embodiment (Ex1), the third embodiment (Ex3), and the fourth embodiment (Ex4), the transistor according to the first embodiment (Ex1) has the largest on / off current ratio, the largest electron mobility, and the smallest swing value equal to or less than the threshold voltage. That is, it can be confirmed that among the first embodiment (Ex1), the third embodiment (Ex3), and the fourth embodiment (Ex4), the transistor according to the first embodiment (Ex1) has the best performance.

[0134] Therefore, it can be confirmed that even if the intermediate layer comprises the same material, the transistor performance varies depending on the thickness of the intermediate layer. That is, it can be confirmed that the transistor performance improves as the thickness of the intermediate layer increases. However, since the intermediate layer is formed by an atomic layer deposition process described later, the process time can increase and therefore the process efficiency can decrease when the intermediate layer is formed to be about 20 nanometers or larger. Therefore, the thickness of the intermediate layer is preferably between about 9 nanometers and about 11 nanometers.

[0135] Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 , Figure 15 , Figure 16 , Figure 17 , Figure 18 and Figure 19 It is a diagram. Figure 6 A diagram illustrating an embodiment of a method for manufacturing a transistor.

[0136] refer to Figure 10 The gate electrode GE can be formed on the substrate SUB (reference). Figure 4 The gate insulating layer GI can be formed on the gate electrode GE while simultaneously covering it.

[0137] refer to Figure 11 The semiconductor layer SCL may be formed on the gate insulating layer GI. The semiconductor layer SCL may be formed to overlap with the gate electrode GE. The semiconductor layer SCL may include a material having a layered structure. The semiconductor layer SCL may include a transition metal dichalcogenide. For example, the semiconductor layer SCL may include molybdenum disulfide.

[0138] refer to Figure 12 A photoresist pattern PR can be formed on the semiconductor layer SCL. The photoresist pattern PR can be formed so as not to overlap with the portion where the interlayer pattern ITP, source electrode SE, and drain electrode DE will be positioned later. That is, after the photoresist layer can be integrally formed on the gate insulating layer GI and the semiconductor layer SCL, a portion of the photoresist layer formed therein where the interlayer pattern ITP, source electrode SE, and drain electrode DE are positioned can be removed. Therefore, multiple photoresist patterns PR spaced apart from each other can be formed.

[0139] refer to Figures 13 to 17 The intermediate layer (ITL) can be integrally formed on the semiconductor layer (SCL) and the photoresist pattern (PR). The intermediate layer (ITL) can be formed using atomic layer deposition (ALD) technology.

[0140] refer to Figure 13 A precursor PRC can be implanted into the surface of each of the semiconductor layer SCL and the photoresist pattern PR. The implanted precursor PRC can be adsorbed onto the surface of each of the semiconductor layer SCL and the photoresist pattern PR. Adsorption of the precursor PRC onto the surface of each of the semiconductor layer SCL and the photoresist pattern PR means that the precursor PRC reacts and bonds with the surface of each of the semiconductor layer SCL and the photoresist pattern PR, and that the precursor PRC is positioned on the surface of each of the semiconductor layer SCL and the photoresist pattern PR without reacting with either surface.

[0141] The precursor PRC may include tetrakis(dimethylamino)titanium (TDMAT).

[0142] refer to Figure 14The injected precursor PRC can be adsorbed onto the surface of each of the semiconductor layer SCL and the photoresist pattern PR to form a layer, and the unadsorbed precursor PRC can then be removed. Thus, a layer of precursor PRC can be formed on the semiconductor layer SCL.

[0143] refer to Figure 15 The reactant RCT can be implanted onto the surface of each of the semiconductor layer SCL and the photoresist pattern PR. The implanted reactant RCT can react with the precursor PRC adsorbed on the surface of each of the semiconductor layer SCL and the photoresist pattern PR. The reactant RCT may include hydrogen sulfide (H2S). Therefore, the reactant RCT and the precursor PRC can react to form titanium disulfide.

[0144] refer to Figure 16 The reactant RCT reacts with the precursor PRC to form a layer of titanium disulfide. Subsequently, any remaining RCT reactant can be removed. Thus, a layer of titanium disulfide can be formed on the semiconductor layer SCL.

[0145] refer to Figure 17 , Figures 13 to 16 The implantation and removal processes of the precursor PRC and the reactant RCT can be repeated to form multiple layers of titanium disulfide (see reference). Figure 7 Therefore, an intermediate layer (ITL) of titanium disulfide with a layered structure can be formed.

[0146] refer to Figure 18 The electrode layer (ETL) can be integrally formed on the intermediate layer (ITL). The electrode layer (ETL) can be formed by depositing metal. For example, the electrode layer (ETL) can include gold.

[0147] refer to Figure 19 The photoresist pattern PR can be removed. That is, the photoresist pattern PR can be removed via a stripping process. Therefore, when removing the photoresist pattern PR, a portion of each of the electrode layer ETL and intermediate layer ITL on the photoresist pattern PR can be removed. Therefore, the portion of the intermediate layer ITL that does not overlap with the photoresist pattern PR can be retained, and thus multiple interlayer patterns ITP spaced apart from each other can be formed. Additionally, only the portion of the electrode layer ETL that does not overlap with the photoresist pattern PR can be retained, and thus source electrodes SE and drain electrodes DE can be formed, respectively overlapping with the interlayer patterns ITP and spaced apart from each other.

[0148] In this embodiment, since the intermediate layer ITL is formed via atomic layer deposition, defect-induced gap states (DIGS) of the semiconductor layer SCL can be suppressed. That is, because the intermediate layer ITL is formed via atomic layer deposition, the material forming the intermediate layer ITL during the intermediate layer formation process can be prevented from damaging the surface of the semiconductor layer SCL or diffusing into the semiconductor layer SCL, thereby minimizing defects on the surface of the semiconductor layer SCL. Therefore, Fermi level depinning can occur, reducing the contact resistance between the semiconductor layer SCL and the intermediate layer ITL, and thus improving the electron mobility of the transistor TR.

[0149] The display device according to the embodiments is applicable to various types of electronic devices. In the embodiments, the electronic device includes the above-described display device, and may also include other modules or devices with additional functions in addition to the display device.

[0150] Figure 20 This is a block diagram of an electronic device according to an embodiment. (Reference) Figure 20 The electronic device 10 may include a display module 11, a processor 12, a memory 13, and a power module 14.

[0151] The processor 12 may include at least one of a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.

[0152] The memory 13 may store data and / or information for operating the processor 12 or the display module 11. When the processor 12 executes an application stored in the memory 13, image data signals and / or input control signals may be transmitted to the display module 11. The display module 11 may process the provided signals and output image information on the display screen.

[0153] The power module 14 may include a power supply module (such as a power adapter or battery device) and a power conversion module. The power conversion module converts the power supplied by the power supply module and generates power to operate the electronic device 10.

[0154] At least one of the aforementioned components of electronic device 10 may be included in a display device (e.g., the aforementioned display device DD) according to the embodiments described above. Furthermore, in terms of functionality, some of a plurality of individual modules included in a single module may be included in the display device, while other modules may be provided separately from the display device. For example, display module 11 is included in the display device, while processor 12, memory 13, and power module 14 are not included in the display device but are provided separately in electronic device 10.

[0155] Figure 21 Schematic diagrams of various embodiments of the electronic device are shown.

[0156] refer to Figure 21 The various types of electronic devices used in the embodiments of the display device (e.g., the display device DD described above) may include electronic devices for displaying images (such as smartphones 10_1a, tablet computers 10_1b, laptop computers 10_1c, televisions (TVs) 10_1d, and desktop monitors 10_1e), wearable electronic devices including display modules (such as smart glasses 10_2a, head-mounted displays (HMDs) 10_2b, and smartwatches 10_2c), and automotive electronic devices 10_3 including display modules (such as central information displays (CIDs) and interior mirror displays arranged in the dashboard, center panel, and instrument panel of a vehicle).

[0157] While the technical spirit of this disclosure has been described in detail with reference to the above embodiments, it should be noted that the above embodiments are for illustrative purposes only and not for limiting purposes. Those skilled in the art will understand that various modifications are possible within the scope of the technical spirit of this disclosure.

[0158] The scope of this disclosure is not limited to the details described in the detailed description of the specification, but should be defined by the claims. The scope of this disclosure is to be interpreted as including all changes or modifications derived from the meaning and scope of the claims and their equivalents.

Claims

1. A transistor, comprising: Gate electrode; A semiconductor layer disposed on the gate electrode; A gate insulating layer disposed between the gate electrode and the semiconductor layer; An electrode layer, the electrode layer comprising a source electrode and a drain electrode spaced apart from each other on the semiconductor layer; as well as An intermediate layer is disposed between the semiconductor layer and the electrode layer, and includes interlayer patterns that overlap with the source electrode and the drain electrode, respectively.

2. The transistor according to claim 1, wherein, Each of the semiconductor layer and the intermediate layer comprises a material having a layered structure.

3. The transistor according to claim 1, wherein, Each of the semiconductor layer and the intermediate layer includes a transition metal dichalcogenide.

4. The transistor according to claim 3, wherein, The semiconductor layer includes molybdenum disulfide.

5. The transistor according to claim 4, wherein, The semiconductor layer includes a layer of molybdenum disulfide.

6. The transistor according to claim 3, wherein, The intermediate layer comprises titanium disulfide.

7. The transistor according to claim 1, wherein, The thickness of the intermediate layer is between 9 nanometers and 11 nanometers.

8. The transistor according to claim 1, wherein, The electrode layer comprises metal.

9. A method for manufacturing a transistor, the method comprising: Form a gate electrode; A gate insulating layer is formed on the gate electrode; A semiconductor layer is formed on the gate insulating layer; as well as An intermediate layer and an electrode layer are formed on the semiconductor layer. The intermediate layer includes interlayer patterns spaced apart from each other, and the electrode layer includes source electrodes and drain electrodes spaced apart from each other and respectively overlapping the interlayer patterns.

10. The method for manufacturing a transistor according to claim 9, further comprising: After the semiconductor layer is formed and before the intermediate layer is formed, a photoresist pattern is formed on the semiconductor layer.

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