Switching converter and control circuit and control method thereof
By adjusting the voltage difference between the peak and valley reference signals in the control circuit of the switching converter, the problem of increased comparator response delay under light load is solved, and efficient turn-on and turn-off control of the switching converter under different load conditions is achieved, thus improving the overall performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- 3PEAK INC
- Filing Date
- 2025-12-19
- Publication Date
- 2026-04-21
AI Technical Summary
In the existing technology, with the improvement of the process, it is difficult to further reduce the minimum conduction time of the switching converter, which affects its transfer ratio and efficiency. In particular, under light load conditions, the error amplification signal is small, which leads to an increase in comparator response delay.
By introducing a signal processing unit into the control circuit of the switching converter, the voltage difference between the peak reference signal and the valley reference signal is adjusted so that a sufficient voltage difference can still be maintained when the error amplification signal is small, thereby shortening the delay time of the comparison unit and improving the response speed.
It effectively reduces the minimum turn-on time of the switching converter and improves its performance, especially enabling faster turn-on and turn-off control under both light and heavy load conditions.
Smart Images
Figure CN121906949A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of power electronics technology, and in particular to a switching converter and its control circuit and control method. Background Technology
[0002] The minimum on-time of a switching converter refers to the shortest time that the main power transistor in the switching converter must remain on in each switching cycle. Its performance is directly related to the switching converter's voltage ratio, efficiency, and other performance characteristics.
[0003] In particular, with continuous improvements in manufacturing processes, the supply voltage required by subsequent circuits is gradually decreasing, which in turn necessitates a continuous reduction in the minimum input voltage that the switching converter can support. Simultaneously, based on power density requirements, it is desirable to further increase the switching frequency. Therefore, reducing the minimum on-time of the switching converter has become a crucial problem that needs to be solved to improve its performance. Summary of the Invention
[0004] In view of the above problems, the purpose of this application is to provide a switching converter and its control circuit and control method, which can reduce the minimum on-time of the switching converter.
[0005] According to one aspect of the present invention, a control circuit for a switching converter is provided, wherein the switching converter includes a main power transistor, a freewheeling transistor, and an inductor connected to a switching node, and the control circuit includes: an error amplifier for providing an error amplification signal based on a feedback signal and a reference voltage, the feedback signal representing the output voltage of the switching converter; a signal processing unit for providing a peak reference signal and a valley reference signal based on the error amplification signal; a comparison unit for providing a first comparison result of a sampled signal and the peak reference signal, and for providing a second comparison result of the sampled signal and the valley reference signal, the sampled signal representing the current flowing through the inductor; and a logic driving circuit for driving the main power transistor to turn on / off based on the first comparison result, the second comparison result, and a clock signal, wherein the signal processing unit further adjusts at least one of the peak reference signal and the valley reference signal according to an adjustment signal, wherein when the error amplification signal is less than a set value, the voltage difference between the peak reference signal and the valley reference signal is greater than or equal to the voltage value represented by the adjustment signal.
[0006] Optionally, the adjustment signal includes a first adjustment signal and / or a second adjustment signal, and the signal processing unit includes: a first gain module for providing the peak reference signal according to the error amplification signal; a second gain module for providing the valley reference signal according to the error amplification signal; and a first adjustment module and / or a second adjustment module, wherein the first adjustment module is connected to the first gain module to pull down the peak reference signal according to the first adjustment signal, and the second adjustment module is connected to the second gain module to raise the peak reference signal according to the second adjustment signal.
[0007] Optionally, the first adjustment signal and the second adjustment signal are the same.
[0008] Optionally, the first gain module includes: a first conversion structure for converting the error amplified signal into a first intermediate signal; and a first mirror structure for providing the peak reference signal based on the first intermediate signal. The second gain module includes: a second conversion structure for converting the error amplified signal into a second intermediate signal; and a second mirror structure for providing the valley reference signal based on the second intermediate signal, wherein the gain of the peak reference signal relative to the error amplified signal is less than the gain of the valley reference signal relative to the error amplified signal.
[0009] Optionally, the first conversion structure includes: a first operational amplifier, whose non-inverting input receives the error amplification signal; a first transistor, whose control terminal is connected to the output terminal of the first operational amplifier, and whose second terminal is connected to the inverting input terminal of the first operational amplifier, the first terminal providing the first intermediate signal; and a first resistor connected between the second terminal of the first transistor and ground. The first mirror structure includes: a second transistor, whose control terminal and second terminal are shorted and connected to the first intermediate signal; and a third transistor, whose control terminal is connected to the control terminal of the second transistor, whose first terminal is connected to the first terminal of the second transistor, the second terminal providing the peak reference signal. The second conversion structure includes: a second operational amplifier, whose non-inverting input receives the error amplification signal; a fourth transistor, whose control terminal is connected to the output terminal of the second operational amplifier, whose second terminal is connected to the inverting input terminal of the second operational amplifier, the first terminal providing the second intermediate signal; and a second resistor connected between the second terminal of the fourth transistor and ground. The second mirror structure includes: a fifth transistor, whose control terminal and second terminal are shorted and connected to the first intermediate signal; and a sixth transistor, whose control terminal is connected to the control terminal of the fifth transistor, whose first terminal is connected to the first terminal of the fifth transistor, the second terminal providing the valley reference signal.
[0010] Optionally, the first adjustment module includes: a seventh transistor, with its first terminal and control terminal shorted and connected to the first adjustment signal; and an eighth transistor, with its control terminal connected to the control terminal of the seventh transistor, its second terminal connected to the second terminal of the seventh transistor, and its first terminal connected to the second terminal of the third transistor to pull down the peak reference signal according to the first adjustment signal.
[0011] Optionally, the second adjustment module includes a current source connected in parallel with the sixth transistor for providing the second adjustment signal to raise the valley reference signal.
[0012] Optionally, the comparison unit includes: a first comparator for comparing the sampled signal and the peak reference signal to provide a first comparison result; and a second comparator for comparing the sampled signal and the valley reference signal to provide a second comparison result.
[0013] According to another aspect of the present invention, a switching converter is provided, comprising: a power circuit including a main power transistor, a freewheeling transistor, and an inductor connected to a switching node; and the aforementioned control circuit for driving the main power transistor to turn on / off.
[0014] According to another aspect of the present invention, a control method for a switching converter is provided, wherein the switching converter includes a main power transistor, a freewheeling transistor, and an inductor connected to a switching node, the control method comprising: obtaining an error amplification signal based on a feedback signal and a reference voltage, the feedback signal representing the output voltage of the switching converter; providing a peak reference signal and a valley reference signal based on the error amplification signal, at least one of the peak reference signal and the valley reference signal being further regulated by an adjustment signal; comparing a sampled signal and the peak reference signal to obtain a first comparison result, the sampled signal representing the current flowing through the inductor; comparing the sampled signal and the valley reference signal to obtain a second comparison result; and driving the main power transistor to turn on and off based on the first comparison result, the second comparison result, and a clock signal, wherein when the error amplification signal is less than a set value, the voltage difference between the peak reference signal and the valley reference signal is greater than or equal to the voltage value represented by the adjustment signal.
[0015] Optionally, the adjustment signal includes a first adjustment signal and a second adjustment signal, and the step of providing a peak reference signal and a valley reference signal based on the error amplification signal and the adjustment signal includes: providing a peak reference signal based on the error amplification signal; providing a valley reference signal based on the error amplification signal; and lowering the peak reference signal based on the first adjustment signal and / or raising the valley reference signal based on the second adjustment signal, wherein the gain of the peak reference signal relative to the error amplification signal is less than the gain of the valley reference signal relative to the error amplification signal.
[0016] According to the switching converter and its control circuit and control method provided in this application, in the dual-loop controlled switching converter, at least one of the peak reference signal and the valley reference signal is adjusted by adjusting the adjustment signal so that the voltage difference between the two is greater than or equal to the voltage value represented by the adjustment signal, thereby expanding the difference between the peak reference signal and the sampled signal. Even when the error amplification signal is small, the delay of the comparison unit can be reduced and the response speed of the comparison unit can be improved, thereby effectively reducing the minimum conduction time and improving the performance of the switching converter. Attached Figure Description
[0017] The above and other objects, features and advantages of this application will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:
[0018] Figure 1A A schematic structural diagram of a switching converter is shown;
[0019] Figure 1B Show Figure 1A The schematic waveform diagram of the switching converter shown is shown.
[0020] Figure 2 This invention provides a schematic structural diagram of a switching converter according to one embodiment of the present application.
[0021] Figure 3 Show Figure 2 A schematic circuit diagram of the signal processing unit;
[0022] Figure 4 A schematic diagram showing the adjustment of the valley reference current is provided.
[0023] Figure 5 Show Figure 2 The waveform diagram of the first comparator in the middle;
[0024] Figure 6 Showing according to Figure 2 A schematic operating waveform of a medium-speed switching converter when it achieves minimum on-time;
[0025] Figure 7This invention provides a schematic structural diagram of a switching converter according to another embodiment of the present application.
[0026] Figure 8 Show Figure 7 A schematic circuit diagram of the signal processing unit;
[0027] Figure 9 This invention provides a schematic structural diagram of a switching converter according to another embodiment of the present application.
[0028] Figure 10 A schematic flowchart of the control method according to an embodiment of this application is shown. Detailed Implementation
[0029] Various embodiments of the present application will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by the same or similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale.
[0030] Certain terms are used in this specification and claims to refer to specific components. Those skilled in the art will understand that manufacturers may use different names to refer to the same component. This specification and claims do not distinguish components based on differences in name, but rather on differences in function.
[0031] It should be understood that, in the following description, "circuit" may include single or combined hardware circuits, programmable circuits, state machine circuits, and / or elements capable of storing instructions executed by the programmable circuit. When an element or circuit is said to be "connected" to another element or "connected" between two nodes, it may be directly coupled or connected to the other element, or there may be intermediate elements; the connection between elements may be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected" to another element, it means that there are no intermediate elements between them.
[0032] Furthermore, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0033] It should also be noted that in the various methods and processes of this application, the order of the steps does not imply the order of execution, nor does it constitute any limitation on the implementation process of the embodiments of this application.
[0034] Figure 1A A schematic structural diagram of a switching converter 1 is shown; Figure 1B Show Figure 1A The schematic waveform diagram of the switching converter 1 shown is shown.
[0035] Switching converters typically include power circuits and control circuits. Based on the structure of the power circuits, they can be further classified into boost converters, buck converters, and buck-boost converters. Figure 1A In this example, the switching converter 1 is a buck converter, which includes a control circuit 20 and a power circuit 10 with a buck architecture.
[0036] Specifically, the input terminal of power circuit 10, i.e., the voltage input terminal of the buck converter, receives the input voltage Vin; the output terminal, i.e., the voltage output terminal of the buck converter, provides the output voltage Vout. (Reference) Figure 1A The power circuit 10 includes a main power transistor 11, a freewheeling transistor 12, an inductor 13, an output capacitor 14, and a load 15.
[0037] exist Figure 1A In this example, both the main power transistor 11 and the freewheeling transistor 12 are NMOS transistors. It should be understood that a transistor has a first terminal, a second terminal, and a control terminal. When the transistor is turned on, current flows from its first terminal to its second terminal. For an NMOS transistor, the first terminal, second terminal, and control terminal are the drain, source, and gate, respectively; for a PMOS transistor, the first terminal, second terminal, and control terminal are the source, drain, and gate, respectively.
[0038] The main power transistor 11 and the freewheeling transistor 12 are connected in series between the voltage input terminal and ground GND, and their common node is the switching node SW. The inductor 13 is connected between the switching node SW and the output terminal, the output capacitor 14 is connected between the output terminal and ground, and the load 15 is connected in parallel with the output capacitor 14.
[0039] Under the control of the corresponding drive signal, the main power transistor 11 and the freewheeling transistor 12 alternately turn on and off. During the conduction period of the main power transistor 11, the freewheeling transistor 12 is off, charging the inductor 13 through the input voltage Vin and supplying power to the output terminal. During the conduction period of the freewheeling transistor 12, the main power transistor 11 is off, and the inductor 13 supplies power to the output terminal through the freewheeling transistor 12. In continuous switching cycles, the output terminal of the power circuit generates a continuous output, which is filtered by the output capacitor 14 to obtain a roughly constant output voltage Vout.
[0040] The control circuit 20 is used to provide the drive signal HG for the main power transistor 11 and the drive signal LG for the freewheeling transistor 12. Figure 1A In the control circuit 20, there are: a sampling unit with a first sampling resistor 21a and a second sampling resistor 21b, an error amplifier 22, a first buffer amplifier 23a, a second buffer amplifier 23b, a first comparator 24a, a second comparator 24b, and a logic drive unit 25.
[0041] During operation, the switching converter 1 obtains a feedback signal Vfb of the output voltage through a sampling unit. Error amplifier 22 generates an error amplification signal Vcomp based on the difference between the reference voltage Vref and the feedback signal Vfb. First buffer amplifier 23a generates a peak reference signal based on the error amplification signal Vcomp, and superimposes it with a slope compensation signal Vramp before inputting it to the inverting input of first comparator 24a. The non-inverting input of first comparator 24a is connected to the current sampling signal of inductor 13, which could be, for example, the first sampling signal Sipk obtained by sampling the main power transistor 11. First comparator 24a provides a first control signal T1 based on the first comparison result between the peak reference signal and the first sampling signal Sipk. Second buffer amplifier 23b generates a valley reference signal based on the error amplification signal Vcomp and provides it to the inverting input of second comparator 24b. The non-inverting input of second comparator 24b is connected to the current sampling signal of inductor 13, which could be, for example, the second sampling signal Sivy obtained by sampling the freewheeling transistor 12. The second comparator 24b provides a second control signal T2 based on the second comparison result between the valley reference signal and the second sampling signal Sivy. The logic drive unit 25 generates a drive signal HG to drive the main power transistor 11 to turn on / off, and generates a drive signal LG to drive the freewheeling transistor 12 to turn on / off, based on the first control signal T1, the second control signal T2 and the clock signal CLK.
[0042] The following is combined Figure 1B The waveform diagram shown further illustrates how the logic drive unit 25 generates the drive signal HG for the main power transistor and the drive signal LG for the freewheeling transistor based on the first control signal T1, the second control signal T2, and the clock signal CLK. Figure 1B In the diagram, Vsw is the potential of the switching node, CLK is the clock signal, T1 is the first control signal, T2 is the second control signal, and Tmin is the minimum on-time of the main power transistor 11.
[0043] It should be noted that the following working principle of the logic driving unit 25 should be well known to those skilled in the art and can be implemented through different architectures, and no further restrictions are imposed in this specification.
[0044] The logic drive unit 25 determines the operating mode of the switching converter 1 based on the level of the second control signal T2. Referring to Figure 1, for example, if the second control signal T2 is high when the pulse of the clock signal CLK arrives, the switching converter 1 operates in peak current control mode; if the second control signal T2 is low when the pulse of the clock signal CLK arrives, the switching converter 1 operates in valley current control mode.
[0045] In peak current control mode, logic drive unit 25 turns on the main power transistor according to the effective edge of the clock signal CLK (e.g., the rising edge, i.e., time t1 and t2 in the figure), raising Vsw to the input voltage Vin. When the first sampling signal Sipk reaches the threshold of the peak reference signal and the slope compensation Vramp superimposed, the first comparator 24a flips, outputting the first level (e.g., high level) of the first control signal T1. Logic drive unit 25 turns off the main power transistor 11 according to the first level of the first control signal T1, turns on the freewheeling transistor 12, and pulls Vsw down to ground. It should be understood that, to ensure output stability and device safety, the on-time of the main power transistor 11 in a single switching cycle is at least the set minimum on-time Tmin. That is, the first control signal T1 will only flip to the first level at least after a minimum on-time Tmin interval from the effective edge of the clock signal CLK.
[0046] In valley current control mode, logic drive unit 25 shields the rising edge of clock signal CLK and turns on main power transistor 11 according to the effective edge of second control signal T2 (e.g., rising edge, i.e., time t3 in the figure), causing Vsw to rise. First control signal T1 flips to the first level after experiencing minimum channel time Tmin, thereby turning off main power transistor 11 and turning on freewheeling transistor 12.
[0047] In other words, in peak current control mode, the main power transistor 11 is turned on according to the effective edge of the clock signal CLK and turned off at least after the minimum on-time Tmin. In valley current control mode, the main power transistor 11 is turned on according to the effective edge of the second control signal T2 and turned off after the minimum on-time Tmin.
[0048] Therefore, shortening the minimum on-time Tmin is key to improving the performance of switching converters.
[0049] Research has revealed that existing technologies, under fixed load conditions, determine the switching point (i.e., the frequency reduction point) of the switching converter to the valley current control mode by increasing the input voltage Vin, and obtain the minimum on-time Tmin by identifying the pulse width of the switching node potential Vsw at this point. However, regardless of whether it is the peak current control mode or the valley current control mode, the main power transistor 11 needs to be turned off by the switching of the first comparator 24a. In other words, the minimum on-time Tmin includes the response delay of the first comparator 24a. Especially under light load conditions, due to the small error amplification signal Vcomp, the switching speed of the first comparator 24a is further reduced, and the impact of the delay of the first comparator 24a on the minimum on-time Tmin is more significant. Therefore, this application provides a switching converter and its control circuit and control method that reduces the minimum on-time Tmin by shortening the response delay of the first comparator 24a, thereby improving the performance of the switching converter.
[0050] Figure 2 This diagram illustrates a schematic structure of a switching converter 2 according to an embodiment of this application. The switching converter 2 includes a power circuit 10 and a control circuit 30.
[0051] exist Figure 2 In the middle, it is still based on and Figure 1A Similarly, a buck converter architecture including main power transistor 11, freewheeling transistor 12, inductor 13, output capacitor 14, and load 15 is used as an example of power circuit 10. However, it should be understood that the control circuit provided in this application can also be adapted to power circuits of any architecture to implement a buck converter, boost converter, buck-boost converter, etc. Furthermore, the power circuit can be as follows: Figure 2 The dual-transistor structure (synchronous rectification) shown can also be a single-transistor structure (asynchronous rectification) with a main power transistor and a freewheeling diode. The topology of the power circuit should be well known to those skilled in the art, and will not be described in detail here.
[0052] The control circuit 30 includes: a sampling unit having a first sampling resistor 21a and a second sampling resistor 21b, an error amplifier 22, a signal processing unit 100, a comparison unit having a first comparator 24a and a second comparator 24b, and a logic drive circuit 25.
[0053] The sampling unit is used to obtain the feedback signal Vfb of the output voltage Vout. Specifically, the first sampling resistor 21a and the second sampling resistor 21b can be connected in series between the output terminal of the power circuit 10 and ground GND, and the intermediate node between them provides the feedback signal Vfb.
[0054] Error amplifier 22 is used to provide an error amplification signal Vcomp based on the feedback signal Vfb and the reference voltage Vref. For example, in... Figure 2In this context, the reference voltage Vref can be connected to the non-inverting input of the error amplifier 22, and the feedback signal Vfb can be connected to the inverting input of the error amplifier 22.
[0055] The signal processing unit 100 provides a peak reference current ipk based on the error amplification signal Vcomp, and a valley reference current ivy based on the error amplification signal Vcomp and the second adjustment signal I2. The peak reference current ipk is specifically represented as a voltage-type peak reference signal Vipk in subsequent circuits, and the valley reference current ivy is specifically represented as a voltage-type valley reference signal Vivy in subsequent circuits. Specifically, when the error amplification signal Vcomp is less than a set value, the voltage difference between the peak reference signal Vipk and the valley reference signal Vivy is greater than or equal to the voltage value represented by the second adjustment signal I2.
[0056] The comparison unit provides a first control signal T1 for a first comparison result between the sampled signal and the peak reference signal Vipk, and a second control signal T2 for a second comparison result between the sampled signal characterizing the inductor current and the valley reference signal Vivy. The sampled signal characterizes the current flowing through inductor 13.
[0057] Specifically, the sampled signals include a first sampled signal Sipk and a second sampled signal Sivy. The comparison unit includes a first comparator 24a for comparing the first sampled signal Sipk and the peak reference signal Vipk; and a second comparator 24b for comparing the second sampled signal Sivy and the valley reference signal Vivy. For example, in... Figure 2 In the first comparator 24a, the non-inverting input is connected to the first sampling signal Sipk, the inverting input is connected to the peak reference signal Vipk, and the output provides the first control signal T1; the non-inverting input of the second comparator 24b is connected to the second sampling signal Sivy, the inverting input is connected to the valley reference signal Vivy, and the output provides the second control signal T2.
[0058] In some embodiments, the first sampling signal Sipk and the second sampling signal Sivy can be obtained by directly sampling the current of inductor 13, in which case the first sampling signal Sipk and the second sampling signal Sivy are the same signal. In other embodiments, the first sampling signal Sipk can be obtained by sampling the current of the main power transistor 11, and the second sampling signal Sivy can be obtained by sampling the current of the freewheeling transistor 12, in which case the first sampling signal Sipk and the second sampling signal Sivy are different signals.
[0059] In some embodiments, slope compensation can also be applied to the first sampled signal Sipk or the peak reference signal Vipk to improve the operating stability of the switching converter. Figure 2In this example, a slope-compensated signal Vramp is provided for the peak reference signal Vipk. That is, the inverting input of the first comparator 24a is connected to the slope-compensated peak reference signal Vipk'.
[0060] The logic drive circuit 25 drives the main power transistor 11 and the freewheeling transistor 12 to turn on and off according to the first control signal T1, the second control signal T2, and the clock signal CLK. Its specific working principle can be found in the description of Figure 1 above, and will not be repeated here.
[0061] Figure 3 Show Figure 2 A schematic circuit diagram of the signal processing unit 100. (See attached diagram.) Figure 3 As shown, the signal processing unit 100 includes a first gain module 110, a second gain module 120, and a second adjustment module 130.
[0062] Combination Figure 2 and Figure 3 The first gain module 110 is used to provide a peak reference current ipk based on the error amplification signal Vcomp. The first gain module 110 includes a first conversion structure 111 and a first mirror structure 112.
[0063] The first conversion structure 111 is used to convert the error amplification signal Vcomp into a first intermediate signal. Specifically, the first conversion structure 111 includes a first operational amplifier 111a, a first transistor 111b, and a first resistor 111c. The non-inverting input of the first operational amplifier 111a receives the error amplification signal Vcomp. The control terminal of the first transistor 111b is connected to the output of the first operational amplifier 111a, its second terminal is connected to the inverting input of the first operational amplifier 111a, and its first terminal provides the first intermediate signal. The first resistor 111c is connected between the second terminal of the first transistor 111b and ground (GND).
[0064] The first mirror structure 112 is used to provide a peak reference current ipk based on a first intermediate signal. Specifically, the first mirror structure 112 includes a second transistor 112a and a third transistor 112b. The control terminal and the second terminal of the second transistor 112a are shorted and connected to the first intermediate signal. The first terminal of the third transistor 112b is connected to the first terminal of the second transistor 112a, the control terminal of the third transistor 112b is connected to the control terminal of the second transistor 112a, and the second terminal of the third transistor 112b provides the peak reference current ipk.
[0065] The second gain module 120 is used to provide a valley reference current ivy based on the error amplification signal Vcomp. The second gain module 120 includes a second conversion structure 121 and a second mirror structure 122.
[0066] The second conversion structure 121 is used to convert the error amplified signal Vcomp into a second intermediate signal. Specifically, the second conversion structure 121 includes a second operational amplifier 121a, a fourth transistor 121b, and a second resistor 121c. The non-inverting input of the second operational amplifier 121a receives the error amplified signal Vcomp. The control terminal of the fourth transistor 121b is connected to the output terminal of the second operational amplifier 121a, its second terminal is connected to the inverting input terminal of the second operational amplifier 121a, and its first terminal provides the second intermediate signal. The second resistor 121c is connected between the second terminal of the fourth transistor 121b and ground (GND).
[0067] The second mirror structure 122 is used to provide a valley reference current ivy based on the second intermediate signal. Specifically, the second mirror structure 122 includes a fifth transistor 122a and a sixth transistor 122b. The control terminal and the second terminal of the fifth transistor 122a are shorted and connected to the second intermediate signal. The first terminal of the sixth transistor 122b is connected to the first terminal of the fifth transistor 122a, the control terminal of the sixth transistor 122b is connected to the control terminal of the fifth transistor 122a, and the second terminal of the sixth transistor 122b provides the valley reference current ivy.
[0068] The second adjustment module 130 is used to raise the valley reference current ivy according to the second adjustment signal I2, that is, to raise the level of the valley reference signal Vivy. Specifically, in Figure 3 In the second regulation module 130, a current source is connected in parallel with the sixth transistor 122b. This current source provides a second regulation signal I2 of the current type to achieve a boosting of the valley reference current ivy.
[0069] Figure 4 A schematic diagram illustrating the adjustment of the valley reference current is shown. Figure 4 The diagram illustrates the relationship between the inductor current IL, specifically the peak reference current ipk and the valley reference current ivy, and the error amplification signal Vcomp. The dashed line represents the valley reference current ivy before the boost, while the solid line represents the valley reference current after the boost based on the second adjustment signal I2. It is evident that the valley reference current ivy is boosted by introducing the second adjustment signal I2. Specifically, when the error amplification signal Vcomp approaches 0, both the unboosted valley reference current ivy and the peak reference current ipk are close to 0. However, after introducing the second adjustment signal I2, even when the error amplification signal Vcomp approaches 0, the valley reference current ivy can still maintain a certain level. That is, when the error amplification signal Vcomp is less than the set value, the difference between the valley reference current ivy and the peak reference current ipk can be maintained, thus ensuring that there is at least a first difference between the peak reference signal Vipk and the valley reference signal Vivy. Furthermore, it should be understood that, as... Figure 4As shown, as the error amplification signal Vcomp increases, the valley reference current ivy and the peak reference current ipk will intersect. Therefore, the set value of the error amplification signal Vcomp should be less than or equal to the voltage value V3 corresponding to the intersection point. In particular, the voltage value V4 corresponding to the maximum value of the valley reference current ivy when it is not adjusted can be selected as the set value of the error amplification signal Vcomp.
[0070] Figure 5 Show Figure 2 The waveform diagram of the first comparator is shown. Here, Sipk represents the first sampling signal; Δ represents the difference between the peak reference signal Vipk and the first sampling signal Sipk when the valley reference current ivy is not boosted; Δ' represents the difference between the peak reference signal Vipk and the first sampling signal Sipk after the valley reference current ivy is boosted by the second adjustment signal I2.
[0071] Combination Figure 4 and Figure 5 When the error amplification signal Vcomp is V1, the corresponding peak reference current ipk is the current value at point A1, and the valley reference current, not raised according to the second adjustment signal I2, is the current value at point B1. After raising the valley reference current ivy according to the second adjustment signal I2, the error amplification signal Vcomp corresponding to the current value at point B1 is reduced to V2. At this time, the peak reference current ipk corresponding to the current value at point B1 decreases to the current value at point A2, that is, the corresponding first reference signal Vipk decreases. Then, with the first sampling signal Sipk remaining unchanged, the voltage difference between the non-inverting input and the inverting input of the first comparator 24a increases, thereby providing a larger charging current to the parasitic capacitor at the output of the first comparator 24a, accelerating the switching speed of the first comparator 24a, and shortening the delay time of the first comparator 24a from the original Δt to Δt'. This also shortens the minimum conduction time Tmin.
[0072] Figure 6 Showing according to Figure 2The diagram illustrates the operating waveform of the switching converter when it achieves its minimum on-time. Here, Vin is the input voltage of the switching converter, Iout is the output current of the switching converter, IL is the inductor current, Vsw is the potential of the switching node, Vcomp and Vcomp' are the error amplification signals before and after the valley reference signal is raised, Vout is the output voltage of the switching converter, Vipk and Vipk' are the peak reference signals before and after the valley reference signal is raised, and Sipk is the first sampling signal. As shown by the arrow, when testing to obtain the minimum on-time Tmin, the input voltage Vin needs to be gradually increased. Correspondingly, the operating mode of switching converter 2 switches from the peak current control mode PCM, which adjusts the on-time of the main power transistor under a fixed switching cycle, to the valley current control mode VCM, which maintains a fixed pulse width (i.e., Tmin) and extends the off-time of the main power transistor. Δ represents the difference between the peak reference signal Vipk and the first sampling signal Sipk when the valley reference current ivy is not boosted; Δ' represents the difference between the peak reference signal Vipk' and the first sampling signal Sipk after the valley reference current ivy is boosted by the second adjustment signal I2. Because the voltage difference between the two input terminals of the first comparator 24a increases from Δ to Δ', the first comparator 24a has a faster switching speed, which is more conducive to reducing the minimum on-time Tmin.
[0073] Figure 7 A schematic structural diagram of a switching converter 3 according to another embodiment of this application is shown. Figure 7 In the middle, it is still based on and Figure 1A and Figure 2 Similarly, a buck architecture comprising a main power transistor 11, a freewheeling transistor 12, an inductor 13, an output capacitor 14, and a load 15 is used as an example of a power circuit 10. Furthermore, the control circuit 40 includes a sampling unit with a first sampling resistor 21a and a second sampling resistor 21b, an error amplifier 22, a comparison unit with a first comparator 24a and a second comparator 24b, and a logic drive circuit 25. Figure 2 The relevant descriptions of the embodiments shown will not be repeated here.
[0074] and Figure 2 The switch converter 2 in the illustrated embodiment differs from the one in that, Figure 7In the switching converter 3 of the illustrated embodiment, the signal processing unit 200 provides a valley reference current ivy based on the error amplification signal Vcomp, and a peak reference current ipk based on the error amplification signal Vcomp and the first adjustment signal I1. In subsequent circuits, the valley reference current ivy is represented as the valley reference signal Vivy, and the peak reference current ipk is represented as the peak reference signal Vipk. By lowering the peak reference current ipk through the first adjustment signal I1, the difference between the peak reference signal Vipk and the valley reference signal Vivy can also be increased. That is, when the error amplification signal Vcomp is less than a set value, the voltage difference between the peak reference signal Vipk and the valley reference signal Vivy is greater than or equal to the voltage value represented by the first adjustment signal I1.
[0075] The first reference signal I1 can be the same as the second reference signal I2.
[0076] Specifically, Figure 8 Show Figure 7 A schematic circuit diagram of the signal processing unit. (e.g.) Figure 8 As shown, the signal processing unit 200 includes a first gain module 110, a second gain module 120, and a first adjustment module 210. The first gain module 110 also includes a first conversion structure 111 having a first operational amplifier 111a, a first transistor 111b, and a first resistor 111c, and a first mirror structure 112 having a second transistor 112a and a third transistor 112b. Similarly, the second gain module includes a second conversion structure 121 having a second operational amplifier 121a, a fourth transistor 121b, and a second resistor 121c, and a second mirror structure 122 having a fifth transistor 122a and a sixth transistor 122b. The descriptions of the first gain module 110 and the second gain module 120 can be found above and will not be repeated here.
[0077] The first adjustment module 210 is used to pull down the peak reference current ipk according to the first adjustment signal I1. Specifically, the first adjustment module 210 may include a seventh transistor 212 and an eighth transistor 211. The first terminal and the control terminal of the seventh transistor 212 are shorted and connected to the first adjustment signal I1. The second terminal of the eighth transistor 211 is connected to the second terminal of the seventh transistor 211, the control terminal is connected to the control terminal of the seventh transistor 211, and the first terminal is connected to the second terminal of the third transistor 112b, so as to pull down the peak reference current ipk according to the first adjustment signal I1.
[0078] It should be understood that having such Figure 2 or Figure 7The switching converter shown, which has peak current control mode and valley current control mode, typically operates in peak current control mode under heavy load and mainly relies on the toggling of the first comparator 24a to turn off the main power transistor 11. Under light load, it operates in valley current mode and mainly relies on the toggling of the second comparator 24b to turn on the main power transistor 11 and relies on the toggling of the first comparator 24a to turn off the main power transistor 11.
[0079] Under heavy load conditions, the error amplification signal Vcomp itself has a relatively large voltage value, such as Figure 2 As shown, the switching converter 2, which indirectly shortens the delay of the first comparator 24a by adjusting the valley reference signal Vivy through the second adjustment signal I2, is particularly suitable for reducing Tmin under heavy load conditions. However, under light load conditions, the error amplification signal Vcomp itself is close to zero. Figure 7 As shown, the switching converter 3, which directly shortens the delay of the first comparator 24a by lowering the peak reference signal Vipk through the first adjustment signal I1, is particularly suitable for reducing Tmin under light load conditions.
[0080] Figure 9 A schematic structural diagram of a switching converter according to another embodiment of this application is shown. Figure 9 In the middle, it is still based on and Figure 1A , Figure 2 and Figure 7 Similarly, a buck architecture comprising a main power transistor 11, a freewheeling transistor 12, an inductor 13, an output capacitor 14, and a load 15 is used as an example of a power circuit 10. Furthermore, the control circuit 50 includes a sampling unit with a first sampling resistor 21a and a second sampling resistor 21b, an error amplifier 22, a comparison unit with a first comparator 24a and a second comparator 24b, and a logic drive circuit 25. Figure 2 The relevant descriptions of the embodiments shown will not be repeated here.
[0081] and Figure 2 The switching converter 2 shown in the embodiment Figure 7 The switch converter 3 in the illustrated embodiment differs from the one in that, Figure 9In the switching converter 4 of the illustrated embodiment, the signal processing unit 300 provides a valley reference current ivy based on the error amplification signal Vcomp and the second adjustment signal I2, and a peak reference current ipk based on the error amplification signal Vcomp and the first adjustment signal I1. In subsequent circuits, the valley reference current ivy is represented as the valley reference signal Vivy, and the peak reference current ipk is represented as the peak reference signal Vipk. By lowering the peak reference current ipk through the first adjustment signal I1 and raising the valley reference current ivy through the second adjustment signal I2, both light and heavy load conditions can be considered, and the difference between the peak reference signal Vipk and the valley reference signal Vivy can be increased in all cases. Specifically, under the combined action of the first adjustment signal I1 and the second adjustment signal I2, when the error amplification signal Vcomp is less than a set value, the voltage difference between the peak reference signal Vipk and the valley reference signal Vivy is greater than or equal to the sum of the voltage values represented by the first adjustment signal I1 and the second adjustment signal I2.
[0082] The first reference signal I1 can be the same as the second reference signal I2.
[0083] Specifically, such as Figure 9 As shown, the signal processing unit 300 includes a first gain module 110, a second gain module 120, a first adjustment module 210, and a second adjustment module 130. The first gain module 110 also includes a first conversion structure 111 having a first operational amplifier 111a, a first transistor 111b, and a first resistor 111c, and a first mirror structure 112 having a second transistor 112a and a third transistor 112b. The second gain module also includes a second conversion structure 121 having a second operational amplifier 121a, a fourth transistor 121b, and a second resistor 121c, and a second mirror structure 122 having a fifth transistor 122a and a sixth transistor 122b. The second adjustment module 130 also includes a current source. The first adjustment module 210 also includes a seventh transistor and an eighth transistor. The descriptions of the first gain module 110, the second gain module 120, and the second adjustment module can be found in the above description. Figure 3 The description of the first adjustment module 210 can be found in the description above. Figure 8 The description will not be repeated here.
[0084] According to the switching converter and its control circuit and control method provided in this application, in the dual-loop controlled switching converter, at least one of the peak reference signal and the valley reference signal is adjusted by adjusting the adjustment signal so that the voltage difference between the two is greater than or equal to the voltage value represented by the adjustment signal, thereby expanding the difference between the peak reference signal and the sampled signal. Even when the error amplification signal is small, the delay of the comparison unit can be reduced and the response speed of the comparison unit can be improved, thereby effectively reducing the minimum conduction time and improving the performance of the switching converter.
[0085] It should be understood that, regardless of Figure 2 , Figure 7 still Figure 9 In the embodiment, the gain of the peak reference signal relative to the error amplification signal should be less than the gain of the valley reference signal relative to the error amplification signal.
[0086] Figure 10 A schematic flowchart illustrating the control method of an embodiment of this application is shown. The control method provided in this application is used for a switching converter and can be implemented, for example, by the control circuit provided above, to shorten the minimum on-time of the switching converter. The control method includes:
[0087] In step S11, an error amplification signal is obtained based on the feedback signal and the reference voltage. The feedback signal characterizes the output voltage of the switching converter.
[0088] In step S12, a peak reference signal and a valley reference signal are provided based on the error amplification signal, and at least one of them is also adjusted by an adjustment signal.
[0089] Specifically, after adjustment by the adjustment signal, when the error amplification signal is less than the set value, the voltage difference between the peak reference signal and the valley reference signal is greater than or equal to the voltage value represented by the adjustment signal.
[0090] In some embodiments, step S12 specifically includes: providing a peak reference signal based on the error amplification signal; providing a valley reference signal based on the error amplification signal; and lowering the peak reference signal based on a first adjustment signal and / or raising the valley reference signal based on a second adjustment signal. The gain of the peak reference signal relative to the error amplification signal should be less than the gain of the valley reference signal relative to the error amplification signal.
[0091] In some embodiments, the first adjustment signal and the second adjustment signal are the same.
[0092] In step S13, the sampled signal and the peak current reference signal are compared to obtain a first comparison result. The sampled signal represents the current flowing through the inductor.
[0093] In step S14, the sampled signal and the valley reference signal are compared to obtain a second comparison result; and
[0094] In step S15, the main power transistor is turned on / off according to the first comparison result, the second comparison result, and the clock signal.
[0095] In some embodiments, the sampling signal of the inductor current is a direct sampling of the inductor current. That is, in steps S13 and S14, the peak reference signal and the valley reference signal are compared with the same sampling signal respectively.
[0096] In some other embodiments, the sampling signal of the inductor current includes a first sampling signal obtained by sampling the main power transistor current and a second sampling signal obtained by sampling the freewheeling transistor current. Accordingly, in step S13, the peak reference signal is compared with the first sampling signal, and in step S14, the valley reference signal is compared with the second sampling signal.
[0097] In some embodiments, the control method provided in this application further includes: before step S13, performing slope compensation on one of the sampled signal and the peak reference signal to improve the stability of the switching converter.
[0098] According to the switching converter and its control circuit and control method provided in this application, in the dual-loop controlled switching converter, at least one of the peak reference signal and the valley reference signal is adjusted by adjusting the adjustment signal so that the voltage difference between the two is greater than or equal to the voltage value represented by the adjustment signal, thereby expanding the difference between the peak reference signal and the sampled signal. Even when the error amplification signal is small, the delay of the comparison unit can be reduced and the response speed of the comparison unit can be improved, thereby effectively reducing the minimum conduction time and improving the performance of the switching converter.
[0099] As described above, these embodiments of this application do not exhaustively cover all details, nor do they limit this application to specific embodiments. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of this application, thereby enabling those skilled in the art to effectively utilize this application and its modifications. The scope of protection of this application should be determined by the scope defined in the claims of this application.
Claims
1. A control circuit for a switching converter, wherein, The switching converter includes a main power transistor, a freewheeling transistor, and an inductor connected to the switching node. The control circuit includes: An error amplifier is used to provide an error amplification signal based on a feedback signal and a reference voltage, wherein the feedback signal characterizes the output voltage of the switching converter; The signal processing unit is used to provide a peak reference signal and a valley reference signal based on the error amplification signal. A comparison unit is configured to provide a first comparison result between the sampled signal and the peak reference signal, and to provide a second comparison result between the sampled signal and the valley reference signal, wherein the sampled signal represents the current flowing through the inductor; and A logic driving circuit is used to drive the main power transistor to turn on / off according to the first comparison result, the second comparison result, and the clock signal. The signal processing unit further adjusts at least one of the peak reference signal and the valley reference signal according to the adjustment signal. When the error amplification signal is less than a set value, the voltage difference between the peak reference signal and the valley reference signal is greater than or equal to the voltage value represented by the adjustment signal.
2. The control circuit according to claim 1, wherein, The adjustment signal includes a first adjustment signal and / or a second adjustment signal. The signal processing unit includes: The first gain module is used to provide the peak reference signal based on the error amplification signal; A second gain module is used to provide the valley reference signal based on the error amplification signal; and First adjustment module and / or second adjustment module, The first adjustment module is connected to the first gain module to pull down the peak reference signal according to the first adjustment signal. The second adjustment module is connected to the second gain module to raise the peak reference signal according to the second adjustment signal.
3. The control circuit according to claim 2, wherein, The first adjustment signal and the second adjustment signal are the same.
4. The control circuit according to claim 2 or 3, wherein, The first gain module includes: A first conversion structure is used to convert the error amplified signal into a first intermediate signal; and A first mirror structure is used to provide the peak reference signal based on the first intermediate signal. The second gain module includes: A second conversion structure is used to convert the error amplified signal into a second intermediate signal; and The second mirror structure is used to provide the valley reference signal based on the second intermediate signal. Wherein, the gain of the peak reference signal relative to the error amplification signal is less than the gain of the valley reference signal relative to the error amplification signal.
5. The control circuit according to claim 4, wherein, The first conversion structure includes: The first operational amplifier receives the error amplification signal at its non-inverting input terminal; A first transistor has its control terminal connected to the output terminal of the first operational amplifier, its second terminal connected to the inverting input terminal of the first operational amplifier, and its first terminal providing the first intermediate signal; and The first resistor is connected between the second terminal of the first transistor and ground. The first mirror structure includes: The second transistor, with its control terminal and second terminal shorted and connected to the first intermediate signal; and The third transistor has its control terminal connected to the control terminal of the second transistor, its first terminal connected to the first terminal of the second transistor, and its second terminal providing the peak reference signal. The second conversion structure includes: The second operational amplifier receives the error amplification signal at its non-inverting input terminal. The fourth transistor has its control terminal connected to the output terminal of the second operational amplifier, its second terminal connected to the inverting input terminal of the second operational amplifier, and its first terminal providing the second intermediate signal; and The second resistor is connected between the second terminal of the fourth transistor and ground. The second mirror structure includes: The fifth transistor, with its control terminal and second terminal shorted and connected to the first intermediate signal; and The sixth transistor has a control terminal connected to the control terminal of the fifth transistor, a first terminal connected to the first terminal of the fifth transistor, and a second terminal providing the valley reference signal.
6. The control circuit according to claim 5, wherein, The first adjustment module includes: The seventh transistor, with its first terminal and control terminal shorted and connected to the first adjustment signal; and The eighth transistor has a control terminal connected to the control terminal of the seventh transistor, a second terminal connected to the second terminal of the seventh transistor, and a first terminal connected to the second terminal of the third transistor to pull down the peak reference signal according to the first adjustment signal.
7. The control circuit according to claim 5, wherein, The second adjustment module includes: A current source, connected in parallel with the sixth transistor, is used to provide the second adjustment signal to raise the valley reference signal.
8. The control circuit according to claim 1, wherein, The comparison unit includes: A first comparator is configured to compare the sampled signal and the peak reference signal to provide a first comparison result; and A second comparator is used to compare the sampled signal and the valley reference signal to provide the second comparison result.
9. A switching converter, wherein, include: The power circuit includes a main power transistor, a freewheeling transistor, and an inductor connected to the switching node; as well as The control circuit as described in any one of claims 1-8 is used to drive the main power transistor to turn on / off.
10. A control method for a switching converter, wherein, The switching converter includes a main power transistor, a freewheeling transistor, and an inductor connected to the switching node, and the control method includes: An error amplification signal is obtained based on the feedback signal and the reference voltage, wherein the feedback signal characterizes the output voltage of the switching converter; A peak reference signal and a valley reference signal are provided based on the error amplification signal, and at least one of the peak reference signal and the valley reference signal is further adjusted by an adjustment signal; A first comparison result is obtained by comparing the sampled signal with the peak reference signal, wherein the sampled signal represents the current flowing through the inductor; The sampled signal and the valley reference signal are compared to obtain a second comparison result; and The main power transistor is turned on and off based on the first comparison result, the second comparison result, and the clock signal. Specifically, when the error amplification signal is less than a set value, the voltage difference between the peak reference signal and the valley reference signal is greater than or equal to the voltage value represented by the adjustment signal.
11. The control method according to claim 10, wherein, The adjustment signal includes a first adjustment signal and a second adjustment signal. The step of providing the peak reference signal and the valley reference signal based on the error amplification signal and the adjustment signal includes: A peak reference signal is provided based on the error amplification signal; A valley reference signal is provided based on the error amplification signal; and The peak reference signal is lowered according to the first adjustment signal and / or the valley reference signal is raised according to the second adjustment signal. Wherein, the gain of the peak reference signal relative to the error amplification signal is less than the gain of the valley reference signal relative to the error amplification signal.