Process method and process equipment of semiconductor device

Abstract

The invention discloses a process method and process equipment of a semiconductor device. The process method comprises the following steps: acquiring a substrate with an original thin film; introducing a first gas into the process cavity; high-temperature plasma treatment is conducted on the first gas, so that the first gas is ionized and excited to release ultraviolet photons, the ultraviolet photons penetrate through the surface of the original thin film, impurity atoms in the original thin film are removed, and the energy of the ultraviolet photons generated by the first gas is larger than the chemical bond energy of the impurity atoms. By executing the steps, the defect density in the tunneling layer thin film can be reduced, so that the overall quality of the thin film is improved, the occurrence of leakage current of the memory can be effectively reduced, the service life of the memory is prolonged, the breakdown voltage of the memory can be improved, and the reliability of the memory is improved.

Description

Technical Field

[0001] This invention relates to the technical field of semiconductor manufacturing, and more specifically to a process method for semiconductor devices and a process equipment for semiconductor devices. Background Technology

[0002] In advanced 3D NAND manufacturing processes, the size of memory cells is constantly shrinking, and the number of stacked layers in memory has exceeded 200, resulting in an aspect ratio of over 50:1 for channel holes. Therefore, extremely high requirements are placed on film fabrication processes. The core ONO structure (silicon oxide barrier layer / silicon nitride storage layer / silicon oxide tunneling layer) in the memory cell is typically fabricated using atomic layer deposition (ALD). The defects, impurities, and density in the silicon oxide tunneling layer of the ONO structure directly determine the film quality, thus affecting the read / write performance and stability of the memory.

[0003] In existing technologies, although ALD processes can achieve nanometer-level thickness control, the high aspect ratio of the channel via structure restricts precursor diffusion, resulting in a gradient density distribution in the deposited silicon oxide film. Furthermore, the generated silicon oxide film contains numerous defects. These defects are repeatedly bombarded by electrons during subsequent use of the memory, leading to accelerated degradation and potentially causing film breakdown, significantly reducing the reliability and lifespan of 3D NAND memory. To address this, some processes utilize the kinetic energy of helium gas to break excess hydrogen bonds between hydrogen atoms and other atoms in low-quality films (such as silicon oxide films), causing hydrogen atoms to detach from the low-quality film and remove hydrogen impurities. However, this method of impurity removal using process gas kinetic energy can only remove impurities on the surface of low-quality films and cannot remove deep impurities within the film, thus having limited effect on improving the overall film quality.

[0004] In order to solve the above-mentioned problems in the prior art, there is an urgent need in the art for a semiconductor device process technology that can reduce the defect density inside the tunneling layer film, thereby improving the overall quality of the film. This technology can not only effectively reduce the occurrence of memory leakage current and extend its service life, but also increase the breakdown voltage of the memory, thereby improving its reliability. Summary of the Invention

[0005] The following provides a brief overview of one or more aspects to offer a basic understanding of them. This overview is not an exhaustive summary of all conceived aspects, nor is it intended to identify key or decisive elements of all aspects, nor to define the scope of any or all aspects. Its sole purpose is to present some concepts of one or more aspects in a simplified form as a prelude to the more detailed descriptions that follow.

[0006] To overcome the aforementioned deficiencies in the prior art, the present invention provides a semiconductor device manufacturing method and a semiconductor device manufacturing apparatus, which can reduce the defect density inside the tunneling layer film, thereby improving the overall quality of the film. This not only effectively reduces the occurrence of memory leakage current and extends its service life, but also increases the breakdown voltage of the memory, thereby improving its reliability.

[0007] Specifically, the process method for the semiconductor device provided by the first aspect of the present invention includes the following steps: obtaining a substrate having a raw thin film; introducing a first gas into a process chamber; and subjecting the first gas to high-temperature plasma treatment to ionize and stimulate the release of ultraviolet photons, so as to remove impurity atoms inside the raw thin film by penetrating the surface of the raw thin film via the ultraviolet photons, wherein the energy of the ultraviolet photons generated by the first gas is greater than the chemical bond energy of the impurity atoms.

[0008] Furthermore, the semiconductor device process apparatus provided according to the second aspect of the present invention includes: a process chamber having an inlet at its upper end for introducing process gas; a radio frequency system including a radio frequency power supply and a radio frequency coil surrounding the outside of the process chamber for plasma treatment of the process gas within the process chamber; and a heating plate holding a substrate for performing the semiconductor device process method provided in the first aspect of the present invention on the raw thin film on the surface of the substrate. Attached Figure Description

[0009] The above-described features and advantages of the present invention will be better understood after reading the following detailed description of embodiments of the present disclosure in conjunction with the accompanying drawings. In the drawings, components are not necessarily drawn to scale, and components having similar related characteristics or features may have the same or similar reference numerals.

[0010] Figure 1 A schematic diagram of a process apparatus for a semiconductor device according to some embodiments of the present invention is shown.

[0011] Figure 2 A flowchart of a process method for a semiconductor device according to some embodiments of the present invention is shown.

[0012] Figure 3A A schematic diagram of a substrate having a pristine thin film is shown, according to some embodiments of the present invention.

[0013] Figure 3B A schematic diagram of the structure of a substrate after completing a first gas high-temperature plasma treatment is shown, according to some embodiments of the present invention.

[0014] Figure 4A flowchart of a process method for a semiconductor device according to other embodiments of the present invention is shown.

[0015] Figure 5A The diagram illustrates the results of wet etching rate testing of pre-films prepared using various different process methods, according to some embodiments of the present invention.

[0016] Figure 5B The diagram illustrates the results of quality testing of films prepared using various different process methods, according to some embodiments of the present invention.

[0017] Figure 6 The diagram shows the results of wet etching rate testing of the prepared thin film on the inner wall and bottom of the channel via according to some embodiments of the present invention.

[0018] Figure label: 100. Process equipment for semiconductor devices; 110 Process cavity; 111 Air intake; 112 Air extraction port; 120 RF power supply; 121 Radio frequency coil; 122 Matching System; 130 heating plate; Steps S210~S230; 300 substrate; 310 Channel through hole; 320 Original tunneling layer; 321 Target tunnel layer; 330 Storage layer; 340 barrier layer; Steps S410~S440 Detailed Implementation

[0019] The following specific embodiments illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. Although the description of the present invention is presented in conjunction with preferred embodiments, this does not mean that the features of the invention are limited to these embodiments. On the contrary, the purpose of describing the invention in conjunction with embodiments is to cover other options or modifications that may be derived based on the claims of the present invention. To provide a thorough understanding of the invention, many specific details will be included in the following description. The invention may also be implemented without using these details. Furthermore, to avoid confusion or obscuring the focus of the invention, some specific details will be omitted in the description.

[0020] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0021] Furthermore, the terms "upper," "lower," "left," "right," "top," "bottom," "horizontal," and "vertical" used in the following description should be understood as the orientations shown in the relevant paragraphs and accompanying drawings. These relative terms are for illustrative purposes only and do not imply that the described apparatus must be manufactured or operated in a specific orientation, and therefore should not be construed as limiting the invention.

[0022] It is understood that although terms such as "first," "second," and "third" may be used herein to describe various components, regions, layers, and / or parts, these components, regions, layers, and / or parts should not be limited by these terms, and these terms are only used to distinguish different components, regions, layers, and / or parts. Therefore, the first components, regions, layers, and / or parts discussed below may be referred to as second components, regions, layers, and / or parts without departing from some embodiments of the present invention.

[0023] As mentioned above, currently, in order to improve thin film quality, some processes utilize the kinetic energy of helium gas to break excess hydrogen bonds formed between hydrogen atoms and other atoms in low-quality thin films (such as silicon oxide thin films), causing hydrogen atoms to detach from the low-quality film and thus removing hydrogen impurities. However, this method of impurity removal using the kinetic energy of process gases can only remove impurities on the surface of low-quality thin films and cannot remove deep impurities inside the film, thus having a limited effect on improving the overall quality of the thin film.

[0024] To address the aforementioned problems in the prior art, this invention provides a semiconductor device manufacturing process and a semiconductor device manufacturing apparatus, which can reduce the defect density inside the tunneling layer film, thereby improving the overall quality of the film. This not only effectively reduces memory leakage current and extends its service life, but also increases the memory's breakdown voltage, thereby enhancing its reliability.

[0025] In some non-limiting embodiments, the process method of the semiconductor device provided in the first aspect of the present invention can be implemented via the process equipment of the semiconductor device provided in the second aspect of the present invention.

[0026] The following description, using examples of semiconductor device fabrication equipment, illustrates the steps of the aforementioned semiconductor device fabrication method. Those skilled in the art will understand that this semiconductor device fabrication equipment is merely a non-limiting embodiment provided by the present invention, intended to clearly demonstrate the main concepts of the invention and provide specific solutions convenient for public implementation, without limiting the entities implementing each step of the semiconductor device fabrication method. Similarly, these embodiments of semiconductor device fabrication equipment are also merely non-limiting embodiments provided by the present invention, and are not intended to limit all operating modes or functions of the semiconductor device fabrication equipment.

[0027] Please refer to Figure 1 . Figure 1 A schematic diagram of a process apparatus for a semiconductor device according to some embodiments of the present invention is shown.

[0028] like Figure 1 As shown, in some embodiments of the present invention, the semiconductor device process equipment 100 may mainly include a process cavity 110, a radio frequency system, and a heating plate 130.

[0029] Specifically, in Figure 1 In the illustrated embodiment, the process chamber 110 can be adapted to various thin film fabrication processes, including but not limited to plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), and metal-organic chemical vapor deposition (MOCVD), and / or etching processes, and can be configured with corresponding structures and accessories, which are not limited herein. The upper end of the process chamber 110 is provided with an air inlet 111 for introducing process gas. Further, the process gas can include, but is not limited to, deposition gas, etching gas, and thin film quality optimization gas. The lower end of the process chamber 110 is provided with an exhaust port 112 for discharging reaction byproducts and / or excess process gas after the process within the chamber is completed.

[0030] Continue as Figure 1 As shown, the radio frequency (RF) system may include an RF power supply 120 and an RF coil 121 surrounding the outside of the process cavity 110. The RF system allows for plasma treatment of process gases within the process cavity 110. Inside the process cavity 110, a heating plate 130 is also provided. A substrate 300 is placed on the heating plate 130 to perform semiconductor device fabrication processes on the raw thin film on the surface of the substrate 300.

[0031] Specifically, the RF power supply 120 can be connected to the RF coil 121 via a matching system 122. Impedance matching via the matching system 122 ensures efficient and stable transfer of RF energy from the RF power supply 120 to the RF coil 121. The output power range of the RF system is 0~4000W. The RF power supply 120 generates a high-frequency alternating current (typically 13.56 MHz or other industry standard frequencies) and inputs this current into the RF coil 121. When the high-frequency alternating current passes through the RF coil 121, the RF coil 121 generates a high-frequency alternating magnetic field around itself (including the internal space of the process cavity 110). According to the law of electromagnetic induction, the alternating magnetic field induces a ring-shaped alternating induced electric field inside the process cavity 110. A small number of free electrons in the process gas within the process cavity 110 are accelerated under the influence of the induced electric field, gaining sufficiently high kinetic energy. These high-energy electrons frequently collide with neutral atoms / molecules in the process gas, transferring energy to the neutral particles and causing them to ionize. This ionization process is amplified by the avalanche effect, eventually forming a plasma composed of electrons, ions, and neutral particles within the process chamber 110.

[0032] The heating plate 130 has a built-in heating element with an operating temperature range of 25°C to 900°C. Furthermore, the heating plate 130 is a movable component capable of lifting, translating, and rotating to adjust the substrate to the target process position.

[0033] Furthermore, in some preferred embodiments, the heating plate 130 may also include electrodes ( Figure 1 (Not shown in the diagram). A plasma process cavity with a composite plasma source configuration (ICP-CCP composite source) is formed by placing an RF coil 121 outside the process cavity 110 and integrating electrodes inside the heating plate 130. The externally placed RF coil 121 generates an alternating magnetic field through inductive coupling (ICP), which mainly ionizes the gas to increase the plasma density. The electrodes inside the heating plate 130 generate an electric field through capacitive coupling (CCP), which mainly applies a bias voltage to control the ion bombardment energy.

[0034] Specifically, a variable capacitor is connected to the lower end of the electrode inside the heating plate 130. By changing the position of the variable capacitor, the vertical acceleration energy of ions during plasma processing can be adjusted. This electrode, serving as the lower electrode of the capacitive coupling system (the upper electrode being a spray plate or chamber wall), is connected to an RF bias power supply. Since the equivalent resistance of the plasma is much higher than the sheath resistance between the electrode and the plasma, the RF voltage will form a DC self-bias on the sheath. Positive ions in the plasma will be vertically accelerated and bombard the wafer surface under the influence of the electric field of this bias. In this embodiment, the RF coil 121 ionizes the gas in ICP mode to generate high-density plasma, providing sufficient active free radicals. The electrode inside the heating plate 130 applies a bias voltage in CCP mode to regulate the vertical bombardment energy of the ions, thereby enabling precise processing of the substrate 300 surface. The two functions are decoupled, allowing for independent control. This enables adjustment of ion energy without changing the plasma density, or increase in plasma density without changing the ion energy, thus greatly expanding the process window and meeting the diverse needs of different processes.

[0035] The aforementioned semiconductor device process equipment integrates plasma generation and high-temperature thermal annealing, and can perform the semiconductor device process method provided in another aspect of the present invention, thereby effectively improving the thin film quality of the silicon oxide tunneling layer in 3D NAND memory, thereby enhancing flash memory performance.

[0036] Specifically, please refer to Figure 2 . Figure 2 A flowchart of a process method for a semiconductor device according to some embodiments of the present invention is shown.

[0037] like Figure 2 As shown, in some embodiments of the present invention, the process method for semiconductor devices may include the following steps S210 to S230.

[0038] First, step S210 can be performed: obtain a substrate with the original thin film.

[0039] Specifically, in some embodiments, it can be combined with Figure 3A A shared understanding. For example... Figure 3AAs shown, in the process of manufacturing a 3D NAND memory, a substrate 300 with a via 310 can be obtained. The via 310 can be formed by etching in multiple alternating layers of dielectric and sacrificial layers. Inside the via 310, a barrier layer 340, a storage layer 330, and a pristine tunneling layer 320 can be deposited sequentially (e.g., using atomic layer deposition). Optionally, the barrier layer 340 can be a silicon oxide thin film, the storage layer 330 can be a silicon nitride thin film, and the pristine tunneling layer 320 can be a silicon oxide thin film, thereby forming an ONO stacked structure on the substrate 300. Figure 3A As shown, the silicon nitride storage layer 330 is located between the silicon oxide barrier layer 340 and the original silicon oxide tunneling layer 320. The original silicon oxide tunneling layer 320 is located inside the via 310. The aspect ratio of the via 310 is typically between 50:1 and 100:1. The original silicon oxide tunneling layer 320 is the original thin film to be processed.

[0040] Then, steps S220 and S230 can be performed. Step S220: Introduce the first gas into the process chamber. Step S230: Perform high-temperature plasma treatment on the first gas to ionize it and stimulate it to release ultraviolet photons, so as to remove impurity atoms inside the original thin film via ultraviolet photons.

[0041] Specifically, in some embodiments, after the initial tunneling layer 320 of silicon oxide is deposited, the entire structure is subjected to high-temperature plasma treatment using a first gas. Since impurity atoms (such as carbon, hydrogen, and metal ions) in the initial tunneling layer 320 of silicon oxide are typically bonded to the silicon oxide lattice via chemical bonds (e.g., C-Si, CO, metal-O bonds), the energy of the ultraviolet photons generated during the ionization of the first gas is usually relatively high, at least greater than the bond energies of the impurity atoms' chemical bonds. Therefore, when the energy of the ultraviolet photons is absorbed by the Si-H, CO, OH, Si-N, and other chemical bonds formed by the silicon oxide impurities, these chemical bonds are broken, causing the impurities to detach from the silicon oxide lattice and form free impurity atoms (such as H, C, and N impurity atoms) or small molecules (such as CO, C...). (etc.). Furthermore, the energy of ultraviolet photons can directly act on adsorbed impurities (such as water molecules and organic residues) on the silicon oxide surface, causing their chemical bonds to break and decompose into volatile substances. Moreover, since ultraviolet photons are essentially high-energy electromagnetic waves, their penetrating power is far greater than the kinetic energy of helium in prior art. Therefore, compared to prior art techniques that utilize the kinetic energy of helium to remove impurities from the film surface, the technique in this invention that uses ultraviolet photons of a first gas to remove impurities within the film can reach deeper impurity atoms within the original film.

[0042] Furthermore, the high-energy ions and neutral particles in the plasma of the first gas exert a physical bombardment effect on the surface of the original tunneling layer 320 of silicon oxide. This physical bombardment desorbs free-state impurity atoms / small molecules generated by ultraviolet photochemical reactions from the surface of the original tunneling layer 320 film. Simultaneously, it slightly etches the defect layer on the silicon oxide surface to expose deeper impurities, further exposing them to ultraviolet radiation. The desorbed impurity atoms can be extracted by a molecular pump through the extraction port 112.

[0043] Furthermore, in some embodiments, the first gas may include an inert gas. The inert gas may include one of helium (He), argon (Ar), neon (Ne), krypton (Kr), and xenon (Xe). For example, when helium is selected as the first gas, it is ionized into a plasma state containing a large number of high-energy electrons, ions, and neutral particles. These high-energy electrons undergo inelastic collisions with He atoms, causing electrons in the atoms to transition from the ground state to a high-energy excited state. When the excited-state electrons fall back to the ground state, they release ultraviolet photons of a specific wavelength. The ultraviolet wavelengths of He plasma are mostly concentrated at 58.4 nm and 102.6 nm, and the energy of their ultraviolet photons can reach 10–25 eV. The breaking energy of the chemical bonds of impurity atoms is typically 2–7 eV. Since the energy of the ultraviolet photons generated by the ionization of the first gas, helium, is much higher than the bond energy of the chemical bonds of the impurity atoms, the chemical bonds formed by the aforementioned silicon oxide impurities will break after absorbing the energy of the ultraviolet photons, thereby causing the impurities to detach from the silicon oxide lattice and form free impurity atoms or small molecules. Therefore, in this invention, the radiation energy of ultraviolet photons generated by the first gas, combined with the synergistic etching effect of plasma, can desorb and remove impurities inside the original thin film.

[0044] For example, when argon is used as the first gas, the ultraviolet wavelengths of Ar plasma are concentrated at 106.7 nm and 104.8 nm, and the energy of its ultraviolet photons can reach 11–12 eV. Similarly, the energy of the ultraviolet photons generated by the ionization of argon as the first gas is much higher than the bond energies of the chemical bonds of impurity atoms (e.g., 2–7 eV). In addition, the ultraviolet wavelength of Ne plasma is concentrated at 30.4 nm, and the energy of its ultraviolet photons is about 40.8 eV. The ultraviolet wavelength of Kr plasma is concentrated at 123.6 nm, and the energy of its ultraviolet photons is about 10.0 eV. The ultraviolet wavelength of Xe plasma is concentrated at 147.0 nm, and the energy of its ultraviolet photons is about 8.4 eV. The energy of the ultraviolet photons generated by these first gases is higher than the breaking energy of the impurity chemical bonds (2–7 eV). Therefore, high-energy ultraviolet photons can break the chemical bonds between impurities and the silicon oxide lattice (e.g., C-Si, metal-O bonds). Combined with the physical bombardment effect of plasma ions, this can further assist in the desorption of free impurities. Furthermore, since Ne plasma has higher ultraviolet photon energy, it is more effective at removing stubborn impurities (such as metallic impurities). Kr and Xe plasmas have slightly lower ultraviolet photon energy, but their plasma bombardment effect is stronger, making them suitable for the desorption of surface-adsorbed impurities.

[0045] In the above embodiments, unlike reactive plasmas such as oxygen plasma, the ultraviolet radiation and physical bombardment of the aforementioned inert gas plasma do not introduce new impurities, nor do they significantly damage the thickness and lattice structure of the original silicon oxide tunneling layer 320, thus meeting the requirements for ultra-thin, low-defect tunneling layers. Moreover, the energy of ultraviolet photons is selective, making them more easily absorbed by impurity chemical bonds, while having a smaller impact on the silicon oxide Si-O bonds (bond energy approximately 8 eV). Therefore, it can maintain the electrical stability of the tunneling layer while removing impurities, without etching the main structure of the silicon oxide tunneling layer.

[0046] In some preferred embodiments, the first gas may include an inert gas mixture. The inert gas mixture may include a mixture of two or more of helium, argon, neon, krypton, and xenon. For example, the inert gas mixture may be a mixture of helium and neon, or a mixture of argon and krypton. In a mixed inert gas plasma, energy transfer occurs between different atoms. For example, when the inert gas mixture is a mixture of helium and neon, after high-energy electrons excite He atoms, the excited state energy of He can be transferred to Ne atoms, causing Ne to emit higher-intensity 30.4 nm ultraviolet photons, whose radiation efficiency is much higher than that of a single inert gas. In this embodiment, the inert gas mixture can combine the advantages of high-energy ultraviolet radiation and controllable physical bombardment, efficiently breaking deep impurity chemical bonds while controlling the plasma bombardment intensity by adjusting the mixing ratio, thus avoiding thickness loss of the ultrathin tunneling layer. For example, increasing the proportion of neon can improve the efficiency of breaking deep impurity chemical bonds. Changing the proportion of krypton and / or xenon can adjust the plasma bombardment intensity.

[0047] In some alternative embodiments, the first gas may also include a weakly reactive gas. In the above embodiments, when the original thin film is a silicon oxide thin film, the weakly reactive gas may include hydrogen (H2) or nitrogen (N2) to avoid damaging the original tunneling layer 320 structure of the silicon oxide. When excited by N2 plasma, the molecules undergo electronic transitions, emitting ultraviolet photons with wavelengths of 210-300 nm and energies of 4.1-5.9 eV. The plasma emits ultraviolet photons at 105–120 nm with energies of 10.3–11.8 eV. The ultraviolet radiation energy from the ionization of these weakly reactive gases is also sufficient to break the chemical bonds of impurities. In addition to the photochemical effect of ultraviolet radiation, the reactive nitrogen particles (N2) generated by the aforementioned N2 plasma... It can react with carbon impurities to generate volatile CN and CN2. Active hydrogen particles in plasma (H It can react with metallic impurities to form metal hydrides, further improving impurity removal efficiency. During the introduction of a weakly reactive gas as the first gas, the plasma power and processing time must be strictly controlled to avoid the active particles etching the silicon oxide lattice (e.g., H₂). This could damage the Si-O bonds, leading to a decrease in the electrical performance of the tunneling layer.

[0048] Furthermore, in some optional embodiments, the first gas may include a mixture of an inert gas and a weakly reactive gas. For example, the first gas may include argon and nitrogen, or helium and hydrogen. By physically bombarding the inert gas, combined with the chemical action of the weakly reactive gas, and synergistic ultraviolet radiation, a balance can be achieved between efficient impurity removal and low substrate damage, which helps to improve the optimization of the original tunneling layer 320 of silicon oxide.

[0049] In some preferred embodiments, during step S230, the bias function in the heating plate 130 can be activated to allow particles dissociated from the first gas to enter structural units with a larger aspect ratio, meeting the step coverage requirement of the high aspect ratio via 310. Specifically, the bias establishes an electric field between the substrate and the plasma, with the field direction perpendicular to the wafer surface. This electric field directionally accelerates positively charged ions, giving them higher kinetic energy, and their movement direction is perpendicular to the wafer surface (i.e., enhanced directionality). For structural units with a large aspect ratio, this bias can directionally accelerate and increase the energy of ions, thereby enabling particles to penetrate the sheath region at the structure entrance, reducing sidewall collision losses, and overcoming charge repulsion within the structure (such as charge accumulation on the inner walls of deep holes hindering subsequent ion entry). This ensures that after reaching the bottom of the structure, the particles still have sufficient energy to remove impurities introduced during silicon oxide deposition.

[0050] Furthermore, during step S230, the temperature of the heating plate 130 is adjusted to a target high temperature to drive the migration of bulk phase atoms, thereby repairing defects such as vacancies in the vacancy film. For the silicon oxide tunneling layer, the improved tunneling layer film is denser, which reduces leakage current and increases the breakdown electric field, thus extending the memory's lifespan. Additionally, during the high-temperature plasma treatment of the first gas, the position of the heating plate 130 can be adjusted (e.g., moved up and down) to adjust the distance between the substrate 300 and the plasma.

[0051] Furthermore, in some optional embodiments, after performing step S230, the tunneling layer film can be further optimized to further improve the film quality.

[0052] Specifically, such as Figure 4 As shown, in some embodiments, the process method for semiconductor devices may further include steps S410 to S440.

[0053] First, step S410 can be performed: obtain the vacancy film after the removal of impurity atoms.

[0054] After completing step S230 above, after removing the impurity atoms from the original thin film, atomic vacancies will be generated in the thin film, forming a vacancy thin film.

[0055] Then, step S420 can be performed to determine the replacement elements based on the composition of the original film.

[0056] Optionally, in the above-described embodiment of the 3D NAND memory fabrication process, the original thin film is a silicon oxide tunneling layer 320. The original thin film is a silicon oxide thin film, and its composition is silicon and oxygen. Therefore, depending on the ease with which oxygen and silicon atoms can be filled, oxygen can be selected as the filling element.

[0057] In some alternative embodiments, the original thin film can be a silicon nitride thin film. In this embodiment, since the thin film composition is silicon and nitrogen, and nitrogen can be selected as the filling element depending on the ease with which nitrogen and silicon atoms can be filled.

[0058] Next, steps S430 and S440 can be performed. Step S430: Based on the replacement element, a second gas containing the replacement element is introduced into the process chamber. Step S440: The second gas is subjected to high-temperature plasma treatment to obtain replacement atoms of the replacement element, which are then used to fill the vacancies left by the removal of impurity atoms, thereby obtaining the target thin film.

[0059] Specifically, in the embodiment where the original thin film is a silicon oxide thin film, the replacement element is oxygen, and correspondingly, the second gas can be an oxygen source gas, such as oxygen. After high-temperature plasma treatment of the oxygen source gas, the ionized oxygen atoms can fill the oxygen vacancies generated after impurity atoms in the vacant thin film, thereby further reducing the defect density within the silicon oxide thin film. For example, in an embodiment where the first gas is helium and the second gas is oxygen, the flow rates of helium and oxygen can be controlled between 500 sccm and 1500 sccm. The power of the radio frequency system can be 2000W-4000W. The pressure within the process chamber 110 can be 50Pa-100Pa. The heating temperature of the heating plate 130 can be 600℃-800℃. The processing time is 5min-8min. After high-temperature plasma treatment, the tunneling layer of silicon oxide becomes denser, effectively suppressing the breakdown effect.

[0060] In other embodiments, where the original thin film is a silicon nitride thin film, the replacement element is nitrogen, and correspondingly, the second gas can be a nitrogen source gas, such as ammonia or nitrogen. By subjecting the nitrogen source gas to high-temperature plasma treatment, the ionized nitrogen atoms can fill the nitrogen vacancies created after impurity atoms detach from the vacancy film, thereby further reducing the defect density within the silicon nitride thin film.

[0061] It is important to emphasize that the order in which the first and second gases are introduced cannot be changed, and they cannot be introduced simultaneously. This invention achieves the function of impurity removal by first using the first gas for high-temperature plasma treatment to remove impurity atoms from the original thin film. Then, the second gas is used for high-temperature plasma treatment to fill the atomic vacancies left by the detached impurity atoms in the vacant film, thereby achieving the function of film repair. Therefore, if the second gas is introduced first, or if the first and second gases are introduced simultaneously, the aforementioned effects of impurity removal and film repair cannot be achieved.

[0062] Furthermore, in some preferred embodiments, during the process of obtaining the target film in step S440 above, the following process can also be performed to ensure that the quality of the obtained target film meets the preset standards.

[0063] Specifically, in some embodiments, the wet etching rate of the prepared thin film obtained after a single high-temperature plasma treatment with a second gas can be detected. For example, when the prepared thin film is a silicon oxide thin film, hydrofluoric acid can be used to test the wet etching rate (WER) of the silicon oxide, thereby obtaining the quality of the prepared silicon oxide thin film. When the wet etching rate of the prepared thin film is below a preset rate threshold, it can be determined that the quality of the prepared thin film has reached the standard of the target thin film. When the wet etching rate of the prepared thin film is greater than the rate threshold, it is determined that the prepared thin film has not reached the standard of the target thin film.

[0064] The following steps can be performed cyclically. In some embodiments, steps S220 and S230 can be repeated. A first gas (such as helium) is introduced into the process chamber 110. The first gas is subjected to high-temperature plasma treatment to ionize and release ultraviolet photons, which penetrate the surface of the prepared film via ultraviolet photons to remove impurity atoms inside, thereby further reducing the content of impurity atoms inside the prepared film.

[0065] In other embodiments, steps SS430 and S440 can be repeated. After obtaining the vacancy film of the pre-film, a second gas containing replacement elements is continued to be introduced. The second gas is subjected to high-temperature plasma treatment to obtain replacement atoms of the replacement elements, which fill the vacancies generated after the impurity atoms are removed, thereby further increasing the filling content of replacement atoms inside the pre-film.

[0066] In addition, in some optional embodiments, steps S220 and S230, as well as steps S430 and S440, can be repeated sequentially to simultaneously improve the effect of impurity removal and film repair in the prepared film.

[0067] After completing any of the above repeated cycles, the wet etching rate of the prepared film can be tested until the quality of the prepared film reaches the standard of the target film. For example, such as Figure 3B As shown, in the above-described embodiment of the 3D NAND memory fabrication process, the target thin film is the target tunneling layer 321, which is an optimized and improved silicon oxide thin film.

[0068] Specifically, please refer to Figure 5A . Figure 5A The diagram illustrates the results of wet etching rate testing of pre-films prepared using various different process methods, according to some embodiments of the present invention.

[0069] like Figure 5A In the illustrated embodiment, a 27nm thick unstructured silicon oxide substrate grown using the ALD process was used as a test piece. A 1% hydrofluoric acid solution was used to measure its wet etching rate (WER) to verify the effect of high-temperature plasma treatment on the quality of the silicon oxide film. A slower WER rate indicates higher quality silicon oxide film, lower defect and impurity content, denser film, and better film quality.

[0070] like Figure 5A As shown, for the sample film without any processing, high-temperature plasma treatment using either helium (first gas) or oxygen (second gas) alone can improve the quality of the silicon oxide pre-film to some extent, thereby reducing the wet etching rate of the silicon oxide pre-film by hydrofluoric acid solution. However, after dual high-temperature plasma treatment with helium and oxygen, the wet etching rate (WER) of the silicon oxide film decreased significantly, by 60% compared to the untreated sample film, indicating a substantial improvement in the quality of the silicon oxide pre-film.

[0071] Furthermore, you can refer to Figure 5B . Figure 5B The diagram illustrates the results of quality testing of films prepared using various different process methods, according to some embodiments of the present invention.

[0072] like Figure 5B As shown, for sample films without any processing, the interface defect density (DIT) and breakdown voltage (VBD) of the silicon oxide pre-film are improved to varying degrees after high-temperature plasma treatment with helium as the first gas and / or oxygen as the second gas. Furthermore, after dual high-temperature plasma treatment with helium and oxygen, the interface defect density of the silicon oxide pre-film is significantly reduced, and the breakdown voltage is greatly increased, thereby improving its breakdown resistance.

[0073] In addition, please refer to Figure 6 . Figure 6 The diagram shows the results of wet etching rate testing of the prepared thin film on the inner wall and bottom of the channel via according to some embodiments of the present invention.

[0074] In verifying the step coverage of the process in this invention for high aspect ratio structures using a 3D NAND structured substrate with vias, the entire substrate was subjected to high-temperature plasma treatment followed by slicing. Figure 6 The test results show that the WER (Wave Ergonomics) at the inner sidewall and bottom of the via is basically similar. This indicates that the semiconductor device fabrication method provided by this invention has good step coverage for high aspect ratio structures.

[0075] Those skilled in the art will understand that the above-described semiconductor device process method based on 3D NAND memory is merely a non-limiting embodiment provided by this invention, intended to clearly demonstrate the main concept of the invention and provide a specific solution convenient for public implementation, rather than to limit the scope of protection of this invention. The above-described semiconductor device process method provided by this invention is applicable to all processes in semiconductor manufacturing involving silicon oxide thin films, and its advantages are particularly prominent for structures with high aspect ratios.

[0076] In summary, the present invention provides a semiconductor device manufacturing method and a semiconductor device manufacturing apparatus, which can reduce the defect density inside the tunneling layer film, thereby improving the overall quality of the film. It can not only effectively reduce the occurrence of memory leakage current and extend its service life, but also improve the breakdown voltage of the memory, thereby enhancing its reliability.

[0077] Although the methods described above are illustrated and depicted as a series of actions for the sake of simplicity, it should be understood and appreciated that these methods are not limited by the order of the actions, as some actions may occur in a different order and / or concurrently with other actions from the illustrations and descriptions herein or not illustrated and described herein but which may be understood by those skilled in the art, according to one or more embodiments.

[0078] The prior description of this disclosure is provided to enable any person skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not intended to be limited to the examples and designs described herein, but should be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A process method for a semiconductor device, characterized in that, Includes the following steps: Obtain a substrate with the original thin film; The first gas is introduced into the process chamber; as well as The first gas is subjected to high-temperature plasma treatment to ionize and release ultraviolet photons. These ultraviolet photons penetrate the surface of the original thin film to remove impurity atoms inside. The energy of the ultraviolet photons generated by the first gas is greater than the chemical bond energy of the impurity atoms.

2. The process method as described in claim 1, characterized in that, The first gas includes at least one of an inert gas, an inert gas mixture, and a weakly reactive gas.

3. The process method as described in claim 2, characterized in that, The inert gas includes at least one of helium, argon, neon, krypton, and xenon, and the weakly reactive gas includes hydrogen or nitrogen.

4. The process method as described in claim 1, characterized in that, After the step of subjecting the first gas to high-temperature plasma treatment to ionize and stimulate the release of ultraviolet photons, the method further includes: Obtain the vacancy film after the impurity atoms have been removed; Based on the composition of the original thin film, the replacement elements are determined; According to the replacement element, a second gas containing the replacement element is introduced into the process chamber; and The second gas is subjected to high-temperature plasma treatment to obtain the replacement atoms of the replacement element, which are then used to fill the vacancies left by the detached impurity atoms, thereby obtaining the target thin film.

5. The process method as described in claim 4, characterized in that, The original thin film includes a silicon oxide thin film and a silicon nitride thin film. The step of determining the replacement element based on the composition of the original thin film includes: When the original thin film is a silicon oxide thin film, the replacement element is determined to be oxygen, and the second gas is an oxygen source gas; or When the original thin film is a silicon nitride thin film, the replacement element is determined to be nitrogen, and the second gas is a nitrogen source gas.

6. The process method as described in claim 4, characterized in that, The steps for obtaining the target thin film include: The wet etching rate of the prepared thin film obtained after a single high-temperature plasma treatment with the second gas was detected. In response to the wet etching rate of the prepared thin film being below a rate threshold, it is determined that the quality of the prepared thin film meets the standard of the target thin film; and In response to the wet etching rate of the prepared film being greater than the rate threshold, it is determined that the prepared film has not met the standard of the target film.

7. The process method as described in claim 6, characterized in that, After the step of determining that the prepared film does not meet the standard of the target film, the method further includes: Repeat the following steps: Continue to introduce the first gas into the process chamber; The first gas is subjected to the high-temperature plasma treatment, causing it to ionize and release ultraviolet photons. These ultraviolet photons penetrate the surface of the prepared thin film to remove impurity atoms within it; and / or After obtaining the vacancy film of the prepared film, the second gas is continued to be introduced; and The second gas is subjected to high-temperature plasma treatment to obtain the replacement atoms of the replacement element, which are then used to fill the vacancies created after the impurity atoms are removed, until the quality of the prepared film reaches the standard of the target film.

8. The process method as described in claim 1, characterized in that, The step of obtaining a substrate with the original thin film includes: Obtaining a substrate with via channels; and A barrier layer, a storage layer, and a primary tunneling layer are sequentially deposited inside the via. The primary tunneling layer is a silicon oxide thin film, which serves as the primary film to be processed.

9. A semiconductor device manufacturing apparatus, characterized in that, include: The process chamber has an air inlet at its upper end for introducing process gas; The radio frequency system includes a radio frequency power supply and a radio frequency coil surrounding the outside of the process cavity, for plasma treatment of the process gas within the process cavity; as well as A heating plate on which a substrate is placed is used to perform a semiconductor device process as described in any one of claims 1 to 8 on a raw thin film on the surface of the substrate.

10. The process equipment as described in claim 9, characterized in that, The heating plate includes electrodes, the lower end of which is connected to a variable capacitor. By changing the position of the variable capacitor, the acceleration energy of ions in the vertical direction during the plasma treatment process can be adjusted.

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