Embedded power module, circuit structure and design method

Abstract

The invention belongs to the technical field of semiconductors, and discloses an embedded power module, a circuit structure and a design method.A TEC radiator and an MOS chip are closely integrated, and the TEC radiator is started in advance before the MOS chip is started by using the active refrigeration capability of the TEC radiator, so that rapid and local thermal suppression is provided at the moment when the MOS chip is started, and the reliability of the embedded power module is improved. A large amount of heat instantaneously released by the MOS chip can be dissipated more timely, the problem of local high temperature generated instantaneously when the MOSFET is switched on in the high-frequency switching process is effectively solved, the generation of temperature peaks is avoided, in addition, the heat dissipation problem is solved, meanwhile, the rapid high-frequency response capability of the MOSFET is not sacrificed, and the performance of the MOSFET chip is fully utilized.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to an embedded power module, circuit structure, and design method. Background Technology

[0002] MOSFETs (Metal-Oxide-Semiconductor Transistors), especially SiC MOSFETs, pose a severe challenge to device reliability in high-frequency, high-power-density applications under high current-rate-of-change conditions due to their rapid temperature rise. This rapid temperature rise typically exhibits a localized, sharp temperature spike, which is far more destructive than an increase in average junction temperature. Specifically, during the turn-on instant of a MOSFET in a high-frequency switching process, it experiences a rapidly rising current, resulting in extremely high instantaneous power dissipation and the release of a large amount of heat.

[0003] Traditional MOSFET devices primarily rely on conjugate thermal conduction to transfer heat from the chip to the outside environment, thereby reducing junction temperature. However, this method is inefficient, preventing the rapid dissipation of large amounts of heat and leading to localized high temperatures (exceeding 250°C for SiC MOSFETs). These localized high temperatures cause uneven thermal stress within the material, which can easily lead to structural damage and shorten device lifespan.

[0004] To address the aforementioned issues, current solutions typically involve increasing the gate resistance of the MOSFET, thereby reducing the rate of change of current during turn-on. However, this approach sacrifices the MOSFET's rapid high-frequency response capability, essentially reducing its frequency and rated usage, failing to fully utilize the MOSFET chip's performance. Therefore, effectively resolving the issue of localized high temperatures generated during the turn-on process of MOSFETs at high frequencies, without sacrificing their high-frequency response capability, is a pressing technical challenge that needs to be addressed.

[0005] To address the aforementioned issues, existing technologies urgently need improvement. Summary of the Invention

[0006] The purpose of this application is to provide an embedded power module, circuit structure and design method that can effectively solve the problem of local high temperature generated during the turn-on instant of MOSFET in high-frequency switching process without sacrificing its high-frequency response capability.

[0007] In a first aspect, this application provides an embedded power module, including a heat dissipation substrate, at least one MOS chip, a TEC heat sink, chip pins, heat sink pins, and a plastic package; Both the MOS chip and the TEC heat sink are disposed on the upper surface of the heat sink substrate. The TEC heat sink has a cutout area, and the MOS chip is disposed within the cutout area. The MOS chip is electrically connected to the chip pins, and the TEC heat sink is electrically connected to the heat sink pins; The encapsulation body encapsulates the heat dissipation substrate, the MOS chip, the TEC heat sink, the chip pins, and the heat sink pins, with the lower surface of the heat dissipation substrate and the upper surface of the TEC heat sink exposed, and each chip pin and each heat sink pin being at least partially exposed.

[0008] Preferably, the MOS chip is a SiC MOSFET chip.

[0009] Optionally, the chip pins and the heat sink pins extend laterally out of the plastic package.

[0010] Optionally, both the chip pins and the heat sink pins extend downwards and are exposed from the lower surface of the molding compound.

[0011] Optionally, one MOS chip is provided.

[0012] Optionally, two MOS chips are provided, and the two MOS chips are connected to form a half-bridge circuit.

[0013] Secondly, this application provides a circuit structure including the embedded power module and driving circuit described above. The driving circuit includes a driving MOSFET, at least one first capacitor, and a second capacitor. The number of first capacitors is the same as the number of MOSFETs in the embedded power module, and each first capacitor is connected between the gate and source of each MOSFET in a one-to-one correspondence. The second capacitor is connected between the gate and source of the driving MOSFET. The capacitance of the second capacitor is less than the capacitance of the first capacitor. The TEC heat sink of the embedded power module is connected to the driving MOSFET. The driving circuit is used to control the on / off state of the MOS chip and the driving MOS transistor using an externally input PWM signal, and to enable the driving MOS transistor to turn on before each MOS chip by using the charging time difference between the first capacitor and the second capacitor, thereby driving the TEC heat sink to start before each MOS chip, so as to form a thermal suppression effect at the moment when the MOS chip turns on.

[0014] Optionally, the embedded power module is provided with one MOS chip, and the first capacitor is correspondingly provided with one; The driving circuit also includes a signal input terminal, two diodes, and a DC power supply; The signal input terminal is used to input an external PWM signal. The anode of the first diode, the first terminal of the first capacitor, and the gate of the MOS chip are all connected to the signal input terminal. The second terminal of the first capacitor is connected to the source of the MOS chip and grounded. The TEC heat sink is connected in parallel with the second diode between the drain of the driving MOS transistor and the DC power supply, and the anode of the second diode is connected to the drain of the driving MOS transistor, and the cathode is connected to the DC power supply.

[0015] Optionally, the embedded power module is provided with two MOS chips, and the two MOS chips are connected to form a half-bridge circuit, and two first capacitors are provided accordingly; The driving circuit also includes two signal input terminals, three diodes, and a DC power supply; The two signal input terminals are used to input two external PWM signals, respectively. The anode of the first diode, the first terminal of the first capacitor, and the gate of the first MOS chip are all connected to the first signal input terminal, and the second terminal of the first capacitor is connected to the source of the first MOS chip and the drain of the second MOS chip. The anode of the second diode, the first terminal of the second first capacitor, and the gate of the second MOS chip are all connected to the second signal input terminal, and the second terminal of the second first capacitor and the source of the second MOS chip are connected and grounded; The cathodes of the first and second diodes and the first terminal of the second capacitor are both connected to the gate of the driving MOS transistor, and the second terminal of the second capacitor is connected to the source of the driving MOS transistor and grounded. The TEC heat sink is connected in parallel with the third diode between the drain of the driving MOS transistor and the DC power supply, and the anode of the third diode is connected to the drain of the driving MOS transistor, and the cathode is connected to the DC power supply.

[0016] Thirdly, this application provides a design method for designing the first capacitor and the second capacitor in the circuit structure described above; the design method includes the following steps: A1. Based on the structure of the embedded power module, establish a simulation model of the embedded power module; A2. Based on the simulation model, the optimal advance time for the TEC heat sink to start before the MOS chip at the preset operating frequency is determined through simulation calculation; A3. Determine the capacitance values ​​of the first capacitor and the second capacitor based on the optimal advance time, so that the difference between the charging time of the first capacitor and the charging time of the second capacitor is equal to the optimal advance time.

[0017] Beneficial Effects: This application provides an embedded power module, circuit structure, and design method that tightly integrates a TEC heatsink with a MOS chip and utilizes the active cooling capability of the TEC heatsink to provide rapid, localized thermal suppression at the instant the MOS chip is turned on. Compared with traditional conjugate heat conduction cooling methods, this application's solution can dissipate the large amount of heat released instantaneously by the MOS chip more promptly, effectively solving the problem of localized high temperatures generated during the high-frequency switching process of the MOSFET and avoiding temperature spikes. Furthermore, through the pre-start mechanism of the TEC heatsink, this application solves the heat dissipation problem without sacrificing the fast high-frequency response capability of the MOSFET, fully utilizing the performance of the MOSFET chip. Therefore, the embedded power module of this application significantly improves the reliability and lifespan of the device, overcoming the shortcomings of existing technologies such as low heat dissipation efficiency, device structural damage caused by localized high temperatures, and sacrifice of high-frequency response capability. Attached Figure Description

[0018] Figure 1 A perspective view of the first type of embedded power module provided in this application.

[0019] Figure 2 This is an internal structure diagram of the first type of embedded power module provided in this application.

[0020] Figure 3 A bottom view of the second type of embedded power module provided in this application.

[0021] Figure 4 This is an internal structure diagram of the second type of embedded power module provided in this application.

[0022] Figure 5 A schematic diagram of the third type of embedded power module provided in this application.

[0023] Figure 6 A schematic diagram of the first circuit structure provided in this application.

[0024] Figure 7 A schematic diagram of the second circuit structure provided in this application.

[0025] Figure 8 A flowchart of the design method provided for this application.

[0026] Figure 9 This is a schematic diagram of the turn-on current curves for the MOS chip and the TEC heatsink.

[0027] Labeling Explanation: 1. Heat dissipation substrate; 2. MOS chip; 3. TEC heat sink; 4. Chip pin; 5. Heat sink pin; 6. Molded package; 100. Embedded power module; 200. Driver circuit; 201. Driver MOS transistor; 202. First capacitor; 203. Second capacitor; 204. Signal input terminal; 205. Diode; 206. DC power supply. Detailed Implementation

[0028] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely represents selected embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0029] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, in the description of this application, terms such as "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0030] Please refer to Figures 1-5 An embedded power module 100 in some embodiments of this application includes a heat dissipation substrate 1, at least one MOS chip 2, a TEC heat sink 3, chip pins 4, heat sink pins 5, and a plastic package 6. Both the MOS chip 2 and the TEC heat sink 3 are disposed on the upper surface of the heat dissipation substrate 1. The TEC heat sink 3 has a hollow area, and the MOS chip 2 is disposed in the hollow area. MOS chip 2 is electrically connected to chip pin 4, and TEC heat sink 3 is electrically connected to heat sink pin 5 (it can be understood that the number of chip pins 4 is adapted to MOS chip 2, and each electrode of MOS chip 2 is connected to the corresponding chip pin 4; the number of heat sink pins 5 is adapted to TEC heat sink 3, and the electrodes of TEC heat sink 3 are connected to the corresponding heat sink pin 5). The molding compound 6 encapsulates the heat dissipation substrate 1, MOS chip 2, TEC heat sink 3, chip pin 4, and heat sink pin 5, with the lower surface of the heat dissipation substrate 1 and the upper surface of the TEC heat sink 3 exposed, and each chip pin 4 and each heat sink pin 5 being at least partially exposed.

[0031] This application achieves tight integration between the TEC heatsink 3 and the MOS chip 2 by embedding the MOS chip 2 into the hollow area of ​​the TEC heatsink 3 and encapsulating it as a whole. This allows for faster and more efficient local heat dissipation when the MOS chip 2 is working, effectively suppressing instantaneous temperature spikes while maintaining the compactness and reliability of the module.

[0032] It should be noted that, during use, the embedded power module 100 of this application, under the control of an external control system, allows the TEC heatsink 3 to remain operational (i.e., maintain current flow) when the MOS chip 2 is in the ON state, and also to remain operational during the ON process of the MOS chip 2 and gradually shut down after the MOS chip 2 is fully ON (thus reducing energy consumption). When the TEC heatsink 3 is not operational (i.e., no current flow), its thermal resistance is greater than that of the plastic encapsulation 6. If the TEC heatsink 3 completely covers the MOS chip 2, it will hinder heat dissipation when the TEC heatsink 3 is not always operational when the MOS chip 2 is in the ON state. Therefore, the TEC heatsink 3 adopts a hollow design, and the MOS chip 2 is placed within the hollow area of ​​the TEC heatsink 3 to avoid this problem.

[0033] The hollowed-out area of ​​the TEC heatsink 3 can be a semi-enclosed structure (in this case, the TEC heatsink 3 semi-encloses the MOS chip 2, such as...). Figure 2 , Figure 4 (as shown) or a fully enclosed structure (in this case, the TEC heatsink 3 fully encloses the MOS chip 2, as shown) Figure 5 (As shown).

[0034] The heat dissipation substrate 1 is the basic structure of the embedded power module 100, mainly used to provide mechanical support and heat conduction path. It is usually made of materials with good thermal conductivity, such as ceramics (e.g., aluminum nitride, alumina) or metal matrix composites (e.g., copper-molybdenum alloy), to ensure that heat can be effectively conducted away from the MOS chip 2.

[0035] MOS chip 2 is the core functional device of the power module, responsible for switching and converting electrical energy. It generates a lot of heat during operation, especially during high-frequency switching.

[0036] The TEC heatsink 3, or semiconductor heatsink, is a device that utilizes the Peltier effect for active cooling. When current flows through the TEC heatsink 3, one side absorbs heat and cools down, while the other side releases heat and heats up. In this application, the TEC heatsink 3 is configured to actively absorb the heat generated by the MOS chip 2 to achieve rapid localized cooling.

[0037] Chip pin 4 and heatsink pin 5 are terminals used for electrical connections between the embedded power module 100 and external circuitry. They are typically made of a highly conductive metal, such as copper or a copper alloy, and are surface-treated to improve solderability and reliability. Leads or connecting tabs (such as...) can be used between the MOS chip 2 and chip pin 4, and between the TEC heatsink 3 and heatsink pin 5. Figure 4 Connectors (as shown) are used for connection.

[0038] The molding compound 6 is used to encapsulate and protect the components inside the embedded power module 100, preventing damage from external environmental factors such as moisture and dust, while also providing insulation and mechanical support. The molding compound material is typically epoxy resin or silicone, which have good insulation and heat resistance properties.

[0039] The embedded power module 100 of this application achieves tight integration between the TEC heatsink 3 and the MOS chip 2 by embedding the MOS chip 2 into the hollow area of ​​the TEC heatsink 3 and encapsulating it entirely in plastic. When the MOS chip 2 generates instantaneous high temperature during high-frequency switching, the TEC heatsink 3 can quickly start (or even start ahead of time) to actively absorb the heat generated by the MOS chip 2. This localized and rapid cooling effectively suppresses the temperature spike generated by the MOS chip 2 at the moment of turn-on, thereby significantly reducing local high temperature, avoiding device structural damage caused by thermal stress, and extending device life. At the same time, since the TEC heatsink 3 is an active cooler, its cooling effect is not limited by the external ambient temperature and can provide stable heat dissipation performance under various operating conditions. In addition, the plastic-encapsulated structure of the module provides good protection for the internal components, ensuring the long-term reliability of the module. The exposed design of the lower surface of the heat sink 1 and the upper surface of the TEC heatsink 3 further optimizes the overall heat dissipation capability of the module, enabling it to work better with the external heat dissipation system.

[0040] The embedded power module 100 proposed in this application represents a significant technological advancement compared to the heat dissipation structures of traditional MOSFET devices. Traditional heat dissipation structures primarily rely on conjugate heat conduction to transfer heat from the chip to the outside environment. This method is inefficient when facing localized, rapid temperature spikes generated during high-frequency switching, resulting in heat accumulation and localized high temperatures. In contrast, this application achieves tight integration between the MOSFET chip 2 and the MOSFET chip 2 by embedding the MOSFET chip 2 within the cutout area of ​​the TEC heatsink 3 and encapsulating it entirely. This design allows the TEC heatsink 3 to directly and efficiently provide localized active cooling for the MOSFET chip 2. Utilizing the Peltier effect, the TEC heatsink 3 can quickly activate and actively absorb heat when the MOSFET chip 2 generates instantaneous high temperatures, effectively suppressing temperature spikes. This active cooling method overcomes the low efficiency of traditional passive heat dissipation, enabling more timely and effective heat removal from the chip. Furthermore, while increasing the gate resistance of the MOSFET to reduce the instantaneous current change rate in traditional solutions can alleviate temperature spikes, it sacrifices the MOSFET's fast high-frequency response capability. The embedded power module 100 of this application fundamentally solves the problem of localized high temperature by optimizing the heat dissipation structure without sacrificing the high-frequency response capability of the MOS chip 2. Therefore, the embedded power module 100 of this application demonstrates significant advantages and innovations in improving the reliability and lifespan of the power module, as well as in fully utilizing the high-frequency and high-power-density performance of the MOS chip 2.

[0041] The specific type of MOS chip 2 can be selected according to actual needs.

[0042] Preferably, MOS chip 2 is a SiC MOSFET chip.

[0043] Specifically, SiC MOSFET chips refer to metal-oxide-semiconductor field-effect transistor chips manufactured using silicon carbide (SiC) material. Compared to traditional silicon (Si)-based MOSFET chips, SiC MOSFET chips possess superior material properties such as a wider bandgap, higher critical electric field strength, and higher thermal conductivity. These properties enable SiC MOSFET chips to operate stably at higher voltages, higher frequencies, and higher temperatures, while exhibiting lower on-resistance and lower switching losses. In practical applications, SiC MOSFET chips can be understood as high-performance power semiconductor devices designed to improve the power conversion efficiency and reliability of power modules.

[0044] Through the above technical solutions, the overall performance of the embedded power module 100 is significantly improved. Specifically, the use of SiC MOSFET chips effectively reduces the conduction and switching losses of the power module, thereby improving power conversion efficiency. Simultaneously, due to the higher voltage withstand capability and faster switching speed of SiC MOSFET chips, the power module can operate at higher voltages and frequencies, achieving higher power density. Furthermore, the excellent high-temperature resistance and thermal conductivity of SiC MOSFET chips, combined with the TEC heatsink 3, further enhance the thermal management capabilities of the power module, improving its reliability and lifespan in harsh environments.

[0045] In some implementations, see Figure 1 Chip pin 4 and heat sink pin 5 extend laterally out of the plastic package 6.

[0046] Specifically, "extending laterally outside the molding compound 6" means that after the chip pins 4 and heat sink pins 5 are encapsulated by the molding compound 6, their exposed portions extend from the side surface (excluding the top and bottom surfaces) of the molding compound 6. For example, these pins can be designed to extend outwards approximately parallel to the plane of the heat sink substrate 1, rather than extending downwards or upwards perpendicular to the plane of the heat sink substrate 1. The purpose is to provide a standardized pin layout for the embedded power module 100 that facilitates external circuit connections.

[0047] This side-extending design facilitates direct surface mounting of the pins to pads on the printed circuit board (PCB) or through-hole mounting, simplifying the module installation process. Simultaneously, this layout helps reduce the overall height of the module, allowing the embedded power module 100 to be better integrated into space-constrained electronic devices.

[0048] In other implementations, see Figure 3 , Figure 4 Both chip pin 4 and heat sink pin 5 extend downwards and are exposed from the lower surface of the plastic package 6.

[0049] Specifically, at this time, chip pin 4 and heat sink pin 5 are usually metal blocks (such as...). Figure 4 As shown), the lower surface of the metal block protrudes from the lower surface of the encapsulation 6; however, the structure of the chip pin 4 and the heat sink pin 5 is not limited to this.

[0050] With the above technical solution, since both chip pin 4 and heat sink pin 5 are led out from the lower surface of the plastic package 6, the embedded power module 100 can achieve a more compact package structure, effectively reducing the overall size of the module, especially in the lateral dimension. Furthermore, this pin layout greatly simplifies the connection process between the module and external circuits (such as printed circuit boards), facilitating automated assembly using surface mount technology, improving production efficiency and connection reliability, while also helping to optimize the module's heat dissipation path and electrical performance.

[0051] The number of MOS chips 2 and the connection structure between MOS chips 2 can be set according to actual needs.

[0052] For example, in some possible implementations, see Figure 2 and Figure 4 There is one MOS chip 2.

[0053] This single MOS chip 2 configuration aims to simplify the internal circuit connections and layout of the module, reduce the number of required pins, and optimize the overall package structure. The solution in this application effectively simplifies the internal structure of the embedded power module 100 by limiting the number of MOS chips 2 to a single one. Since only the electrical connections and heat dissipation of one MOS chip 2 need to be managed, the number of chip pins 4 can be reduced, and the wiring inside the plastic package 6 can be simplified. This simplification not only reduces the complexity of the manufacturing process but also makes miniaturization of the module possible. Furthermore, the single MOS chip 2 configuration also makes the design of the drive circuit more straightforward, avoiding the complex problems of current sharing and voltage sharing caused by multiple chips connected in parallel or series.

[0054] In other implementations, see Figure 5 and Figure 7 There are two MOS chips 2, and the two MOS chips 2 are connected to form a half-bridge circuit.

[0055] A half-bridge circuit is a basic power conversion topology, typically consisting of two series-connected switching devices (e.g., MOS chip 2) and a midpoint. One MOS chip 2 acts as the high-side switch, and the other MOS chip 2 acts as the low-side switch. The connection between these two MOS chips 2 creates a common connection point between their source and drain, which typically serves as the output terminal of the half-bridge (e.g., ...). Figure 7 (AC terminal in the circuit). This connection method allows the two MOS chips 2 to work together, controlling the current flow and voltage output by alternately turning them on and off.

[0056] The solution presented in this application effectively overcomes the limitations of a single MOS chip 2 in constructing complex power conversion topologies by integrating two MOS chips 2 into the same embedded power module 100 and configuring them as a half-bridge circuit. In the half-bridge circuit, the two MOS chips 2, through complementary or alternating switching operations, can achieve chopping or inverting functions for the DC power supply. For example, when the high-side MOS chip is turned on, current flows from the power supply to the load; when the low-side MOS chip is turned on, current flows from the load to ground. By precisely controlling the switching timing of these two MOS chips 2, the required AC voltage or pulse width modulation (PWM) signal can be generated, thereby achieving efficient power conversion. This integration method reduces external wiring and parasitic inductance, improves switching speed and efficiency, and reduces system noise.

[0057] refer to Figure 6 , Figure 7 This application provides a circuit structure including the aforementioned embedded power module 100 and a driving circuit 200. The driving circuit 200 includes a driving MOSFET 201, at least one first capacitor 202, and a second capacitor 203. The number of first capacitors 202 is the same as the number of MOSFET chips 2 in the embedded power module 100, and each first capacitor 202 is connected between the gate and source of each MOSFET chip 2 in a one-to-one correspondence. The second capacitor 203 is connected between the gate and source of the driving MOSFET 201. The capacitance of the second capacitor 203 is smaller than the capacitance of the first capacitor 202 (therefore, the charging time of the second capacitor 203 is shorter than the charging time of the first capacitor 202). The TEC heat sink 3 of the embedded power module 100 is connected to the driving MOSFET 201. The driving circuit 200 is used to control the on / off state of the MOS chip 2 and the driving MOS transistor 201 using an externally input PWM signal. By using the charging time difference between the first capacitor 202 and the second capacitor 203, the driving MOS transistor 201 is turned on before each MOS chip 2. Thus, the driving MOS transistor 201 drives the TEC heat sink 3 to start before each MOS chip 2, so as to form a thermal suppression effect at the moment the MOS chip 2 is turned on.

[0058] This circuit structure aims to solve the problem of localized temperature spikes caused by rapid temperature rise of the MOS chip 2 under high current change rate conditions in traditional MOSFET applications at high frequencies and high power densities, while avoiding sacrificing its high-frequency response capability. By introducing a drive circuit 200 and cleverly utilizing the charging time difference between the first capacitor 202 and the second capacitor 203, this application enables the drive MOS transistor 201 to turn on before the MOS chip 2, thereby ensuring that the TEC heatsink 3 is pre-started before the MOS chip 2 turns on. This pre-start mechanism allows the TEC heatsink 3 to locally cool the MOS chip 2 before it generates a large amount of instantaneous heat, thus forming an effective thermal suppression effect at the moment the MOS chip 2 turns on, significantly reducing temperature spikes and improving device reliability and lifespan.

[0059] The specific structure and working principle of the embedded power module 100 have been described in the above embodiments and will not be repeated here. It should be emphasized that the embedded power module 100 integrates the MOS chip 2 and the TEC heatsink 3, providing the core power switch and active cooling unit for the circuit structure of this application. The circuit structure of this application further includes a drive circuit 200. The core function of the drive circuit 200 is to precisely control the on / off state of the MOS chip 2 in the embedded power module 100 and coordinate the startup timing of the TEC heatsink 3.

[0060] The driving MOSFET 201 in the driving circuit 200 serves as a switch or control element for the TEC heatsink 3. For example, the driving MOSFET 201 can be an independent power MOSFET, whose on and off states directly affect the power supply to the TEC heatsink 3. In some implementations, the driving MOSFET 201 can also be a BJT transistor or a relay, as long as it can control the power supply to the TEC heatsink 3.

[0061] The first capacitor 202 is mainly used to influence the rising edge of the gate voltage of the MOS chip 2, thereby indirectly controlling the turn-on time of the MOS chip 2. For example, the first capacitor 202 can be a ceramic capacitor, a film capacitor, or an electrolytic capacitor, and its capacitance value directly affects the gate charging time of the MOS chip 2. The second capacitor 203 is connected between the gate and source of the driving MOS transistor 201. Its function is to influence the rising edge of the gate voltage of the driving MOS transistor 201, thereby controlling the turn-on time of the driving MOS transistor 201. The second capacitor 203 can also be a capacitor of the above type, but its capacitance value is designed to be smaller than that of the first capacitor 202. This capacitance difference is the key to enabling the driving MOS transistor 201 to turn on before the MOS chip 2.

[0062] The TEC heatsink 3 is connected to the driver MOSFET 201. This connection ensures that the driver MOSFET 201 can directly control the power supply and startup of the TEC heatsink 3. For example, the TEC heatsink 3 can be connected in series between the drain of the driver MOSFET 201 and the power supply. When the driver MOSFET 201 is turned on, current flows through the TEC heatsink 3, causing it to begin cooling. Alternatively, the TEC heatsink 3 can also be connected to the driver MOSFET 201 through a separate switching circuit. The driver MOSFET 201 provides a control signal to trigger this switching circuit, thereby controlling the power supply to the TEC heatsink 3.

[0063] The driving circuit 200 operates by using an externally input PWM signal to control the switching of the MOS chip 2 and the driving MOS transistor 201. It utilizes the charging time difference between the first capacitor 202 and the second capacitor 203 to ensure that the driving MOS transistor 201 turns on before each MOS chip 2. Specifically, when the PWM signal arrives, because the capacitance of the second capacitor 203 is smaller than that of the first capacitor 202, the time required for the second capacitor 203 to charge to the turn-on voltage of the driving MOS transistor 201 is shorter than the time required for the first capacitor 202 to charge to the turn-on voltage of the MOS chip 2. Therefore, the driving MOS transistor 201 turns on before the MOS chip 2. Once the driving MOS transistor 201 turns on, the TEC heatsink 3 immediately starts, beginning pre-cooling the MOS chip 2 (the current changes of the TEC heatsink 3 and the MOS chip 2 during this process are as follows...). Figure 9 As shown, Δt represents the time advance that the driving MOSFET 201 turns on before the MOSFET chip 2, and I ds I is the current of MOS chip 2. TEC (This refers to the current of the TEC heatsink 3). This pre-cooling effect occurs before the MOS chip 2 is actually turned on and generates a large amount of instantaneous heat, thus creating an effective thermal suppression effect at the moment the MOS chip 2 is turned on. For example, the PWM signal can be provided by an external controller, and its frequency and duty cycle can be adjusted according to the actual application requirements. Precise control of the charging time difference can be achieved by selecting a capacitor with an appropriate capacitance value, or it can be fine-tuned by introducing additional delay elements in the gate drive circuit.

[0064] The core innovation of this application lies in introducing a dedicated driving circuit 200 and cleverly utilizing the charging time difference between the first capacitor 202 and the second capacitor 203 to pre-start the TEC heatsink 3 before the MOS chip 2 is turned on. This active, time-controlled pre-cooling mechanism allows the TEC heatsink 3 to locally cool the MOS chip 2 before it generates a large amount of instantaneous heat. Therefore, at the instant the MOS chip 2 is turned on, a thermal suppression effect is already formed, significantly reducing local temperature spikes and preventing device structural damage caused by thermal stress. This solution fundamentally solves the problem of local high temperatures without affecting the high-frequency switching performance of the MOS chip 2, fully leveraging the advantages of the MOS chip 2 in high-frequency, high-power-density applications, and greatly improving the reliability and lifespan of the power module.

[0065] In some possible implementations, see Figure 6 For the case where the embedded power module 100 has a MOS chip 2, the first capacitor 202 is correspondingly provided with one; At this time, the drive circuit 200 also includes a signal input terminal 204, two diodes 205 and a DC power supply 206; Signal input terminal 204 is used to input external PWM signals. The anode of the first diode 205, the first terminal of the first capacitor 202, and the gate of the MOS chip 2 are all connected to signal input terminal 204. The second terminal of the first capacitor 202 is connected to the source of the MOS chip 2 and grounded. The TEC heat sink 3 and the second diode 205 are connected in parallel between the drain of the driving MOSFET 201 and the DC power supply 206. The anode of the second diode 205 is connected to the drain of the driving MOSFET 201, and the cathode is connected to the DC power supply 206.

[0066] Specifically, when the embedded power module 100 contains only one MOS chip 2, the configuration of the drive circuit 200 can be simplified and optimized. The signal input terminal 204 is configured to receive an external pulse width modulation (PWM) signal, which controls the on / off state of the MOS chip 2 and the driving MOS transistor 201. A first diode 205 is configured to guide current, with its anode electrically connected to the signal input terminal 204, the first terminal of the first capacitor 202, and the gate of the MOS chip 2, ensuring that the PWM signal can be effectively transmitted to the gate of the MOS chip 2 and providing a charging path for the first capacitor 202. The second terminal of the first capacitor 202 is connected to the source of the MOS chip 2 and grounded, forming a bypass capacitor between the gate and source of the MOS chip 2. Furthermore, the TEC heatsink 3 is designed to be connected in parallel with the second diode 205, and this parallel structure is further connected between the drain of the driving MOS transistor 201 and the DC power supply 206. The anode of the second diode 205 is connected to the drain of the aforementioned driving MOSFET 201, and the cathode is connected to the aforementioned DC power supply 206. This configuration is designed to ensure that the TEC heatsink 3 receives a stable power supply when the driving MOSFET 201 is turned on, and to prevent reverse current from damaging the TEC heatsink 3. The aforementioned DC power supply 206 provides the necessary energy for the entire driving circuit 200.

[0067] The above technical solution provides a specific and optimized drive circuit structure for an embedded power module 100 containing only one MOS chip 2. This structure clearly defines the connection methods of the signal input terminal 204, diode 205, and DC power supply 206, thereby simplifying circuit design and reducing implementation complexity. Simultaneously, this explicit connection ensures that the TEC heatsink 3 can reliably start up before the MOS chip 2 is powered on, effectively achieving thermal suppression in single-MOS chip 2 applications, improving the operational stability and reliability of the power module, and helping to extend the lifespan of the MOS chip 2.

[0068] In some possible implementations, see Figure 7 For the case where the embedded power module 100 is equipped with two MOS chips 2 and the two MOS chips 2 are connected to form a half-bridge circuit, two first capacitors 202 are correspondingly provided. At this time, the drive circuit 200 also includes two signal input terminals 204, three diodes 205 and a DC power supply 206; The two signal input terminals 204 are used to input two external PWM signals respectively; The anode of the first diode 205, the first terminal of the first capacitor 202, and the gate of the first MOS chip 2 (referring to the high-side MOS chip) are all connected to the first signal input terminal 204. The second terminal of the first capacitor 202 is connected to the source of the first MOS chip 2 and the drain of the second MOS chip 2 (referring to the low-side MOS chip). The anode of the second diode 205, the first terminal of the second first capacitor 202, and the gate of the second MOS chip 2 are all connected to the second signal input terminal 204. The second terminal of the second first capacitor 202 and the source of the second MOS chip 2 are connected and grounded. The cathodes of the first and second diodes 205 and the first terminal of the second capacitor 203 are both connected to the gate of the driving MOSFET 201, and the second terminal of the second capacitor 203 is connected to the source of the driving MOSFET 201 and grounded. The TEC heat sink 3 and the third diode 205 are connected in parallel between the drain of the driving MOSFET 201 and the DC power supply 206. The anode of the third diode 205 is connected to the drain of the driving MOSFET 201, and the cathode is connected to the DC power supply 206.

[0069] This application's solution achieves independent and precise drive control of the two MOS chips 2 in the half-bridge circuit by introducing two independent signal input terminals 204 and corresponding diodes 205 and first capacitors 202. When the first PWM signal is input, it charges the gate of the first MOS chip 2 through the first capacitor 202, and simultaneously, the signal acts on the gate of the driving MOS transistor 201 through the first diode 205. Similarly, when the second PWM signal is input, it charges the gate of the second MOS chip 2 through the second first capacitor 202, and simultaneously acts on the gate of the driving MOS transistor 201 through the second diode 205. Since the gate of the driving MOS transistor 201 simultaneously receives signals from both diodes 205 and is connected to the second capacitor 203, and the capacitance of the second capacitor 203 is smaller than that of the first capacitor 202, the driving MOS transistor 201 will turn on before the corresponding MOS chip 2, regardless of which MOS chip 2 is about to turn on. Once the driving MOS transistor 201 is turned on, the DC power supply 206 supplies power to the TEC heatsink 3 through the driving MOS transistor 201, enabling it to start. Therefore, the TEC heatsink 3 is activated the instant either MOS chip 2 is turned on, thus providing effective thermal suppression before the MOS chip 2 begins to conduct and generate heat. This design ensures that both MOS chips 2 in the half-bridge circuit receive timely thermal management during their respective operating cycles, effectively preventing performance degradation or damage caused by heat accumulation.

[0070] Through the above technical solution, this application provides an optimized driving and thermal management scheme for an embedded power module 100 containing two MOS chips 2 forming a half-bridge circuit. This scheme, through independent PWM signal input and precise capacitor configuration, ensures that each MOS chip 2 in the half-bridge circuit is pre-activated by the TEC heatsink 3 before power-on, thus achieving efficient and reliable instantaneous thermal suppression even in complex scenarios involving multiple chips working together. This not only improves the operational stability and reliability of the half-bridge circuit but also extends the lifespan of the MOS chips 2, making it particularly suitable for applications with high power density and thermal management requirements. It effectively solves the complexity of thermal management timing control in traditional half-bridge topologies.

[0071] refer to Figure 8 This application also provides a design method for designing the first capacitor 202 and the second capacitor 203 in the circuit structure described above; the design method includes the following steps: A1. Based on the structure of the embedded power module 100, establish a simulation model of the embedded power module 100; A2. Based on the simulation model, the optimal advance time for the TEC heat sink 3 to start before the MOS chip 2 under the preset operating frequency is determined by simulation calculation. A3. Determine the capacitance values ​​of the first capacitor 202 and the second capacitor 203 based on the optimal advance time, so that the difference between the charging time of the first capacitor 202 and the charging time of the second capacitor 203 is equal to the optimal advance time.

[0072] The design method proposed in this application aims to address the serious challenge to device reliability posed by rapid temperature rise in traditional MOSFETs (especially SiC MOSFETs) under high current change rate conditions in high-frequency, high-power-density applications. This rapid temperature rise typically manifests as localized, sharp temperature spikes, which are far more destructive than the increase in average junction temperature. Traditional heat dissipation structures are inefficient and cannot dissipate the large amount of heat released instantaneously, leading to localized high temperatures. Existing solutions, such as increasing the gate resistance, sacrifice the MOSFET's rapid high-frequency response capability. To address this, this application establishes a simulation model of an embedded power module 100 and, based on this model, accurately calculates the optimal advance time for the TEC heatsink 3 to start before the MOS chip 2. This allows for the determination of the capacitance values ​​of the first capacitor 202 and the second capacitor 203, ensuring that the TEC heatsink 3 starts up in advance and provides thermal suppression at the instant the MOS chip 2 is turned on. Therefore, this method provides a systematic and quantifiable approach to optimize key parameters in the circuit structure, effectively suppressing instantaneous temperature spikes, improving the reliability and lifespan of the power module, without sacrificing its high-frequency response capability.

[0073] To better understand the design method proposed in this application, the key steps involved will be described in detail below.

[0074] First, in step A1, a simulation model of the embedded power module 100 is established based on its structure. This simulation model aims to accurately reflect the electrical and thermal characteristics of the power module. Specifically, the model can be constructed using specialized simulation software (e.g., SPICE, ANSYS, or COMSOL) based on the physical dimensions, material properties, component layout, and electrical connections of the embedded power module 100. For example, parameters of each component can be manually input, such as the equivalent circuit model of the MOS chip 2, the thermoelectric characteristics of the TEC heatsink 3, the thermal conductivity of the heat dissipation substrate 1, and the parasitic parameters of the pins, to form a comprehensive simulation environment. This simulation model can be a lumped parameter model or a distributed parameter model, and its complexity depends on the required simulation accuracy and computational resources.

[0075] Secondly, in step A2, based on the simulation model, the optimal advance time for the TEC heatsink 3 to start before the MOS chip 2 at the preset operating frequency is determined through simulation calculations. This step is the core of this design method. In the simulation model, the startup timing of the TEC heatsink 3 and the MOS chip 2 under different advance times can be simulated, and the temperature response of the MOS chip 2 at the instant of turn-on can be observed. For example, by gradually adjusting the startup advance of the TEC heatsink 3 in the simulation and monitoring the peak value of the junction temperature of the MOS chip 2, an advance time that can effectively suppress temperature spikes without affecting overall performance can be found. This optimal advance time refers to the minimum advance amount that ensures the TEC heatsink 3 fully exerts its thermal suppression function while avoiding unnecessary energy consumption or negative impacts on circuit performance. The preset operating frequency refers to the specific or designated operating frequency at which the TEC heatsink 3 and the MOS chip 2 are designed to operate in the circuit or system. This frequency is determined and set in advance during the system design phase based on factors such as application requirements, device characteristics, and performance goals; for example, 50kHz, but not limited to this.

[0076] Furthermore, in step A3, the capacitance values ​​of the first capacitor 202 and the second capacitor 203 are determined based on the optimal advance time, so that the difference between the charging time of the first capacitor 202 and the charging time of the second capacitor 203 equals the optimal advance time. Once the optimal advance time is determined, the combination of capacitor values ​​required to meet this advance time can be calculated based on the electrical characteristics of the circuit and the charging and discharging principle of the capacitor. For example, the capacitance values ​​of the first capacitor 202 and the second capacitor 203 can be determined through iterative calculation or analytical solution using the charging time constant formula of the RC circuit and the resistance parameters of the drive circuit 200. In actual operation, a target charging time difference can be set first based on the optimal advance time, and then a series of standard capacitor values ​​can be selected for simulation verification. Finally, the capacitor combination closest to the target value can be selected.

[0077] The core innovation of this design method lies in providing a systematic and quantifiable approach to optimize key parameters in the circuit structure (the capacitance values ​​of the first capacitor 202 and the second capacitor 203) to enable the TEC heatsink 3 to actively start before the MOS chip 2 is turned on, thereby achieving an instantaneous thermal suppression effect. By establishing a precise simulation model and performing simulation calculations, this method can determine the optimal advance time for the TEC heatsink 3 to start and accurately design the capacitor values ​​accordingly. This proactive and precise control strategy allows the power module to effectively suppress instantaneous temperature spikes without sacrificing the high-frequency response capability of the MOS chip 2, fundamentally solving the problem of localized high temperatures. Therefore, this design method not only improves the reliability and lifespan of the power module but also fully leverages the performance potential of the MOS chip 2 in high-frequency, high-power-density applications, demonstrating significant advantages and innovation.

[0078] The above description is merely an embodiment of this application and is not intended to limit the scope of protection of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. An embedded power module, characterized in that, It includes a heat dissipation substrate (1), at least one MOS chip (2), a TEC heat sink (3), chip pins (4), heat sink pins (5), and a plastic package (6). The MOS chip (2) and the TEC heat sink (3) are both disposed on the upper surface of the heat dissipation substrate (1). The TEC heat sink (3) has a hollow area, and the MOS chip (2) is disposed in the hollow area. The MOS chip (2) is electrically connected to the chip pin (4), and the TEC heat sink (3) is electrically connected to the heat sink pin (5); The encapsulation body (6) encapsulates the heat dissipation substrate (1), the MOS chip (2), the TEC heat sink (3), the chip pins (4) and the heat sink pins (5), with the lower surface of the heat dissipation substrate (1) and the upper surface of the TEC heat sink (3) exposed, and each chip pin (4) and each heat sink pin (5) at least partially exposed.

2. The embedded power module according to claim 1, characterized in that, The MOS chip (2) is a SiC MOSFET chip.

3. The embedded power module according to claim 1, characterized in that, The chip pin (4) and the heat sink pin (5) extend laterally out of the encapsulation (6).

4. The embedded power module according to claim 1, characterized in that, Both the chip pin (4) and the heat sink pin (5) extend downward and are exposed from the lower surface of the encapsulation (6).

5. The embedded power module according to any one of claims 1-4, characterized in that, The MOS chip (2) is provided with one.

6. The embedded power module according to any one of claims 1-4, characterized in that, There are two MOS chips (2), and the two MOS chips (2) are connected to form a half-bridge circuit.

7. A circuit structure, characterized in that, The embedded power module (100) and driving circuit (200) according to any one of claims 1-4 are included. The driving circuit (200) includes a driving MOS transistor (201), at least one first capacitor (202), and a second capacitor (203). The number of first capacitors (202) is the same as the number of MOS chips (2) of the embedded power module (100), and each first capacitor (202) is connected between the gate and source of each MOS chip (2) in a one-to-one correspondence. The second capacitor (203) is connected between the gate and source of the driving MOS transistor (201). The capacitance of the second capacitor (203) is less than the capacitance of the first capacitor (202). The TEC heat sink (3) of the embedded power module (100) is connected to the driving MOS transistor (201). The driving circuit (200) is used to control the on / off state of the MOS chip (2) and the driving MOS transistor (201) by using the externally input PWM signal, and by using the charging time difference between the first capacitor (202) and the second capacitor (203), the driving MOS transistor (201) is turned on before each of the MOS chips (2), thereby driving the TEC heat sink (3) to start before each of the MOS chips (2) through the driving MOS transistor (201), so as to form a heat suppression effect at the moment when the MOS chip (2) is turned on.

8. The circuit structure according to claim 7, characterized in that, The embedded power module (100) is provided with a MOS chip (2), and the first capacitor (202) is correspondingly provided with one; The driving circuit (200) also includes a signal input terminal (204), two diodes (205) and a DC power supply (206). The signal input terminal (204) is used to input an external PWM signal. The anode of the first diode (205), the first terminal of the first capacitor (202) and the gate of the MOS chip (2) are all connected to the signal input terminal (204). The second terminal of the first capacitor (202) is connected to the source of the MOS chip (2) and grounded. The TEC heat sink (3) and the second diode (205) are connected in parallel between the drain of the driving MOS transistor (201) and the DC power supply (206), and the anode of the second diode (205) is connected to the drain of the driving MOS transistor (201), and the cathode is connected to the DC power supply (206).

9. The circuit structure according to claim 7, characterized in that, The embedded power module (100) is provided with two MOS chips (2), and the two MOS chips (2) are connected to form a half-bridge circuit, and two first capacitors (202) are provided accordingly; The driving circuit (200) also includes two signal input terminals (204), three diodes (205) and a DC power supply (206). The two signal input terminals (204) are respectively used to input two external PWM signals; The anode of the first diode (205), the first terminal of the first capacitor (202) and the gate of the first MOS chip (2) are all connected to the first signal input terminal (204), and the second terminal of the first capacitor (202) is connected to the source of the first MOS chip (2) and the drain of the second MOS chip (2); The anode of the second diode (205), the first terminal of the second first capacitor (202) and the gate of the second MOS chip (2) are all connected to the second signal input terminal (204), and the second terminal of the second first capacitor (202) and the source of the second MOS chip (2) are connected and grounded; The cathodes of the first and second diodes (205) and the first terminal of the second capacitor (203) are both connected to the gate of the driving MOS transistor (201), and the second terminal of the second capacitor (203) is connected to the source of the driving MOS transistor (201) and grounded; The TEC heat sink (3) and the third diode (205) are connected in parallel between the drain of the driving MOS transistor (201) and the DC power supply (206), and the anode of the third diode (205) is connected to the drain of the driving MOS transistor (201), and the cathode is connected to the DC power supply (206).

10. A design method, characterized in that, The method is used to design a first capacitor (202) and a second capacitor (203) in the circuit structure according to any one of claims 7-9; the design method includes the steps of: A1. Based on the structure of the embedded power module (100), establish a simulation model of the embedded power module (100); A2. Based on the simulation model, the optimal advance time for the TEC heat sink (3) to start before the MOS chip (2) at the preset operating frequency is determined by simulation calculation; A3. Determine the capacitance values ​​of the first capacitor (202) and the second capacitor (203) according to the optimal advance time, so that the difference between the charging time of the first capacitor (202) and the charging time of the second capacitor (203) is equal to the optimal advance time.

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