Single-wire transmission method, device and equipment and computer readable storage medium

Abstract

The invention discloses a single-line transmission method, device and equipment and a computer readable storage medium, which are applied to the technical field of computers, and comprise the following steps: packaging internal bus parallel data into a parallel data message according to a register read-write message protocol, and converting the parallel data message into a serial bit stream; mapping each logic bit of the serial bit stream into a level signal of a corresponding duty ratio according to a duty ratio coding rule; the duty ratio coding rule is that a logic bit 0 represents that a single high level exists in a clock period, and the duty ratio of the single high level does not reach half, and a logic bit 1 represents that a plurality of discontinuous high levels exist in the clock period, and the duty ratios of the plurality of discontinuous high levels reach half; and controlling the level conversion of the single signal line through a switching circuit according to the level signal, and transmitting the coded bit stream to the slave device bit by bit. According to the invention, the problems of high PCB design difficulty, high cost, signal interference and data error risk caused by a large number of signal lines are solved.

Description

Technical Field

[0001] This invention relates to the field of computing technology, and in particular to a single-wire transmission method, apparatus, device, and computer-readable storage medium. Background Technology

[0002] Current hardware boards require a large number of signal lines. For example, the I2C interface requires two signal lines, SPI requires four or more, and JTAG also requires four signal lines. More signal lines increase the difficulty of PCB routing and also increase costs. Furthermore, multiple signal lines pose a risk of interference between each other. Moreover, if multiple data signals are present on a single signal line, synchronization of these signals is required, which also carries the risk of data errors.

[0003] Therefore, how to reduce the number of signal lines, thereby reducing PCB design difficulty, cost, and the risk of signal interference and data errors while ensuring interface communication performance and reliability is a technical problem that urgently needs to be solved. Summary of the Invention

[0004] In view of this, the purpose of the present invention is to provide a single-wire transmission method, apparatus, device and computer-readable storage medium, which solves the problems of complex signal lines, difficult PCB design, high cost and risk of signal interference and data error in the prior art.

[0005] To address the aforementioned technical problems, this invention provides a single-wire transmission method, comprising:

[0006] According to the register read / write message protocol, the internal bus parallel data is encapsulated into parallel data messages, and the parallel data messages are converted into serial bit streams;

[0007] According to the duty cycle encoding rule, each logic bit of the serial bit stream is mapped to a level signal with a corresponding duty cycle; the duty cycle encoding rule is that logic bit 0 indicates that there is a single high level within the clock cycle and the duty cycle of the single high level is not half, and logic bit 1 indicates that there are multiple discontinuous high levels within the clock cycle and the duty cycle of the multiple discontinuous high levels reaches half.

[0008] Based on the level signal, the level change of a single signal line is controlled by a switching circuit, and the encoded bit stream is transmitted bit by bit to the slave device, so that the slave device can decode the encoded bit stream according to the duty cycle encoding rule and convert it into the parallel data packet.

[0009] On the one hand, the fields of the parallel data packet, in logical order, include: a fixed header for identifying the start of the packet; a device address for distinguishing different slave devices on the same hardware link; read / write control bits for identifying read or write operations on the slave device register; a register address for locating the register within the target slave device; a valid data field for storing register data to be read or written; and a checksum generated based on the device address, the read / write control bits, the register address, and the valid data field.

[0010] On the one hand, the process of generating the verification code includes:

[0011] According to the logical order, the device address, the read / write control bit, the register address, and the valid data are concatenated sequentially to form a continuous binary sequence;

[0012] Configure the check register and set the check base bit mode, wherein the check base bit mode is 1011 in binary; the initial value of the check register is set to 000.

[0013] Using the check register and the check reference bit mode, the continuous binary sequence is subjected to bit-by-bit iterative operation. After the bit-by-bit iterative operation is completed, the final binary value stored in the check register is used as the check code, and the check code is embedded into the end field of the parallel data packet to complete the packet encapsulation.

[0014] The step of performing bit-by-bit iterative operations on the continuous binary sequence using the check register and the check reference bit pattern includes:

[0015] Starting from the most significant bit of the continuous binary sequence, each logical bit is extracted sequentially and XORed with the most significant bit of the check register.

[0016] If the XOR result is 1, then the entire check register is shifted left by 1 bit, and then XORed with the preset check reference bit pattern to update the binary value of the check register.

[0017] If the XOR result is 0, then the entire check register is shifted left by 1 bit, while keeping the other bits of the check register unchanged;

[0018] Repeat the bit-by-bit iterative operation until all logical bits in the continuous binary sequence have been traversed.

[0019] On one hand, after controlling the level transformation of a single signal line through a switching circuit according to the level signal, and transmitting the encoded bit stream bit by bit to the slave device, the method further includes:

[0020] When the confirmation signal sent by the slave device through the single signal line is received, the transmission is completed; the confirmation signal is a signal formed by the slave device pulling the single signal line low for a preset number of cycles within the response window after verifying and passing the check code.

[0021] If the definite signal sent by the slave device through the single signal line is not received, it is retransmitted.

[0022] On the one hand, converting the parallel data packets into a serial bit stream includes:

[0023] The parallel data message is converted into a serial bit stream by a serial-to-parallel conversion logic circuit. After receiving the parallel data message, the serial-to-parallel conversion logic circuit decomposes the parallel bits of each field in the order of message header, device address, read / write control bits, register address, valid data field, and checksum, and outputs them sequentially according to the timing sequence to form the continuous serial bit stream.

[0024] On the one hand, according to the duty cycle encoding rule, each logic bit of the serial bit stream is mapped to a level signal corresponding to the duty cycle, including:

[0025] When the logic bit in the serial bit stream is 0, it is mapped to a level signal with a high level duration of 1 / n and a low level duration of n-1 / n within a single clock cycle; n represents the total number of divisions within a single clock cycle, and n is a positive integer greater than 2;

[0026] When a logic bit in the serial bit stream is 1, it is mapped to a level signal in a single clock cycle in which the proportion of discontinuous high-level durations reaches 1 / 2 and the proportion of low-level durations is less than 1 / 2.

[0027] On the one hand, it also includes: in the initial state, the slave device interface is configured as an input mode, and the master device interface is configured as an output mode and outputs a low level; when the master device pulls the interface level high and outputs a message header, the transmission of the serial bit stream is started.

[0028] The present invention also provides a single-wire transmission device, applied to a main device, comprising:

[0029] The encapsulation and conversion module is used to encapsulate internal bus parallel data into parallel data packets according to the register read and write message protocol, and convert the parallel data packets into a serial bit stream.

[0030] The mapping module is used to map each logic bit of the serial bit stream to a level signal with a corresponding duty cycle according to the duty cycle encoding rule. The duty cycle encoding rule is that logic bit 0 indicates that there is a single high level within the clock cycle and the duty cycle of the single high level is not half, and logic bit 1 indicates that there are multiple discontinuous high levels within the clock cycle and the duty cycle of the multiple discontinuous high levels reaches half.

[0031] The level conversion module is used to control the level conversion of a single signal line through a switching circuit according to the level signal, and transmit the encoded bit stream bit by bit to the slave device, so that the slave device can decode the encoded bit stream according to the duty cycle encoding rule and convert it into the parallel data packet.

[0032] The present invention also provides a single-wire transmission device, comprising:

[0033] Memory, used to store computer programs;

[0034] A processor is used to implement the single-wire transmission method described above when executing the computer program.

[0035] The present invention also provides a computer-readable storage medium storing computer-executable instructions, which, when loaded and executed by a processor, implement the single-wire transmission method described above.

[0036] The present invention also provides a computer program product, including a computer program / instructions that, when executed by a processor, implement the steps of the single-wire transmission method described above.

[0037] As can be seen from the above technical solution, the present invention encapsulates internal bus parallel data into parallel data packets according to the register read / write message protocol, and converts the parallel data packets into a serial bit stream; according to the duty cycle encoding rule, each logic bit of the serial bit stream is mapped to a level signal corresponding to the duty cycle; the duty cycle encoding rule is that logic bit 0 indicates that there is a single high level within the clock cycle, and the duty cycle of the single high level does not reach half, and logic bit 1 indicates that there are multiple discontinuous high levels within the clock cycle, and the duty cycle of the multiple discontinuous high levels reaches half; according to the level signal, the level change of the single signal line is controlled by the switching circuit, and the encoded bit stream is transmitted bit by bit to the slave device, so that the slave device decodes the encoded bit stream according to the duty cycle encoding rule and converts it into a parallel data packet. The beneficial effects of this invention are as follows: This single-wire transmission method specifically addresses the pain point of numerous signal lines in low-speed interfaces. By replacing traditional multi-signal-line transmission with a single signal line, it significantly reduces PCB routing difficulty and hardware costs, while avoiding the risk of interference between multiple signal lines. The duty cycle encoding rule, which distinguishes logic bits 0 and 1 by a single segment of low duty cycle high level and multiple segments of high duty cycle discontinuous high level, not only ensures clear identification of bit signals but also improves decoding accuracy, effectively reducing the risk of data transmission errors and enhancing the reliability and practicality of low-speed interface communication. This invention distinguishes logic bits using dual features: the number of high-level segments (single / multiple segments) and the duty cycle. This not only avoids the shortcomings of traditional solutions that rely on a single time threshold and are susceptible to noise and signal jitter, but also resists periodic distortion caused by clock drift and signal attenuation through discrete segment features, significantly reducing the risk of misjudgment and improving stability. At the same time, it does not rely on a single negative transition to trigger an interrupt, which can naturally filter out invalid decoding operations caused by false transitions. Furthermore, the duty cycle ratio is less affected by absolute time distortion, making it more suitable for complex PCB environments or long-distance transmission scenarios. Overall, it improves the anti-interference capability, decoding accuracy, and environmental adaptability of low-speed interface data transmission.

[0038] In addition, the present invention also provides a single-wire transmission device, equipment, and computer-readable storage medium, which also have the above-mentioned beneficial effects. Attached Figure Description

[0039] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0040] Figure 1 A flowchart of a single-wire transmission method provided in an embodiment of the present invention;

[0041] Figure 2An example diagram of a duty cycle encoding rule provided in an embodiment of the present invention;

[0042] Figure 3 An example diagram of an interface provided in an embodiment of the present invention;

[0043] Figure 4 This is a schematic diagram of the structure of a single-line transmission device provided in an embodiment of the present invention;

[0044] Figure 5 This is a schematic diagram of a single-line transmission device provided in an embodiment of the present invention. Detailed Implementation

[0045] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0046] First, let's analyze some of the terms used in this application:

[0047] BMC: The BMC chip, short for Baseboard Management Controller, is a dedicated embedded chip used to monitor and manage server hardware resources. It is typically integrated onto the server motherboard, but can also be installed as a standalone hardware device via PCIe or other connectors. The BMC chip has its own independent processor, memory, and operating system, allowing it to operate independently of the server's CPU, memory, operating system, and other hardware and software components. Through communication with other hardware components, the BMC chip enables remote monitoring, control, and management of the server, including power on / off, restart, hardware resource allocation and configuration, power control, BIOS settings, and fault alarms. Furthermore, the BMC chip supports standard protocols such as IPMI (Intelligent Platform Management Interface), allowing administrators to remotely access and manage the server over a network, significantly improving server manageability and maintainability. The BMC chip also features logging and security management functions, recording server operating status and events in real time, and providing security measures such as remote authentication and access control to ensure the secure and stable operation of the server.

[0048] I2C: I2C (Inter-Integrated Circuit) is a two-wire serial bus protocol designed to connect low-speed peripherals to microcontrollers. Its core uses two signal lines, SDA (data line) and SCL (clock line), and bus level control is achieved through open-drain outputs and pull-up resistors. It supports multi-master, multi-slave architectures, allowing up to 112 nodes (7-bit addressing) or 1008 nodes (10-bit addressing) to be connected on the same bus. The protocol defines standard mode (100Kbps), fast mode (400Kbps), and high-speed mode (3.4Mbps), and uses an arbitration mechanism to avoid multi-master conflicts. Hardware-wise, it requires only two wires for connection, eliminating the need for dedicated interface chips, and supports hot-swapping and dynamic device addition / removal. It is widely used in low-speed communication scenarios such as sensors, memory (e.g., EEPROM), and display control.

[0049] SPI Interface: SPI (Serial Peripheral Interface) is a high-speed, full-duplex, synchronous communication bus primarily used for communication between microcontrollers and various peripheral devices. An SPI interface typically includes four pins: SCLK (clock line), MOSI (Master Data Output, Slave Data Input), MISO (Master Data Input, Slave Data Output), and CS (Chip Select). The master device provides the clock signal via SCLK, while data is transmitted between the master and slave devices via the MOSI and MISO lines. The CS line is used to activate a specific slave device. SPI communication is fast, flexibly configurable, and suitable for various application scenarios, such as connecting memory and sensor devices, making it one of the important communication methods in embedded systems.

[0050] JTAG (Joint Test Action Group) is an international standard test protocol (IEEE 1149.1 compliant) primarily used for internal chip testing. Most advanced devices support the JTAG protocol, such as DSPs and FPGAs. A standard JTAG interface has four lines: TMS, TCK, TDI, and TDO, representing mode selection, clock, data input, and data output, respectively.

[0051] Current hardware boards (such as server motherboards with integrated BMC) require numerous signal lines for low-speed interfaces. For example, I2C requires two signal lines, SPI requires four or more, and JTAG requires four. More signal lines increase the difficulty of PCB routing and pose a risk of increased costs. Furthermore, multiple signal lines also present the risk of interference between each other. Moreover, if multiple data signals are present on a single signal line, synchronization is required, which also carries the risk of data errors. To address this, this invention provides a single-wire transmission method, utilizing a single wire (signal line) for data transmission. For chip design, this reduces the number of pins used for chip transmission, thus shrinking the chip size. For hardware boards, it reduces design complexity, shrinks board size, and saves hardware costs. This innovative design not only improves the overall system integration but also enhances system stability and reliability, providing strong support for the miniaturization and efficiency of electronic devices, and has broad application prospects and significant economic benefits.

[0052] Please refer to the details. Figure 1 , Figure 1 A flowchart illustrating a single-wire transmission method provided in an embodiment of the present invention. The method may include:

[0053] S101: According to the register read / write message protocol, encapsulate the internal bus parallel data into parallel data messages and convert the parallel data messages into a serial bit stream.

[0054] The execution entity in this embodiment is the main device (i.e., the host). This embodiment does not limit the type of host device, as long as it can perform the single-wire transmission method. The practical application scenario for this method is for low-speed interfaces such as sensors and peripheral chips, which actively notify the host device when specific events (such as faults, threshold triggers, or state changes) occur. The host device (slave device) can be a controller such as a CPU or MCU, while the slave device can be a data acquisition chip such as a sensor or ADC.

[0055] This step follows a pre-agreed register read / write message protocol, organizing and packaging the multiple parallel data transmitted simultaneously on the master device's internal bus into a standardized parallel data message according to the protocol's format requirements (ensuring a unified data format that both master and slave devices can recognize). Subsequently, this standardized parallel data message is converted from a parallel format of simultaneous multi-channel data transmission into a serial bit stream (a sequence of 0 / 1 logic values) where single-channel data is transmitted sequentially, preparing for subsequent single-signal-line transmission.

[0056] Furthermore, it may also include an initialization process that enables one-way communication: in the initial state, the slave device interface is configured as an input mode, and the master device interface is configured as an output mode and outputs a low level; when the master device pulls the interface level high and outputs a message header, the transmission of the serial bit stream is started.

[0057] In this embodiment, according to a certain protocol, the master and slave devices establish a connection during link initialization and negotiate their transmission rates to ensure correct data transmission. This interface allows only the master to initiate data transmission, while the slave can only passively receive data. The slave device interface is set to input mode (receive signals only), and the master device interface is set to output mode (transmit signals only), with the master device initially outputting a low level (link standby state). Only when the master device actively switches the interface level to a high level and sends a header to identify the start of transmission does the subsequent single-wire transmission process of the serial bit stream officially begin.

[0058] Of course, this embodiment can also achieve bidirectional communication: the bus is normally controlled by the master device and remains low when idle. When a slave device has an emergency to report, it actively pulls the bus high and maintains a predefined special waveform (e.g., two consecutive 1-bit bits plus a special address code) during the idle window when the master device is not communicating. The master device periodically checks whether the bus has this "interrupt signal," and once identified, immediately initiates a dedicated response process. This eliminates the need for additional signal lines, does not disrupt the core architecture of master-driven transmission, and overcomes the limitation of slave devices only being able to passively receive data. It achieves timely reporting and conflict-free handling of emergency events, balancing the simplicity of single-wire transmission with the real-time nature of system response.

[0059] Furthermore, the fields of the aforementioned parallel data packets, arranged in logical order, may specifically include: a fixed header for identifying the start of the packet; a device address for distinguishing different slave devices on the same hardware link; read / write control bits for identifying read or write operations on the slave device's registers; a register address for locating the registers within the target slave device; a valid data field for storing the register data to be read or written; and a checksum generated based on the device address, read / write control bits, register address, and valid data field.

[0060] This embodiment converts data on the internal data bus into data packets of a specific format for external transmission. The packet format can be found in Table 1, which is an example table of register read / write packet protocols. The packet header indicates the start of the packet and is fixed at 16 bits (0xA5A5), but can be configured according to actual needs. When 0xA5A5 is detected, the entire packet is received. Because there can be multiple slave devices on the hardware link, each assigned an address, the second part of the packet can use 4 bits to distinguish different slave devices on the same hardware link. Since it involves reading or writing to slave device registers, 1 bit can be used. Each slave device has many registers, distinguished by their addresses, so the fourth part can be a 10-bit register address. The fifth part is the data to be read or written to the registers, totaling 64 bits. Each register is defined as 64 bits. Finally, there is a 3-bit checksum at the end of the packet, covering the device address, R / W bits, register address, and the 64-bit register read / write data. The receiver calculates the local CRC and compares it with the check bit; if they do not match, the frame is discarded.

[0061] Table 1. Example Table of Register Read / Write Message Protocol

[0062]

[0063] Furthermore, the above-mentioned checksum generation process may include: sequentially concatenating the device address, read / write control bits, register address, and valid data in logical order to form a continuous binary sequence; configuring a checksum register and setting the checksum bit mode, where the checksum bit mode binary value is 1011; setting the initial value of the checksum register to 000; performing bit-by-bit iterative operations on the continuous binary sequence using the checksum register and the checksum bit mode; after the bit-by-bit iterative operations are completed, using the final binary value remaining in the checksum register as the checksum, and embedding the checksum into the end field of the parallel data packet to complete the packet encapsulation. The above-mentioned bit-by-bit iterative operation on the continuous binary sequence using the check register and the check reference bit pattern can specifically include: starting from the most significant bit of the continuous binary sequence, extracting each logical bit sequentially and performing an XOR operation with the most significant bit of the check register; if the XOR result is 1, shifting the entire check register left by 1 bit, and then performing an XOR operation with the preset check reference bit pattern to update the binary value of the check register; if the XOR result is 0, shifting the entire check register left by 1 bit, keeping the other bits of the check register unchanged; repeating the bit-by-bit iterative operation until all logical bits in the continuous binary sequence have been traversed. In this embodiment, a continuous binary sequence is first formed by concatenating the device address, read / write control bits, register address, and valid data in the logical order. Then, using a check register with an initial value of 000 and a preset check reference bit pattern (1011), the sequence is subjected to an iterative operation of XOR judgment-left shift-conditional XOR reference bit by bit starting from the most significant bit. Finally, the operation result is embedded as a check code at the end of the parallel data packet to complete the encapsulation. This simple and efficient bit-by-bit iterative verification mechanism can quickly detect errors such as bit flips during data transmission without additional hardware support or signal lines, improving the accuracy and reliability of message transmission. At the same time, it adapts to the low-complexity design requirements of single-wire transmission and ensures the integrity of data interaction between master and slave devices.

[0064] Furthermore, the above-mentioned conversion of parallel data packets into a serial bit stream can specifically include: converting parallel data packets into a serial bit stream through a serial-to-parallel conversion logic circuit; after receiving the parallel data packet, the serial-to-parallel conversion logic circuit decomposes the parallel bits of each field in the order of packet header, device address, read / write control bits, register address, valid data field, and checksum, and outputs them sequentially according to the timing sequence to form a continuous serial bit stream.

[0065] In this embodiment, the core of the serial-to-parallel conversion logic circuit is to convert parallel data packets into a serial bit stream. Specifically, after receiving a packet, the parallel bits of each field are decomposed bit by bit and output sequentially according to a preset order: packet header, device address, read / write control bits, register address, valid data fields, and checksum, forming a continuous serial bit stream. By fixing the field order and timing control, this not only adapts to the serial communication requirements of single-wire transmission but also ensures that the bit stream is consistent with the packet protocol, guaranteeing that the slave device can accurately decode and restore the data in the corresponding order. Furthermore, the logic circuit is simple to implement without additional hardware overhead, aligning with the core goals of simplifying hardware design and reducing costs, while also improving the orderliness of data transmission and the reliability of decoding.

[0066] S102: According to the duty cycle encoding rule, each logic bit of the serial bit stream is mapped to a level signal with the corresponding duty cycle; the duty cycle encoding rule is that logic bit 0 indicates that there is a single high level in the clock cycle and the duty cycle of the single high level is not half, and logic bit 1 indicates that there are multiple discontinuous high levels in the clock cycle and the duty cycle of the multiple discontinuous high levels reaches half.

[0067] This step maps each logic bit in the serial bit stream to a corresponding level signal according to a preset duty cycle encoding rule: logic bit 0 corresponds to a single high level within a clock cycle (duty cycle not reaching half), and logic bit 1 corresponds to multiple discontinuous high levels within a clock cycle (duty cycle reaching half). This encoding method distinguishes bits by the dual characteristics of the number of level segments and duty cycle, which not only meets the signal transmission requirements of single-wire transmission, but also reduces the risk of multi-signal interference and decoding misjudgment. Moreover, it can achieve clear identification of bit signals without complex hardware, taking into account both transmission reliability and hardware simplification goals, which fits the design core of low-speed interfaces with fewer signal lines and lower cost.

[0068] Furthermore, according to the duty cycle encoding rule, each logic bit of the serial bit stream is mapped to a level signal with a corresponding duty cycle. Specifically, this can include: when a logic bit in the serial bit stream is 0, it is mapped to a level signal in which the high level duration accounts for 1 / n and the low level duration accounts for n-1 / n within a single clock cycle; n represents the total number of divisions within a single clock cycle, and n is a positive integer greater than 2; when a logic bit in the serial bit stream is 1, it is mapped to a level signal in which multiple discontinuous high level durations account for 1 / 2 and low level durations account for less than 1 / 2 within a single clock cycle.

[0069] In this embodiment, each logic bit in the serial bit stream is mapped to a corresponding level signal according to a preset rule: logic bit 0 is mapped to a single high level (1 / n, where n is the total number of clock cycles) and a long low level (n-1 / n) within a single clock cycle; logic bit 1 is mapped to multiple discontinuous high levels (totaling 1 / 2) and short low levels (less than 1 / 2) within a single clock cycle. This embodiment does not limit n; for example, it can be 6 or 8. It is understood that n is an integer greater than 2. For example, refer to... Figure 2 , Figure 2 This is an example diagram of a duty cycle encoding rule provided for an embodiment of the present invention.

[0070] Furthermore, this embodiment also explains the reference for duty cycle and the correlation with clock cycle: the reference for calculating duty cycle is a single preset clock cycle. The duration of this clock cycle corresponds one-to-one with the transmission rate negotiated by the master and slave devices during the link initialization phase. Moreover, the mapping process of each logical bit occupies a complete clock cycle, ensuring that the level signals of adjacent logical bits do not overlap in time.

[0071] Furthermore, in this embodiment, the mapping process of logic bits is strictly synchronized with the clock signal: the start time of the clock cycle is the trigger point for the switching of the level signal, and the duration of the high level is precisely matched with the proportion of the clock cycle according to the mapping rules, ensuring that the receiver can identify the duty cycle through clock synchronization sampling, and thus restore the logic bits.

[0072] S103: Based on the level signal, the switching circuit controls the level change of the single signal line, and transmits the encoded bit stream bit by bit to the slave device, so that the slave device can decode the encoded bit stream according to the duty cycle encoding rule and convert it into a parallel data message.

[0073] For details, please refer to Figure 3 , Figure 3This is an example diagram of an interface provided by an embodiment of the present invention. The logic circuit controls the power and ground paths of the signal lines, i.e., pull-up or pull-down control of the interface lines, increasing the signal driving capability. The switching circuit can be a MOS switch circuit. When data needs to be sent, the logic circuit buffers the data, converts it from parallel data to serial data (0 or 1), and sends it out one bit at a time. When sending 0 or 1, the aforementioned 0 / 1 bit transmission method is followed. In this way, data transmission is achieved through a single signal line, completely solving the problems of difficult PCB routing, high cost, and interference risks associated with traditional multi-signal lines. The switching circuit control logic is simple, the hardware implementation cost is low, and the decoding process corresponds one-to-one with the encoding rules, ensuring the integrity and accuracy of data from transmission to reconstruction, perfectly meeting the core requirements of simplified design and improved reliability for low-speed interfaces. The encoded bitstream in this step refers to the physical layer signal stream after encoding and level switching according to the duty cycle encoding rules. Furthermore, this embodiment also describes the physical parameters of the level signal: the high level of the level signal is the power supply voltage (Vcc) adapted to the hardware link, and the low level is the ground potential (GND); during the mapping process, the switching between high and low levels is achieved through a MOS switching circuit, and the switching response time is less than 1 / 10 of the clock cycle, so as to avoid duty cycle deviation caused by level switching delay.

[0074] Furthermore, after transmitting the encoded bit stream bit by bit to the slave device by controlling the level change of a single signal line according to the level signal through a switching circuit, the above may further include: when a confirmation signal sent by the slave device through the single signal line is received, the transmission is completed; the confirmation signal is a signal formed by the slave device pulling the single signal line low for a preset number of cycles within the response window after verifying the checksum according to the check code and passing the verification; when no confirmation signal sent by the slave device through the single signal line is received, the transmission is retransmitted. This embodiment does not limit the preset number of cycles, for example, it can be 1 or 2. To further improve reliability, in this embodiment, after successful reception, the slave device can pull the bus low for 1 cycle within the predefined response window as an confirmation signal (ACK), and the master device retransmits if it does not receive the ACK.

[0075] Furthermore, the switching circuit includes a MOS transistor switching unit and a signal shaping module. The MOS transistor switching unit controls the high-low switching of a single signal line based on the duty cycle-encoded level signal. The signal shaping module performs edge sharpening and noise filtering on the switched level signal, and then transmits the shaped level signal bit by bit to the slave device. In this embodiment, the MOS transistor switching unit receives the duty cycle-encoded level signal and achieves high-low level control of a single signal line by switching between on / off states. The signal shaping module performs two key processes on the switched level signal: edge sharpening (correcting the blurry edges during level transitions to make the high / low level boundaries clear) and noise filtering (removing glitches, noise, and other interference components from the signal). The signal shaping module sharpens the edges to make level transitions clearer, preventing misjudgment of the duty cycle by slave devices due to blurred edges. Noise filtering eliminates interference noise during transmission, further reducing the risk of decoding errors and meeting the signal clarity requirements of single-wire transmission. Using mature MOSFETs as switching units, combined with a simple signal shaping module, the hardware structure is concise and cost-effective, without adding extra signal lines, continuing the core advantages of minimal wiring and low cost. The shaped signal has stronger anti-interference capabilities, maintaining stable transmission even in scenarios prone to signal distortion, such as complex PCB layouts and long-distance transmission, thus broadening the applicability of the solution. Signal shaping only optimizes the signal shape, without changing the number of level segments and the core characteristics of the duty cycle encoding rules, ensuring that slave devices can accurately decode according to the original rules, balancing optimization and compatibility.

[0076] The single-wire transmission method provided in this embodiment of the invention is as follows: S101: According to the register read / write message protocol, the internal bus parallel data is encapsulated into parallel data packets, and the parallel data packets are converted into a serial bit stream; S102: According to the duty cycle encoding rule, each logic bit of the serial bit stream is mapped to a level signal corresponding to the duty cycle; the duty cycle encoding rule is that logic bit 0 indicates that there is a single high level within the clock cycle, and the duty cycle of the single high level does not reach half, and logic bit 1 indicates that there are multiple discontinuous high levels within the clock cycle, and the duty cycle of the multiple discontinuous high levels reaches half; S103: According to the level signal, the level change of the single signal line is controlled by the switching circuit, and the encoded bit stream is transmitted bit by bit to the slave device, so that the slave device decodes the encoded bit stream according to the duty cycle encoding rule and converts it into a parallel data packet. This single-wire transmission method specifically addresses the pain point of numerous signal lines in low-speed interfaces. By replacing traditional multi-signal-line transmission with a single signal line, it significantly reduces PCB routing complexity and hardware costs, while also avoiding the risk of interference between multiple signal lines. The duty cycle encoding rule, which distinguishes logic bits 0 and 1 by a single segment of low duty cycle high level and multiple segments of high duty cycle discontinuous high level, ensures clear identification of bit signals, improves decoding accuracy, effectively reduces the risk of data transmission errors, and enhances the reliability and practicality of low-speed interface communication. Furthermore, this invention distinguishes logic bits using dual features of high-level segment count (single / multiple segments) and duty cycle. This not only avoids the shortcomings of traditional solutions that rely on a single time threshold and are susceptible to noise and signal jitter, but also resists periodic distortion caused by clock drift and signal attenuation through discrete segment count features, significantly reducing the risk of misjudgment and improving stability. At the same time, it does not rely on a single negative transition to trigger an interrupt, which can naturally filter out invalid decoding operations caused by false transitions. Moreover, the duty cycle ratio is less affected by absolute time distortion, making it more suitable for complex PCB environments or long-distance transmission scenarios. Overall, it improves the anti-interference capability, decoding accuracy, and environmental adaptability of low-speed interface data transmission.

[0077] The single-line transmission device provided in the embodiments of the present invention will be described below. The single-line transmission device described below can be referred to in correspondence with the single-line transmission method described above.

[0078] Please refer to the details. Figure 4 , Figure 4 A schematic diagram of a single-wire transmission device provided in an embodiment of the present invention may include:

[0079] The encapsulation and conversion module 100 is used to encapsulate internal bus parallel data into parallel data packets according to the register read and write message protocol, and convert the parallel data packets into a serial bit stream.

[0080] The mapping module 200 is used to map each logic bit of the serial bit stream to a level signal with a corresponding duty cycle according to the duty cycle encoding rule; the duty cycle encoding rule is that logic bit 0 indicates that there is a single high level within the clock cycle and the duty cycle of the single high level is not half, and logic bit 1 indicates that there are multiple discontinuous high levels within the clock cycle and the duty cycle of the multiple discontinuous high levels reaches half.

[0081] The level conversion module 300 is used to control the level conversion of a single signal line through a switching circuit according to the level signal, and transmit the encoded bit stream bit by bit to the slave device, so that the slave device can decode the encoded bit stream according to the duty cycle encoding rule and convert it into the parallel data packet.

[0082] Based on the above embodiments, the fields of the parallel data packet, in logical order, may specifically include: a fixed header for identifying the start of the packet; a device address for distinguishing different slave devices on the same hardware link; read / write control bits for identifying read or write operations on the slave device register; a register address for locating the register within the target slave device; a valid data field for storing register data to be read or written; and a checksum generated based on the device address, the read / write control bits, the register address, and the valid data field.

[0083] Based on the above embodiments, the process of generating the verification code may specifically include:

[0084] The splicing unit is used to sequentially splice the device address, the read / write control bit, the register address, and the valid data according to the logical order to form a continuous binary sequence;

[0085] A configuration unit is used to configure the verification register and set the verification base bit mode, wherein the binary value of the verification base bit mode is 1011; the initial value of the verification register is set to 000.

[0086] The iterative operation unit is used to perform bit-by-bit iterative operation on the continuous binary sequence using the check register and the check reference bit mode. After the bit-by-bit iterative operation is completed, the final binary value stored in the check register is used as the check code, and the check code is embedded into the end field of the parallel data message to complete the message encapsulation.

[0087] The iterative operation unit may include:

[0088] The arithmetic subunit is used to extract each logical bit from the most significant bit of the continuous binary sequence and perform an XOR operation with the most significant bit of the check register.

[0089] The first result subunit is used to shift the entire verification register one bit to the left if the XOR result is 1, and then XOR it with the preset verification base bit pattern to update the binary value of the verification register.

[0090] The second result subunit is used to shift the entire check register to the left by 1 bit if the XOR result is 0, while keeping the other bits of the check register unchanged.

[0091] The sub-unit is traversed by repeating bit-by-bit iterative operations until all logical bits in the continuous binary sequence have been traversed.

[0092] Based on the above embodiments, the single-line transmission device may further include:

[0093] The transmission completion module is used to transmit the encoded bit stream bit by bit to the slave device by controlling the level change of a single signal line according to the level signal through a switching circuit. When the slave device sends a confirmation signal through the single signal line, the transmission is completed. The confirmation signal is a signal formed by the slave device pulling the single signal line low for a preset number of cycles within the response window after verifying the check code according to the check code and passing the verification.

[0094] The transmission failure retransmission module is used to retransmit when the definite signal sent by the slave device through the single signal line is not received.

[0095] Based on the above embodiments, the encapsulation conversion module 100 may include:

[0096] The conversion unit is used to convert the parallel data message into a serial bit stream through a serial-to-parallel conversion logic circuit. After receiving the parallel data message, the serial-to-parallel conversion logic circuit decomposes the parallel bits of each field in the order of message header, device address, read / write control bits, register address, valid data field, and checksum, and outputs them sequentially according to the timing sequence to form the continuous serial bit stream.

[0097] Based on any of the above embodiments, the mapping module 200 may include:

[0098] The first mapping unit is used to map the serial bit stream to a level signal with a high level duration of 1 / n and a low level duration of n-1 / n within a single clock cycle when the logic bit in the serial bit stream is 0; n represents the total number of divisions within a single clock cycle, and n is a positive integer greater than 2.

[0099] The second mapping unit is used to map the serial bit stream to a level signal in a single clock cycle in which the proportion of discontinuous high-level durations reaches 1 / 2 and the proportion of low-level durations is less than 1 / 2 when the logic bit in the serial bit stream is 1.

[0100] Based on the above embodiments, the single-line transmission device may further include:

[0101] An initialization module is used to configure the slave device interface as input mode and the master device interface as output mode with a low level output in the initial state; when the master device pulls the interface level high and outputs a message header, the transmission of the serial bit stream is started.

[0102] It should be noted that the order of the modules and units in the above-mentioned single-line transmission device can be changed without affecting the logic.

[0103] The single-wire transmission device provided in this embodiment of the invention uses an encapsulation and conversion module 100 to encapsulate internal bus parallel data into parallel data packets according to a register read / write message protocol, and converts the parallel data packets into a serial bit stream. A mapping module 200 maps each logic bit of the serial bit stream to a level signal corresponding to a duty cycle according to a duty cycle encoding rule. The duty cycle encoding rule is that logic bit 0 indicates a single high level within a clock cycle, and the duty cycle of that single high level is not half; logic bit 1 indicates multiple discontinuous high levels within a clock cycle, and the duty cycle of these multiple discontinuous high levels reaches half. A level conversion module 300 controls the level conversion of a single signal line according to the level signal via a switching circuit, transmitting the encoded bit stream bit by bit to the slave device, so that the slave device decodes the encoded bit stream according to the duty cycle encoding rule and converts it into the parallel data packets. This device specifically addresses the pain point of numerous signal lines in low-speed interfaces. By replacing traditional multi-signal-line transmission with a single signal line, it significantly reduces PCB routing complexity and hardware costs, while also avoiding the risk of interference between multiple signal lines. The duty cycle encoding rule, which distinguishes logic bits 0 and 1 by a single segment of low duty cycle high level and multiple segments of high duty cycle discontinuous high level, ensures clear identification of bit signals, improves decoding accuracy, effectively reduces the risk of data transmission errors, and enhances the reliability and practicality of low-speed interface communication. Furthermore, this invention distinguishes logic bits using dual features of high-level segment count (single / multiple segments) and duty cycle. This not only avoids the shortcomings of traditional solutions that rely on a single time threshold and are susceptible to noise and signal jitter, but also resists periodic distortion caused by clock drift and signal attenuation through discrete segment count features, significantly reducing the risk of misjudgment and improving stability. At the same time, it does not rely on a single negative transition to trigger an interrupt, which can naturally filter out invalid decoding operations caused by false transitions. Moreover, the duty cycle ratio is less affected by absolute time distortion, making it more suitable for complex PCB environments or long-distance transmission scenarios. Overall, it improves the anti-interference capability, decoding accuracy, and environmental adaptability of low-speed interface data transmission.

[0104] Figure 5This is a schematic diagram of the structure of a single-line transmission device provided in an embodiment of the present invention, as shown below. Figure 5 As shown, the single-line transmission device includes:

[0105] Memory 60 is used to store computer programs;

[0106] The processor 61 is used to implement the steps of the single-wire transmission method as described in the above embodiments when executing a computer program.

[0107] The single-line transmission device provided in this embodiment may include, but is not limited to, smartphones, tablets, laptops, or desktop computers.

[0108] The processor 61 may include one or more processing cores, such as a quad-core processor or an octa-core processor. The processor 61 may be implemented using at least one hardware form selected from Digital Signal Processing (DSP), Field-Programmable Gate Array (FPGA), and Programmable Logic Array (PLA). The processor 61 may also include a main processor and a coprocessor. The main processor, also known as the Central Processing Unit (CPU), is used to process data in the wake-up state; the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, the processor 61 may integrate a Graphics Processing Unit (GPU), which is responsible for rendering and drawing the content to be displayed on the screen. In some embodiments, the processor 61 may also include an Artificial Intelligence (AI) processor, which handles computational operations related to machine learning.

[0109] The memory 60 may include one or more computer-readable storage media, which may be non-transitory. The memory 60 may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices or flash memory devices. In this embodiment, the memory 60 is used to store at least the following computer program 601, which, after being loaded and executed by the processor 61, is capable of implementing the relevant steps of the single-wire transmission method disclosed in any of the foregoing embodiments. In addition, the resources stored in the memory 60 may also include an operating system 602 and data 603, etc., and the storage method may be temporary storage or permanent storage. The operating system 602 may include Windows, Unix, Linux, etc. The data 603 may include, but is not limited to, data related to the single-wire transmission method.

[0110] In some embodiments, the single-line transmission device may further include a display screen 62, an input / output interface 63, a communication interface 64, a power supply 65, and a communication bus 66.

[0111] Those skilled in the art will understand that Figure 5 The structure shown does not constitute a limitation on single-wire transmission devices and may include more or fewer components than illustrated.

[0112] It is understood that if the single-line transmission method in the above embodiments is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the current technology, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and executes all or part of the steps of the methods in the various embodiments of the present invention. The aforementioned storage medium includes: USB flash drive, mobile hard drive, read-only memory (ROM), random access memory (RAM), electrically erasable programmable ROM, register, hard disk, removable disk, CD-ROM, magnetic disk, or optical disk, and other media capable of storing program code.

[0113] Based on this, embodiments of the present invention also provide a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps of the single-wire transmission method described above.

[0114] The following describes a computer program product provided by an embodiment of this application. The computer program product described below can be referred to in conjunction with other embodiments described herein.

[0115] A computer program product includes a computer program / instructions that, when executed by a processor, implement the steps of the aforementioned disclosed single-wire transmission method.

[0116] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section.

[0117] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0118] Finally, it should be noted that in this document, relationships such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus.

[0119] The present invention provides a detailed description of a single-line transmission method, apparatus, device, and computer-readable storage medium. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, those skilled in the art will recognize that, based on the ideas of the present invention, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A single-wire transmission method, characterized in that, Applied to the main equipment, including: According to the register read / write message protocol, the internal bus parallel data is encapsulated into parallel data messages, and the parallel data messages are converted into serial bit streams; According to the duty cycle encoding rule, each logic bit of the serial bit stream is mapped to a level signal with a corresponding duty cycle; the duty cycle encoding rule is that logic bit 0 indicates that there is a single high level within the clock cycle and the duty cycle of the single high level is not half, and logic bit 1 indicates that there are multiple discontinuous high levels within the clock cycle and the duty cycle of the multiple discontinuous high levels reaches half. Based on the level signal, the level change of a single signal line is controlled by a switching circuit, and the encoded bit stream is transmitted bit by bit to the slave device, so that the slave device can decode the encoded bit stream according to the duty cycle encoding rule and convert it into the parallel data packet.

2. The single-line transmission method according to claim 1, characterized in that, The fields of the parallel data packet, in logical order, include: a fixed header for identifying the start of the packet; a device address for distinguishing different slave devices on the same hardware link; read / write control bits for identifying read or write operations on the slave device registers; a register address for locating the registers within the target slave device; a valid data field for storing register data to be read or written; and a checksum generated based on the device address, the read / write control bits, the register address, and the valid data field.

3. The single-line transmission method according to claim 2, characterized in that, The process of generating the checksum includes: According to the logical order, the device address, the read / write control bit, the register address, and the valid data are concatenated sequentially to form a continuous binary sequence; Configure the check register and set the check base bit mode, wherein the check base bit mode is 1011 in binary; the initial value of the check register is set to 000. Using the check register and the check reference bit mode, the continuous binary sequence is subjected to bit-by-bit iterative operation. After the bit-by-bit iterative operation is completed, the final binary value stored in the check register is used as the check code, and the check code is embedded in the end field of the parallel data packet to complete the packet encapsulation. The step of performing bit-by-bit iterative operations on the continuous binary sequence using the check register and the check reference bit pattern includes: Starting from the most significant bit of the continuous binary sequence, each logical bit is extracted sequentially and XORed with the most significant bit of the check register. If the XOR result is 1, then the entire check register is shifted left by 1 bit, and then XORed with the preset check reference bit pattern to update the binary value of the check register. If the XOR result is 0, then the entire check register is shifted left by 1 bit, while keeping the other bits of the check register unchanged; Repeat the bit-by-bit iterative operation until all logical bits in the continuous binary sequence have been traversed.

4. The single-line transmission method according to claim 2, characterized in that, After transmitting the encoded bit stream bit by bit to the slave device by controlling the level change of a single signal line through a switching circuit according to the level signal, the process further includes: When the confirmation signal sent by the slave device through the single signal line is received, the transmission is completed; the confirmation signal is a signal formed by the slave device pulling the single signal line low for a preset number of cycles within the response window after verifying and passing the check code. If the definite signal sent by the slave device through the single signal line is not received, it is retransmitted.

5. The single-line transmission method according to claim 2, characterized in that, Converting the parallel data packets into a serial bit stream includes: The parallel data message is converted into a serial bit stream by a serial-to-parallel conversion logic circuit. After receiving the parallel data message, the serial-to-parallel conversion logic circuit decomposes the parallel bits of each field in the order of message header, device address, read / write control bits, register address, valid data field, and checksum, and outputs them sequentially according to the timing sequence to form the continuous serial bit stream.

6. The single-wire transmission method according to any one of claims 1 to 5, characterized in that, According to the duty cycle encoding rule, each logic bit of the serial bit stream is mapped to a level signal corresponding to the duty cycle, including: When the logic bit in the serial bit stream is 0, it is mapped to a level signal with a high level duration of 1 / n and a low level duration of n-1 / n within a single clock cycle; n represents the total number of divisions within a single clock cycle, and n is a positive integer greater than 2; When a logic bit in the serial bit stream is 1, it is mapped to a level signal in a single clock cycle in which the proportion of discontinuous high-level durations reaches 1 / 2 and the proportion of low-level durations is less than 1 / 2.

7. The single-line transmission method according to claim 1, characterized in that, Also includes: In the initial state, the slave device interface is configured in input mode, and the master device interface is configured in output mode and outputs a low level. When the master device pulls the interface level high and outputs a message header, it starts the transmission of the serial bit stream.

8. A single-wire transmission device, characterized in that, Applied to the main equipment, including: The encapsulation and conversion module is used to encapsulate internal bus parallel data into parallel data packets according to the register read and write message protocol, and convert the parallel data packets into a serial bit stream. The mapping module is used to map each logic bit of the serial bit stream to a level signal with a corresponding duty cycle according to the duty cycle encoding rule. The duty cycle encoding rule is that logic bit 0 indicates that there is a single high level within the clock cycle and the duty cycle of the single high level is not half, and logic bit 1 indicates that there are multiple discontinuous high levels within the clock cycle and the duty cycle of the multiple discontinuous high levels reaches half. The level conversion module is used to control the level conversion of a single signal line through a switching circuit according to the level signal, and transmit the encoded bit stream bit by bit to the slave device, so that the slave device can decode the encoded bit stream according to the duty cycle encoding rule and convert it into the parallel data packet.

9. A single-line transmission device, characterized in that, include: Memory, used to store computer programs; A processor for implementing the single-wire transmission method as described in any one of claims 1 to 7 when executing the computer program.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions, which, when loaded and executed by a processor, implement the single-wire transmission method as described in any one of claims 1 to 7.

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