Multifunctional PLC (Programmable Logic Controller) expansion device based on FPGA (Field Programmable Gate Array) and configuration method thereof

Abstract

The invention discloses a multifunctional PLC expansion device based on an FPGA and a configuration method thereof.The device comprises the FPGA, the FPGA comprises a communication module, a function configuration module, a pulse output module, a serial port module, a pulse counting module and an IO control module, the communication module is used for receiving a configuration instruction, and the function configuration module is used for receiving the configuration instruction; the function configuration module is respectively connected with the communication module, the pulse output module, the serial port module and the pulse counting module, and is used for selectively activating any one of the pulse output module, the serial port module or the pulse counting module according to the configuration instruction; and the IO control module is respectively connected with the pulse output module, the serial port module and the pulse counting module for function output.

Description

Technical Field

[0001] This invention relates to the field of industrial automation control technology, specifically to a multi-functional PLC expansion device based on FPGA and its configuration method. Background Technology

[0002] In industrial settings, PLC expansion modules typically use dedicated chips to implement single functions. For example, chips such as MAX485 are used for RS485 communication; dedicated encoder interface chips (such as LS7366R) are used to process differential encoder inputs; and dedicated pulse generators or motion control chips are used to implement differential pulse outputs.

[0003] In addition, some manufacturers have tried to integrate multiple functions through microcontrollers (MCUs), but due to limitations in processing speed and parallel capabilities, there are performance bottlenecks in high-speed pulse or real-time encoder acquisition.

[0004] Therefore, the existing technology has the following drawbacks: (1) High hardware redundancy: Each function requires an independent circuit board or module, resulting in a large variety of materials and high BOM costs; (2) Poor flexibility: Users cannot dynamically switch module functions according to actual needs and must select the hardware type in advance; (3) High R&D and production costs: Different PCBs need to be designed, tested and verified separately for different functions, which increases the development cycle; (4) Low resource utilization: Single functional modules are idle in non-corresponding application scenarios.

[0005] Based on the above background, this application aims to solve the above problems and provide a multi-functional PLC expansion device and configuration method that features hardware reuse, configurable functions, and optimized cost. Summary of the Invention

[0006] To address these issues, this invention proposes a multi-functional PLC expansion device based on FPGA and its configuration method.

[0007] According to one aspect of the present invention, a multi-functional PLC expansion device based on FPGA is provided, comprising an FPGA, wherein the FPGA includes a communication module, a function configuration module, a pulse output module, a serial port module, a pulse counting module, and an I / O control module. The communication module is used to receive configuration instructions. The function configuration module is connected to the communication module, the pulse output module, the serial port module, and the pulse counting module respectively, and is used to select and activate any one of the pulse output module, the serial port module, or the pulse counting module according to the configuration instructions. The I / O control module is connected to the pulse output module, the serial port module, and the pulse counting module respectively to perform function output.

[0008] Specifically, it also includes an external circuit module, which is connected to the IO control module. The external circuit module includes a first differential signal circuit and a second differential circuit. The first differential signal circuit includes a first high-speed differential transceiver chip, first to fifth resistors, a first TVS protection device, and first to third capacitors. The IOA1 interface of the I / O control module is connected to the receiver output of the first high-speed differential transceiver chip. The IOA2 interface of the I / O control module is connected to the receiver enable and driver enable terminals of the first high-speed differential transceiver chip. The IOA3 interface of the I / O control module is connected to the driver input of the first high-speed differential transceiver chip. The power supply terminal of the first high-speed differential transceiver chip is connected to a power supply, one end of the first capacitor, and one end of the first resistor. The non-inverting input of the chip is connected to the other end of the first resistor and one end of the third resistor. The inverting input of the first high-speed differential transceiver chip is connected to one end of the second resistor and one end of the fourth resistor. The other end of the third resistor is connected to one end of the second capacitor, one end of the fifth resistor, and one protection terminal of the first TVS protection device. The other end of the fourth resistor is connected to one end of the third capacitor, one end of the fifth resistor, and another protection terminal of the first TVS protection device. The other end of the first capacitor, the ground terminal of the first high-speed differential transceiver chip, the other end of the second resistor, the other end of the second capacitor, the other end of the third capacitor, and the ground terminal of the first TVS protection device are all grounded. The second differential signal circuit includes a second high-speed differential transceiver chip, sixth to tenth resistors, a second TVS protection device, and fourth to sixth capacitors. The IOB1 interface of the I / O control module is connected to the receiver output of the second high-speed differential transceiver chip. The IOB2 interface of the I / O control module is connected to the receiver enable and driver enable terminals of the second high-speed differential transceiver chip. The IOB3 interface of the I / O control module is connected to the driver input of the second high-speed differential transceiver chip. The power supply terminal of the second high-speed differential transceiver chip is connected to the power supply, one end of the fourth capacitor, and one end of the sixth resistor. The non-inverting input of the chip is connected to the other end of the sixth resistor and one end of the eighth resistor. The inverting input of the second high-speed differential transceiver chip is connected to one end of the seventh resistor and one end of the ninth resistor. The other end of the eighth resistor is connected to one end of the fifth capacitor, one end of the tenth resistor, and one protection terminal of the second TVS protection device. The other end of the ninth resistor is connected to one end of the sixth capacitor, the other end of the tenth resistor, and the other protection terminal of the second TVS protection device. The other end of the fourth capacitor, the ground terminal of the second high-speed differential transceiver chip, the other end of the seventh resistor, the other end of the fifth capacitor, the other end of the sixth capacitor, and the ground terminal of the second TVS protection device are all grounded. The first, second, sixth, and seventh resistors have the same resistance value; the third, fourth, eighth, and ninth resistors have the same resistance value; the fifth and tenth resistors have the same resistance value; the first and fourth capacitors have the same capacitance value; and the second, third, fifth, and sixth capacitors have the same capacitance value.

[0009] Specifically, when the communication module receives a serial port enable configuration command, the function configuration module activates the serial port module. The receiving serial port of the serial port module is set to receive the output after the AND operation of the IOA1 and IOB1 interfaces of the IO control module. The IOA3 interface of the IO control module receives the output of the transmitting interface of the serial port module. The third high-speed differential transceiver chip of the serial port module is connected to the IOA2 interface of the IO control module. The transmitting and receiving states are switched by controlling the logic of the IOB2 interface of the IO control module. The serial port module supports RS422 or RS485 protocols.

[0010] Specifically, the serial port enable configuration instruction includes serial port configuration parameters and protocol configuration parameters. The serial port configuration parameters include serial port number, data bits, baud rate, parity method, and stop bits. The protocol configuration parameters include communication protocol type, station number, timeout, transmission interval, bit mode, inter-character timeout, whether to enable start character, and whether to enable stop character.

[0011] Specifically, when the communication module receives a pulse counting enable configuration command, the function configuration module activates the pulse counting module to perform pulse counting, controls the logic of the IOA2 and IOB2 interfaces of the IO control module to be 0, one end of the pulse counting module receives the input of the IOA1 interface of the IO control module, and the other end of the pulse counting module receives the input of the IOB1 interface of the IO control module.

[0012] Specifically, the pulse counting enable configuration instruction includes pulse counting mode parameters, which include pulse + direction mode, encoder A / B phase mode, and single-phase counting mode.

[0013] Specifically, when the communication module receives a pulse output enable configuration command, the function configuration module activates the pulse output module to configure the pulse signal for output, controls the logic of the IOA2 and IOB2 interfaces of the IO control module to be 1, the IOA3 interface of the IO control module receives the output from one end of the pulse output module, and the IOB3 interface of the IO control module receives the output from the other end of the pulse output module.

[0014] Specifically, the pulse output enable configuration instruction includes pulse output mode parameters, which include pulse + direction mode, A / B phase mode and CW / CCW mode.

[0015] According to one aspect of the present invention, a configuration method for a multi-functional PLC expansion device based on an FPGA is proposed, comprising the following steps according to the device described above: S1, configuration instructions are sent from the host computer to the FPGA, which includes a pulse output module, a serial port module and a pulse counting module; S2, when the FPGA receives the configuration instruction, the FPGA selects to activate any one of the pulse output module, the serial port module, or the pulse counting module to perform functional output according to the configuration instruction.

[0016] The advantages of this invention are: Hardware reuse reduces costs: A single PCB can perform three functions, reducing the number of discrete components and lowering material procurement and inventory management costs. Improve R&D efficiency: Avoid developing hardware separately for each function and shorten product iteration cycles; Enhanced user flexibility: Users can freely switch module functions according to on-site needs without replacing hardware; Improve system integration: FPGA has strong parallel processing capabilities, which can simultaneously ensure high-speed pulse accuracy and communication real-time performance; High compatibility: Supports RS422 / RS485 dual protocols, adaptable to a variety of industrial equipment; Compared with traditional multi-module solutions, this invention has significant advantages in terms of cost, flexibility and integration, and is especially suitable for small and medium-sized automation equipment manufacturers. Attached Figure Description

[0017] The accompanying drawings are included to provide a further understanding of the embodiments and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments and, together with the description, serve to explain the principles of the invention. Other embodiments and many anticipated advantages of the embodiments will be readily recognized as they become better understood through reference to the following detailed description. Elements in the drawings are not necessarily to scale. The same reference numerals refer to corresponding similar parts.

[0018] Figure 1 A schematic diagram of the structure of a multi-functional PLC expansion device based on FPGA according to the present invention is shown. Figure 2 A schematic diagram of the peripheral circuit of a multi-functional PLC expansion device based on an FPGA according to the present invention is shown. Figure 3An equivalent schematic diagram of the circuit configuration of a serial port module of a multi-functional PLC expansion device based on an FPGA according to the present invention is shown. Figure 4 A schematic diagram of the configuration interface for configuring serial port function in a multi-functional PLC expansion device based on FPGA according to the present invention is shown. Figure 5 An equivalent schematic diagram of the circuit configuration of a pulse counting module of a multi-functional PLC expansion device based on an FPGA according to the present invention is shown. Figure 6 A schematic diagram of the configuration interface for configuring the pulse counting function of a multi-functional PLC expansion device based on FPGA according to the present invention is shown. Figure 7 A schematic diagram of the configuration interface for configuring input device attributes when configuring the pulse counting function of a multi-functional PLC expansion device based on FPGA according to the present invention is shown. Figure 8 A schematic diagram of the configuration interface for configuring the pulse counting mode when configuring the pulse counting function of a multi-functional PLC expansion device based on FPGA according to the present invention is shown. Figure 9 An equivalent schematic diagram of the circuit configuration of a pulse output module of an FPGA-based multifunctional PLC expansion device according to the present invention is shown. Figure 10 A schematic diagram of the configuration interface for configuring the pulse output function of a multi-functional PLC expansion device based on FPGA according to the present invention is shown. Figure 11 A schematic diagram of the configuration interface for configuring output device attributes when configuring the pulse output function of a multi-functional PLC expansion device based on FPGA according to the present invention is shown. Figure 12 A schematic diagram of the configuration interface for configuring the pulse output mode when configuring the pulse output function of a multi-functional PLC expansion device based on FPGA according to the present invention is shown. Figure 13 A flowchart illustrating a configuration method for a multi-functional PLC expansion device based on an FPGA according to the present invention is shown.

[0019] Explanation of reference numerals in the attached figures: R1~R10 correspond to the first to the tenth resistors, respectively; U1~U2 correspond to the first high-speed differential transceiver chip and the second high-speed differential transceiver chip, respectively; C1~C6 correspond to the first to the sixth capacitors, respectively; D1~D2 correspond to the first TVS protection device and the second TVS protection device, respectively; R represents the receiver output of the high-speed differential transceiver chip; RE represents the receiver enable pin of the high-speed differential transceiver chip; DE represents the driver enable pin of the high-speed differential transceiver chip; D represents the driver input of the high-speed differential transceiver chip; A represents the non-inverting input of the high-speed differential transceiver chip; B represents the inverting input of the high-speed differential transceiver chip; M represents the differential signal. Detailed Implementation

[0020] The present application will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings.

[0021] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0022] Figure 1 A multi-functional PLC expansion device based on an FPGA is shown. The FPGA includes a communication module, a function configuration module, a pulse output module, a serial port module, a pulse counting module, and an I / O control module. The communication module is used to receive configuration commands. The function configuration module is connected to the communication module, the pulse output module, the serial port module, and the pulse counting module, respectively, and is used to select and activate any one of the pulse output module, the serial port module, or the pulse counting module according to the configuration commands. The I / O control module is connected to the pulse output module, the serial port module, and the pulse counting module to output functions.

[0023] In a specific embodiment, such as Figure 2 As shown, it also includes an external circuit module, which is connected to the IO control module. The external circuit module includes a first differential signal circuit and a second differential circuit. The first differential signal circuit includes a first high-speed differential transceiver chip U1, first to fifth resistors R1~R5, a first TVS protection device D1, and first to third capacitors C1~C3. The IOA1 interface of the I / O control module is connected to the receiver output terminal R of the first high-speed differential transceiver chip U1. The IOA2 interface of the I / O control module is connected to the receiver enable terminal RE and the driver enable terminal DE of the first high-speed differential transceiver chip U1. The IOA3 interface of the I / O control module is connected to the driver input terminal D of the first high-speed differential transceiver chip U1. The power supply terminal of the first high-speed differential transceiver chip U1 is connected to the power supply VCC, one end of the first capacitor C1, and one end of the first resistor R1. The non-inverting input A of the first high-speed differential transceiver chip U1 is connected to the other end of the first resistor R1 and one end of the third resistor R3. The inverting input B of the first high-speed differential transceiver chip U1 is connected to one end of the second resistor R2 and one end of the fourth resistor R4. The other end of the third resistor R3 is connected to one end of the second capacitor C2, one end of the fifth resistor R5, and one protection terminal of the first TVS protection device D1. The other end of the fourth resistor R4 is connected to one end of the third capacitor C3, the other end of the fifth resistor R5, and the other protection terminal of the first TVS protection device D1. The other end of the first capacitor C1, the ground terminal of the first high-speed differential transceiver chip U1, the other end of the second resistor R2, the other end of the second capacitor C2, the other end of the third capacitor C3, and the ground terminal of the first TVS protection device D1 are all grounded. The second differential signal circuit includes a second high-speed differential transceiver chip U2, sixth to tenth resistors R6~R10, a second TVS protection device D2, and fourth to sixth capacitors C4~C6. The IOB1 interface of the I / O control module is connected to the receiver output terminal R of the second high-speed differential transceiver chip U2. The IOB2 interface of the I / O control module is connected to the receiver enable terminal RE and the driver enable terminal DE of the second high-speed differential transceiver chip U2. The IOB3 interface of the I / O control module is connected to the driver input terminal D of the second high-speed differential transceiver chip U2. The power supply terminal of the second high-speed differential transceiver chip U2 is connected to the power supply, one end of the fourth capacitor C4, and one end of the sixth resistor R6. The non-inverting input A is connected to the other end of the sixth resistor R6 and one end of the eighth resistor R8. The inverting input B of the second high-speed differential transceiver chip U2 is connected to one end of the seventh resistor R7 and one end of the ninth resistor R9. The other end of the eighth resistor RB is connected to one end of the fifth capacitor C5, one end of the tenth resistor R10, and one protection terminal of the second TVS protection device D2. The other end of the ninth resistor R9 is connected to one end of the sixth capacitor C6, the other end of the tenth resistor R10, and the other protection terminal of the second TVS protection device D2. The other end of the fourth capacitor C4, the ground terminal of the second high-speed differential transceiver chip U2, the other end of the seventh resistor R7, the other end of the fifth capacitor C5, the other end of the sixth capacitor C6, and the ground terminal of the second TVS protection device D2 are all grounded. The electrical symbol M represents the differential signal transmitted and received by the high-speed differential transceiver chip, and they are arranged in pairs in the circuit diagram.

[0024] The first resistor R1, the second resistor R2, the sixth resistor R6, and the seventh resistor R7 have the same resistance value. The third resistor R3, the fourth resistor R4, the eighth resistor R8, and the ninth resistor R9 have the same resistance value. The fifth resistor R5 and the tenth resistor R10 have the same resistance value. The first capacitor C1 and the fourth capacitor C4 have the same capacitance value. The second capacitor C2, the third capacitor C3, the fifth capacitor C4, and the sixth capacitor C6 have the same capacitance value.

[0025] The high-speed differential transceiver chip U1 and U2 are used to convert logic signals into differential signals. Resistors R1 and R6 act as pull-up bias resistors. Resistors R2 and R7 act as pull-down bias resistors. These resistors ensure that the bus value is a fixed "logic 1" when idle or floating, preventing false triggering. Resistors R5 and R10 act as terminating resistors, improving the circuit's immunity to common-mode interference and enhancing long-distance transmission capability. Resistors R3, R4, R8, and R9 act as source-end series matching / damping resistors, limiting current and balancing fault isolation and signal integrity. Capacitors C1 and C4 act as decoupling capacitors, while C2, C3, C4, and C6 act as filtering capacitors. The function of the first TVS protection device D1 and the second TVS protection device D2 is to protect the circuit and prevent the high-speed differential transceiver chip from being damaged.

[0026] In one optional embodiment, the resistances of the first resistor R1, the second resistor R2, the sixth resistor R6, and the seventh resistor R7 are 4.7 kΩ; the resistances of the fifth resistor R5 and the tenth resistor R10 are 120 Ω; and the resistances of the third resistor R3, the fourth resistor R4, the eighth resistor R8, and the ninth resistor R9 are 22 Ω. The capacitances of the first capacitor C1 and the fourth capacitor C4 are 100 nF. The capacitances of the second capacitor C2, the third capacitor C3, the fifth capacitor C4, and the sixth capacitor C6 are 100 pF.

[0027] In an optional embodiment, the high-speed differential transceiver chip can be selected as SP485EE or SP485EF, and the TVS protection device can be selected as PSM712-LF-T7.

[0028] In a specific embodiment, the user selects the target function (serial port / encoder input / pulse output) through the host computer software. The host computer configures the configuration parameters and the selected target function as the corresponding configuration instructions and sends them to the device through the PLC master station. After receiving the configuration instructions, the FPGA loads the corresponding functional module and initializes the peripheral circuit, so that the device enters the specified working mode and executes the corresponding function.

[0029] like Figure 3As shown, when the communication module receives a serial port enable configuration command, the function configuration module activates the serial port module. The receiving serial port of the serial port module is set to receive the output after the AND operation of the IOA1 and IOB1 interfaces of the IO control module. The IOA3 interface of the IO control module receives the output of the transmitting interface of the serial port module. The third high-speed differential transceiver chip of the serial port module is connected to the IOA2 interface of the IO control module. The transmitting and receiving states are switched by controlling the logic of the IOB2 interface of the IO control module. The serial port module supports RS422 or RS485 protocols.

[0030] In one specific embodiment, the device can be used as an RS485 communication device for MODBUS RTU communication between a PLC and a frequency converter. Figure 4 As shown, the user configures parameters and selects the target function (serial port) on the host computer and outputs a serial port enable configuration command. The serial port enable configuration command includes serial port configuration parameters and protocol configuration parameters. The serial port configuration parameters are set as follows: serial port number is 10, data bits are 8, baud rate is 9600, parity mode is even parity, and stop bits are 1. The protocol configuration parameters are set as follows: communication protocol type is MODBUS RTU, station number is 1, timeout is 10, transmission interval is 50, bit mode is 16, inter-character timeout is 10, start character is disabled, and stop character is disabled.

[0031] The FPGA's communication module detects the serial port enable signal, and the function configuration module activates the serial port module, setting the RE / DE pins of the corresponding interface to the input state (RE=0, DE=0). When the start bit is received, the UART receive logic is started. After receiving the complete data frame, it is parsed according to the MODBUS RTU protocol. If an acknowledgment is required, DE=1 is set, switching to the output state and sending response data. After completion, the input state is restored, automatically completing data transmission and reception, and realizing remote parameter reading and writing.

[0032] like Figure 5 As shown, when the communication module receives a pulse counting enable configuration command, the function configuration module activates the pulse counting module and selects the corresponding pulse counting mode for pulse counting. It controls the logic of the IOA2 and IOB2 interfaces of the IO control module to be 0. One end of the pulse counting module receives the input of the IOA1 interface of the IO control module, and the other end of the pulse counting module receives the input of the IOB1 interface of the IO control module. The pulse counting modes include pulse + direction mode, encoder A / B phase mode, and single-phase counting mode.

[0033] In one specific embodiment, the device can be used as an encoder input device, connected to an incremental encoder, for servo motor position feedback. For example... Figures 6-8 As shown, after configuring the device as an encoder on the host computer, the user can create a new motion control axis. In the "Axis Property Configuration" interface, the axis type can be selected as "Local Encoder Axis," and the IN port (IN0 / IN1) output port can be selected as the input device. In the "Axis Property Configuration" interface, switch to the "Mode / Parameter Setting" interface and select the counting mode (AB phase, pulse + direction, single phase), generating a pulse counting enable configuration command. Then, the FPGA detects the pulse counting enable configuration command, sets the RE / DE pins to the input state (RE=0, DE=0), and starts the corresponding logic according to different encoder mode configurations (supporting pulse + direction mode, encoder A / B phase mode, and single-phase counting mode), converting these signals into pulse counts for the PLC to read.

[0034] Regardless of the counting mode, the FPGA feeds back the current pulse count to the PLC (only when the A / B phase is configured with an n-fold frequency multiplication, the PLC uses the formula P). (Calculate the number of pulses at n times the frequency using n / 4). The PLC calculates the speed based on the position difference between the two acquisitions. The PLC reads the pulse count P every 1ms. The pulse count at the current moment is... The number of pulses at the last millisecond is If the user-defined unit (e.g., 5 mm / pulse) is U, then the current velocity... ).

[0035] like Figure 9 As shown, when the communication module receives a pulse output enable configuration command, the function configuration module activates the pulse output module and selects the corresponding pulse output mode to configure the pulse signal for output. It controls the logic of the IOA2 and IOB2 interfaces of the IO control module to be 1. The IOA3 interface of the IO control module receives the output from one end of the pulse output module, and the IOB3 interface of the IO control module receives the output from the other end of the pulse output module. The pulse output modes include pulse + direction mode, A / B phase mode, and CW / CCW mode.

[0036] In one specific embodiment, such as Figures 10-12As shown, the device can be used as a high-speed pulse output device to control a stepper motor driver. The user selects the pulse output function on the host computer and sets the pulse frequency to 200kHz and the pulse count to 10000. A new motion control axis is created. In the axis attribute configuration interface, the axis type is selected as a local pulse axis, and this OUT port (OUT0 / OUT1) is selected as the output device. In the "Axis Attribute Configuration" interface, switching to the "Mode / Parameter Setting" interface, the output mode (AB phase, pulse + direction, CW / CCW) is selected, and a pulse output enable configuration command is generated. Then, the FPGA sets the RE / DE pins to the output state (RE=1, DE=1) according to the pulse output enable configuration command. After receiving the pulse position information, the FPGA outputs pulses according to different pulse output mode configurations (supporting pulse + direction mode, A / B phase mode, CW / CCW mode), driving the motor to operate precisely.

[0037] like Figure 13 As shown, according to one aspect of the present invention, a configuration method for a multi-functional PLC expansion device based on an FPGA is proposed, comprising the following steps according to the device described above: S1, configuration instructions are sent from the host computer to the FPGA, which includes a pulse output module, a serial port module and a pulse counting module; S2, when the FPGA receives the configuration instruction, the FPGA selects to activate any one of the pulse output module, the serial port module, or the pulse counting module to perform functional output according to the configuration instruction.

[0038] The above description is merely a preferred embodiment of this application and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of the invention involved in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the above-described inventive concept. For example, technical solutions formed by substituting the above-described features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A multi-functional PLC expansion device based on FPGA, characterized in that, The system includes an FPGA, which comprises a communication module, a function configuration module, a pulse output module, a serial port module, a pulse counting module, and an I / O control module. The communication module receives configuration commands. The function configuration module is connected to the communication module, the pulse output module, the serial port module, and the pulse counting module, respectively, and is used to select and activate any one of the pulse output module, the serial port module, or the pulse counting module according to the configuration commands. The I / O control module is connected to the pulse output module, the serial port module, and the pulse counting module to output functions.

2. The FPGA-based multi-functional PLC expansion device according to claim 1, characterized in that, It also includes an external circuit module, which is connected to the IO control module. The external circuit module includes a first differential signal circuit and a second differential circuit. The first differential signal circuit includes a first high-speed differential transceiver chip, first to fifth resistors, a first TVS protection device, and first to third capacitors. The IOA1 interface of the I / O control module is connected to the receiver output of the first high-speed differential transceiver chip. The IOA2 interface of the I / O control module is connected to the receiver enable and driver enable terminals of the first high-speed differential transceiver chip. The IOA3 interface of the I / O control module is connected to the driver input of the first high-speed differential transceiver chip. The power supply terminal of the first high-speed differential transceiver chip is connected to a power supply, one end of the first capacitor, and one end of the first resistor. The non-inverting input of the chip is connected to the other end of the first resistor and one end of the third resistor. The inverting input of the first high-speed differential transceiver chip is connected to one end of the second resistor and one end of the fourth resistor. The other end of the third resistor is connected to one end of the second capacitor, one end of the fifth resistor, and one protection terminal of the first TVS protection device. The other end of the fourth resistor is connected to one end of the third capacitor, one end of the fifth resistor, and another protection terminal of the first TVS protection device. The other end of the first capacitor, the ground terminal of the first high-speed differential transceiver chip, the other end of the second resistor, the other end of the second capacitor, the other end of the third capacitor, and the ground terminal of the first TVS protection device are all grounded. The second differential signal circuit includes a second high-speed differential transceiver chip, sixth to tenth resistors, a second TVS protection device, and fourth to sixth capacitors. The IOB1 interface of the I / O control module is connected to the receiver output of the second high-speed differential transceiver chip. The IOB2 interface of the I / O control module is connected to the receiver enable and driver enable terminals of the second high-speed differential transceiver chip. The IOB3 interface of the I / O control module is connected to the driver input of the second high-speed differential transceiver chip. The power supply terminal of the second high-speed differential transceiver chip is connected to the power supply, one end of the fourth capacitor, and one end of the sixth resistor. The non-inverting input of the chip is connected to the other end of the sixth resistor and one end of the eighth resistor. The inverting input of the second high-speed differential transceiver chip is connected to one end of the seventh resistor and one end of the ninth resistor. The other end of the eighth resistor is connected to one end of the fifth capacitor, one end of the tenth resistor, and one protection terminal of the second TVS protection device. The other end of the ninth resistor is connected to one end of the sixth capacitor, the other end of the tenth resistor, and the other protection terminal of the second TVS protection device. The other end of the fourth capacitor, the ground terminal of the second high-speed differential transceiver chip, the other end of the seventh resistor, the other end of the fifth capacitor, the other end of the sixth capacitor, and the ground terminal of the second TVS protection device are all grounded. The first, second, sixth, and seventh resistors have the same resistance value; the third, fourth, eighth, and ninth resistors have the same resistance value; the fifth and tenth resistors have the same resistance value; the first and fourth capacitors have the same capacitance value; and the second, third, fifth, and sixth capacitors have the same capacitance value.

3. The FPGA-based multi-functional PLC expansion device according to claim 2, characterized in that, When the communication module receives a serial port enable configuration command, the function configuration module activates the serial port module. The receiving serial port of the serial port module is set to receive the output after the AND operation of the IOA1 and IOB1 interfaces of the IO control module. The IOA3 interface of the IO control module receives the output of the transmitting interface of the serial port module. The third high-speed differential transceiver chip of the serial port module is connected to the IOA2 interface of the IO control module. The transmitting and receiving states are switched by controlling the logic of the IOB2 interface of the IO control module. The serial port module supports RS422 or RS485 protocols.

4. The FPGA-based multi-functional PLC expansion device according to claim 3, characterized in that, The serial port enable configuration instruction includes serial port configuration parameters and protocol configuration parameters. The serial port configuration parameters include serial port number, data bits, baud rate, parity mode, and stop bits. The protocol configuration parameters include communication protocol type, station number, timeout, transmission interval, bit mode, timeout between characters, whether to enable start character, and whether to enable stop character.

5. A multi-functional PLC expansion device based on FPGA according to claim 2, characterized in that, When the communication module receives a pulse counting enable configuration command, the function configuration module activates the pulse counting module to perform pulse counting, controls the logic of the IOA2 and IOB2 interfaces of the IO control module to be 0, one end of the pulse counting module receives the input of the IOA1 interface of the IO control module, and the other end of the pulse counting module receives the input of the IOB1 interface of the IO control module.

6. The FPGA-based multi-functional PLC expansion device according to claim 5, characterized in that, The pulse counting enable configuration instruction includes pulse counting mode parameters, which include pulse + direction mode, encoder A / B phase mode, and single-phase counting mode.

7. A multi-functional PLC expansion device based on FPGA according to claim 2, characterized in that, When the communication module receives a pulse output enable configuration command, the function configuration module activates the pulse output module to configure the pulse signal for output, controls the logic of the IOA2 and IOB2 interfaces of the IO control module to be 1, the IOA3 interface of the IO control module receives the output from one end of the pulse output module, and the IOB3 interface of the IO control module receives the output from the other end of the pulse output module.

8. The FPGA-based multi-functional PLC expansion device according to claim 7, characterized in that, The pulse output enable configuration command includes pulse output mode parameters, which include pulse + direction mode, A / B phase mode and CW / CCW mode.

9. A configuration method for a multi-functional PLC expansion device based on FPGA, characterized in that, The apparatus according to any one of claims 1 to 8 comprises the following steps: S1, configuration instructions are sent from the host computer to the FPGA, which includes a pulse output module, a serial port module and a pulse counting module; S2, when the FPGA receives the configuration instruction, the FPGA selects to activate any one of the pulse output module, the serial port module, or the pulse counting module to perform functional output according to the configuration instruction.

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