Linear voltage regulator

Abstract

The invention discloses a linear voltage regulator. According to the linear voltage regulator, a charge pump generates output voltage according to input voltage, a pre-voltage-stabilizing module divides the input voltage and outputs first voltage to the first end of a power tube according to divided voltage of the input voltage or the output voltage of the charge pump, the first voltage is lower than the input voltage, and the situation that the input voltage is too high to break down the power tube is avoided. The control end of the power tube is connected with the output end of the error amplification module, and the second end of the power tube is the output end of the linear voltage regulator. The output voltage feedback module generates feedback voltage according to the output voltage of the power tube and outputs the feedback voltage to the first input end of the error amplification module, reference voltage is connected to the second input end of the error amplification module, and the control end voltage of the power tube is adjusted according to the reference voltage and the feedback voltage so as to ensure that the output voltage is stable. The technical scheme of the invention can be adapted to a general BCD process platform, the design of the linear voltage regulator with high input voltage is realized under the general BCD process, and the cost is low.

Description

A linear regulator Technical Field

[0001] This invention relates to the field of power electronics technology, and more particularly to a linear voltage regulator. Background Technology

[0002] With the development of automotive electronics and industrial control, electronic devices are placing higher demands on the stability, reliability, and adaptability of power supply systems. Linear regulators can accurately convert fluctuating input voltages into stable output voltages and are widely used in the power supply links of various electronic systems, providing continuous and reliable power to chips, sensors, processors, and other electronic devices that are sensitive to power quality. Bipolar-CMOS-DMOS (BCD) technology combines the integration capabilities of digital logic circuits, analog circuits, and power devices, and has good compatibility, making it an important process platform for the research and development and production of linear regulators.

[0003] Existing domestically used BCD process platforms generally suffer from limited process voltage withstand capabilities, supporting mostly low-to-medium voltage devices ranging from 40V to 60V, making it difficult to directly implement linear regulators with high input voltage specifications. Currently, two common approaches are used to meet the application requirements of high input voltage scenarios in fields such as automotive electronics and industrial control: employing dedicated high-voltage processes or external cascade structures to achieve high input voltage tolerance, thereby completing a stable high-to-low voltage conversion.

[0004] However, the above solutions are difficult to adapt to general BCD process platforms and have high manufacturing costs. Summary of the Invention

[0005] This invention provides a linear regulator that is compatible with a general-purpose BCD process platform, enabling the design of a linear regulator with high input voltage under the general-purpose BCD process without increasing manufacturing costs.

[0006] According to one aspect of the present invention, a linear voltage regulator is provided. The linear voltage regulator of this embodiment includes a pre-regulation module, a charge pump, a power transistor, an output voltage feedback module, and an error amplification module. The input terminal of the charge pump is connected to an input voltage, and the charge pump is used to generate an output voltage at its output terminal based on the input voltage. The first input terminal of the pre-regulation module is connected to the input voltage, and the second input terminal of the pre-regulation module is connected to the output terminal of the charge pump. The pre-regulation module is used to output a first voltage at its first output terminal based on the voltage division of the input voltage or the output voltage of the charge pump, and to output a second voltage from its second output terminal when the difference between the first voltage and a preset regulated voltage is greater than a first threshold. The first terminal of the power transistor is connected to the pre-regulation module. The first output terminal of the voltage regulator module is connected to the control terminal of the power transistor, which is connected to the output terminal of the error amplifier module. The second terminal of the power transistor is the output terminal of the linear regulator. The input terminal of the output voltage feedback module is connected to the second terminal of the power transistor, and the output terminal of the output voltage feedback module is connected to the first input terminal of the error amplifier module. This module generates a feedback voltage based on the output voltage of the power transistor. The fixed potential terminal of the output voltage feedback module is grounded. The second input terminal of the error amplifier module is connected to a reference voltage, and the power supply terminal of the error amplifier module is connected to the second output terminal of the pre-regulator module. This second voltage provides the operating voltage for the error amplifier module, which adjusts the control terminal voltage of the power transistor based on the reference voltage and the feedback voltage.

[0007] Optionally, the charge pump includes a first capacitor, a second capacitor, a switching transistor, and a third capacitor; the first terminal of the first capacitor is connected to the input voltage, the second terminal of the first capacitor is connected to the first terminal of the second capacitor, and the second terminal of the second capacitor is grounded; the first terminal of the switching transistor is connected to the second terminal of the first capacitor, the second terminal of the switching transistor is connected to the first terminal of the third capacitor, the control terminal of the switching transistor is connected to a switching timing signal, the second terminal of the third capacitor is grounded, the switching transistor is used to transfer the charge of the first and second capacitors to the third capacitor under the control of the switching timing signal, and the first terminal of the third capacitor is the output terminal of the charge pump.

[0008] Optionally, the pre-regulator module includes a buck unit and a regulator unit; the first input terminal of the buck unit is the first input terminal of the pre-regulator module, and the first input terminal of the buck unit is connected to the input voltage. The buck unit is used to generate a voltage divider based on the input voltage. The second input terminal of the buck unit is the second input terminal of the pre-regulator module, and the first output terminal of the buck unit is the first output terminal of the pre-regulator module. The buck unit is used to output a first voltage at its first output terminal based on the voltage divider of the input voltage or the output voltage of the charge pump. The input terminal of the regulator unit is connected to the first output terminal of the buck unit, and the output terminal of the regulator unit is the second output terminal of the pre-regulator module. The control terminal of the regulator unit is connected to the second output terminal of the buck unit. When the difference between the first voltage and the voltage at the control terminal of the regulator unit is greater than a first threshold, the regulator unit outputs a second voltage. The fixed potential terminal of the regulator unit is grounded.

[0009] Optionally, the step-down unit includes a first resistor and a second resistor; the first end of the first resistor is connected to the input voltage, the second end of the first resistor is connected to the first end of the second resistor, and the second end of the second resistor is connected to the control terminal of the voltage regulator unit; the first resistor and the second resistor are connected in series to divide the input voltage to generate a divided voltage; the second end of the first resistor is the first output terminal of the step-down unit.

[0010] Optionally, the voltage regulator unit includes a first diode, a second diode, a third diode, and a Zener transistor; the cathode of the first diode is connected to the control terminal of the Zener transistor, the anode of the first diode is connected to the cathode of the second diode, the anode of the second diode is connected to the cathode of the third diode, and the anode of the third diode is grounded; the first terminal of the Zener transistor is connected to the first output terminal of the buck unit, the control terminal of the Zener transistor is connected to the second output terminal of the buck unit, and the second terminal of the Zener transistor is the output terminal of the voltage regulator unit.

[0011] Optionally, the linear regulator in this embodiment of the invention further includes a feedforward compensation module; the input terminal of the feedforward compensation module is connected to the output terminal of the error amplification module, the power supply terminal of the feedforward compensation module is connected to the power supply voltage, and the output terminal of the feedforward compensation module is connected to the control terminal of the power transistor for adjusting the zero point of the control terminal of the power transistor.

[0012] Optionally, the feedforward compensation module includes a compensation transistor; the second terminal of the compensation transistor is connected to the power supply voltage, the first terminal of the compensation transistor is connected to the control terminal of the power transistor, and the control terminal of the compensation transistor is connected to the output terminal of the error amplifier module.

[0013] Optionally, the linear regulator in this embodiment of the invention further includes a dynamic slew rate enhancement module; the input terminal of the dynamic slew rate enhancement module is connected to the output terminal of the error amplification module, and the output terminal of the dynamic slew rate enhancement module is connected to the control terminal of the power transistor, for enhancing the slew rate of the control terminal of the power transistor.

[0014] Optionally, the error amplification module includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a first bias current source; the first terminal of the first transistor and the first terminal of the second transistor are both connected to the first bias current source; the control terminal of the first transistor is connected to the output terminal of the output voltage feedback module; the control terminal of the second transistor is connected to a reference voltage; the second terminal of the first transistor is connected to the second terminal of the third transistor; the control terminal of the third transistor is connected to the first terminal of the third transistor; the first terminal of the third transistor is connected to the first terminal of the fifth transistor; the first terminal of the second transistor is connected to the first terminal of the fourth transistor; the first terminal of the fourth transistor is connected to the control terminal of the fourth transistor; the control terminal of the fourth transistor is connected to the control terminal of the fifth transistor; the second terminals of the fourth transistor and the second terminals of the fifth transistor are both connected to the second output terminal of the pre-regulation module; and the fixed potential terminal of the first bias current source is grounded.

[0015] Optionally, the dynamic slew rate enhancement module includes a sixth transistor, a seventh transistor, an eighth transistor, and a second bias current source; the control terminal of the sixth transistor is connected to the first terminal of the third transistor, the first terminal of the sixth transistor is connected to the second bias current source, the second terminal of the sixth transistor is connected to the first terminal of the seventh transistor, the first terminal of the seventh transistor is connected to the second terminal of the power transistor, the control terminal of the seventh transistor is connected to the second terminal of the third transistor, the second terminal of the seventh transistor is connected to the first terminal of the eighth transistor, the control terminal of the eighth transistor is connected to the first terminal of the sixth transistor, and the power supply terminals of the second terminal of the eighth transistor and the second bias current source are both connected to a second voltage.

[0016] The technical solution of this invention, through the inclusion of a charge pump and a pre-regulator module, utilizes a charge pump to step down the input voltage to generate an output voltage. The pre-regulator module divides the input voltage to generate a divided voltage. When the external load power demand is high, the first output terminal of the pre-regulator module outputs a first voltage based on the output voltage of the charge pump. This first voltage is connected to the first terminal of the power transistor. When the external load power demand is low, the first output terminal of the pre-regulator module outputs a first voltage based on the divided voltage of the input voltage. This first voltage is also connected to the first terminal of the power transistor. The first voltage is lower than the input voltage to prevent the power transistor from breaking down due to excessively high input voltage exceeding its withstand voltage limit. This effectively widens the input voltage range and eliminates the need for external cascade structures, thus reducing manufacturing costs. The input terminal of the output voltage feedback module is connected to the second terminal of the power transistor, and its output terminal is connected to the first input terminal of the error amplifier module. A feedback voltage is generated based on the output voltage. The pre-regulator module generates a stable second voltage to provide the operating voltage for the error amplifier module. The second input terminal of the error amplifier module is connected to a reference voltage. The control terminal voltage of the power transistor is adjusted based on the reference voltage and the feedback voltage, enabling the linear regulator to output a stable output voltage. In summary, the technical solution of this invention expands the input voltage range of linear regulators, can be adapted to BCD process platforms, and enables the design of high input voltage linear regulators under general BCD processes without increasing manufacturing costs.

[0017] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 is a schematic diagram of a linear voltage regulator provided in an embodiment of the present invention; Figure 2 is a schematic diagram of another linear voltage regulator provided in an embodiment of the present invention; Figure 3 is a circuit diagram of a linear voltage regulator provided in an embodiment of the present invention. Detailed Implementation

[0020] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0021] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0022] Figure 1 is a schematic diagram of a linear voltage regulator provided in an embodiment of the present invention. The linear voltage regulator of the present invention is applicable to fields that require stable output voltage under conditions of large input voltage, such as automotive power supply systems, industrial control systems, aerospace and other fields. The present invention does not impose specific limitations. As shown in Figure 1, the linear regulator of this embodiment includes a pre-regulation module 100, a charge pump 110, a power transistor 120, an output voltage feedback module 130, and an error amplification module 140. The input terminal of the charge pump 110 is connected to the input voltage VIN, and the charge pump 110 generates an output voltage V1 at its output terminal based on the input voltage VIN. The first input terminal of the pre-regulation module 100 is connected to the input voltage VIN, and the second input terminal of the pre-regulation module 100 is connected to the output terminal of the charge pump 110. The pre-regulation module 100 outputs a first voltage V2 at its first output terminal based on the voltage division of the input voltage VIN or the output voltage V1 of the charge pump, and outputs a second voltage VREG from its second output terminal when the difference between the first voltage V2 and the preset regulated voltage is greater than a first threshold. The first terminal of the power transistor 120 is connected to the first terminal of the pre-regulation module 100. At the output terminal, the control terminal of power transistor 120 is connected to the output terminal of error amplifier module 140, and the second terminal of power transistor 120 is the output terminal of linear regulator; the input terminal of output voltage feedback module 130 is connected to the second terminal of power transistor 120, and the output terminal of output voltage feedback module 130 is connected to the first input terminal of error amplifier module 140, which is used to generate feedback voltage VFB according to the output voltage of power transistor 120; the fixed potential terminal of output voltage feedback module 130 is grounded; the second input terminal of error amplifier module 140 is connected to reference voltage VREF, and the power supply terminal of error amplifier module 140 is connected to the second output terminal of pre-regulator module 100. The second voltage VREG is used to provide operating voltage for error amplifier module 140, and error amplifier module 140 is used to adjust the control terminal voltage of power transistor 120 according to reference voltage VREF and feedback voltage VFB.

[0023] In this embodiment of the invention, the charge pump 110 can step down the input voltage VIN to generate an output voltage V1. The input voltage VIN is high voltage, and the output voltage V1 of the charge pump 110 is medium voltage. For example, the input voltage VIN can be 100V, and the output voltage V1 of the charge pump 110 can be 50V.

[0024] The pre-regulator module 100 can generate a voltage divider based on the input voltage VIN. The voltage divider is a medium voltage, for example, 48V. The pre-regulator module 100 can output a first voltage V2 at the first output terminal based on the voltage divider, or based on the output voltage V1 of the charge pump 110. When the linear regulator operates under conditions where the input voltage VIN is high, the first voltage V2 output by the pre-regulator module 100 can prevent the excessively high input voltage VIN from damaging the power transistor 120.

[0025] The pre-regulator module 100 also has a voltage regulation function. The preset regulated voltage can be a stable voltage value that the second output terminal of the pre-regulator module 100 is expected to maintain, which can be configured by hardware parameters and preset. The first threshold can be a threshold condition for the pre-regulator module 100 to output a second voltage VREG at the second output terminal. When the difference between the first voltage V2 and the preset regulated voltage exceeds the first threshold, the second output terminal of the pre-regulator module 100 can output a stable second voltage VREG. Ideally, the second voltage VREG is equal to the preset regulated voltage. The second voltage VREG can be used to provide operating power to other circuit modules inside the linear regulator. For example, the second output terminal of the pre-regulator module 100 is connected to the power supply terminal of the error amplifier module 140, and the second voltage VREG provides a stable operating voltage for the error amplifier module 140.

[0026] Power transistor 120 can regulate the unstable first voltage V2 to output a stable output voltage VOUT. Power transistor 120 can also be used as the load current carrier in a high-dropout linear regulator. Power transistor 120 can be an N-type MOSFET, with its first terminal serving as the drain, its second terminal as the source, and its control terminal as the gate.

[0027] The output voltage feedback module 130 can sample the output voltage VOUT of the power transistor 120 and generate a feedback voltage VFB based on the output voltage VOUT. The feedback voltage VFB has a linear relationship with the output voltage VOUT, so that the feedback voltage VFB can characterize the output voltage VOUT.

[0028] The error amplification module 140 can adjust the voltage at the control terminal of the power transistor 120 to regulate the conduction level of the power transistor 120, thereby stabilizing the output voltage VOUT of the power transistor 120. The second input terminal of the error amplification module 140 can be connected to a reference voltage VREF, and the first input terminal can be connected to a feedback voltage VFB. For example, the non-inverting input terminal of the error amplification module 140 can be connected to the reference voltage VREF, and the inverting input terminal can be connected to the feedback voltage VFB. When the feedback voltage VFB exceeds the reference voltage VREF, the voltage at the output terminal of the error amplification module 140 decreases, and the gate voltage of the power transistor 120 decreases, thereby reducing the conduction level of the power transistor 120 and thus reducing the output voltage VOUT of the power transistor 120. When the feedback voltage VFB is less than the reference voltage VREF, the voltage at the output terminal of the error amplification module 140 increases, and the gate voltage of the power transistor 120 increases, thereby increasing the conduction level of the power transistor 120 and thus increasing the output voltage VOUT of the power transistor 120.

[0029] Specifically, the input terminal of the linear regulator is connected to the input voltage VIN, meaning the charge pump 110 and the first input terminal of the pre-regulator module 100 are both connected to VIN. When the load demand is high, the charge pump 110 steps down the input voltage VIN to generate an output voltage V1. The pre-regulator module 100 outputs a first voltage V2 at its first output terminal based on the output voltage V1 of the charge pump 110, supplying power to the drain of the power transistor 120 to provide a larger load current and meet the power demand of the external load. When the load demand is low, the pre-regulator module 100 steps down the input voltage VIN and outputs a first voltage V2 at its first output terminal to supply power to the drain of the power transistor 120 to provide a smaller load current, reducing power consumption while meeting the power demand of the external load. The first voltage V2 is connected to the drain of the power transistor 120. Since the first voltage V2 is lower than the input voltage VIN, the linear regulator can operate normally as long as the first voltage V2 is within the drain withstand voltage range of the power transistor 120. The gate voltage of power transistor 120 affects its conduction level. A higher conduction level results in a higher output voltage VOUT, and vice versa. The output voltage feedback module 130 samples the output voltage VOUT of power transistor 120 and generates a feedback voltage VFB. The second voltage VREG output by the pre-regulation module 100 provides the operating voltage for the error amplification module 140. The fixed potential terminal of the error amplification module 140 is grounded. The error amplification module 140 can adjust its output voltage according to the magnitude of the feedback voltage VFB to regulate the gate voltage of power transistor 120, thereby maintaining the stability of the output voltage VOUT of power transistor 120.

[0030] According to the technical solution of this embodiment of the invention, by setting a charge pump and a pre-regulator module, the charge pump steps down the input voltage to generate an output voltage, and the pre-regulator module divides the input voltage to generate a divided voltage. When the external load power demand is large, the first output terminal of the pre-regulator module outputs a first voltage based on the output voltage of the charge pump. This first voltage is connected to the first terminal of the power transistor. When the external load power demand is small, the first output terminal of the pre-regulator module outputs a first voltage based on the divided voltage of the input voltage. This first voltage is also connected to the first terminal of the power transistor. The first voltage is lower than the input voltage to avoid the power transistor being damaged due to excessively high input voltage exceeding its withstand voltage limit. This effectively widens the range of the input voltage and eliminates the need for an external cascaded structure, thus not increasing manufacturing costs. The input terminal of the output voltage feedback module is connected to the second terminal of the power transistor, and the output terminal of the output voltage feedback module is connected to the first input terminal of the error amplifier module. A feedback voltage is generated based on the output voltage. The pre-regulator module generates a stable second voltage to provide the operating voltage for the error amplifier module. The second input terminal of the error amplifier module is connected to a reference voltage. The control terminal voltage of the power transistor is adjusted according to the reference voltage and the feedback voltage, so that the linear regulator outputs a stable output voltage. In summary, the technical solution of this invention expands the input voltage range of linear regulators, can be adapted to BCD process platforms, and enables the design of high input voltage linear regulators under general BCD processes without increasing manufacturing costs.

[0031] Based on the above embodiments, Figure 2 is a schematic diagram of another linear regulator provided by the present invention. In some embodiments, the linear regulator further includes a feedforward compensation module 160; the input terminal of the feedforward compensation module 160 is connected to the output terminal of the error amplification module 140, the power supply terminal of the feedforward compensation module 160 is connected to the power supply voltage, and the output terminal of the feedforward compensation module 160 is connected to the control terminal of the power transistor 120 for adjusting the zero point of the control terminal of the power transistor 120.

[0032] Among them, the feedforward compensation module 160 has impedance characteristics. The power supply voltage connected to the power supply terminal of the feedforward compensation module 160 can be the second voltage VREG. A feedforward path is introduced between the operational amplifier module 140 and the control terminal of the power transistor 120. The feedforward compensation module 160 can perform feedforward compensation on the zero point of the control terminal of the power transistor 120, which can improve the phase margin of the linear regulator system and increase its stability.

[0033] Optionally, the feedforward compensation module 160 includes a compensation transistor; the second terminal of the compensation transistor is connected to the power supply voltage, the first terminal of the compensation transistor is connected to the control terminal of the power transistor 120, and the control terminal of the compensation transistor 120 is connected to the output terminal of the error amplification module 140.

[0034] The compensation transistor can be a P-type MOSFET. Its first terminal can be the drain, its second terminal can be the source, and its control terminal can be the gate. The output of the error amplifier module 140 can provide a small signal current to the compensation transistor, enabling it to form a low-frequency compensation zero at the gate of the power transistor 120. This compensates for the gate pole VG of the power transistor 120, increasing the range of the load current or the capacitance value without affecting the output impedance of the power transistor 120 or the main pole formed by the load capacitance, thus achieving stable output across a wide load range for the linear regulator.

[0035] Referring again to Figure 2, in some embodiments, the linear regulator further includes a dynamic slew rate enhancement module 170; the input of the dynamic slew rate enhancement module 170 is connected to the output of the error amplification module 140, and the output of the dynamic slew rate enhancement module 170 is connected to the control terminal of the power transistor 120, for enhancing the slew rate of the control terminal of the power transistor 120.

[0036] The output of the error amplification module 140 can be connected to the control terminal of the power transistor 120 through the dynamic slew rate enhancement module 170. The dynamic slew rate enhancement module 170 can separate the gate pole VG of the power transistor 120 from the output pole, expand the loop bandwidth of the linear regulator, and make the bandwidth of the error amplification module 140 wider. It also speeds up the response speed to the feedback voltage VFB. When the load current fluctuates, the error amplification module 140 can drive the power transistor 120 to adjust the output voltage VOUT more quickly in order to adjust the load current, improve the transient response capability of the linear regulator, and thus improve the dynamic slew rate.

[0037] Optionally, the output voltage feedback module 130 may include a first feedback resistor RF1 and a second feedback resistor RF2. The first end of the first feedback resistor RF1 is connected to the second end of the power transistor 120, the second end of the first feedback resistor RF1 is connected to the first end of the second feedback resistor RF2, the second end of the first feedback resistor RF1 is a feedback node, the feedback node is connected to the first input terminal of the error amplifier module 140, and the second end of the second feedback resistor RF2 is grounded.

[0038] The first feedback resistor RF1 and the second feedback resistor RF2 are connected in series. When current flows through them, a voltage divider is generated at the second terminal of the first feedback resistor RF1 to sample the output voltage VOUT of the power transistor 120 and generate a feedback voltage VFB. The feedback voltage VFB has a linear relationship with the output voltage VOUT.

[0039] Figure 3 is a circuit diagram of a linear regulator provided in an embodiment of the present invention. In some embodiments, the charge pump 110 includes a first capacitor C1, a second capacitor C2, a switching transistor P0, and a third capacitor C3. The first terminal of the first capacitor C1 is connected to the input voltage VIN, the second terminal of the first capacitor C1 is connected to the first terminal of the second capacitor C2, and the second terminal of the second capacitor C2 is grounded. The first terminal of the switching transistor P0 is connected to the second terminal of the first capacitor C1, the second terminal of the switching transistor P0 is connected to the first terminal of the third capacitor C3, the control terminal of the switching transistor P0 is connected to a switching timing signal, and the second terminal of the third capacitor C3 is grounded. The switching transistor P0 is used to transfer the charge of the first capacitor C1 and the second capacitor C2 to the third capacitor C3 under the control of the switching timing signal. The first terminal of the third capacitor C3 is the output terminal of the charge pump 110.

[0040] The series connection of the first capacitor C1 and the second capacitor C2 allows for voltage division of the input voltage VIN. Simultaneously, both capacitors C1 and C2 can store electrical charge. For example, if the input voltage VIN is 100V, the capacitance values ​​of the first capacitor C1 and the second capacitor C2 can be equal. The voltage generated at the second terminal of the first capacitor C1 is half of the input voltage VIN, i.e., the voltage at the second terminal of the first capacitor C1 is 50V. The charge stored in the first capacitor C1 is the product of its voltage and its capacitance.

[0041] Switching timing signals can be pulse signals with a fixed frequency and duty cycle. For example, switching timing signals can be oscillation signals (OSC) generated by a PWM controller or oscillator. The oscillation signals (OSC) can be periodic square wave signals or rectangular wave signals.

[0042] The switching transistor P0 can be a P-type MOSFET. The first terminal of the switching transistor P0 is the source of the P-type MOSFET, the second terminal is the drain of the P-type MOSFET, and the control terminal is the gate of the P-type MOSFET. The gate of the switching transistor P0 is connected to a switching timing signal for precise control of its on / off timing. For example, when the oscillation signal OSC is high, the switching transistor P0 is on, transferring the charge stored in the first capacitor C1 and the second capacitor C2 to the third capacitor C3. The third capacitor C3 stores the charge and generates an output voltage V1. When the oscillation signal OSC is low, the switching transistor P0 is off, stopping the transfer of charge stored in the first and second capacitors C1 and C2 to the third capacitor C3. The output voltage V1 is then output at the output terminal of the charge pump 110, i.e., the first terminal of the third capacitor C3. By adjusting the duty cycle of the switching timing signal, the buck ratio can be flexibly adjusted without changing the hardware circuit, allowing the charge pump 110 to output different output voltages V1. By using charge transfer, the charge pump 110 has low energy loss and the output impedance of the switching transistor P0 is small. Therefore, when the pre-regulator module 100 outputs the first voltage V2 to the power transistor based on the output voltage of the charge pump 110, it can carry a large current.

[0043] Specifically, the output of the linear regulator is connected to an external transistor. The linear regulator is integrated on a chip, which also contains an oscillator. The oscillator outputs an oscillation signal OSC, which drives the external transistor. When the external transistor is on, it can carry a large load current to meet the power demand of the external load of the linear regulator. When the external power demand of the linear regulator is large, the chip needs to drive the external transistor, and the oscillator generates an oscillation signal OSC. At the same time, the oscillation signal OSC can control the on or off state of the switching transistor P0 in the charge pump 110. At this time, the pre-regulator module 100 can output a first voltage V2 at the first output terminal according to the output voltage V1 of the charge pump 110, and supply power to the first terminal of the power transistor 120 to provide a larger load current to meet the larger power demand of the load.

[0044] Referring again to Figure 3, in some embodiments, the pre-regulator module 100 includes a buck unit 101 and a regulator unit 102. The first input terminal of the buck unit 101 is the first input terminal of the pre-regulator module 100, and the first input terminal of the buck unit 101 is connected to the input voltage VIN. The buck unit 101 is used to generate a voltage divider based on the input voltage VIN. The second input terminal of the buck unit 101 is the second input terminal of the pre-regulator module 100, and the first output terminal of the buck unit 101 is the first output terminal of the pre-regulator module 100. The buck unit 101 is used to generate a voltage divider based on the input voltage VIN. The voltage divider voltage of the input voltage VIN or the output voltage V1 of the charge pump 110 outputs a first voltage V2 at the first output terminal; the input terminal of the voltage regulator unit 102 is connected to the first output terminal of the buck unit 101, the output terminal of the voltage regulator unit 102 is the second output terminal of the pre-regulator module 100, the control terminal of the voltage regulator unit 102 is connected to the second output terminal of the buck unit 101, and when the difference between the first voltage V2 and the voltage at the control terminal of the voltage regulator unit 102 is greater than the first threshold, the voltage regulator unit 102 outputs a second voltage VREG; the fixed potential terminal of the voltage regulator unit 102 is grounded.

[0045] The buck unit 101 can have impedance characteristics, dividing the input voltage VIN to generate a divided voltage VIN. The first voltage V2 output by the buck unit 101 can be connected to the first terminal of the power transistor 120, providing a lower drain voltage for the power transistor 120. The second voltage VREG generated by the voltage regulator unit 102 can be used to provide operating power to other circuit modules inside the high-dropout linear regulator. For example, the output terminal of the voltage regulator unit 102 is connected to the power supply terminal of the error amplifier module, and the second voltage VREG output by the voltage regulator unit 102 provides a stable operating voltage for the error amplifier module 140.

[0046] Referring again to Figure 3, optionally, the step-down unit 101 includes a first resistor R1 and a second resistor R2; the first end of the first resistor R1 is connected to the input voltage VIN, the second end of the first resistor R1 is connected to the first end of the second resistor R2, and the second end of the second resistor R2 is connected to the control terminal of the voltage regulator unit 102; the first resistor R1 and the second resistor R2 are connected in series to divide the input voltage VIN to generate a divided voltage; the second end of the first resistor R1 is the first output terminal of the step-down unit 101.

[0047] The first resistor R1 and the second resistor R2 are connected in series. Based on the resistance values ​​of the first resistor R1 and the second resistor R2, the input voltage VIN can be divided.

[0048] During the pre-start-up phase or standby state of the linear regulator, when the power demand of the external load of the linear regulator is small, the chip does not need to drive the external transistor and the oscillator does not oscillate. At this time, the pre-regulator module 100 can output the first voltage V2 at the first output terminal according to the voltage division of the input voltage to supply power to the first terminal of the power transistor 120, so that the load has a small operating current in a low power consumption state.

[0049] Referring again to Figure 3, optionally, the voltage regulator unit 102 includes a first diode D1, a second diode D2, a third diode D3, and a Zener transistor N0; the cathode of the first diode D1 is connected to the control terminal of the Zener transistor N0, the anode of the first diode D1 is connected to the cathode of the second diode D2, the anode of the second diode D2 is connected to the cathode of the third diode D3, and the anode of the third diode D3 is grounded; the first terminal of the Zener transistor N0 is connected to the first output terminal of the buck unit 101, the control terminal of the Zener transistor N0 is connected to the second output terminal of the buck unit 101, and the second terminal of the Zener transistor N0 is the output terminal of the voltage regulator unit 102.

[0050] In this circuit, the first diode D1, the second diode D2, and the third diode D3 can be Zener diodes, connected in series in the same direction to form a diode voltage regulator circuit. The second output terminal of the step-down unit 101 provides bias current to the first diode D1, the second diode D2, and the third diode D3, enabling the diode voltage regulator circuit to establish a preset regulated voltage. The preset regulated voltage is the sum of the regulated voltage values ​​of the first diode D1, the second diode D2, and the third diode D3. The Zener transistor N0 can be an N-type MOSFET. The first terminal of the Zener transistor N0 can be the drain of the N-type MOSFET, the second terminal of the Zener transistor N0 can be the source of the N-type MOSFET, and the control terminal of the Zener transistor N0 can be the gate of the N-type MOSFET.

[0051] Specifically, the drain of Zener transistor N0 is connected to a first voltage V2, the second output terminal of buck unit 101 provides sufficient bias current to the diode voltage regulator circuit, the first diode D1, the second diode D2 and the third diode D3 are in reverse breakdown state, the control terminal of Zener transistor N0 is connected to a preset regulated voltage, when the difference between the first voltage V2 and the reference voltage is higher than a first threshold, for example, when the difference between the first voltage V2 and the preset regulated voltage is greater than 1, Zener transistor N0 can output a second voltage VREG, the second voltage VREG being the preset regulated voltage.

[0052] Optionally, the error amplification module 140 includes a first transistor NA1, a second transistor NA2, a third transistor NA3, a fourth transistor PA1, a fifth transistor PA2, and a first bias current source IB1.

[0053] The first terminal of the first transistor NA1 and the first terminal of the second transistor NA2 are both connected to the first bias current source IB1. The control terminal of the first transistor NA1 is connected to the output terminal of the output voltage feedback module 130. The control terminal of the second transistor NA2 is connected to the reference voltage VREF. The second terminal of the first transistor NA1 is connected to the second terminal of the third transistor NA3. The control terminal of the third transistor NA3 is connected to the first terminal of the third transistor NA3. The first terminal of the third transistor NA3 is connected to the first terminal of the fifth transistor PA2. The first terminal of the second transistor NA2 is connected to the first terminal of the fourth transistor PA1. The first terminal of the fourth transistor PA1 is connected to the control terminal of the fourth transistor PA1. The control terminal of transistor A1 is connected to the control terminal of the fifth transistor PA2. The second terminals of both the fourth transistor PA1 and the fifth transistor PA2 are connected to the second output terminal of the pre-regulator module 150. The fixed potential terminal of the first bias current source IB1 is grounded. The first transistor NA1 and the second transistor NA2 can be NPN transistors. The first terminal of the first transistor NA1 and the first terminal of the second transistor NA2 can be the emitters of the NPN transistors. The second terminals of the first transistor NA1 and the second terminals of the second transistor NA2 can be the collectors of the NPN transistors. The control terminals of the first transistor NA1 and the second transistor NA2 can be the bases of the NPN transistors. The third transistor NA3 can be an N-type MOSFET. The first terminal of the third transistor NA3 can be the drain of the N-type MOSFET. The second terminal of the third transistor NA3 can be the source of the N-type MOSFET. The control terminal of the third transistor NA3 can be the gate of the N-type MOSFET. The fourth transistor PA1 and the fifth transistor PA2 can be P-type MOS transistors. The first terminal of the fourth transistor PA1 and the first terminal of the fifth transistor PA2 can be the drain of the P-type MOS transistors. The second terminal of the fourth transistor PA1 and the second terminal of the fifth transistor PA2 can be the source of the P-type MOS transistors. The control terminal of the fourth transistor PA1 and the control terminal of the fifth transistor PA2 can be the gate of the P-type MOS transistors.

[0054] Specifically, the first transistor NA1 and the second transistor NA2 form the differential input pair of the error amplifier module 140. The control terminal of the first transistor NA1 can be the inverting input terminal of the error amplifier module 140, connected to the feedback voltage VFB. The control terminal of the second transistor NA2 can be the non-inverting input terminal of the error amplifier module 140, connected to the reference voltage VREF. The third transistor NA3 is a common-mode feedback transistor, and the first bias current source IB1 provides bias current for the differential input pair and the common-mode feedback transistor. The fourth transistor PA1 and the fifth transistor PA2 form a PMOS current mirror. The sources of both the fourth transistor PA1 and the fifth transistor PA2 are connected to the second voltage VREG. The fourth transistor PA1 and the fifth transistor PA2 amplify the error signal of the differential input pair. The third transistor NA3 outputs a stable error amplification signal. If the feedback voltage VFB is small, the output voltage of the error amplification module 140 is large, the gate voltage of the power transistor 120 is large, the conduction degree of the power transistor 120 is large, and the output voltage VOUT of the power transistor 120 increases. If the feedback voltage VFB is large, the output voltage of the error amplification module 140 is small, the gate voltage of the power transistor 120 is small, the conduction degree of the power transistor 120 is small, and the output voltage VOUT of the power transistor 120 decreases, thus forming a voltage regulation closed loop for the power transistor 120.

[0055] Optionally, the dynamic slew rate enhancement module 170 includes a sixth transistor NA4, a seventh transistor PA3, an eighth transistor PA4, and a second bias current source IB2.

[0056] The control terminal of the sixth transistor NA4 is connected to the first terminal of the third transistor NA3. The first terminal of the sixth transistor NA4 is connected to the second bias current source IB2. The second terminal of the sixth transistor NA4 is connected to the first terminal of the seventh transistor PA3. The first terminal of the seventh transistor PA3 is connected to the second terminal of the power transistor 120. The control terminal of the seventh transistor PA3 is connected to the second terminal of the third transistor NA3. The second terminal of the seventh transistor PA3 is connected to the first terminal of the eighth transistor PA4. The control terminal of the eighth transistor PA4 is connected to the first terminal of the sixth transistor NA4. The second terminal of the eighth transistor PA4 and the power supply terminal of the second bias current source IB2 are both connected to the second voltage VREG.

[0057] In this configuration, the sixth transistor NA4 can be an N-type MOSFET. The first terminal of the sixth transistor NA4 can be the drain of the N-type MOSFET, the second terminal of the sixth transistor NA4 can be the source of the N-type MOSFET, and the control terminal of the sixth transistor NA4 can be the gate of the N-type MOSFET. Similarly, the seventh transistor PA3 and the eighth transistor PA4 can be P-type MOSFETs. The first terminals of the seventh transistor PA3 and the eighth transistor PA4 can be the drains of the P-type MOSFETs, the second terminals of the seventh transistor PA3 and the eighth transistor PA4 can be the sources of the P-type MOSFETs, and the control terminals of the seventh transistor PA3 and the eighth transistor PA4 can be the gates of the P-type MOSFETs.

[0058] Specifically, when the load current increases, the gate voltage of power transistor 120 needs to be increased to provide more current output. Error amplifier module 140 adjusts the gate voltage of the seventh transistor PA3 to increase the gate voltage of power transistor 120. When the gate voltage of the seventh transistor PA3 increases, the gate voltage of the sixth transistor NA4 also increases, causing the gate voltage of the eighth transistor PA4 to decrease. The current of the eighth transistor PA4 increases, resulting in a larger operating current for the seventh transistor PA3. This increases the small-signal transconductance of the seventh transistor PA3 and reduces the small-signal resistance of the gate of power transistor 120, thereby pushing up the pole of the gate of power transistor 120 and separating the pole of the gate of power transistor 120 from the output pole. After pole separation, the loop bandwidth of the linear regulator is expanded, allowing the bandwidth of error amplifier module 140 to be designed to be wider, and the response speed to the feedback voltage VFB is faster. When the load fluctuates, error amplifier module 140 can drive power transistor 120 to adjust the current more quickly, improving the transient response capability of the linear regulator and thus improving the dynamic slew rate.

[0059] Optionally, the second terminal of the compensation transistor is connected to a power supply voltage, which can be the second voltage VREG output by the pre-regulator module 100. The first terminal of the compensation transistor is connected to the control terminal of the power transistor 120, and the control terminal of the compensation transistor 120 is connected to the control terminal of the fifth transistor PA2 of the error amplifier module 140. The gate of the compensation transistor is controlled by the fifth transistor PA2 in the error amplifier module 140, thereby providing a feedforward zero at the gate of the power transistor 120 based on the output of the error amplifier module 140, improving the stability of the linear regulator.

[0060] For example, with a linear regulator inputting a 100V high voltage, the zero-point compensation generated by the feedforward compensation module can achieve system stability within a load current range of 0-100mA. Facing load switching of 0-100mA, the dynamic response speed is within 10μs.

[0061] According to the technical solution of the present invention, by setting a charge pump and a pre-regulation module, the linear regulator has a wider input range; by setting a feedforward compensation module, the linear regulator has a wider load range; and by setting a dynamic slew rate enhancement module, the dynamic response capability of the linear regulator is improved. In summary, the linear regulator of the present invention can balance stability with a wide input range and a wide load range with high-speed dynamic response capability.

[0062] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0063] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A linear voltage regulator, characterized in that, The system includes a pre-regulator module, a charge pump, a power transistor, an output voltage feedback module, and an error amplifier module. The charge pump's input terminal is connected to an input voltage, and it generates an output voltage based on the input voltage. The pre-regulator module's first input terminal is connected to the input voltage, and its second input terminal is connected to the output terminal of the charge pump. The pre-regulator module outputs a first voltage at its first output terminal based on the voltage division of the input voltage or the output voltage of the charge pump, and outputs a second voltage at its second output terminal when the difference between the first voltage and a preset regulated voltage exceeds a first threshold. The power transistor's first terminal is connected to the first output terminal of the pre-regulator module, and its control terminal is connected to... The output terminal of the error amplification module is connected to the second terminal of the power transistor, which is also the output terminal of the linear regulator. The input terminal of the output voltage feedback module is connected to the second terminal of the power transistor, and the output terminal of the output voltage feedback module is connected to the first input terminal of the error amplification module, which is used to generate a feedback voltage based on the output voltage of the power transistor. The fixed potential terminal of the output voltage feedback module is grounded. The second input terminal of the error amplification module is connected to a reference voltage, and the power supply terminal of the error amplification module is connected to the second output terminal of the pre-regulation module. The second voltage is used to provide the operating voltage for the error amplification module, and the error amplification module is used to adjust the control terminal voltage of the power transistor based on the reference voltage and the feedback voltage.

2. The linear voltage regulator according to claim 1, characterized in that, The charge pump includes a first capacitor, a second capacitor, a switching transistor, and a third capacitor. The first terminal of the first capacitor is connected to the input voltage, and the second terminal of the first capacitor is connected to the first terminal of the second capacitor, which is grounded. The first terminal of the switching transistor is connected to the second terminal of the first capacitor, and the second terminal of the switching transistor is connected to the first terminal of the third capacitor. The control terminal of the switching transistor is connected to a switching timing signal, and the second terminal of the third capacitor is grounded. The switching transistor is used to transfer the charge from the first and second capacitors to the third capacitor under the control of the switching timing signal. The first terminal of the third capacitor is the output terminal of the charge pump.

3. The linear voltage regulator according to claim 1, characterized in that, The pre-regulator module includes a buck unit and a regulator unit. The first input terminal of the buck unit is the first input terminal of the pre-regulator module, and the first input terminal of the buck unit is connected to the input voltage. The buck unit generates a voltage divider based on the input voltage. The second input terminal of the buck unit is the second input terminal of the pre-regulator module. The first output terminal of the buck unit is the first output terminal of the pre-regulator module. The buck unit outputs a first voltage at its first output terminal based on the voltage divider of the input voltage or the output voltage of the charge pump. The input terminal of the regulator unit is connected to the first output terminal of the buck unit, and the output terminal of the regulator unit is the second output terminal of the pre-regulator module. The control terminal of the regulator unit is connected to the second output terminal of the buck unit. When the difference between the first voltage and the control terminal voltage of the regulator unit is greater than a first threshold, the regulator unit outputs a second voltage. The fixed potential terminal of the regulator unit is grounded.

4. The linear voltage regulator according to claim 3, characterized in that, The step-down unit includes a first resistor and a second resistor; the first end of the first resistor is connected to the input voltage, the second end of the first resistor is connected to the first end of the second resistor, and the second end of the second resistor is connected to the control terminal of the voltage regulator unit; the first resistor and the second resistor are connected in series to divide the input voltage to generate a divided voltage; the second end of the first resistor is the first output terminal of the step-down unit.

5. The linear voltage regulator according to claim 3, characterized in that, The voltage regulator unit includes a first diode, a second diode, a third diode, and a Zener transistor; the cathode of the first diode is connected to the control terminal of the Zener transistor, the anode of the first diode is connected to the cathode of the second diode, the anode of the second diode is connected to the cathode of the third diode, and the anode of the third diode is grounded; the first terminal of the Zener transistor is connected to the first output terminal of the buck unit, the control terminal of the Zener transistor is connected to the second output terminal of the buck unit, and the second terminal of the Zener transistor is the output terminal of the voltage regulator unit.

6. The linear voltage regulator according to claim 1, characterized in that, It also includes a feedforward compensation module; the input terminal of the feedforward compensation module is connected to the output terminal of the error amplification module, the power supply terminal of the feedforward compensation module is connected to the power supply voltage, and the output terminal of the feedforward compensation module is connected to the control terminal of the power transistor for adjusting the zero point of the control terminal of the power transistor.

7. The linear regulator according to claim 6, characterized in that, The feedforward compensation module includes a compensation transistor; the second terminal of the compensation transistor is connected to the power supply voltage, the first terminal of the compensation transistor is connected to the control terminal of the power transistor, and the control terminal of the compensation transistor is connected to the output terminal of the error amplification module.

8. The linear regulator according to claim 1, characterized in that, It also includes a dynamic slew rate enhancement module; the input of the dynamic slew rate enhancement module is connected to the output of the error amplification module, and the output of the dynamic slew rate enhancement module is connected to the control terminal of the power transistor, for enhancing the slew rate of the control terminal of the power transistor.

9. The linear voltage regulator according to claim 1, characterized in that, The error amplification module includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a first bias current source. The first terminals of the first and second transistors are both connected to the first bias current source. The control terminal of the first transistor is connected to the output terminal of the output voltage feedback module. The control terminal of the second transistor is connected to the reference voltage. The second terminal of the first transistor is connected to the second terminal of the third transistor. The control terminal of the third transistor is connected to the first terminal of the third transistor. The first terminal of the third transistor is connected to the first terminal of the fifth transistor. The first terminal of the second transistor is connected to the first terminal of the fourth transistor. The first terminal of the fourth transistor is connected to the control terminal of the fourth transistor. The control terminal of the fourth transistor is connected to the control terminal of the fifth transistor. The second terminals of the fourth and fifth transistors are both connected to the second output terminal of the pre-regulatory module. The fixed potential terminal of the first bias current source is grounded.

10. The linear regulator according to claim 8, characterized in that, The dynamic slew rate enhancement module includes a sixth transistor, a seventh transistor, an eighth transistor, and a second bias current source. The control terminal of the sixth transistor is connected to the first terminal of the third transistor, the first terminal of the sixth transistor is connected to the second bias current source, the second terminal of the sixth transistor is connected to the first terminal of the seventh transistor, the first terminal of the seventh transistor is connected to the second terminal of the power transistor, the control terminal of the seventh transistor is connected to the second terminal of the third transistor, the second terminal of the seventh transistor is connected to the first terminal of the eighth transistor, the control terminal of the eighth transistor is connected to the first terminal of the sixth transistor, and the power supply terminals of the second terminal of the eighth transistor and the second bias current source are both connected to a second voltage.

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