Fan-out packaging integrated heat dissipation structure and preparation method thereof

Abstract

The invention provides a fan-out type packaging integrated heat dissipation structure and a preparation method thereof. The fan-out type packaging integrated heat dissipation structure comprises a fan-out type packaging structure, a first medium-thermal interface material layer is arranged on the fan-out type packaging structure, and a radiator and / or a soaking piece are / is arranged on the first medium-thermal interface material layer; wherein the fan-out type packaging structure comprises a chip which is in contact with the first medium-thermal interface material layer, and the thickness of the first medium-thermal interface material layer is less than 100 microns. According to the fan-out type packaging integrated heat dissipation structure and the preparation method thereof provided by the embodiment of the invention, the heat dissipation effect of the fan-out type packaging structure is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and specifically to a fan-out packaged integrated heat dissipation structure and its fabrication method. Background Technology

[0002] With the emergence of technologies such as Embedded Wafer Level Ball Grid Array (eWLB) and Integrated Fan-Out (InFO), fan-out packaging has made significant progress. Compared with traditional packaging technologies, fan-out packaging eliminates the need for a packaging substrate, enabling smaller size and better heat dissipation performance.

[0003] In existing technologies, heat dissipation in multi-chip, high-density integrated fan-out packages is difficult to achieve due to the lack of heat dissipation paths with lower thermal resistance. One approach is to directly attach the heatsink to the fan-out package to enhance top-path heat dissipation. However, fan-out packages contain wafer-level or panel-level molded epoxy molding compound (EMC) to protect the chip, control warpage, and support the heatsink. This typically results in an overmolded layer between the chip and the heatsink for electrical insulation. The low thermal conductivity of this overmolded layer becomes a bottleneck for heat dissipation performance, while its high specific heat capacity dominates the overall heat capacity of the fan-out package. This heat retention leads to a rise in steady-state temperature, hindering continuous heat dissipation from the fan-out package.

[0004] Therefore, how to propose a fan-out package integrated heat dissipation structure to improve the heat dissipation effect of the fan-out package has become an important issue that needs to be addressed in this field. Summary of the Invention

[0005] To address the problems in the prior art, embodiments of the present invention provide a fan-out packaged integrated heat dissipation structure and its preparation method, which can at least partially solve the problems existing in the prior art.

[0006] In a first aspect, the present invention proposes a fan-out packaged integrated heat dissipation structure, including a fan-out packaged structure, a first dielectric-thermal interface material layer disposed on the fan-out packaged structure, and a heat sink or heat spreader disposed on the first dielectric-thermal interface material layer; wherein, the chip included in the fan-out packaged structure is in contact with the first dielectric-thermal interface material layer, and the thickness of the first dielectric-thermal interface material layer is less than 100 micrometers.

[0007] Furthermore, the fan-out type packaged integrated heat dissipation structure provided in the embodiments of the present invention further includes: when a heat spreader is provided on the dielectric-thermal interface material layer, a second dielectric-thermal interface material layer is provided on the heat spreader, and a heat sink is provided on the second dielectric-thermal interface material layer.

[0008] Furthermore, the fan-out package structure includes a chip embedding layer, a redistribution layer, and a solder ball layer. The chip embedding layer includes at least one chip and a mold for embedding the at least one chip, and the solder ball layer includes a plurality of solder balls.

[0009] Furthermore, the chip embedding layer includes multiple chips with different heights. An auxiliary layer is provided on the chip with the lower height to make the physical height of each chip consistent. A third dielectric-thermal interface material layer is provided between at least one chip with a lower height and the corresponding auxiliary layer.

[0010] Furthermore, the first dielectric-thermal interface material layer adopts an interface material with dielectric insulation properties and thermal conductivity.

[0011] Secondly, this invention proposes a method for fabricating a fan-out type packaged integrated heat dissipation structure, comprising:

[0012] A fan-out package structure is prepared; wherein, during the preparation of the fan-out package structure, a first dielectric-thermal interface material layer is formed on the chip of the fan-out package structure, and a heat sink or heat spreader is disposed on the first dielectric-thermal interface material layer.

[0013] Furthermore, the fabrication of the fan-out package structure includes:

[0014] Each chip is bonded to a temporary carrier board with its front side facing up.

[0015] The chip on the temporary carrier is molded and packaged to obtain a first intermediate structure;

[0016] The first intermediate structure is debonded to remove the temporary carrier board, thereby obtaining a molded packaged chip structure;

[0017] A first dielectric material is deposited on an auxiliary carrier to obtain an auxiliary bonding assembly; and a second dielectric material is deposited on the surface of the molded packaged chip structure on the side exposed on the back of the chip to obtain a molded packaged chip bonding assembly; wherein the auxiliary carrier is a heat sink or a heat spreader.

[0018] The auxiliary bonding component is melt-bonded to the molded package chip bonding component to obtain a second intermediate structure; wherein, the second intermediate structure includes a first dielectric-thermal interface material layer;

[0019] Based on the second intermediate structure, a redistribution layer and a solder ball layer are formed sequentially to obtain a fan-out package structure.

[0020] Furthermore, the fabrication of the fan-out package structure includes:

[0021] Each chip is bonded face down onto a temporary carrier board;

[0022] The chip on the temporary carrier is molded and packaged to obtain a third intermediate structure;

[0023] The overmolded third intermediate structure is ground to expose the back side of each chip, thus obtaining the fourth intermediate structure;

[0024] A first dielectric material is deposited on an auxiliary carrier to obtain an auxiliary bonding assembly; and a second dielectric material is deposited on the exposed back surface of the fourth intermediate structure to obtain a chip bonding assembly; wherein the auxiliary carrier is a heat sink or a heat spreader.

[0025] The auxiliary bonding component is fused to the chip bonding component to obtain a fifth intermediate structure; wherein, the fifth intermediate structure includes a first dielectric-thermal interface material layer;

[0026] The fifth intermediate structure is debonded to remove the temporary carrier plate, thereby obtaining the sixth intermediate structure;

[0027] Based on the sixth intermediate structure, a redistribution layer and a solder ball layer are formed sequentially to obtain a fan-out package structure.

[0028] Furthermore, if the multiple chips bonded to the temporary carrier have different heights, the process further includes the following steps before molding and packaging the chips on the temporary carrier:

[0029] A third dielectric material is deposited on a chip with a relatively low height, and a fourth dielectric material is deposited on the corresponding auxiliary layer;

[0030] Chips with lower heights due to the deposition of the third dielectric material are fused and bonded to the corresponding auxiliary layer with the deposition of the fourth dielectric material, so that the physical heights of each chip are consistent.

[0031] Furthermore, the fabrication of the fan-out package structure includes:

[0032] A fifth dielectric material is deposited on the back side of each chip, and a sixth dielectric material is deposited on an auxiliary carrier; wherein the auxiliary carrier is a heat sink or a heat spreader.

[0033] A chip with a fifth dielectric material deposited is fused and bonded to an auxiliary carrier plate with a sixth dielectric material deposited to obtain a seventh intermediate structure; wherein, the seventh intermediate structure includes a first dielectric-thermal interface material layer;

[0034] The chip on the seventh intermediate structure is molded and packaged to obtain the eighth intermediate structure;

[0035] The overmolded eighth intermediate structure is ground to expose the front side of each chip, thus obtaining the ninth intermediate structure;

[0036] Based on the ninth intermediate structure, a redistribution layer and a solder ball layer are formed sequentially to obtain a fan-out package structure.

[0037] Furthermore, after integrating the heat sink on the first dielectric-thermal interface material layer, further integration of the heat sink includes:

[0038] A seventh dielectric material is deposited on the heat sink, and an eighth dielectric material is deposited on the heat spreader.

[0039] The heat sink with the seventh dielectric material is fused together with the heat spreader with the eighth dielectric material.

[0040] The fan-out packaged integrated heat dissipation structure and its preparation method provided by the present invention include a fan-out packaged structure, a first dielectric-thermal interface material layer disposed on the fan-out packaged structure, and a heat sink or heat spreader disposed on the first dielectric-thermal interface material layer; wherein, the chip included in the fan-out packaged structure is in contact with the first dielectric-thermal interface material layer, and the thickness of the first dielectric-thermal interface material layer is less than 100 micrometers. Since the first dielectric-thermal interface material layer is in direct contact with the chip and is relatively thin, the heat dissipation effect of the fan-out packaged structure is improved. Attached Figure Description

[0041] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. In the drawings:

[0042] Figure 1 This is a schematic diagram of a fan-out type packaged integrated heat dissipation structure provided in an embodiment of the present invention.

[0043] Figure 2 This is a schematic diagram of a fan-out type packaged integrated heat dissipation structure provided in another embodiment of the present invention.

[0044] Figure 3 This is a schematic diagram of a fan-out packaged integrated heat dissipation structure provided in another embodiment of the present invention.

[0045] Figure 4This is a schematic diagram of a fan-out packaged integrated heat dissipation structure provided in another embodiment of the present invention.

[0046] Figure 5 This is a schematic flowchart of a method for preparing a fan-out packaged integrated heat dissipation structure according to an embodiment of the present invention.

[0047] Figure 6 This is a schematic diagram of the process for preparing a fan-out packaging structure according to an embodiment of the present invention.

[0048] Figure 7 This is a schematic diagram of the process for preparing a fan-out packaging structure according to another embodiment of the present invention.

[0049] Figure 8 This is a schematic diagram of the process for preparing a fan-out packaging structure according to another embodiment of the present invention.

[0050] Figure 9 This is a schematic diagram of the process for preparing a fan-out packaging structure according to another embodiment of the present invention.

[0051] Figure 10 This is a schematic flowchart of a method for preparing a fan-out type packaged integrated heat dissipation structure according to another embodiment of the present invention.

[0052] Figure 11A This is a schematic diagram of the structure of a chip and a temporary carrier board after bonding, according to an embodiment of the present invention.

[0053] Figure 11B This is a schematic diagram of the molded and packaged structure provided in an embodiment of the present invention.

[0054] Figure 11C This is a schematic diagram of the debonded structure provided in an embodiment of the present invention.

[0055] Figure 11D This is a schematic diagram of the structure of a molded packaged chip bonding assembly provided in an embodiment of the present invention.

[0056] Figure 11E This is a schematic diagram of the structure of an auxiliary bonding component provided in an embodiment of the present invention.

[0057] Figure 11F This is a schematic diagram of the second intermediate structure provided in an embodiment of the present invention.

[0058] Figure 11G This is a schematic diagram of the structure after grinding according to an embodiment of the present invention.

[0059] Figure 11H This is a schematic diagram of the structure after forming a redistribution layer according to an embodiment of the present invention.

[0060] Figure 11IThis is a schematic diagram of the structure after forming a solder ball layer according to an embodiment of the present invention.

[0061] Figure 12A This is a schematic diagram of the structure of a chip and a temporary carrier board after bonding, according to an embodiment of the present invention.

[0062] Figure 12B This is a schematic diagram of the molded and packaged structure provided in an embodiment of the present invention.

[0063] Figure 12C This is a schematic diagram of the fourth intermediate structure provided in an embodiment of the present invention.

[0064] Figure 12D This is a schematic diagram of the structure of a chip bonding assembly provided in an embodiment of the present invention.

[0065] Figure 12E This is a schematic diagram of the structure of an auxiliary bonding component provided in an embodiment of the present invention.

[0066] Figure 12F This is a schematic diagram of the fifth intermediate structure provided in an embodiment of the present invention.

[0067] Figure 12G This is a schematic diagram of the sixth intermediate structure provided in an embodiment of the present invention.

[0068] Figure 12H This is a schematic diagram of the structure after forming a redistribution layer according to an embodiment of the present invention.

[0069] Figure 12I This is a schematic diagram of the structure after forming a solder ball layer according to an embodiment of the present invention.

[0070] Figure 13A This is a schematic diagram of the seventh intermediate structure provided in an embodiment of the present invention.

[0071] Figure 13B This is a schematic diagram of the eighth intermediate structure provided in an embodiment of the present invention.

[0072] Figure 13C This is a schematic diagram of the ninth intermediate structure provided in an embodiment of the present invention.

[0073] Figure 13D This is a schematic diagram of the structure after forming a redistribution layer according to an embodiment of the present invention.

[0074] Figure 13E This is a schematic diagram of the structure after forming a solder ball layer according to an embodiment of the present invention. Detailed Implementation

[0075] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the embodiments of the present invention will be further described in detail below with reference to the accompanying drawings. Here, the illustrative embodiments and their descriptions are used to explain the present invention, but are not intended to limit the present invention. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this application can be arbitrarily combined with each other. The acquisition, storage, use, and processing of data in the technical solutions of this application all comply with relevant laws and regulations. The user information in the embodiments of this application is obtained through legal and compliant means, and the acquisition, storage, use, and processing of user information have been authorized and agreed upon by the customer.

[0076] To facilitate understanding of the technical solution provided in this application, the relevant content of the technical solution in this application will be explained below.

[0077] As advanced system integration demands more functionalities, fan-out packaging technology is evolving towards higher density. Its applications have expanded from single-chip packaging to multi-chip heterogeneous integration, and from initially focusing primarily on low-power devices to gradually extending to high-power devices. With the development and evolution of fan-out packaging technology, its power consumption (or power density) has increased accordingly. This increase in power consumption leads to a sharp rise in junction temperature, posing a risk of reduced system performance and compromised component reliability.

[0078] In multi-chip, high-density integrated fan-out package heat dissipation, heat is difficult to dissipate from the fan-out package due to the lack of a heat dissipation path with lower thermal resistance, and the low thermal conductivity of the overmolded film becomes a bottleneck for the package's heat dissipation performance. Therefore, this invention provides a fan-out package integrated heat dissipation structure that removes the overmolded film and incorporates a dielectric-thermal interface material with good dielectric insulation and thermal conductivity on the fan-out package structure to improve its heat dissipation capability. Furthermore, it is applicable to scenarios where certain chips are prohibited from being electrically connected to the heat sink, expanding the applicability of the fan-out package integrated heat dissipation structure.

[0079] Figure 1 This is a schematic diagram of a fan-out packaged integrated heat dissipation structure provided in an embodiment of the present invention, as shown below. Figure 1 As shown, the fan-out packaged integrated heat dissipation structure provided in this embodiment of the invention includes a fan-out packaged structure 1, a first dielectric-thermal interface material layer 2 disposed on the fan-out packaged structure 1, and a heat sink 3 disposed on the first dielectric-thermal interface material layer 2; wherein, the chip 101-1 included in the fan-out packaged structure 1 is in contact with the first dielectric-thermal interface material layer 2, and the thickness of the first dielectric-thermal interface material layer 2 is less than 100 micrometers.

[0080] Specifically, the fan-out package structure 1 includes a chip 101-1. To better dissipate heat from the chip 101-1, the back side of the chip 101-1 contacts a first dielectric-thermal interface material layer 2. The use of the first dielectric-thermal interface material layer 2 between the chip 101-1 and the heat sink 3 reduces interface thermal resistance and package thermal capacity, enhances heat dissipation along the top path of the chip 101-1, and meets the increased power density and heat flux density requirements for heat dissipation performance. The thickness of the first dielectric-thermal interface material layer 2 is less than 100 micrometers, which provides better thermal conductivity. The first dielectric-thermal interface material layer 2 can be made of a dielectric-thermal interface material, such as SiO2, SiN, SiCN, Al2O3, AlN, or a combination of multiple inorganic dielectric materials. Compared to molding, dielectric-thermal interface materials have lower specific heat capacity, bonding thickness down to the micrometer level, and some dielectric-thermal interface materials have higher thermal conductivity, resulting in better heat dissipation. The heat sink 3 can be made of semiconductor materials such as Si, inorganic non-metallic materials with high thermal conductivity such as diamond, or metallic materials such as Al and Cu. The heat sink 3 can be further fabricated with microchannels or other heat dissipation configurations to enhance heat dissipation.

[0081] Figure 2 This is a schematic diagram of a fan-out packaged integrated heat dissipation structure provided in an embodiment of the present invention, as shown below. Figure 2 As shown, the fan-out packaged integrated heat dissipation structure provided in this embodiment of the invention includes a fan-out packaged structure 1, a first dielectric-thermal interface material layer 2 disposed on the fan-out packaged structure 1, and a heat spreader 4 disposed on the first dielectric-thermal interface material layer 2; wherein, the chip included in the fan-out packaged structure 1 is in contact with the first dielectric-thermal interface material layer 2, and the thickness of the first dielectric-thermal interface material layer 2 is less than 100 micrometers.

[0082] Specifically, the fan-out package structure 1 includes a chip 101-1. To better dissipate heat from the chip 101-1, the back side of the chip 101-1 contacts a first dielectric-thermal interface material layer 2. The use of the first dielectric-thermal interface material layer 2 between the chip 101-1 and the heat sink 4 reduces interface thermal resistance and package thermal capacity, enhances heat dissipation along the top path of the chip 101-1, and meets the increased power density and heat flux density requirements for heat dissipation performance. The thickness of the first dielectric-thermal interface material layer 2 is less than 100 micrometers, which provides better thermal conductivity. The first dielectric-thermal interface material layer 2 can be made of a dielectric-thermal interface material, such as SiO2, SiN, SiCN, Al2O3, AlN, or a combination of multiple inorganic dielectric materials. Compared to molding, dielectric-thermal interface materials have lower specific heat capacity, bonding thickness down to the micrometer level, and some dielectric-thermal interface materials have higher thermal conductivity, resulting in better heat dissipation. The vapor chamber 4 can be made of semiconductor materials such as Si, inorganic non-metallic materials with high thermal conductivity such as diamond, or metallic materials such as Al and Cu. The vapor chamber has a high thermal conductivity and low diffusion thermal resistance, which facilitates rapid lateral and longitudinal heat diffusion, so it can make full use of the heat dissipation space outside the package.

[0083] The fan-out package integrated heat dissipation structure provided in this embodiment of the invention includes a fan-out package structure, a first dielectric-thermal interface material layer disposed on the fan-out package structure, and a heat sink or heat spreader disposed on the first dielectric-thermal interface material layer; wherein, the chip included in the fan-out package structure is in contact with the first dielectric-thermal interface material layer, and the thickness of the first dielectric-thermal interface material layer is less than 100 micrometers. Since the first dielectric-thermal interface material layer is in direct contact with the chip and is relatively thin, the heat dissipation effect of the fan-out package structure is improved.

[0084] Figure 3 This is a schematic diagram of a fan-out packaged integrated heat dissipation structure provided in another embodiment of the present invention, as shown below. Figure 3 As shown, based on the above embodiments, the fan-out packaged integrated heat dissipation structure provided in this embodiment further includes: when a heat spreader 4 is disposed on the heat spreader 2, a second heat spreader 5 is disposed on the heat spreader 4, and a heat sink 3 is disposed on the second heat spreader 5. The second heat spreader 5 can be made of a heat spreader 4.

[0085] like Figure 1 ,like Figure 2 and Figure 3As shown, based on the above embodiments, the fan-out package structure 1 further includes a chip embedding layer 101, a redistribution layer (RDL) 102 and a solder ball layer 103. The chip embedding layer 101 includes at least one chip 101-1 and a mold 101-2 embedded in the at least one chip 101-1. The solder ball layer 103 includes a plurality of solder balls 103-1.

[0086] Specifically, at least one chip 101-1 is encapsulated within the molding 101-2 of the chip embedding layer 101. The molding 101-2 may be made of epoxy molding compound (EMC). The number of chips 101-1 is set according to actual needs, and is not limited in this embodiment of the invention.

[0087] For example, the chip embedding layer 101, the redistribution layer 102, and the solder ball layer 103 are stacked in sequence.

[0088] Figure 4 This is a schematic diagram of a fan-out packaged integrated heat dissipation structure provided in another embodiment of the present invention, as shown below. Figure 4 As shown, based on the above embodiments, the chip embedding layer 101 further includes a plurality of chips 101-1, and the plurality of chips 101-1 have different heights. An auxiliary layer 101-4 is provided on the chip 101-1 with a lower height so that the physical height of each chip is consistent. A third dielectric-thermal interface material layer 101-3 is provided between at least one chip 101-1 with a lower height and the corresponding auxiliary layer 101-4.

[0089] Specifically, the auxiliary layer 101-4 can be made of materials such as structural silicon or diamond. The auxiliary layer 101-4 is bonded to the chip 101-1 via a dielectric-thermal interface material to form a third dielectric-thermal interface material layer 101-3. Through the auxiliary layer 101-4 and the third dielectric-thermal interface material layer 101-3, the physical height of each chip 101-1 is made consistent, providing better structural support. The third dielectric-thermal interface material layer 101-3 can enhance the heat dissipation of the corresponding chip 101-1. For a chip 101-1 with the third dielectric-thermal interface material layer 101-3, the physical height of the chip 101-1 is the sum of the height of the chip 101-1, the height of the third dielectric-thermal interface material layer 101-3, and the height of the auxiliary layer 101-4. For a chip 101-1 without the third dielectric-thermal interface material layer 101-3, the physical height of the chip 101-1 is the same as the chip 101-1's height.

[0090] Based on the above embodiments, the first dielectric-thermal interface material layer 2 further adopts an interface material with dielectric insulation and thermal conductivity. For example, inorganic dielectric materials such as SiO2, SiN, SiCN, Al2O3, and AlN, or a combination of multiple inorganic dielectric materials.

[0091] Figure 5 This is a schematic flowchart of a method for fabricating a fan-out packaged integrated heat dissipation structure according to an embodiment of the present invention, as shown below. Figure 5 As shown, the method for fabricating a fan-out type packaged integrated heat dissipation structure provided in this embodiment of the invention includes:

[0092] S501. Prepare a fan-out package structure; wherein, during the preparation of the fan-out package structure, a first dielectric-thermal interface material layer is formed on the chip of the fan-out package structure, and a heat sink or heat spreader is disposed on the first dielectric-thermal interface material layer.

[0093] Specifically, the existing fan-out packaging structure fabrication process includes temporarily bonding the chip to a temporary carrier, molding and encapsulating, removing the temporary carrier, fabricating a redistribution layer, and ball-mounting. In the fabrication of the fan-out packaging structure in this application, a dielectric-thermal interface material is bonded to the chip as the first dielectric-thermal interface material layer, allowing direct contact between the chip and the first dielectric-thermal interface material layer for better heat dissipation. Simultaneously, a heat sink or vapor chamber is integrated on the first dielectric-thermal interface material layer. The first dielectric-thermal interface material layer 2 can be a dielectric-thermal interface material, such as SiO2, SiN, SiCN, Al2O3, AlN, or a combination of multiple inorganic dielectric materials. The first dielectric-thermal interface material layer reduces interface thermal resistance and package thermal capacity. The heat sink can be made of semiconductor materials such as Si, inorganic non-metallic materials with high thermal conductivity such as diamond, or metallic materials such as Al or Cu. The heat spreader 4 can be made of semiconductor materials such as Si, inorganic non-metallic materials with high thermal conductivity such as diamond, or metallic materials such as Al and Cu.

[0094] The present invention provides a method for fabricating a fan-out package integrated heat dissipation structure. During the fabrication of the fan-out package structure, a first dielectric-thermal interface material layer is formed on the chip of the fan-out package structure, and a heat sink or heat spreader is disposed on the first dielectric-thermal interface material layer. Because the first dielectric-thermal interface material layer is in direct contact with the chip, the heat spreader can reduce interface thermal resistance and package thermal capacity, enhance top-path heat dissipation of the fan-out package structure, and improve the heat dissipation effect of the integrated heat dissipation structure. Furthermore, the heat sink or heat spreader can be integrated during the fabrication of the fan-out package structure, eliminating the need to integrate it separately after the fan-out package structure is completed, thus reducing fabrication processes and manufacturing costs.

[0095] Figure 6 This is a schematic diagram of the process for fabricating a fan-out packaging structure according to an embodiment of the present invention, as shown below. Figure 6 As shown, based on the above embodiments, the preparation of the fan-out packaging structure further includes:

[0096] S601. Attach each chip face up onto a temporary carrier board;

[0097] Specifically, each chip is placed face-up and bonded to a temporary carrier using bonding adhesive. After bonding, the back side of each chip faces the temporary carrier.

[0098] S602. Mold and package the chip on the temporary carrier to obtain a first intermediate structure;

[0099] Specifically, a temporary carrier board for bonding the chips is placed in a mold and compressed using epoxy molding compound. EMC fills all the gaps between the chips and completely encapsulates them. After heating and curing, the first intermediate structure is obtained.

[0100] S603. Debond the first intermediate structure to remove the temporary carrier board and obtain a molded packaged chip structure;

[0101] Specifically, the first intermediate structure is debonded, and the temporary carrier is removed from the first intermediate structure to expose the back side of each chip, resulting in a molded package chip structure made of molding compound with the chips embedded therein. The debonding can be achieved using methods such as laser, thermal sliding, or chemical solvents, selected according to actual needs; this embodiment of the invention does not impose any limitations.

[0102] S604. A first dielectric material is deposited on an auxiliary carrier to obtain an auxiliary bonding assembly; and a second dielectric material is deposited on the surface of the molded packaged chip structure on the side exposed on the back of the chip to obtain a molded packaged chip bonding assembly; wherein, the auxiliary carrier is a heat sink or a heat spreader.

[0103] Specifically, a first dielectric material is deposited on an auxiliary carrier to obtain an auxiliary bonding assembly. A second dielectric material is deposited on the exposed back surface of the molded packaged chip structure to obtain the molded packaged chip bonding assembly. The first dielectric material can be an inorganic dielectric material such as SiO2, SiN, SiCN, Al2O3, or AlN; the second dielectric material can also be an inorganic dielectric material such as SiO2, SiN, SiCN, Al2O3, or AlN. The first and second dielectric materials can be the same or different. The auxiliary carrier can be a heat sink or a vapor chamber.

[0104] S605. The auxiliary bonding component is melt-bonded to the molded package chip bonding component to obtain a second intermediate structure; wherein, the second intermediate structure includes a first dielectric-thermal interface material layer;

[0105] Specifically, the side of the auxiliary bonding component deposited with the first dielectric material is fused together with the side of the molding package chip bonding component deposited with the second dielectric material to obtain a second intermediate structure. The fused-bonded first and second dielectric materials form a first dielectric-thermal interface material layer. Because the first dielectric-thermal interface material layer is formed by fusion bonding, it can be made relatively thin, which is beneficial for chip heat dissipation.

[0106] For example, a 2μm thick SiO2 dielectric material is deposited on one side of the exposed back surface of the molded package chip structure to obtain a molded package chip bonding assembly. A 1μm thick SiN dielectric material is deposited on the silicon wafer to obtain an auxiliary bonding assembly. The molded package chip bonding assembly and the auxiliary bonding assembly are fused together to form a first dielectric-thermal interface material layer between one side of the back surface of the molded package chip structure and the silicon wafer, resulting in a second intermediate structure.

[0107] S606. Based on the second intermediate structure, a redistribution layer and a solder ball layer are formed in sequence to obtain a fan-out package structure.

[0108] Specifically, after obtaining the second intermediate structure, the overmolded second intermediate structure is ground to expose the pads of each chip. Then, a redistribution layer is formed on one side of the exposed chip pads of the second intermediate structure. Multiple solder balls are fabricated on the surface of the redistribution layer to form a solder ball layer. After slicing and removing the auxiliary carrier board, a fan-out package structure is obtained.

[0109] Figure 7 This is a schematic diagram of the process for preparing a fan-out packaging structure according to another embodiment of the present invention, as shown below. Figure 7 As shown, based on the above embodiments, the preparation of the fan-out packaging structure further includes:

[0110] S701. Attach each chip face down onto a temporary carrier board;

[0111] Specifically, each chip is placed face-down and bonded to a temporary carrier using bonding adhesive. After bonding, the front side of each chip faces the temporary carrier.

[0112] S702. Mold and package the chip on the temporary carrier to obtain a third intermediate structure;

[0113] Specifically, a temporary carrier board for bonding the chips is placed in a mold and compressed using epoxy molding compound. EMC fills all the gaps between the chips and completely encapsulates them. After heating and curing, a third intermediate structure is obtained.

[0114] S703. Grind the overmolded third intermediate structure to expose the back side of each chip, thereby obtaining the fourth intermediate structure;

[0115] Specifically, the overmolded third intermediate structure is ground to expose the back side of each chip, thus obtaining the fourth intermediate structure.

[0116] S704. A first dielectric material is deposited on an auxiliary carrier to obtain an auxiliary bonding assembly; and a second dielectric material is deposited on the exposed back side of the fourth intermediate structure to obtain a chip bonding assembly; wherein, the auxiliary carrier is a heat sink or a heat spreader.

[0117] Specifically, a first dielectric material is deposited on an auxiliary carrier to obtain an auxiliary bonding assembly. A second dielectric material is deposited on the exposed back surface of the fourth intermediate structure to obtain a chip bonding assembly. The first dielectric material can be an inorganic dielectric material such as SiO2, SiN, SiCN, Al2O3, or AlN; the second dielectric material can also be an inorganic dielectric material such as SiO2, SiN, SiCN, Al2O3, or AlN. The first and second dielectric materials can be the same or different. The auxiliary carrier can be a heat sink or a heat spreader. S705, the auxiliary bonding assembly is fused to the chip bonding assembly to obtain a fifth intermediate structure; wherein the fifth intermediate structure includes a first dielectric-thermal interface material layer.

[0118] Specifically, the side of the auxiliary bonding component deposited with the first dielectric material is fused together with the side of the chip bonding component deposited with the second dielectric material to obtain the fifth intermediate structure. The fused-bonded first and second dielectric materials form a first dielectric-thermal interface material layer. Because the first dielectric-thermal interface material layer is formed by fusion bonding, it can be made relatively thin, which is beneficial for chip heat dissipation.

[0119] S706. Debond the fifth intermediate structure to remove the temporary carrier plate and obtain the sixth intermediate structure;

[0120] Specifically, the fifth intermediate structure is debonded, and the temporary carrier is removed from the fifth intermediate structure to expose the front side of each chip, resulting in a sixth intermediate structure. The sixth intermediate structure includes a chip embedding layer, a first dielectric-thermal interface material layer, and an auxiliary carrier layer stacked sequentially. The debonding can be achieved using methods such as laser, thermal sliding, or chemical solvents, selected according to actual needs; this embodiment of the invention does not impose any limitations.

[0121] S707. Based on the sixth intermediate structure, a redistribution layer and a solder ball layer are formed in sequence to obtain a fan-out package structure.

[0122] Specifically, after obtaining the sixth intermediate structure, a redistribution layer is formed on one side of the exposed chip pad of the second intermediate structure. Multiple solder balls are fabricated on the surface of the redistribution layer to form a solder ball layer. After slicing and removing the auxiliary carrier board, a fan-out package structure is obtained.

[0123] Figure 8 This is a schematic diagram of the process for fabricating a fan-out packaging structure according to another embodiment of the present invention, as shown below. Figure 8 As shown, based on the above embodiments, further, if the heights of the multiple chips bonded to the temporary carrier are different, the following steps are included before molding and packaging the chips on the temporary carrier:

[0124] S801, Deposit a third dielectric material on the chip with a lower height, and deposit a fourth dielectric material on the corresponding auxiliary layer;

[0125] Specifically, if multiple chips are bonded to a temporary carrier with different heights, a third dielectric material can be deposited on the chip with the lower height, and a fourth dielectric material can be deposited on the auxiliary layer corresponding to the chip with the lower height. The third dielectric material can be an inorganic dielectric material such as SiO2, SiN, SiCN, Al2O3, or AlN; the fourth dielectric material can also be an inorganic dielectric material such as SiO2, SiN, SiCN, Al2O3, or AlN. The third and fourth dielectric materials can be the same or different. The auxiliary layer can be made of materials such as structural silicon or diamond, selected according to actual needs; this embodiment of the invention does not impose limitations.

[0126] S802, The chip with a lower height of the deposited third dielectric material is fused and bonded to the corresponding auxiliary layer of the deposited fourth dielectric material to make the physical height of each chip consistent.

[0127] Specifically, a chip with a lower height due to the deposition of the third dielectric material is fused to a corresponding auxiliary layer with a deposition of the fourth dielectric material using the third and fourth dielectric materials. After fusion bonding, the physical heights of all chips are consistent. A third dielectric-thermal interface material layer is formed between the lower-height chip and the corresponding auxiliary layer. For chips without an auxiliary layer, the physical height of the chip is simply the chip's own height. For chips with an auxiliary layer, the physical height of the chip is the sum of the chip's height, the height of the third dielectric-thermal interface material layer, and the height of the auxiliary layer.

[0128] By stacking a third dielectric-thermal interface material layer and an auxiliary layer on relatively low-height chips, the back of the chips is prevented from being molded. This allows heat generated by the chips to be transferred to the first dielectric-thermal interface material layer through the third dielectric-thermal interface material layer and the auxiliary layer, which is beneficial for chip heat dissipation. The uniform physical height of each chip provides better structural support for the structures on the chip.

[0129] Figure 9 This is a schematic diagram of the process for fabricating a fan-out packaging structure according to another embodiment of the present invention, as shown below. Figure 9 As shown, based on the above embodiments, the preparation of the fan-out packaging structure further includes:

[0130] S901. A fifth dielectric material is deposited on the back side of each chip, and a sixth dielectric material is deposited on an auxiliary carrier; wherein, the auxiliary carrier is a heat sink or a heat spreader.

[0131] Specifically, a fifth dielectric material is deposited on the back side of each chip, and a sixth dielectric material is deposited on an auxiliary carrier. The fifth dielectric material can be an inorganic dielectric material such as SiO2, SiN, SiCN, Al2O3, or AlN; the sixth dielectric material can also be an inorganic dielectric material such as SiO2, SiN, SiCN, Al2O3, or AlN. The fifth and sixth dielectric materials can be the same or different. The auxiliary carrier is a heat sink or a vapor chamber.

[0132] S902. The chip with the fifth dielectric material deposited is fused and bonded to the auxiliary carrier plate with the sixth dielectric material deposited to obtain a seventh intermediate structure; wherein, the seventh intermediate structure includes a first dielectric-thermal interface material layer;

[0133] Specifically, a chip with a fifth dielectric material deposited is fused to an auxiliary carrier with a sixth dielectric material deposited, and the fifth and sixth dielectric materials are then fused together to obtain a seventh intermediate structure. After fusion bonding, the fifth and sixth dielectric materials form a first dielectric-thermal interface material layer.

[0134] S903. Mold and package the chip on the seventh intermediate structure to obtain the eighth intermediate structure;

[0135] Specifically, the seventh intermediate structure of the bonded chip is placed in a mold and compressed using epoxy molding compound. EMC fills all the gaps between the chips and completely encapsulates them. After heating and curing, the eighth intermediate structure is obtained.

[0136] S904. Grind the overmolded material of the eighth intermediate structure to expose the front side of each chip, thereby obtaining the ninth intermediate structure;

[0137] Specifically, the overmolded eighth intermediate structure is ground to expose the front side of each chip, thus obtaining the ninth intermediate structure.

[0138] S905. Based on the ninth intermediate structure, a redistribution layer and a solder ball layer are formed sequentially to obtain a fan-out package structure.

[0139] Specifically, after obtaining the ninth intermediate structure, a redistribution layer is formed on one side of the exposed chip pad of the ninth intermediate structure. Multiple solder balls are fabricated on the surface of the redistribution layer to form a solder ball layer. After slicing, a fan-out package structure is obtained.

[0140] Figure 10 This is a schematic flowchart of a method for fabricating a fan-out packaged integrated heat dissipation structure according to another embodiment of the present invention, as shown below. Figure 10 As shown, based on the above embodiments, further integrating the heat sink after integrating it on the first dielectric-thermal interface material layer includes:

[0141] S1001. Deposit a seventh dielectric material on the heat sink and deposit an eighth dielectric material on the heat spreader.

[0142] Specifically, in the process of fabricating the fan-out package structure, a heat sink is integrated on the first dielectric-thermal interface material layer. An eighth dielectric material is deposited on the heat sink, and a seventh dielectric material is deposited on the heat sink. The seventh dielectric material can be an inorganic dielectric material such as SiO2, SiN, SiCN, Al2O3, or AlN; the eighth dielectric material can also be an inorganic dielectric material such as SiO2, SiN, SiCN, Al2O3, or AlN. The seventh and eighth dielectric materials can be the same or different.

[0143] S1002, The heat sink with the seventh dielectric material is fused together with the heat spreader with the eighth dielectric material.

[0144] Specifically, a heat sink with a seventh dielectric material deposited and a heat spreader with an eighth dielectric material deposited are fused together by the seventh dielectric material and the eighth dielectric material. After fusion bonding, the seventh dielectric material and the eighth dielectric material form a second dielectric-thermal interface material layer.

[0145] The following specific embodiment illustrates the detailed implementation process of fabricating a fan-out packaging structure.

[0146] Step 1: Bond the chip onto the temporary carrier board. Using bonding adhesive 1103, bond the chip 1101 onto the temporary carrier board 1102, as follows: Figure 11A As shown. Among them, the front of chip 1101 is facing upwards.

[0147] The second step is to mold and encapsulate the chip. A temporary carrier board 1102 for bonding the chip 1101 is placed in a mold, and epoxy molding compound 1104 is used for compression molding. The epoxy molding compound 1104 fills all the gaps between the chips 1101 and completely encapsulates them. After heat curing, the first intermediate structure 11-1 is obtained, as shown below. Figure 11B As shown.

[0148] The third step is to debond the first intermediate structure. The first intermediate structure 11-1 is debonded, and the temporary carrier 1102 is removed from it, exposing the back side of each chip 1101, resulting in the molded packaged chip structure 11-2, as shown below. Figure 11C As shown.

[0149] Step 4: Deposit the second dielectric material. A second dielectric material 1105 is deposited on the exposed back surface of the molded package chip structure 11-2 to obtain the molded package chip bonding assembly 11-3, as shown below. Figure 11D As shown.

[0150] Step 5: Deposit the first dielectric material. The first dielectric material 1107 is deposited on the auxiliary carrier 1106 to obtain the auxiliary bonding assembly 11-4, as shown below. Figure 11E As shown.

[0151] Step 6: Melt bonding of auxiliary bonding components and molded packaged chip bonding components. The auxiliary bonding component 11-4 is deposited on one side of the first dielectric material 1107, opposite to the side of the molded packaged chip bonding component 11-3 deposited with the second dielectric material 1105. Melt bonding is then performed to obtain the second intermediate structure 11-5. After the first dielectric material 1107 and the second dielectric material 1105 are melt-bonded, a first dielectric-thermal interface material layer 1108 is formed, as shown below. Figure 11F As shown.

[0152] Step 7: Grinding the second intermediate structure. Grind the overmolded second intermediate structure 11-5 to expose the pads of each chip 1101, as shown below. Figure 11G As shown.

[0153] Step 8: Forming the redistribution layer. A redistribution layer 1109 is formed on one side of the surface of the exposed pads of chip 1101, as shown below. Figure 11H As shown.

[0154] Step 9: Forming the solder ball layer. Multiple solder balls 1110 are fabricated on the surface of the redistribution layer 1109 to form a solder ball layer, as shown below. Figure 11I As shown.

[0155] Step 10: After slicing and removing the auxiliary carrier board, a fan-out package structure can be obtained.

[0156] The following describes the specific implementation process of fabricating a fan-out packaging structure using another specific embodiment.

[0157] Step 1: Bond the chip onto the temporary carrier board. Using bonding adhesive 1203, bond the chip 1201 onto the temporary carrier board 1202, as follows: Figure 12A As shown. In this case, the reverse side of chip 1201 is facing upwards.

[0158] The second step is to mold and encapsulate the chip. A temporary carrier board 1202 for bonding the chip 1201 is placed in a mold, and epoxy molding compound 1204 is used for compression molding. The epoxy molding compound 1204 fills all the gaps between the chips 1201 and completely encapsulates them. After heat curing, the third intermediate structure 12-1 is obtained, as shown below. Figure 12B As shown.

[0159] The third step is to grind the third intermediate structure. The overmolded third intermediate structure 12-1 is then ground to expose the back of each chip, resulting in the fourth intermediate structure 12-2, as shown below. Figure 12C As shown.

[0160] Step 4: Deposit the second dielectric material. Deposit the second dielectric material 1205 on the exposed back surface of the fourth intermediate structure 12-2 to obtain the chip bonding assembly 12-3, as shown below. Figure 12D As shown.

[0161] Step 5: Deposit the first dielectric material. The first dielectric material 1207 is deposited on the auxiliary carrier plate 1206 to obtain the auxiliary bonding assembly 12-4, as shown below. Figure 12E As shown.

[0162] Step 6: Melt bonding of auxiliary bonding components and chip bonding components. The auxiliary bonding component 12-4 is deposited on one side of the first dielectric material 1207, opposite to the chip bonding component 12-3 on the side of the second dielectric material 1205, and melt-bonded to obtain the fifth intermediate structure 12-5. After the first dielectric material 1207 and the second dielectric material 1205 are melt-bonded, a first dielectric-thermal interface material layer 1208 is formed, as shown below. Figure 12F As shown.

[0163] Step 7: Debond the fifth intermediate structure. Debond the fifth intermediate structure 12-5, remove the temporary carrier 1202 from the fifth intermediate structure 12-5, exposing the back side of each chip 1201, to obtain the sixth intermediate structure 11-6, as shown below. Figure 12G As shown.

[0164] Step 8: Forming the redistribution layer. A redistribution layer 1209 is formed on one side of the surface exposing the pads of chip 1201, as shown below. Figure 12H As shown.

[0165] Step 9: Forming the solder ball layer. Multiple solder balls 1210 are fabricated on the surface of the redistribution layer 1209 to form a solder ball layer, as shown below. Figure 12I As shown.

[0166] Step 10: After slicing and removing the auxiliary carrier board, a fan-out package structure can be obtained.

[0167] The following specific example illustrates the detailed implementation process of fabricating a fan-out packaging structure.

[0168] Step 1: Melt-bond the chips onto an auxiliary carrier. A fifth dielectric material is deposited on the back side of each chip 1301, and a sixth dielectric material is deposited on the auxiliary carrier 1302. The chip 1301 with the fifth dielectric material deposited and the auxiliary carrier 1302 with the sixth dielectric material deposited are melt-bonded together using the fifth and sixth dielectric materials to obtain a seventh intermediate structure 13-1. After melt bonding, the fifth and sixth dielectric materials form a first dielectric-thermal interface material layer 1303, as shown below. Figure 13A As shown. The auxiliary carrier plate 1302 uses a heat sink or a heat spreader.

[0169] The second step is to mold and encapsulate the chip. The seventh intermediate structure 13-1 is placed in a mold and compressed using epoxy molding compound 1304. The epoxy molding compound 1304 fills all the gaps between the chips 1301 and completely encapsulates them. After heat curing, the eighth intermediate structure 13-2 is obtained, as shown below. Figure 13B As shown.

[0170] Step 3: Grinding the eighth intermediate structure. Grinding the overmolded material of the eighth intermediate structure 13-2 exposes the front side of each chip 1301, resulting in the ninth intermediate structure 13-3, as shown below. Figure 13C As shown.

[0171] Step 4: Forming the redistribution layer. A redistribution layer 1305 is formed on one side of the surface exposing the pads of chip 1301, as shown below. Figure 13D As shown.

[0172] Step 5: Forming the solder ball layer. Multiple solder balls 1306 are fabricated on the surface of the redistribution layer 1305 to form a solder ball layer, as shown below. Figure 13E As shown.

[0173] Step 6: After slicing, a fan-out package structure can be obtained.

[0174] The fan-out package integrated heat dissipation structure proposed in this application directly integrates the Heatsink or Heat Spreader onto the fan-out package using a Dielectric Thermal Interface Material (Dielectric-TIM) to enhance heat dissipation along the top path, meeting the increased power density and heat flux density requirements for heat dissipation performance. In the fan-out package structure, to achieve better heat dissipation, the overmolding on the back of the chip is removed, and Dielectric-TIM is used between the chip and the Heatsink or Heat Spreader to reduce interface thermal resistance and package thermal capacity. When multiple chips have different physical heights, an auxiliary layer such as structural silicon or diamond is integrated on the chip with the lower height. The chip and the auxiliary layer are bonded using Dielectric-TIM. This ensures that the physical heights of all chips are consistent, providing better structural support, and also enhances the chip's heat dissipation.

[0175] In the description of this specification, the references to terms such as "an embodiment," "a specific embodiment," "some embodiments," "for example," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0176] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A fan-out type packaged integrated heat dissipation structure, characterized in that, The package includes a fan-out package structure, on which a first dielectric-thermal interface material layer is disposed, and a heat sink or heat spreader is disposed on the first dielectric-thermal interface material layer; wherein the chip included in the fan-out package structure is in contact with the first dielectric-thermal interface material layer, and the thickness of the first dielectric-thermal interface material layer is less than 100 micrometers.

2. The fan-out type packaged integrated heat dissipation structure according to claim 1, characterized in that, Also includes: When a heat exchanger is provided on the medium-thermal interface material layer, a second medium-thermal interface material layer is provided on the heat exchanger, and a heat sink is provided on the second medium-thermal interface material layer of the heat exchanger.

3. The fan-out type packaged integrated heat dissipation structure according to claim 1 or 2, characterized in that, The fan-out package structure includes a chip embedding layer, a redistribution layer, and a solder ball layer. The chip embedding layer includes at least one chip and a mold for embedding the at least one chip. The solder ball layer includes a plurality of solder balls.

4. The fan-out type packaged integrated heat dissipation structure according to claim 3, characterized in that, The chip embedding layer includes multiple chips with different heights. An auxiliary layer is set on the chip with the lower height to make the physical height of each chip consistent. A third dielectric-thermal interface material layer is set between at least one chip with a lower height and the corresponding auxiliary layer.

5. The fan-out type packaged integrated heat dissipation structure according to claim 1, characterized in that, The first dielectric-thermal interface material layer is made of an interface material with dielectric insulation and thermal conductivity.

6. A method for fabricating a fan-out type packaged integrated heat dissipation structure, characterized in that, include: A fan-out package structure is prepared; wherein, during the preparation of the fan-out package structure, a first dielectric-thermal interface material layer is formed on the chip of the fan-out package structure, and a heat sink or heat spreader is disposed on the first dielectric-thermal interface material layer.

7. The method according to claim 6, characterized in that, The preparation of the fan-out package structure includes: Each chip is bonded to a temporary carrier board with its front side facing up. The chip on the temporary carrier is molded and packaged to obtain a first intermediate structure; The first intermediate structure is debonded to remove the temporary carrier board, thereby obtaining a molded packaged chip structure; A first dielectric material is deposited on an auxiliary carrier to obtain an auxiliary bonding assembly; and a second dielectric material is deposited on the surface of the molded packaged chip structure on the side exposed on the back of the chip to obtain a molded packaged chip bonding assembly; wherein the auxiliary carrier is a heat sink or a heat spreader. The auxiliary bonding component is melt-bonded to the molded package chip bonding component to obtain a second intermediate structure; wherein, the second intermediate structure includes a first dielectric-thermal interface material layer; Based on the second intermediate structure, a redistribution layer and a solder ball layer are formed sequentially to obtain a fan-out package structure.

8. The method according to claim 6, characterized in that, The preparation of the fan-out package structure includes: Each chip is bonded face down onto a temporary carrier board; The chip on the temporary carrier is molded and packaged to obtain a third intermediate structure; The overmolded third intermediate structure is ground to expose the back side of each chip, thus obtaining the fourth intermediate structure; A first dielectric material is deposited on an auxiliary carrier to obtain an auxiliary bonding assembly; and a second dielectric material is deposited on the exposed back surface of the fourth intermediate structure to obtain a chip bonding assembly; wherein the auxiliary carrier is a heat sink or a heat spreader. The auxiliary bonding component is fused to the chip bonding component to obtain a fifth intermediate structure; wherein, the fifth intermediate structure includes a first dielectric-thermal interface material layer; The fifth intermediate structure is debonded to remove the temporary carrier plate, thereby obtaining the sixth intermediate structure; Based on the sixth intermediate structure, a redistribution layer and a solder ball layer are formed sequentially to obtain a fan-out package structure.

9. The method according to claim 7 or 8, characterized in that, If the multiple chips bonded to the temporary carrier have different heights, the process before molding and packaging the chips on the temporary carrier also includes: A third dielectric material is deposited on a chip with a relatively low height, and a fourth dielectric material is deposited on the corresponding auxiliary layer; Chips with lower heights due to the deposition of the third dielectric material are fused and bonded to the corresponding auxiliary layer with the deposition of the fourth dielectric material, so that the physical heights of each chip are consistent.

10. The method according to claim 6, characterized in that, The preparation of the fan-out package structure includes: A fifth dielectric material is deposited on the back side of each chip, and a sixth dielectric material is deposited on an auxiliary carrier; wherein the auxiliary carrier is a heat sink or a heat spreader. A chip with a fifth dielectric material deposited is fused and bonded to an auxiliary carrier plate with a sixth dielectric material deposited to obtain a seventh intermediate structure; wherein, the seventh intermediate structure includes a first dielectric-thermal interface material layer; The chip on the seventh intermediate structure is molded and packaged to obtain the eighth intermediate structure; The overmolded eighth intermediate structure is ground to expose the front side of each chip, thus obtaining the ninth intermediate structure; Based on the ninth intermediate structure, a redistribution layer and a solder ball layer are formed sequentially to obtain a fan-out package structure.

11. The method according to claim 6, characterized in that, After integrating a heat sink on the first dielectric-thermal interface material layer, further integration of a heat sink includes: A seventh dielectric material is deposited on the heat sink, and an eighth dielectric material is deposited on the heat spreader. The heat sink with the seventh dielectric material is fused together with the heat spreader with the eighth dielectric material.

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