Memory adapter plate for radio frequency core particle integration system and preparation method of memory adapter plate

Abstract

The invention provides a memory adapter plate for a radio frequency core particle integration system and a preparation method thereof, and the preparation method comprises the steps: providing a semiconductor substrate of which the edge part is provided with a plurality of grooves which are distributed at intervals, and forming a grounding layer; providing a plurality of radio frequency core particles, and correspondingly placing the plurality of radio frequency core particles in the plurality of grooves; a first rewiring layer is formed on the grounding layer, a second rewiring layer is formed on the first rewiring layer, the second rewiring layer comprises a non-wiring area and a wiring area surrounding the non-wiring area, and a conductive circuit layer of the second rewiring layer is arranged in the wiring area; forming a memristor switch matrix on the non-wiring area, wherein the memristor switch matrix comprises a plurality of input ends and a plurality of output ends; the memory adapter plate prepared by the preparation method of the memory adapter plate for the radio frequency core particle integration system meets the requirements of parasitic suppression, process compatibility and thickness reduction, and the radio frequency core particle integration system which is simple in structure, low in cost and low in power consumption is constructed.

Description

Technical Field

[0001] This invention belongs to the field of radio frequency chip integration technology, and relates to a memory adapter board for radio frequency chip integration systems. Background Technology

[0002] In recent years, the rapid development of 5G communication, satellite Internet, and intelligent driving has driven the evolution of radio frequency systems towards miniaturization, complexity, and high frequency. The operating frequency bands of key applications such as 5G millimeter-wave base station modules and satellite communication radio frequency front-ends have exceeded 24GHz. A single module needs to integrate multiple types of radio frequency chips, which puts forward stringent requirements on signal integrity, thermal management, and reliability in extreme environments.

[0003] Current mainstream chip integration systems use active silicon interconnect boards as the interconnect carrier. These boards integrate active devices on a silicon substrate to achieve chip interconnection. While designed to meet the needs of digital chips, they are not optimized for the characteristics of RF chips and have several drawbacks: First, they are costly, requiring cross-processing of front-end chip manufacturing and back-end packaging. Second, they suffer from severe power consumption, with high static power consumption of active devices. Third, they cannot effectively suppress parasitic effects, requiring additional amplification circuits for compensation, creating a vicious cycle of power consumption. Fourth, the process steps are cumbersome and difficult to simplify, with the stacking of active devices and multi-layer structures resulting in a large integrated structure thickness, which restricts the miniaturization of RF systems.

[0004] Therefore, how to provide a memory-type adapter board for RF chip integration systems to meet the requirements of parasitic suppression, process simplification, and thickness reduction, and to build an RF chip integration system with simple structure, process compatibility, low cost, and low power consumption, has become an important problem that needs to be solved by those skilled in the art.

[0005] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating understanding by those skilled in the art. It should not be assumed that these technical solutions are known to those skilled in the art simply because they have been described in the background section of this application. Summary of the Invention

[0006] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a memory-type adapter board for radio frequency chip integration systems, which solves the problems of high cost, high power consumption, inability to suppress parasitic effects, and large thickness of integrated structure in the prior art chip integration systems that use active silicon adapter boards as interconnect carriers.

[0007] To achieve the above and other related objectives, the present invention provides a method for fabricating a memory adapter board for an integrated radio frequency chip system, comprising:

[0008] A semiconductor substrate is provided, the semiconductor substrate including a first surface and a second surface disposed opposite to each other, and the first surface of the semiconductor substrate including a middle portion and an edge portion surrounding the middle portion, the edge portion having a plurality of spaced grooves;

[0009] A ground layer is formed on the first surface of the semiconductor substrate and the inner wall of the groove;

[0010] A plurality of radio frequency (RF) chips are provided, each of the RF chips having a first surface and a second surface facing away from each other. The first surface is provided with a metal pad, and the second surface is a ground plane. The plurality of RF chips are placed in the plurality of grooves with the first surfaces facing upwards, so that the ground plane of the RF chip is electrically connected to the ground plane.

[0011] A first redistribution layer is formed on the ground layer, the first redistribution layer is electrically connected to the metal pads of the RF chip, and the ground layer has an external portion exposed outside the first redistribution layer;

[0012] A second redistribution layer is formed on the first redistribution layer. The second redistribution layer includes a non-routing region and a wiring region surrounding the non-routing region. A conductive line layer of the second redistribution layer is disposed in the wiring region and is electrically connected to the conductive line layer of the first redistribution layer.

[0013] A memristor switch matrix is ​​formed on the non-wiring area. The memristor switch matrix includes multiple input terminals and multiple output terminals. Each input terminal and each output terminal is electrically connected to the conductive line layer in the wiring area, so as to be electrically connected to the corresponding RF chip through the second redistribution layer and the first redistribution layer in sequence.

[0014] Optionally, the step of forming the first redistribution layer includes:

[0015] A first dielectric layer is formed on a first surface of the semiconductor substrate, the first dielectric layer covering the ground layer and the radio frequency chip, and the first dielectric layer is patterned to form a plurality of vias on the first dielectric layer that expose the ground layer and the first surface of the radio frequency chip;

[0016] A first seed layer is formed on the first dielectric layer, the first seed layer covering the inner wall of the via and the first surface of the radio frequency chip exposed on the first dielectric layer;

[0017] A first dry film layer is formed on the first seed layer, and the first dry film layer is patterned to form a plurality of openings corresponding to the through holes of the first dielectric layer in the first dry film layer;

[0018] A first conductive pillar is formed in the through-hole of the first dielectric layer by electroplating, and the patterned first dry film layer is removed.

[0019] A first photoresist layer is formed on the first seed layer and the conductive pillar, and the first photoresist layer is patterned.

[0020] A first wiring conductive layer is formed on the first dielectric layer by electroplating, and the patterned first photoresist layer is removed.

[0021] The first seed layer exposed outside the first wiring conductive layer is removed to obtain the first rewiring layer.

[0022] Optionally, the step of forming the second redistribution layer includes:

[0023] A second dielectric layer is formed on the first redistribution layer. The second dielectric layer includes a non-patterned region and a patterned region surrounding the non-patterned region. The second dielectric layer within the patterned region is patterned to form a plurality of vias that expose the first wiring conductive layer.

[0024] A second seed layer is formed on the second dielectric layer, the second seed layer covering the inner wall of the via and the first wiring conductive layer exposed on the second dielectric layer;

[0025] A second dry film layer is formed on the second seed layer, and the second dry film layer is patterned to form a plurality of openings corresponding to the through holes of the second dielectric layer in the second dry film layer;

[0026] A second conductive pillar is formed in the through-hole of the second dielectric layer by electroplating, and the patterned second dry film layer is removed.

[0027] A second photoresist layer is formed on the second seed layer and the second conductive pillar, and the second photoresist layer is patterned.

[0028] A second wiring conductive layer is formed on the second dielectric layer by electroplating, and the patterned second photoresist layer is removed.

[0029] The second seed layer exposed outside the second wiring conductive layer is removed to obtain the second rewiring layer.

[0030] Optionally, the steps of forming the memristor switching matrix include:

[0031] Multiple bottom electrodes are formed on the second dielectric layer in the non-patterned area, and the bottom electrodes are spaced apart along the X direction, with both ends of each bottom electrode electrically connected to the two wiring conductive layers.

[0032] A memristor functional layer is spin-coated onto the second dielectric layer within the non-patterned region, and the memristor functional layer covers the bottom electrode;

[0033] The memristor functional layer is graphically represented, and the memristor functional layer outside the preset switch matrix unit area is removed to obtain the memristor functional layer unit.

[0034] Multiple top electrodes are formed on the second dielectric layer in the non-patterned region, and the top electrodes are spaced apart along the Y direction and cover the memristor functional layer unit. The two ends of each top electrode are electrically connected to the two wiring conductive layer.

[0035] Optionally, the thickness of the radio frequency chip is the same as the depth of the corresponding groove.

[0036] Optionally, before placing the plurality of radio frequency chips with their active surfaces facing upwards into the plurality of grooves, the method further includes the step of injecting conductive silver paste into the plurality of grooves to form a conductive silver paste layer between the passive surface of the radio frequency chip and the inner wall of the groove.

[0037] Optionally, the memristor functional layer includes a Nafion layer.

[0038] Optionally, the radio frequency chip includes GaAs chips, CMOS chips, and GaN chips.

[0039] The present invention also provides a memory adapter board for an integrated radio frequency chip system, comprising:

[0040] A semiconductor substrate, the semiconductor substrate including a first surface and a second surface disposed opposite to each other, wherein the first surface of the semiconductor substrate includes a middle portion and an edge portion surrounding the middle portion, and the edge portion has a plurality of spaced grooves.

[0041] A grounding layer is located on the first surface of the semiconductor substrate and on the inner wall of the groove;

[0042] Multiple radio frequency (RF) chips are placed in multiple grooves. Each RF chip has a first surface and a second surface facing away from each other. The first surface is provided with a metal pad, and the second surface is a ground plane. The first surfaces of the multiple RF chips face upwards, and the ground plane is electrically connected to the ground layer.

[0043] A first redistribution layer is located on the ground layer, the first redistribution layer is electrically connected to the metal pads of the RF chip, and the ground layer has an external portion exposed outside the first redistribution layer;

[0044] A second rerouting layer is located on the first rerouting layer. The second rerouting layer includes a non-routing area and a wiring area surrounding the non-routing area. A conductive line layer of the second rerouting layer is disposed in the wiring area and is electrically connected to the conductive line layer of the first rerouting layer.

[0045] A memristor switch matrix is ​​located on the non-wiring area. The memristor switch matrix includes multiple input terminals and multiple output terminals. Each input terminal and each output terminal is electrically connected to the conductive line layer in the wiring area, so as to be electrically connected to the corresponding RF chip through the second rewiring layer and the first rewiring layer in sequence.

[0046] The present invention also provides an integrated radio frequency chip system, comprising:

[0047] The aforementioned memory adapter board and antenna assembly for a radio frequency chip integrated system include an antenna assembly comprising a support substrate and a transmitting antenna and a receiving antenna disposed on the support substrate. The support substrate is fastened to the side of the memory adapter board for the radio frequency chip integrated system that has the second redistribution layer. The transmitting antenna is electrically connected to the output terminal of the memristor switch matrix through the second redistribution layer, and the receiving antenna is electrically connected to the input terminal of the memristor switch matrix through the second redistribution layer. Furthermore, the ground terminals of both the transmitting and receiving antennas are electrically connected to the external portion of the ground layer.

[0048] As described above, the method for fabricating a memory adapter board for an integrated radio frequency (RF) chip system according to the present invention includes: providing a semiconductor substrate, the semiconductor substrate including a first surface and a second surface disposed opposite to each other, and the first surface of the semiconductor substrate including a middle portion and an edge portion surrounding the middle portion, the edge portion having a plurality of spaced grooves; forming a ground layer on the first surface of the semiconductor substrate and the inner wall of the grooves; providing a plurality of RF chips, each RF chip having a first surface and a second surface opposite to each other, the first surface having a metal pad, the second surface being a ground plane, the plurality of RF chips being placed in the plurality of grooves with the first surfaces facing upwards, such that the ground plane of the RF chip is electrically connected to the ground layer; forming a first redistribution layer on the first surface of the semiconductor substrate and the inner wall of the grooves. On the ground plane, a first redistribution layer is electrically connected to the metal pads of the RF chip, and the ground plane has an external portion exposed outside the first redistribution layer; a second redistribution layer is formed on the first redistribution layer, the second redistribution layer includes a non-wiring area and a wiring area surrounding the non-wiring area, and a conductive line layer of the second redistribution layer is disposed in the wiring area and electrically connected to the conductive line layer of the first redistribution layer; a memristor switch matrix is ​​formed on the non-wiring area, the memristor switch matrix includes multiple input terminals and multiple output terminals, each input terminal and each output terminal is electrically connected to the conductive line layer in the wiring area, so as to be electrically connected to the corresponding RF chip through the second redistribution layer and the first redistribution layer in sequence. The method for fabricating a memory-type adapter board for an RF chip integrated system of the present invention can meet the requirements of parasitic suppression, process simplification, and thickness reduction, and construct an RF chip integrated system with simple structure, process compatibility, low cost, and low power consumption. Attached Figure Description

[0049] Figure 1 The diagram shows a process flow chart of the fabrication method of the memory adapter board for radio frequency chip integrated system of the present invention.

[0050] Figure 2 The diagram shows a schematic of the semiconductor substrate structure in the method for fabricating a memory adapter for a radio frequency chip integrated system according to the present invention.

[0051] Figure 3 Displayed as Figure 2 Top view of the structure shown.

[0052] Figure 4 The diagram shown is a schematic of the structure obtained by placing multiple radio frequency chips into multiple grooves in the method for preparing a memory adapter board for a radio frequency chip integration system according to the present invention.

[0053] Figure 5 The diagram shown is a schematic of the structure obtained after forming the first redistribution layer in the fabrication method of the memory adapter board for radio frequency chip integrated system of the present invention.

[0054] Figure 6 The diagram shown is a schematic of the structure obtained after forming the first dielectric layer in the method for fabricating a memory adapter board for an integrated radio frequency chip system according to the present invention.

[0055] Figure 7 The diagram shown is a schematic of the structure obtained after forming the first seed layer in the method for preparing a memory adapter board for an integrated radio frequency chip system according to the present invention.

[0056] Figure 8 The diagram shown is a schematic of the structure obtained after forming the first dry film layer in the method for preparing a memory adapter for an integrated radio frequency chip system according to the present invention.

[0057] Figure 9 The diagram shows a schematic of the structure obtained after forming the first conductive pillar in the method for preparing a memory adapter board for an integrated radio frequency chip system according to the present invention.

[0058] Figure 10 The diagram shown is a schematic of the structure obtained after forming the first photoresist layer in the method for preparing a memory adapter for an integrated radio frequency chip system according to the present invention.

[0059] Figure 11 The diagram shows a schematic of the structure obtained after forming the first wiring conductive layer in the method for fabricating a memory adapter board for an integrated radio frequency chip system according to the present invention.

[0060] Figure 12 The diagram shown is a schematic of the structure obtained after forming the second redistribution layer in the fabrication method of the memory adapter board for radio frequency chip integrated system of the present invention.

[0061] Figure 13 Displayed as Figure 12 Top view of the structure shown.

[0062] Figure 14 The diagram shows a schematic of the structure obtained after forming the second dielectric layer in the method for fabricating a memory adapter board for an integrated radio frequency chip system according to the present invention.

[0063] Figure 15 Displayed as Figure 14 Top view of the structure shown.

[0064] Figure 16 The diagram shown is a schematic of the structure obtained after patterning the second dielectric layer in the method for fabricating a memory adapter board for an integrated radio frequency chip system according to the present invention.

[0065] Figure 17 The diagram shows a schematic of the structure obtained after forming the second seed layer in the method for preparing a memory adapter board for an integrated radio frequency chip system according to the present invention.

[0066] Figure 18 The diagram shows a schematic of the structure obtained after forming the second dry film layer in the method for preparing a memory adapter for an integrated radio frequency chip system according to the present invention.

[0067] Figure 19 The diagram shows a schematic of the structure obtained after forming the second conductive pillar in the method for preparing a memory adapter board for an integrated radio frequency chip system according to the present invention.

[0068] Figure 20 The diagram shown is a schematic of the structure obtained after forming the second photoresist layer in the method for preparing a memory adapter for an integrated radio frequency chip system according to the present invention.

[0069] Figure 21 The diagram shown is a schematic of the structure obtained after forming the second wiring conductive layer in the method for preparing a memory adapter board for an integrated radio frequency chip system according to the present invention.

[0070] Figure 22 The diagram shown is a schematic of the structure obtained after forming a memristor switching matrix in the fabrication method of the memory adapter board for radio frequency chip integrated system of the present invention.

[0071] Figure 23 Displayed as Figure 22 Top view of the structure shown.

[0072] Figure 24 The diagram shows the signal path switching of the memristor switch matrix in the memory adapter board for radio frequency chip integration system of the present invention.

[0073] Figure 25 The diagram shows a schematic of the structure obtained after forming multiple bottom electrodes in the method for fabricating a memory adapter for an integrated radio frequency chip system according to the present invention.

[0074] Figure 26 The diagram shows a schematic of the structure obtained after spin-coating the memristor functional layer in the fabrication method of the memory adapter board for radio frequency chip integrated system of the present invention.

[0075] Figure 27 The diagram shown is a schematic of the structure obtained after patterning the memristor functional layer in the fabrication method of the memory adapter board for radio frequency chip integrated system of the present invention.

[0076] Figure 28 The diagram shown is a three-dimensional structural schematic of a memory adapter board for an integrated radio frequency chip system according to the present invention.

[0077] Figure 29 The diagram shown is an eye diagram simulation result of the memristor switching matrix in the memory adapter board for RF chip integration system of the present invention.

[0078] Figure 30 The diagram shows the working state of the memristor switch matrix in the memory adapter board for radio frequency chip integration system of the present invention.

[0079] Figure 31 The diagram shows the connection of the radio frequency chip integration system of the present invention.

[0080] Figure 32 The diagram shows a first typical operating state of the radio frequency chip integration system of the present invention.

[0081] Figure 33a The diagram shows the frequency response of the transmit channel under a first typical operating state of the RF chip integrated system of the present invention.

[0082] Figure 33b The diagram shows the frequency response of the receiving channel under the first typical operating state of the RF chip integrated system of the present invention.

[0083] Figure 34a The image shows the antenna gain pattern of the transmitting antenna under a first typical operating state of the RF chip integrated system of the present invention.

[0084] Figure 34b The image shows the antenna gain pattern of the receiving antenna in a first typical operating state of the RF chip integrated system of the present invention.

[0085] Figure 35 The diagram shows a second typical operating state of the radio frequency chip integration system of the present invention.

[0086] Figure 36a The diagram shows the frequency response of the transmit channel under a second typical operating state of the RF chip integrated system of the present invention.

[0087] Figure 36b The diagram shows the frequency response of the receiving channel under a second typical operating state of the RF chip integrated system of the present invention.

[0088] Figure 37a The image shows the antenna gain pattern of the transmitting antenna under a second typical operating state of the RF chip integrated system of the present invention.

[0089] Figure 37b The image shows the antenna gain pattern of the receiving antenna in a second typical operating state of the RF chip integrated system of the present invention.

[0090] Explanation of reference numerals in the attached figures: 1 Semiconductor substrate, 101 Middle portion, 102 Edge portion, 2 Groove, 3 Ground layer, 4 RF chip, 5 First redistribution layer, 501 First dielectric layer, 502 First seed layer, 503 First conductive pillar, 504 First wiring conductive layer, 6 Second redistribution layer, 601 Second dielectric layer, 602 Second seed layer, 603 Second conductive pillar, 604 Second wiring conductive layer, 7 Non-wiring area, 8 Wiring area, 9 Memristor switch matrix, 9a Input terminal, 9b Output terminal, 901 Bottom electrode, 902 Memristor functional layer, 903 Top electrode, 10, 16 Through-hole, 11 First dry film layer, 12, 18 Opening, 13 First photoresist layer, 14 Non-patterned area, 15 Patterned area, 17 Second dry film layer, 19 Second photoresist layer. Detailed Implementation

[0091] Due to the variety of packaging carriers, the main integrated circuit packaging methods can be divided into the following categories: System-on-a-Box (SiB) technology, System-on-Board (SoB) technology, System-on-Chip (SoC) technology, and System-in-Package (SiP), etc. With the advancement of packaging technology, a number of representative advanced packaging integration processes have emerged, among which TSMC's Advanced System-on-Chip (SoIC) is a prime example. However, with Moore's Law facing significant challenges, there is an urgent need for new packaging integration technologies to overcome the physical limitations imposed by the shrinking size of transistors. Chip-in-chip integration technology is the most representative system integration technology, significantly improving the flexibility of system architecture.

[0092] Chip-integrated systems with 2.5D / 3D architectures have attracted significant attention due to their reusability, configuration flexibility, and ease of IP core updates during design. Chip-integration technology differs significantly from SoC technology in its integration methods. Chip-integration is well-suited for high-density semiconductor material integration in RF and millimeter-wave applications, and interconnect technology is a crucial element within chip-integrated systems. Advanced packaging technologies, such as silicon interposers and wafer-level fan-out packaging, are key to achieving chip-integration. By assembling small chips and passive devices with various standardized functions on passive silicon interposers, performance and yield can be improved.

[0093] Universal Chip Interconnect Express (UCIe) is a commonly used high-speed chip interconnect method. In the UCIe advanced packaging system, two key technologies improve the interconnect density in chip integration systems. Passive silicon interposers typically provide fixed interconnects between chips; representative technologies include Intel's Embedded Multi-Chip Interconnect Bridge (EMIB) and TSMC's Chip-Wafer-Substrate (CoWoS) technology. Intel's EMIB technology achieves a trade-off between system packaging performance, density, and cost. This process improves the local interconnect density of the packaged system. EMIB technology can only provide fixed signal path connections, and its path regulation depends on the control chip connected to the input / output (I / O) signal ports. CoWoS, similar to EMIB, also provides high-density fixed interconnects. However, to achieve more flexible chip integration systems, advanced packaging interconnect technologies with signal reconfigurability are needed.

[0094] Currently, researchers have proposed a chip-based heterogeneous integration system based on an active silicon interposer, which includes an adjustable silicon interposer switch. The silicon interposer switch matrix can be implemented using front-end processes (FEOL), such as CMOS and GaAs processes, or using back-end processes (BEOL) or nanoelectromechanical systems (NEMS). However, integrating chip-based systems onto active silicon interposers typically fails to effectively suppress parasitic effects, resulting in high system cost, high power consumption, and high circuit complexity. This makes it difficult to meet the requirements of RF chip-based integrated systems for signal integrity, thermal management, and reliability in extreme environments.

[0095] In response, this invention proposes a memory-type adapter board for RF chip integration systems, which can meet the requirements of parasitic suppression, process simplification, and thickness reduction, thereby constructing an RF chip integration system with simple structure, process compatibility, low cost, and low power consumption.

[0096] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0097] It should be emphasized that the term "including / comprises" as used herein refers to the presence of a feature, whole, step, or component, but does not exclude the presence or addition of one or more other features, wholes, steps, or components.

[0098] Features described and / or illustrated for one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments.

[0099] In the detailed description of embodiments of the present invention, for ease of explanation, the schematic diagrams illustrating the device structure may be partially enlarged without adhering to the general scale, and the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. Furthermore, in actual manufacturing, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0100] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include directions other than those depicted in the drawings for devices in use or operation. Furthermore, when a layer is referred to as being “between” two layers, it may be the only layer between the two layers, or there may be one or more layers in between.

[0101] In the context of this application, the structure described above the first feature may include embodiments in which the first and second features are in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0102] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0103] Example 1

[0104] This embodiment provides a method for fabricating a memory-type adapter board for an RF chip integrated system. Please refer to [link to relevant documentation]. Figure 1 The diagram shows a process flow chart of the fabrication method of the memory adapter board for an RF chip integrated system according to the present invention, which includes at least the following steps:

[0105] S1: A semiconductor substrate is provided, the semiconductor substrate including a first surface and a second surface disposed opposite to each other, and the first surface of the semiconductor substrate includes a middle portion and an edge portion surrounding the middle portion, the edge portion having a plurality of spaced grooves;

[0106] S2: A ground layer is formed on the first surface of the semiconductor substrate and the inner wall of the groove;

[0107] S3: Provide multiple radio frequency (RF) chips, each of which has a first surface and a second surface facing away from each other. The first surface is provided with a metal pad, and the second surface is a ground plane. Place the multiple RF chips with their first surfaces facing upwards in the multiple grooves, so that the ground plane of the RF chip is electrically connected to the ground plane.

[0108] S4: A first redistribution layer is formed on the ground layer, the first redistribution layer being electrically connected to the metal pads of the RF chip, and the ground layer having an external portion exposed outside the first redistribution layer;

[0109] S5: A second rerouting layer is formed on the first rerouting layer. The second rerouting layer includes a non-routing area and a wiring area surrounding the non-routing area. A conductive line layer of the second rerouting layer is disposed in the wiring area and is electrically connected to the conductive line layer of the first rerouting layer.

[0110] S6: Form a memristor switch matrix on the non-wiring area. The memristor switch matrix includes multiple input terminals and multiple output terminals. Each input terminal and each output terminal is electrically connected to the conductive line layer in the wiring area, so as to be electrically connected to the corresponding RF chip through the second rewiring layer and the first rewiring layer in sequence.

[0111] The following section, using a structural diagram, details the specific implementation methods for each of the above steps.

[0112] Please refer to the following first. Figures 2 to 3 Step S1: A semiconductor substrate 1 is provided. The semiconductor substrate 1 includes a first surface and a second surface disposed opposite to each other. The first surface of the semiconductor substrate 1 includes a central portion 101 and an edge portion 102 surrounding the central portion 101. The edge portion 102 has a plurality of spaced grooves 2. Figure 2 for Figure 3 The cross-sectional view along the AA' direction is shown below. For clarity, the preparation process will be explained later. Figures 4 to 12 , Figure 14 , Figures 16 to 22 All are with Figure 2 A cross-sectional view on the same vertical plane.

[0113] As an example, the semiconductor substrate 1 is a high-resistivity silicon substrate with a resistivity greater than 10000 Ω·cm.

[0114] As an example, the process for forming the groove 2 is a Bosch reactive ion etching process. The multiple grooves 2 have different depths. In this embodiment, the groove 2 has three different depths. During the etching process, when the shallower groove is etched, the groove is protected with tape. After multiple etching cycles, other deeper grooves can be obtained.

[0115] As an example, the thickness of the semiconductor substrate 1 is 445 μm, and the thickness of the radio frequency chip 4 ranges from 0 to 300 μm, such as 200 μm or 150 μm.

[0116] Please see again Figure 4 Step S2: Form a ground layer 3 on the first surface of the semiconductor substrate 1 and the inner wall of the groove 2.

[0117] Specifically, the grounding layer 3 is formed by first sputtering a copper seed layer and then electroplating a metal layer.

[0118] Please see again Figure 4 Step S3: Provide multiple radio frequency chips 4, each radio frequency chip 4 having a first surface and a second surface facing away from each other. The first surface is provided with a metal pad (not shown in the figure), and the second surface is a ground plane. Place the multiple radio frequency chips 4 with the first surface facing up in the multiple grooves 2, so that the ground plane of the radio frequency chip 4 is electrically connected to the ground layer 3.

[0119] As an example, the thickness of the RF chip 4 is the same as the depth of the corresponding groove 2, and the RF chips of different thicknesses are embedded into the grooves of different depths by a pick-and-place machine.

[0120] As an example, before placing the multiple radio frequency chips 4 with their active surfaces facing upwards into the multiple grooves 2, the method further includes injecting conductive silver paste into the multiple grooves 2 to form a conductive silver paste layer between the passive surface of the radio frequency chip 4 and the inner wall of the groove 2.

[0121] As an example, the RF chip 4 includes a GaAs chip, a CMOS chip, and a GaN chip.

[0122] Specifically, embedding the RF chip 4 within the semiconductor substrate 1 ensures that the upper surface of the RF chip 4 is substantially coplanar with the surface of the semiconductor substrate 1 (without significant protrusions). Furthermore, the RF chip 4 and the semiconductor substrate 1 are in close, large-area contact, with direct contact and a short interconnection path with the ground layer 3. This reduces parasitic inductance and capacitance, avoids parasitic effects, matches the impedance requirements of the RF signal, and reduces signal distortion. Moreover, the RF chip 4 is encapsulated by the semiconductor substrate 1, which (e.g., a silicon substrate) is itself an excellent electromagnetic shielding medium. This effectively provides each RF chip 4 with an independent shielding cavity, reducing crosstalk between different RF chips 4. Additionally, if a silicon substrate is used, the thermal conductivity of silicon (approximately 150 W / (m·K)) is much higher than that of air (0.026 W / (m·K)) and solder paste (approximately 50 W / (m·K)). The heat from the RF chip 4 can be rapidly conducted and diffused through the semiconductor substrate 1, significantly improving the reliability and performance stability of the RF chip 4. In addition, radio frequency systems are often used in environments such as base stations, satellites, and radar (where they frequently encounter temperature cycling, vibration, and shock), so mechanical reliability is crucial. By embedding the radio frequency chip 4 into the semiconductor substrate 1, the contact area between the two is large, and the stress can be evenly distributed across the entire contact surface between the chip and the substrate, rather than concentrated on the bumps. Furthermore, the coplanar structure has no height difference, resulting in a flatter structure and stronger resistance to vibration and temperature cycling.

[0123] Please see again Figure 5 Step S4 is executed: a first redistribution layer 5 is formed on the ground layer 3. The first redistribution layer 5 is electrically connected to the metal pads of the RF chip 4, and the ground layer 3 has an external portion exposed outside the first redistribution layer 5.

[0124] As an example, the steps for forming the first rerouting layer 5 include:

[0125] (1) Please refer to Figure 6 A first dielectric layer 501 is formed on the first surface of the semiconductor substrate 1. The first dielectric layer 501 covers the ground layer 3 and the radio frequency chip 4. The first dielectric layer 501 is patterned to form a plurality of vias 10 in the first dielectric layer 501 that expose the ground layer 3 and the first surface of the radio frequency chip 4.

[0126] As an example, the thickness of the first dielectric layer 501 is 40 μm.

[0127] As an example, the material of the first dielectric layer 501 includes epoxy negative photoresist (SU8). After spin coating SU8, air bubbles are removed by a disposable dropper, and pre-baking is performed. Then, the vias of the first dielectric layer 501 are exposed. After exposure, post-baking is performed, followed by development and hardening treatment.

[0128] (2) Please refer to Figure 7 A first seed layer 502 is formed on the first dielectric layer 501, and the first seed layer 502 covers the inner wall of the through hole 10 and the first surface of the radio frequency chip 4 exposed on the first dielectric layer 501.

[0129] As an example, the first seed layer 502 is a 15 nm thick Cr layer.

[0130] As an example, the process for forming the first seed layer 502 is a magnetron sputtering process, that is, magnetron sputtering is used to sequentially sputter 30 nm of chromium and 300 nm of copper onto the first dielectric layer 501 to form the first seed layer 502.

[0131] (3) Please refer to Figure 8 A first dry film layer 11 is formed on the first seed layer 502, and the first dry film layer 11 is patterned to form a plurality of openings 12 corresponding to the through holes of the first dielectric layer 501 in the first dry film layer 11.

[0132] As an example, the first dry film layer 11 is a negative light imaging electroplating resistant and corrosion resistant dry film (FM820).

[0133] (4) Please refer to Figure 9 The first conductive pillar 503 is formed in the through hole of the first dielectric layer 501 by electroplating process, and the patterned first dry film layer 11 is removed. Before electroplating, the part to be electroplated should be wetted in a vacuum environment to ensure that all through holes are uniformly plated.

[0134] (5) Please refer to Figure 10 A first photoresist layer 13 is formed on the first seed layer 502 and the conductive pillars, and the first photoresist layer 13 is patterned.

[0135] (6) Please refer to Figure 11 An electroplating process is used to form a first wiring conductive layer 504 on the first dielectric layer 501, and the patterned first photoresist layer 13 is removed.

[0136] As an example, the first wiring conductive layer 504 is a 1 μm thick Cu layer.

[0137] As an example, the first photoresist layer 13 was removed by immersion in an acetone solution.

[0138] (7) Please refer to the following: Figure 5 The first seed layer 502 exposed outside the first wiring conductive layer 504 is removed to obtain the first rewiring layer 5.

[0139] As an example, an ion beam etching process is used to remove the first seed layer 502 exposed outside the first wiring conductive layer 504.

[0140] As an example

[0141] Please see again Figures 12 to 13 Step S5: A second redistribution layer 6 is formed on the first redistribution layer 5. The second redistribution layer 6 includes a non-wiring area 7 and a wiring area 8 surrounding the non-wiring area 7. The conductive line layer of the second redistribution layer 6 is disposed in the wiring area 8 and electrically connected to the conductive line layer of the first redistribution layer 5.

[0142] As an example, the steps for forming the second rerouting layer 6 include:

[0143] (1) Please refer to Figures 14 to 16 A second dielectric layer 601 is formed on the first redistribution layer 5. The second dielectric layer 601 includes a non-patterned region 14 and a patterned region 15 surrounding the non-patterned region 14. The second dielectric layer 601 within the patterned region 15 is patterned to form a plurality of vias 16 that expose the first wiring conductive layer 504.

[0144] As an example, the thickness of the second dielectric layer 601 is 40 μm.

[0145] (2) Please refer to Figure 17 A second seed layer 602 is formed on the second dielectric layer 601, and the second seed layer 602 covers the inner wall of the through hole 16 and the first wiring conductive layer 504 exposed on the second dielectric layer 601.

[0146] As an example, the second seed layer 602 is a 15 nm thick Cr layer.

[0147] (3) Please refer to Figure 18 A second dry film layer 17 is formed on the second seed layer 602, and the second dry film layer 17 is patterned to form a plurality of openings 18 corresponding to the through holes of the second dielectric layer 601 in the second dry film layer 17.

[0148] (4) Please refer to Figure 19 A second conductive pillar 603 is formed in the through hole of the second dielectric layer 601 by electroplating, and the patterned second dry film layer 17 is removed.

[0149] (5) Please refer to Figure 20 A second photoresist layer 19 is formed on the second seed layer 602 and the second conductive pillar 603, and the second photoresist layer 19 is patterned.

[0150] (6) Please refer to Figure 21 A second wiring conductive layer 604 is formed on the second dielectric layer 601 using an electroplating process, and the patterned second photoresist layer 19 is removed.

[0151] (7) Please refer to the following: Figure 12 Remove the second seed layer 602 that is exposed outside the second wiring conductive layer 604 to obtain the second rewiring layer 6.

[0152] As an example, the second wiring conductive layer 604 is a 1 μm thick Cu layer.

[0153] Please see again Figures 22 to 23 Step S6: Form a memristor switch matrix 9 on the non-wiring area 7. The memristor switch matrix 9 includes multiple input terminals 9a and multiple output terminals 9b. Each input terminal 9a and each output terminal 9b is electrically connected to the conductive line layer in the wiring area 8, so as to be electrically connected to the corresponding RF chip 4 through the second rewiring layer 6 and the first rewiring layer 5 in sequence.

[0154] Specifically, the memristor switch matrix 9 is composed of multiple memristor units, and each input terminal 9a and each output terminal 9b is connected to a corresponding RF chip 4. Please refer to [link / reference]. Figure 24 The diagram illustrates the signal path switching of the memristor switch matrix 9 in the memory adapter board of the RF chip 4 integrated system of the present invention. When the switching state of the corresponding memristor unit is edited (i.e., the switching state of the memristor is changed; in the diagram, ON represents the memristor being on and the circuit being conductive, and OFF represents the memristor being off and the circuit being non-conductive), a signal path is established from one specific input terminal 9a to another specific output terminal 9b (the arrows in the diagram indicate the signal path), thereby realizing a pathway connecting the two RF chips 4 that are respectively connected to the specific input terminal 9a and the output terminal 9b. Therefore, by changing the switching state of the corresponding memristor units at different positions, reconfigurable interconnection between the RF chips 4 can be achieved.

[0155] As an example, the steps to form the memristor switch matrix 9 include:

[0156] (1) Please refer to Figure 25 Multiple bottom electrodes 901 are formed on the second dielectric layer 601 within the non-patterned region 14, and the bottom electrodes 901 are spaced apart along the X direction. The two ends of each bottom electrode 901 are electrically connected to the second wiring conductive layer.

[0157] As an example, the bottom electrode 901 is formed by electron beam evaporation deposition. In this embodiment, the bottom electrode 901 is formed by electron beam evaporation deposition of a 20 nm thick Ti layer and a 200 nm thick Au layer.

[0158] (2) Please refer to Figure 26 A memristor functional layer 902 is spin-coated onto the second dielectric layer 601 within the non-patterned region 14, and the memristor functional layer 902 covers the bottom electrode 901.

[0159] As an example, the memristor functional layer 902 is prepared by spin coating. In this embodiment, the memristor functional layer 902 is formed by spin coating to prepare a 500 nm thick layer of perfluorosulfonic acid-polytetrafluoroethylene copolymer (Nafion).

[0160] (3) Please refer to Figure 27 The memristor functional layer 902 is graphically represented, and the memristor functional layer 902 outside the preset switch matrix unit area is removed to obtain the memristor functional layer 902 unit.

[0161] Specifically, the memristor functional layer 902 above the bottom electrode 901 is first protected by photolithography, and then the remaining memristor functional layer 902 is removed by ion beam etching (IBE).

[0162] (4) Please refer to the following: Figure 22 Multiple top electrodes 903 are formed on the second dielectric layer 601 within the non-patterned region 14, and the top electrodes 903 are spaced apart along the Y direction and cover the memristor functional layer 902 unit. The two ends of each top electrode 903 are electrically connected to the two wiring conductive layer.

[0163] As an example, the top electrode 903 is formed using radio frequency magnetron sputtering and ion beam etching. In this embodiment, the top electrode 903 is formed by depositing a 500 nm thick Cu layer by radio frequency magnetron sputtering and then patterning it using ion beam etching.

[0164] As an example, the bottom electrode 901 is an inert electrode, and the top electrode 903 is an active electrode.

[0165] The units of the memristor switch matrix 9 are compatible with the process of passive silicon adapter boards, and have the advantages of low complexity and low cost compared with active silicon adapter boards.

[0166] To demonstrate the quality of high-speed signal transmission in the memristor switch matrix 9, a software simulation was performed to illustrate the transmission of a 30 Gbps high-speed signal within the memristor switch matrix 9. (See [link to simulation]). Figure 29 The image shown is an eye diagram simulation result of the memristor switch matrix 9 in the memory adapter board of the RF chip 4 integrated system of the present invention. It can be found that the eye height of the eye diagram is 0.71V and the root mean square value of jitter is 1.3 ps, indicating that the memristor switch matrix 9 has good high-speed signal transmission effect.

[0167] Further, please refer to Figure 30 The diagram shows the working state of the memristor switch matrix 9 in the memory adapter board of the RF chip 4 integrated system of the present invention. The memristor units in the memristor switch matrix 9 are conductive bridge type switch units. The structure of the memristor unit is shown in the figure. The top electrode 903 is a copper electrode, and the bottom electrode 901 is a gold electrode. A layer of titanium metal is deposited as an adhesion layer between the gold electrode, the high-resistivity silicon, and the second dielectric layer 601. The memristor functional layer 902 (i.e., dielectric layer) between the top electrode 903 and the bottom electrode 901 is made of Nafion thin film. When a positive voltage is applied to the top electrode 903, conductive filaments are formed in the memristor functional layer 902, which is the SET process of the memristor unit, constructing the on state of the memristor unit (switch unit). Conversely, when a negative voltage is applied to the top electrode 903, the conductive filaments in the memristor functional layer 902 break, which is the RESET process of the memristor unit, constructing the off state of the memristor unit. Furthermore, the on / off states of the memristor units are non-volatile, forming a memory-based adapter board with the memristor switch matrix 9, which can subsequently integrate chips with different processes / functions. The memristor switch matrix 9 provides reconfigurable interconnects for these chips.

[0168] This embodiment presents a method for fabricating a memory-based adapter board for RF chip-integrated systems. Addressing the prominent issues of high cost, high power consumption, and high circuit complexity in existing silicon adapter board packaging technologies, this method achieves reconfigurable signal paths between chips while realizing high-speed interconnection. This enhances the flexibility of the subsequent RF chip-integrated system architecture and reduces the cost of implementing reconfigurable functionality in RF chip-integrated systems. Furthermore, the memory-based adapter board fabricated using this method is primarily used for reconfigurable signal paths in chip-integrated RF systems. Its greatest advantage compared to other types of adapter boards lies in its complete compatibility with existing packaging technologies, enabling reconfigurable functionality during the packaging process. This is fundamentally different from existing chip-integrated systems based on active silicon adapter board technology, resulting in reduced system cost and power consumption, and improved overall energy efficiency.

[0169] Example 2

[0170] This embodiment provides a memory-type adapter board for an integrated RF chip 4 system. Please refer to [link to relevant documentation]. Figures 22 to 23 The memory adapter board for the RF chip 4 integrated system includes a semiconductor substrate 1, a ground layer 3, multiple RF chips 4, a first redistribution layer 5, a second redistribution layer 6, and a memristor switch matrix 9. The semiconductor substrate 1 includes a first surface and a second surface disposed opposite to each other. The first surface of the semiconductor substrate 1 includes a central portion 101 and an edge portion 102 surrounding the central portion 101. The edge portion 102 has multiple spaced grooves 2. The ground layer 3 is located on the first surface of the semiconductor substrate 1 and the inner wall of the grooves 2. Multiple RF chips 4 are correspondingly placed within the multiple grooves 2. Each RF chip 4 has a first surface and a second surface facing away from each other. The first surface has metal pads, and the second surface is a ground plane. The first surfaces of the multiple RF chips 4 face upwards, and the ground plane is electrically connected to the ground layer 3. The first redistribution layer 5 is located on... On the ground layer 3, the first redistribution layer 5 is electrically connected to the metal pads of the RF chip 4, and the ground layer 3 has an external portion exposed outside the first redistribution layer 5; the second redistribution layer 6 is located on the first redistribution layer 5, the second redistribution layer 6 includes a non-wiring area 7 and a wiring area 8 surrounding the non-wiring area 7, the conductive line layer of the second redistribution layer 6 is disposed in the wiring area 8 and electrically connected to the conductive line layer of the first redistribution layer 5; the memristor switch matrix 9 is located on the non-wiring area 7, the memristor switch matrix 9 includes a plurality of input terminals 9a and a plurality of output terminals 9b, each of the input terminals 9a and each of the output terminals 9b is electrically connected to the conductive line layer in the wiring area 8, so as to be electrically connected to the corresponding RF chip 4 through the second redistribution layer 6 and the first redistribution layer 5 in sequence.

[0171] It should be noted that the memory adapter board for the RF chip 4 integrated system in this embodiment can be fabricated using the fabrication method for the memory adapter board for the RF chip 4 integrated system described in Embodiment 1, or it can be fabricated using other suitable fabrication methods.

[0172] For example, please refer to Figure 28 The diagram shows a three-dimensional structural schematic of a memory adapter board for an integrated system of radio frequency chip 4 according to the present invention. There are multiple memristor switch matrices 9, which are arranged at intervals. For ease of display, the radio frequency chip 4 and the first wiring conductive layer 504 are marked with dashed lines to indicate their positions.

[0173] The memory adapter board for RF chip integration system of this embodiment integrates RF chips in a passive adapter board and then connects to a reconfigurable transmission line network consisting of a memristor switch matrix, a first redistribution layer, and a second redistribution layer. The reconfigurable transmission line network can construct signal paths between any RF chips, thereby enabling efficient configuration of hardware resources. Furthermore, the RF chip connection does not require the use of wire bonding and / or surface mount technology (SMT). By optimizing the interconnection and adapter structure between the RF chips and the memristor switch matrix, good impedance matching and field matching can be achieved, thereby reducing the impact of parasitic effects.

[0174] Example 3

[0175] This embodiment provides a radio frequency chip 4 integrated system, which includes:

[0176] As described in Embodiment 2, the memory adapter board and antenna assembly for the RF chip 4 integrated system include a support substrate and a transmitting antenna and a receiving antenna disposed on the support substrate. The support substrate is fastened to the side of the memory adapter board for the RF chip 4 integrated system that has the second redistribution layer 6. The transmitting antenna is electrically connected to the output terminal 9b of the memristor switch matrix 9 through the second redistribution layer 6. The receiving antenna is electrically connected to the input terminal 9a of the memristor switch matrix 9 through the second redistribution layer 6. The ground terminals of both the transmitting and receiving antennas are electrically connected to the external portion of the ground layer 3.

[0177] It should be noted that, apart from the antenna assembly, all components (including the chip and the redistribution layer) are on the semiconductor substrate 1. The antenna assembly is then interconnected with the memory adapter board for the RF chip 4 integrated system by wafer bonding or other means. The resulting RF chip 4 integrated system can flexibly select and switch the system path according to the target response and has reconfigurable frequency response.

[0178] Please see Figure 31 The RF chip 4 integrated system includes a memristor switch matrix 9, two transmit channels, two receive channels, two sets of transmit antennas, and two sets of receive antennas. The transmit channels and the receive antennas are connected to the input terminal 9a of the memristor switch matrix 9, and the receive channels and the transmit antennas are connected to the output terminal 9b of the memristor switch matrix 9. Each transmit channel and receive channel is composed of three different chips.

[0179] As an example, the receiving channel includes GaAs chips and CMOS chips to implement low-noise amplification and amplitude-phase control functions, respectively, and the transmitting channel includes GaN chips and CMOS chips to implement power amplification and amplitude-phase control functions, respectively.

[0180] To verify the reconfigurable frequency response of the RF chip 4 integrated system based on the memory adapter board for the RF chip 4 integrated system, link simulation was performed in combination with each chip, and the frequency response and antenna gain pattern of the transmit and receive channels of the RF chip 4 integrated system under two typical operating states were obtained.

[0181] When the RF chip 4 integrated system is in the first typical operating state, please refer to Figure 32 Its radio frequency path is as follows Figure 32 As indicated by the arrows, the signal is transmitted from the transmitting channel to the transmitting antenna via the memristor switch matrix 9, then transmitted by the transmitting antenna to the receiving antenna, and finally transmitted by the receiving antenna to the receiving channel via the memristor switch matrix 9. See also... Figure 33a and Figure 33b In the first typical operating state, the center frequency of the transmit link is 25.25 GHz, which is the same as the center frequency of the receive link. The in-band gain of the transmit link is better than 15 dB, and the gain of the receive link is better than 5 dB. The gain patterns of the transmit and receive antennas can be obtained by superimposing the simulation results of the gain pattern at a single frequency point with the link gain, as shown below. Figure 34a and Figure 34b As shown, it can be seen that Figure 34a The transmitting antenna exhibits left-hand circular polarization characteristics, while Figure 34b In the middle, the receiving antenna exhibits right-hand circular polarization characteristics.

[0182] By utilizing the reconfigurable characteristics of the memristor switch matrix 9 in the memory adapter board for the RF chip 4 integrated system, the connection paths of the receive link and transmit link to the antenna are interchanged, resulting in a second typical operating state of the RF chip 4 integrated system. Please refer to [link to relevant documentation]. Figure 35 Its radio frequency path is as follows Figure 35 As indicated by the arrow, in the second typical operating state, please refer to... Figure 36a and Figure 36b The center frequency of the transmitting channel is 27 GHz, which is the same as the center frequency of the receiving link. The in-band gain of the transmitting channel is higher than 10 dB, and the gain of the receiving channel is higher than 5 dB. The gain patterns of the transmitting and receiving channels were analyzed at 27 GHz, as shown below. Figure 37a and Figure 37b As shown, Figure 37a China's transmitting antenna and Figure 37bThe receiving antennas exhibited both right-hand and left-hand circular polarization characteristics. These results verify that the memory adapter board used in the RF chip 4 integrated system can perform signal path modulation and achieve reconfigurable signal paths between RF chips 4.

[0183] The RF chip integration system in this embodiment uses the memory adapter board for RF chip integration systems described in Embodiment 2, which enables the reconfiguration of signal paths between RF chips.

[0184] In summary, the method for fabricating a memory adapter board for an integrated radio frequency (RF) chip system according to the present invention includes: providing a semiconductor substrate, the semiconductor substrate including a first surface and a second surface disposed opposite to each other, and the first surface of the semiconductor substrate including a middle portion and an edge portion surrounding the middle portion, the edge portion having a plurality of spaced grooves; forming a ground layer on the first surface of the semiconductor substrate and the inner wall of the grooves; providing a plurality of RF chips, each RF chip having a first surface and a second surface opposite to each other, the first surface having a metal pad, the second surface being a ground plane, the plurality of RF chips being placed in the plurality of grooves with the first surfaces facing upwards, such that the ground plane of the RF chip is electrically connected to the ground layer; forming a first redistribution layer on the first surface of the semiconductor substrate and the inner wall of the grooves. On the ground plane, a first redistribution layer is electrically connected to the metal pads of the RF chip, and the ground plane has an external portion exposed outside the first redistribution layer; a second redistribution layer is formed on the first redistribution layer, the second redistribution layer includes a non-wiring area and a wiring area surrounding the non-wiring area, and a conductive line layer of the second redistribution layer is disposed in the wiring area and electrically connected to the conductive line layer of the first redistribution layer; a memristor switch matrix is ​​formed on the non-wiring area, the memristor switch matrix includes multiple input terminals and multiple output terminals, each input terminal and each output terminal is electrically connected to the conductive line layer in the wiring area, so as to sequentially connect to the corresponding RF chip through the second redistribution layer and the first redistribution layer. The method for fabricating a memory-type adapter board for an RF chip integrated system of the present invention can meet the requirements of parasitic suppression, process simplification, and thickness reduction, and construct an RF chip integrated system with simple structure, process compatibility, low cost, and low power consumption. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0185] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for fabricating a memory-type adapter board for an integrated radio frequency chip system, characterized in that, include: A semiconductor substrate is provided, the semiconductor substrate including a first surface and a second surface disposed opposite to each other, and the first surface of the semiconductor substrate including a middle portion and an edge portion surrounding the middle portion, the edge portion having a plurality of spaced grooves; A ground layer is formed on the first surface of the semiconductor substrate and the inner wall of the groove; A plurality of radio frequency (RF) chips are provided, each of the RF chips having a first surface and a second surface facing away from each other. The first surface is provided with a metal pad, and the second surface is a ground plane. The plurality of RF chips are placed in the plurality of grooves with the first surfaces facing upwards, so that the ground plane of the RF chip is electrically connected to the ground plane. A first redistribution layer is formed on the ground layer, the first redistribution layer is electrically connected to the metal pads of the RF chip, and the ground layer has an external portion exposed outside the first redistribution layer; A second redistribution layer is formed on the first redistribution layer. The second redistribution layer includes a non-routing region and a wiring region surrounding the non-routing region. A conductive line layer of the second redistribution layer is disposed in the wiring region and is electrically connected to the conductive line layer of the first redistribution layer. A memristor switch matrix is ​​formed on the non-wiring area. The memristor switch matrix includes multiple input terminals and multiple output terminals. Each input terminal and each output terminal is electrically connected to the conductive line layer in the wiring area, so as to be electrically connected to the corresponding RF chip through the second redistribution layer and the first redistribution layer in sequence.

2. The method for fabricating a memory adapter board for an integrated radio frequency chip system according to claim 1, characterized in that, The steps of forming the first redistribution layer include: A first dielectric layer is formed on a first surface of the semiconductor substrate, the first dielectric layer covering the ground layer and the radio frequency chip, and the first dielectric layer is patterned to form a plurality of vias on the first dielectric layer that expose the ground layer and the first surface of the radio frequency chip; A first seed layer is formed on the first dielectric layer, the first seed layer covering the inner wall of the via and the first surface of the radio frequency chip exposed on the first dielectric layer; A first dry film layer is formed on the first seed layer, and the first dry film layer is patterned to form a plurality of openings corresponding to the through holes of the first dielectric layer in the first dry film layer; A first conductive pillar is formed in the through-hole of the first dielectric layer by electroplating, and the patterned first dry film layer is removed. A first photoresist layer is formed on the first seed layer and the conductive pillar, and the first photoresist layer is patterned. A first wiring conductive layer is formed on the first dielectric layer by electroplating, and the patterned first photoresist layer is removed. The first seed layer exposed outside the first wiring conductive layer is removed to obtain the first rewiring layer.

3. The method for fabricating a memory adapter board for an integrated radio frequency chip system according to claim 1, characterized in that, The steps for forming the second redistribution layer include: A second dielectric layer is formed on the first redistribution layer. The second dielectric layer includes a non-patterned region and a patterned region surrounding the non-patterned region. The second dielectric layer within the patterned region is patterned to form a plurality of vias that expose the first wiring conductive layer. A second seed layer is formed on the second dielectric layer, the second seed layer covering the inner wall of the via and the first wiring conductive layer exposed on the second dielectric layer; A second dry film layer is formed on the second seed layer, and the second dry film layer is patterned to form a plurality of openings corresponding to the through holes of the second dielectric layer in the second dry film layer; A second conductive pillar is formed in the through-hole of the second dielectric layer by electroplating, and the patterned second dry film layer is removed. A second photoresist layer is formed on the second seed layer and the second conductive pillar, and the second photoresist layer is patterned. A second wiring conductive layer is formed on the second dielectric layer by electroplating, and the patterned second photoresist layer is removed. The second seed layer exposed outside the second wiring conductive layer is removed to obtain the second rewiring layer.

4. The method for fabricating a memory adapter board for an integrated radio frequency chip system according to claim 3, characterized in that, The steps to form a memristor switching matrix include: Multiple bottom electrodes are formed on the second dielectric layer in the non-patterned area, and the bottom electrodes are spaced apart along the X direction, with both ends of each bottom electrode electrically connected to the two wiring conductive layers. A memristor functional layer is spin-coated onto the second dielectric layer within the non-patterned region, and the memristor functional layer covers the bottom electrode; The memristor functional layer is graphically represented, and the memristor functional layer outside the preset switch matrix unit area is removed to obtain the memristor functional layer unit. Multiple top electrodes are formed on the second dielectric layer in the non-patterned region, and the top electrodes are spaced apart along the Y direction and cover the memristor functional layer unit. The two ends of each top electrode are electrically connected to the two wiring conductive layer.

5. The method for fabricating a memory adapter board for an integrated radio frequency chip system according to claim 1, characterized in that: The thickness of the radio frequency chip is the same as the depth of the corresponding groove.

6. The method for fabricating a memory adapter board for an integrated radio frequency chip system according to claim 1, characterized in that: Before placing the multiple radio frequency chips with their active surfaces facing upwards into the multiple grooves, the method further includes the step of injecting conductive silver paste into the multiple grooves to form a conductive silver paste layer between the passive surface of the radio frequency chip and the inner wall of the groove.

7. The method for fabricating a memory adapter board for an integrated radio frequency chip system according to claim 1, characterized in that: The memristor functional layer includes the Nafion layer.

8. The method for fabricating a memory adapter board for an integrated radio frequency chip system according to claim 1, characterized in that: The radio frequency chips include GaAs chips, CMOS chips, and GaN chips.

9. A memory-type adapter board for use in radio frequency chip integrated systems, characterized in that, include: A semiconductor substrate, the semiconductor substrate including a first surface and a second surface disposed opposite to each other, wherein the first surface of the semiconductor substrate includes a middle portion and an edge portion surrounding the middle portion, and the edge portion has a plurality of spaced grooves. A grounding layer is located on the first surface of the semiconductor substrate and on the inner wall of the groove; Multiple radio frequency (RF) chips are placed in multiple grooves. Each RF chip has a first surface and a second surface facing away from each other. The first surface is provided with a metal pad, and the second surface is a ground plane. The first surfaces of the multiple RF chips face upwards, and the ground plane is electrically connected to the ground layer. A first redistribution layer is located on the ground layer, the first redistribution layer is electrically connected to the metal pads of the RF chip, and the ground layer has an external portion exposed outside the first redistribution layer; A second rerouting layer is located on the first rerouting layer. The second rerouting layer includes a non-routing area and a wiring area surrounding the non-routing area. A conductive line layer of the second rerouting layer is disposed in the wiring area and is electrically connected to the conductive line layer of the first rerouting layer. A memristor switch matrix is ​​located on the non-wiring area. The memristor switch matrix includes multiple input terminals and multiple output terminals. Each input terminal and each output terminal is electrically connected to the conductive line layer in the wiring area, so as to be electrically connected to the corresponding RF chip through the second rewiring layer and the first rewiring layer in sequence.

10. A radio frequency chip integration system, characterized in that, include: The memory adapter board and antenna assembly for a radio frequency chip integrated system according to claim 9, wherein the antenna assembly includes a support substrate and a transmitting antenna and a receiving antenna disposed on the support substrate, the support substrate is fastened to the side of the memory adapter board for the radio frequency chip integrated system having the second redistribution layer, the transmitting antenna is electrically connected to the output terminal of the memristor switch matrix through the second redistribution layer, the receiving antenna is electrically connected to the input terminal of the memristor switch matrix through the second redistribution layer, and the ground terminals of the transmitting antenna and the receiving antenna are both electrically connected to the external portion of the ground layer.

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