Substrate including conductive posts on pad structures

Abstract

In one aspect, a substrate for an integrated circuit (IC) package includes: a first dielectric layer; a first metallization layer on the first surface of the first dielectric layer and including a first pad structure and a first trace structure; a second metallization layer on a second surface of the first dielectric layer and including a second pad structure and a second trace structure; a second dielectric layer on the second surface of the first dielectric layer; and a third metallization layer on the second surface of the second dielectric layer and having a third pad structure. The substrate also includes a conductive pillar coupled to the second pad structure and a second via structure embedded in the second dielectric layer. A second via structure has a first end coupled to the conductive pillar and a second end coupled to the third pad structure.

Description

Technical Field

[0001] This disclosure relates generally to a substrate for an integrated circuit (IC) package, and more specifically to a substrate including conductive pillars on a pad structure. Background Technology

[0002] IC technology has made significant progress in improving computing power through the miniaturization of electronic components. An IC chip or IC die may include a set of circuitry integrated thereon. In some embodiments, an IC device can be formed by incorporating and protecting one or more IC chips or dies within an IC package, wherein various power and signal nodes of the one or more IC chips are electrically coupled to corresponding conductive terminals of the IC package via electrical paths formed in one or more packaging substrates of the IC package. Unless otherwise specified, the term "substrate" in this disclosure refers to a packaging substrate used to encapsulate one or more IC chips, which is different from the semiconductor substrate used to form the IC chips.

[0003] Various packaging technologies are found in many electronic devices, including processors, servers, radio frequency (RF) ICs, and so on. Advanced packaging and processing technologies enable complex devices such as multi-die devices and system-on-a-chip (SoC) devices, which may include multiple functional blocks, each designed to perform a specific function, such as microprocessor functions, graphics processing unit (GPU) functions, communication functions (e.g., Wi-Fi, Bluetooth, and other communications), etc.

[0004] For example, a PoP (PoS) packaging method can correspond to vertically combining discrete logic and / or memory chips or dies to reduce the size of IC devices. In some examples, the PoP packaging method can be used in conjunction with a molded embedded packaging method, which may be referred to as a molded embedded stacked package method or a MEP (Molded Embedded Package) method. In some examples, in IC packages formed based on PoP and / or MEP packaging methods, each chip can be mounted on a corresponding substrate, and a special type of substrate (also known as an interposer) can be used to couple the different substrates on which the chips are mounted.

[0005] In some examples, increasing the number of metallization layers on the substrate of the IC package can increase the wiring flexibility of the IC package and thus enhance the functionality and / or performance of the resulting IC device. In some examples, increasing the number of metallization layers on the substrate of the IC package can also increase the overall thickness of the IC package, which can affect the overall size of the electronic device incorporating the resulting IC device and thus negatively impact the overall product design constraints and / or market competitiveness of the electronic device.

[0006] Therefore, there is a need for improved substrates and manufacturing methods for IC packages to solve the above problems. Summary of the Invention

[0007] The following is a simplified summary of the invention relating to one or more aspects disclosed herein. Therefore, this summary should not be considered an exhaustive overview relating to all conceived aspects, nor should it be considered to identify key or decisive elements relating to all conceived aspects or to depict the scope associated with any particular aspect. Thus, the sole purpose of this summary is to present, in a simplified form, certain concepts relating to one or more aspects involving the mechanisms disclosed herein, prior to the detailed description presented below.

[0008] In one aspect, a substrate for an integrated circuit (IC) package includes: a first dielectric layer; a first metallization layer located on a first surface of the first dielectric layer, the first metallization layer including a first pad structure and a first trace structure; a second metallization layer located on a second surface of the first dielectric layer, the second metallization layer including a second pad structure and a second trace structure; a conductive pillar coupled to the second pad structure; a second dielectric layer located on the second surface of the first dielectric layer, the first surface of the second dielectric layer facing the second surface of the first dielectric layer, and the second metallization layer and the conductive pillar are at least partially embedded in the second dielectric layer; a second via structure embedded in the second dielectric layer, the second via structure having a first end coupled to the conductive pillar; and a third metallization layer located on the second surface of the second dielectric layer and having a third pad structure, the second via structure having a second end coupled to the third pad structure.

[0009] In one aspect, a method of manufacturing a substrate for an integrated circuit (IC) package includes: forming a first metallization layer on a first surface of a first dielectric layer, the first metallization layer including a first pad structure and a first trace structure; forming a second metallization layer on a second surface of the first dielectric layer, the second metallization layer including a second pad structure and a second trace structure; forming a conductive pillar coupled to the second pad structure; forming a second dielectric layer on the second surface of the first dielectric layer, the first surface of the second dielectric layer facing the second surface of the first dielectric layer, and the second metallization layer and the conductive pillar being at least partially embedded in the second dielectric layer; forming a second via structure embedded in the second dielectric layer, the second via structure having a first end coupled to the conductive pillar; and forming a third metallization layer located on the second surface of the second dielectric layer and having a third pad structure, the second via structure having a second end coupled to the third pad structure.

[0010] In one aspect, an electronic device includes an integrated circuit (IC) package comprising: a first dielectric layer; a first metallization layer located on a first surface of the first dielectric layer, the first metallization layer including a first pad structure and a first trace structure; a second metallization layer located on a second surface of the first dielectric layer, the second metallization layer including a second pad structure and a second trace structure; a conductive pillar coupled to the second pad structure; a second dielectric layer located on the second surface of the first dielectric layer, the first surface of the second dielectric layer facing the second surface of the first dielectric layer, and the second metallization layer and the conductive pillar being at least partially embedded in the second dielectric layer; a second via structure embedded in the second dielectric layer, the second via structure having a first end coupled to the conductive pillar; and a third metallization layer located on the second surface of the second dielectric layer and having a third pad structure, the second via structure having a second end coupled to the third pad structure.

[0011] Based on the accompanying drawings and detailed description, other objects and advantages associated with the aspects disclosed herein will be apparent to those skilled in the art. Attached Figure Description

[0012] The accompanying drawings are provided to help describe various aspects of this disclosure, and are provided for illustrative purposes only and not to limit the aspects.

[0013] Figure 1 This is a cross-sectional view of an integrated circuit (IC) package according to various aspects of this disclosure.

[0014] Figure 2A A portion of an example of a first substrate for an IC package is illustrated according to various aspects of this disclosure.

[0015] Figure 2B A portion of an example of a second substrate for an IC package is illustrated according to various aspects of this disclosure.

[0016] Figures 3A to 3J The structures at various stages of manufacturing a substrate for an IC package are illustrated according to various aspects of this disclosure.

[0017] Figure 4 Methods for manufacturing substrates for IC packages according to various aspects of this disclosure are illustrated.

[0018] Figure 5 Mobile devices according to various aspects of this disclosure are illustrated.

[0019] Figure 6Various electronic devices that can be incorporated into an IC package as described herein are illustrated according to various aspects of this disclosure.

[0020] By convention, the features depicted in the accompanying drawings may not be drawn to scale. Accordingly, for clarity, the dimensions of the depicted features may be arbitrarily enlarged or reduced. By convention, some drawings are simplified for clarity. Therefore, the drawings may not depict all components of a particular device or method. Furthermore, similar reference numerals are used throughout the specification and drawings to represent similar features. Detailed Implementation

[0021] Various aspects of this disclosure are provided below in the description of various examples provided for illustrative purposes and in the accompanying drawings. Alternative aspects may be devised without departing from the scope of this disclosure. Additionally, well-known elements of this disclosure will not be described in detail or will be omitted so as not to obscure the relevant details of this disclosure.

[0022] The terms “exemplary” and / or “example” are used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” and / or “example” is not necessarily to be construed as superior to or better than other aspects. Similarly, the term “aspects of this disclosure” does not require that all aspects of this disclosure include the features, advantages, or modes of operation discussed.

[0023] In some of the described example implementations, instances are identified where the various component structures and operational parts are derived from known conventional techniques and subsequently arranged according to one or more aspects. In such instances, the internal details of known conventional component structures and / or operational parts may be omitted to help avoid potential confusion with the concepts illustrated in the exemplary aspects disclosed herein.

[0024] The terminology used herein is for descriptive purposes only and is not intended to be limiting. As used herein, the singular forms “a,” “some,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprising,” “having,” “including,” and / or “containing,” when used herein, indicate the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. Furthermore, terms such as “approximately,” “generally,” etc., indicate that the examples provided are not intended to be limited to precise numerical values ​​or geometries and include normal variations due to manufacturing tolerances and variations, material variations, and other design considerations.

[0025] As noted above, various aspects generally relate to the fabrication of a substrate, which includes a metallization layer with a reduced thickness; and conductive pillars coupled to pad structures of the metallization layer to increase the overall margin for drilling openings to form a stacked via structure. In some aspects, the substrate may correspond to a package substrate (e.g., an interposer) in an IC package.

[0026] Specific aspects of the subject matter described in this disclosure can be implemented to achieve one or more of the following potential advantages. In some examples, the risk of drilling through the openings of the stacked via structure can be reduced without increasing the thickness of the metallization layer. Furthermore, the overall thickness of the IC package incorporated into such a substrate can be reduced.

[0027] Figure 1 This is a cross-sectional view of the IC package 100 according to various aspects of this disclosure. In some aspects, Figure 1 This is a simplified cross-sectional view of IC package 100, and some details and components of IC package 100 can be seen in... Figure 1 The Chinese characters are simplified or omitted.

[0028] In some aspects, such as Figure 1 As shown, the IC package 100 may be based on the PoP packaging method. The IC package 100 may include a first package portion 110 located above the second package portion 130, wherein an interposer layer 150 couples the first package portion 110 to the second package portion 130.

[0029] The first package portion 110 may include a first substrate 112 and a first package terminal 114 (e.g., solder bump or copper pillar bump) electrically coupling the first substrate 112 to an interposer 150. In some aspects, the first package terminal 114 may also be configured to mechanically couple the first substrate 112 and the interposer 150. The first package portion 110 may include a first IC chip 120 mounted on the first substrate 112 via a first IC terminal 122 (e.g., solder bump or copper pillar bump). In some aspects, the first package portion 110 may also include a first molding compound portion 118 disposed on the first substrate 112 and covering the first IC chip 120. In some aspects, the first molding compound portion 118 may surround only the first IC terminal 122 without covering the first IC chip 120. In some aspects, the first package portion 110 may not include the first molding compound portion 118. In some aspects, the first IC terminal 122, the first molding compound portion 118, or both may also be configured to mechanically couple the first IC chip 120 and the first substrate 112.

[0030] The second package portion 130 may include a second substrate 132 and second package terminals 134 (e.g., solder bumps or copper pillar bumps) for electrically coupling the IC package 100 to an external component (such as a circuit board). The second package portion 130 may include a second IC chip 140 mounted on the second substrate 132 via second IC terminals 142 (e.g., solder bumps or copper pillar bumps). The second package portion 130 may include conductive structures 136 (e.g., solder bumps, copper pillar bumps, or vias) electrically coupling the second substrate 132 to an interposer 150. In some aspects, the second package portion 130 may also include a second molding compound portion 138 disposed on the second substrate 132 and covering the second IC chip 140. In some aspects, the second molding compound portion 138 may surround the conductive structure 136. In some aspects, the second molding compound portion 138 may only surround the second IC terminals 142, without covering the second IC chip 140 and / or without surrounding the conductive structure 136. In some respects, the second encapsulation portion 130 may not include the second molding compound portion 138.

[0031] In some aspects, the second IC terminal 142, the second molding compound portion 138, or both may be configured to mechanically couple the second IC chip 140 and the second substrate 132. In some aspects, the conductive structure 136, the second molding compound portion 138, or both may be configured to mechanically couple the second substrate 132 and the interposer 150.

[0032] As used herein, the interposer 150 is configured to electrically couple substrates 112 and 132, and in some respects, couples IC chips 120 and 140 through substrates 112 and 132 and additional components (e.g., other IC chips, active components such as discrete transistors or operational amplifiers, and / or passive components such as resistors, capacitors and / or inductors) optionally formed on or embedded in substrates 112 and / or substrates 132.

[0033] It should be understood that the illustrated configurations and descriptions provided herein are merely illustrative of the various aspects disclosed herein. Therefore, the above illustrative examples should not be construed as limiting the various aspects disclosed and claimed herein.

[0034] Figure 2A A portion of a first substrate example 200A for an IC package according to various aspects of the present disclosure is illustrated. In some aspects, the first substrate example 200A may correspond to Figure 1 The first substrate 112, the second substrate 132, or the interlayer 150 are in the middle.

[0035] like Figure 2AAs shown, the first substrate example 200A may include a first dielectric layer 210, a first metallization layer 220 located on a first surface 212 of the first dielectric layer 210, and a second metallization layer 230 located on a second surface 214 of the first dielectric layer 210. The first dielectric layer 210 may include a dielectric material in which pre-impregnated reinforcing components are embedded. In some aspects, the first dielectric layer 210 may include a prepreg (also referred to as PPG), which may contain a polymer resin in which fiberglass sheets are impregnated. In some aspects, the thickness T of the first dielectric layer 210 is... D1 It is available in the range of 15 micrometers (µm) to 30 µm. In some aspects, the thickness T D1 It can be approximately 20µm.

[0036] The first metallization layer 220 may include one or more trace structures 222 and 224 and one or more pad structures 226. In some aspects, the thickness T of the one or more trace structures 222 and 224 and / or the one or more pad structures 226 is... M1 It can be in the range of 10µm to 15µm. In some aspects, the thickness T M1 The thickness can be approximately 13µm. In some aspects, the first metallization layer 220 may comprise a conductive material such as copper. The second metallization layer 230 may comprise one or more trace structures 232 and 234 and one or more pad structures 236. In some aspects, the thickness T of the one or more trace structures 232 and 234 and / or the one or more pad structures 236 is... M2 It is available in the range of 8µm to 15µm. In some aspects, the thickness T M2 It can be about 10µm. In some aspects, the second metallization layer 230 may contain a conductive material such as copper.

[0037] like Figure 2A As shown, the first substrate example 200A may include a second dielectric layer 240 located on a second surface 214 of the first dielectric layer 210. In some aspects, a first surface 242 of the second dielectric layer 240 may face the second surface 214 of the first dielectric layer 210. In some aspects, a second metallization layer 230 may be at least partially embedded in the second dielectric layer 240. In some aspects, the thickness T of the portion of the second dielectric layer extending beyond the second metallization layer 230 is measured. D2+ It is available in the range of 18µm to 30µm. In some aspects, the thickness T D2+ It can be approximately 22µm. In some respects, the overall thickness T of the second dielectric layer 240 is... D2 It is available in the range of 26µm to 45µm.

[0038] like Figure 2AAs shown, the first substrate example 200A may include a third metallization layer 250 located on a second surface 244 of the second dielectric layer 240. The third metallization layer 250 may include one or more trace structures 252 and one or more pad structures 254 and 256. In some aspects, the thickness T of the one or more trace structures 252 and / or the one or more pad structures 254 and 256... M3 It can be in the range of 10µm to 15µm. In some aspects, the thickness T M3 It can be approximately 13µm. In some aspects, the third metallization layer 250 may contain a conductive material such as copper.

[0039] Furthermore, the first substrate example 200A may include a first solder resist layer 260 covering at least a portion of the first surface 212 of the first dielectric layer 210 and a portion of the first metallization layer 220. For example, the first solder resist layer 260 may have an opening 262 defined therein that exposes a portion of the pad structure 226. In some aspects, the thickness T of the portion of the first solder resist layer 260 extending beyond the first metallization layer 220 is measured. S1+ It is available in the range of 10µm to 15µm. In some aspects, T S1+ It can be approximately 12µm.

[0040] Furthermore, the first substrate example 200A may include a second solder resist layer 270 covering at least a portion of the second surface 244 of the second dielectric layer 240 and a portion of the third metallization layer 250. For example, the second solder resist layer 270 may have an opening 272 defined therein, which exposes a portion of the pad structure 256. In some aspects, the thickness T of the portion of the second solder resist layer 270 extending beyond the third metallization layer 250 is measured. S2+ It is available in the range of 10µm to 15µm. In some aspects, T S2+ It can be approximately 12µm.

[0041] like Figure 2A As shown, the first substrate example 200A may include a first via structure 282 embedded in the first dielectric layer 210 and a second via structure 284 embedded in the second dielectric layer 240. In some aspects, the first via structure 282 may include a first end coupled to a pad structure 236 and a second end coupled to a pad structure 226. In some aspects, the second via structure 284 may include a first end coupled to a pad structure 236 and a second end coupled to a pad structure 254. In some aspects, one or more bump structures ( Figure 2A (Not shown) may be formed in openings 262 and 272 and electrically coupled to pad structures 226 and 256.

[0042] In some aspects, the first via structure 282 and the second via structure 284 may comprise a conductive material such as copper. In some aspects, the first via structure 282 may be formed based on an opening through the first dielectric layer 210, and such an opening may be defined by performing a mechanical drilling process or a laser drilling process (e.g., using a CO2 laser) from the top of the first substrate example 200A (indicated by an arrow labeled "from top"). Similarly, the second via structure 284 may be formed based on an opening through the second dielectric layer 240, and such an opening may be defined by performing another mechanical drilling process or another laser drilling process (e.g., using a CO2 laser) from the bottom of the first substrate example 200A (indicated by an arrow labeled "from bottom").

[0043] In some aspects, to reduce the overall thickness of an IC package (e.g., IC package 100), one approach is to reduce the thickness of the substrate (e.g., substrate 112, substrate 132, or interposer 150). Figure 2A In the example shown, the thickness of the second metallization layer 230 can be reduced (e.g., thickness T). M2 However, a thinner thickness increases the risk of penetrating the pad structure 236 during a laser drilling process used to define the openings of the first and second via structures 282. In some aspects, the openings can be filled with copper using a copper plating process, and during this process, the penetrated pad structure may introduce voids or cracks in the first and / or second via structures 282. This can lead to reduced reliability of stacked vias (e.g., one of the first via structure 282 and the second via structure 284 stacked on top of the other). To address this reliability issue, one approach is to increase (or not decrease) the thickness of the second metallization layer 230, which could result in a thicker substrate. Another approach is to avoid having stacked vias, which can limit the wiring flexibility of the substrate and thus lead to performance degradation.

[0044] Figure 2B A portion of a second substrate example 200B for an IC package according to various aspects of this disclosure is illustrated. In some aspects, the second substrate example 200B may correspond to Figure 1 The first substrate 112, the second substrate 132, or the interposer 150 are used. In some aspects, various components of the second substrate example 200B that are the same as or similar to those of the first substrate example 200A are given the same reference numerals, and detailed descriptions of these components may be omitted.

[0045] like Figure 2BAs shown, the difference between the second substrate example 200B and the first substrate example 200A is that the thickness of the second metallization layer 230' in the second substrate example 200B is less than the thickness of the second metallization layer 230 in the first substrate example 200A, and the conductive pillar 290 is disposed between the pad structure 236' and the second via structure 284'.

[0046] like Figure 2B As shown, the second substrate example 200B may include a first dielectric layer 210, a first metallization layer 220, and a third metallization layer 250 that are the same as or similar to the corresponding components of the first substrate example 200A. The second metallization layer 230' of the second substrate example 200B may have a thickness T that is less than that of the second metallization layer 230 of the first substrate example 200A. M2 Thickness T M2 In some aspects, the second substrate example 200B may include a second dielectric layer 240', which can be made of a dielectric layer having a thickness T. D2 Reduced overall thickness T D2 Unlike the second dielectric layer 240 in the second substrate example 200B, the second dielectric layer 240 may not contain embedded glass fibers in some aspects. In some aspects, it may be based on an Ajinomoto deposited film. ® (ABF), photoimageable dielectric (PID) and / or resin-coated copper (RCC) are used to form the second dielectric layer 240'.

[0047] In some aspects, the second metallization layer 230' of the second substrate example 200B may include one or more trace structures 232' and 234' and one or more pad structures 236'. In some aspects, the thickness T of the one or more trace structures 232' and 234' and / or the one or more pad structures 236' is... M2 It can be equal to or less than 6µm. In some aspects, the thickness T M2 The thickness can range from 2µm to 5µm. In some aspects, the second metallization layer 230' may contain a conductive material such as copper. In some aspects, the thickness T of the portion of the second dielectric layer 240' extending beyond the second metallization layer 230' is measured. D2+ It can be in the range of 18µm to 30µm, or it can be the same thickness T as the first substrate example 200A. D2+ similar.

[0048] like Figure 2BAs shown, the second substrate example 200B may include a conductive post 290 coupled to the pad structure 236'. In some aspects, the conductive post 290 may comprise a conductive material such as copper. In some aspects, the second via structure 284' of the second substrate example 200B may include a first end coupled to the conductive post 290 and a second end coupled to the pad structure 254. In some aspects, the thickness T of the conductive post 290 is... STUD It can be in the range of 5µm to 30µm. Therefore, the thickness of one or more trace structures 232' and 234' (which can be determined by thickness T) M2' (Indicated) can be less than the combined thickness of pad structure 236' and conductive post 290 (which can be determined by thickness T) M2' and thickness T STUD The sum is represented by ( ).

[0049] In some aspects, compared to the first substrate example 200A, the conductive pillars 290 of the second substrate example 200B can increase the effective thickness of the conductive material for the drilling process of the via structure 284'. Therefore, the incorporation of the conductive pillars 290 can mitigate the risk of drill penetration without increasing (or further reducing) the thickness of the second metallization layer 230'. Thus, the thickness of the second substrate example 200B and the overall thickness of the IC package incorporated into the second substrate example 200B can be reduced. In some aspects, reducing the thickness of the second metallization layer 230' can also reduce the risk of glass contact on the first dielectric layer 210. In some aspects, glass contact problems may correspond to glass fibers in the prepreg material or core layer of the first dielectric layer 210 contacting the metal layer (e.g., the second metallization layer 230'), which may lead to copper migration and thus may fail to meet certain reliability requirements, such as those required for bias high accelerated stress testing (BHAST).

[0050] Figures 3A to 3J Examples of substrates (such as those used in the manufacture of IC packages) according to various aspects of this disclosure are illustrated. Figure 2B The structure of each stage of the second substrate (Example 200B) in the example. Figures 3A to 3J exemplified with Figure 2B Components that are the same as or similar to those in the figures are given the same reference numerals, and detailed descriptions of these components may be omitted.

[0051] like Figure 3A As shown, a structure 300A is provided, including a first conductive layer 312 and a carrier 314 disposed on the first conductive layer 312. In some aspects, the first conductive layer 312 may comprise a conductive material such as copper. In some aspects, the carrier 314 may comprise an insulating panel that can be chemically and / or mechanically removed from the first conductive layer 312 at a later stage. In some aspects, structure 300A may be based on a removable copper foil structure that can be used as a pre-manufactured component.

[0052] like Figure 3B As shown, structure 300B is formed by attaching a first dielectric layer 210 to structure 300A (e.g., a removable copper foil structure) and forming a second conductive layer 316 on a second surface 214 of the first dielectric layer 210. In some aspects, the first conductive layer 312 may be located on the first surface 212 of the first dielectric layer 210. In some aspects, the first dielectric layer 210 may include a dielectric material in which pre-impregnated reinforcing components are embedded. In some aspects, the dielectric material may include resin, and the reinforcing components may include glass fiber. In some aspects, the resin may be in an uncured or incompletely cured state during the attachment of the first dielectric layer 210 to structure 300A, and is subsequently cured to complete structure 300B. In some aspects, the second conductive layer 316 may comprise a conductive material such as copper.

[0053] In some aspects, the first dielectric layer 210 may have a second conductive layer 316 pre-fabricated thereon before being attached to the structure 300A. In some aspects, the first dielectric layer 210 may be laminated to the structure 300A first, and then the second conductive layer 316 may be laminated to the first dielectric layer 210.

[0054] like Figure 3C As shown, structure 300C is formed based on structure 300B by forming a second metallization layer 230' on the second surface 214 of the first dielectric layer 210 based on the second conductive layer 316. In some aspects, the second metallization layer 230' may include pad structures 236' and trace structures 232' and 234'. In some aspects, the second metallization layer 230' may be formed by patterning the second conductive layer 316 to form a conductive pattern, performing a plating process to increase the thickness of the conductive pattern, and optionally performing an etching and / or cleaning process to remove excess conductive material on the second surface 214 of the first dielectric layer 210. In some aspects, the material and thickness of the second metallization layer 230' may be as described above. Figure 2B The discussion.

[0055] like Figure 3D As shown, structure 300D is formed based on structure 300C by performing a mask process to form a patterned mask layer 322 that covers a trace structure (e.g., trace structures 232' and 234') of the second metallization layer 230' and exposes a portion of the pad structure (e.g., pad structure 236') of the second metallization layer 230'.

[0056] like Figure 3EAs shown, structure 300E is formed based on structure 300D by performing a plating process using a patterned mask layer 322 as a mask to form conductive pillars 324 and 290 on the corresponding pad structures (e.g., conductive pillar 290 on pad structure 236'). After forming the conductive pillars 324 and 290, the patterned mask layer 322 can be removed. In some aspects, the material and thickness of the conductive pillar 290 may be as referenced above. Figure 2B The material and thickness discussed can also be applied to conductive post 324.

[0057] like Figure 3F As shown, structure 300F is formed based on structure 300E by forming a second dielectric layer 240' on the second surface 214 of the first dielectric layer 210 and forming a third conductive layer 332 on the second dielectric layer 240'. In some aspects, the first surface 242' of the second dielectric layer 240' may be arranged to face the second surface 214 of the first dielectric layer 210. In some aspects, the second metallization layer 230' and the conductive pillars 324 and 290 may be at least partially embedded in the second dielectric layer 240'.

[0058] In some aspects, the second dielectric layer 240' and the third conductive layer 332 may be based on an RCC layer that can be used as a pre-manufactured component. In some aspects, the second dielectric layer 240' and the third conductive layer 332 may be formed by attaching the RCC layer to the first dielectric layer 210 after the formation of the second metallization layer 230' and the conductive pillars 324 and 290. In some aspects, the second dielectric layer 240' may include a resin that is in an uncured or incompletely cured state during the stage of attaching the RCC layer to the first dielectric layer 210, and may subsequently be cured to complete the structure 300F.

[0059] In some aspects, the second dielectric layer 240' may not contain embedded glass fibers. In other aspects, the second dielectric layer 240' may be formed based on ABF, PID, and / or RCC.

[0060] like Figure 3G As shown, structure 300G is formed based on structure 300F by removing carrier 314 after forming conductive pillars 324 and 290 to expose the first conductive layer 312. In some aspects, carrier 314 may be mechanically removed from the first conductive layer 312 (e.g., by mechanical cutting or peeling).

[0061] like Figure 3HAs shown, structure 300H is formed based on structure 300G by forming first openings 342, 344, and 346 through the first conductive layer 312 and the first dielectric layer 210 to expose at least a portion of the pad structure of the second metallization layer 230' (e.g., the first opening 346 exposes a portion of the pad structure 236'); and forming second openings 352, 354, and 356 through the third conductive layer 332 and the second dielectric layer 240' to expose at least a portion of the conductive pillars 324 and 290 (e.g., the second opening 356 exposes a portion of the conductive pillar 290). In some aspects, the first openings 342, 344, and 346 and the second openings 352, 354, and 356 may be formed based on mechanical drilling or laser drilling (e.g., by using a CO2 laser). In some respects, because the conductive post (e.g., conductive post 290) increases the overall margin for drilling openings (e.g., first opening 346 and second opening 356), the risk of the drilling process penetrating openings 346 and 356 can be reduced without increasing the thickness of the second metallization layer 230'.

[0062] like Figure 3I As shown, structure 300I is formed based on structure 300H in the following manner: a first metallization layer 220 is formed on the first surface 212 of the first dielectric layer 210 based on the first conductive layer 312; a third metallization layer 250 is formed on the second surface 244 of the second dielectric layer 240 based on the third conductive layer 332; first via structures 362, 364 and 282 are formed based on the first openings 342, 344 and 346; and second via structures 372, 374 and 284' are formed based on the second openings 352, 354 and 356.

[0063] In some aspects, the first metallization layer 220 may include pad structures (e.g., pad structure 226) and trace structures (e.g., trace structures 222 and 224). In some aspects, the first metallization layer 220 may be formed by patterning the first conductive layer 312 to form a conductive pattern, performing a plating process to increase the thickness of the conductive pattern (and filling the first openings 342, 344, and 346 to form first via structures 362, 364, and 282), and optionally performing etching and / or cleaning processes to remove excess conductive material on the first surface 212 of the first dielectric layer 210. In some aspects, the material and thickness of the first metallization layer 220 may be as described above. Figure 2B The discussion.

[0064] In some aspects, the third metallization layer 250 may include pad structures (e.g., pad structures 254 and 256) and trace structures (e.g., trace structure 252). In some aspects, the third metallization layer 250 may be formed by patterning the third conductive layer 332 to form a conductive pattern, performing a plating process to increase the thickness of the conductive pattern (and filling the second openings 352, 354, and 356 to form second via structures 372, 374, and 284'), and optionally performing etching and / or cleaning processes to remove excess conductive material on the second surface 244' of the second dielectric layer 240'. In some aspects, the material and thickness of the third metallization layer 250 may be as described above. Figure 2B The discussion.

[0065] like Figure 3J As shown, structure 300J is formed based on structure 300I by forming a first solder resist layer 260 covering at least a portion of the first surface 212 of the first dielectric layer 210 and a portion of the first metallization layer 220; and forming a second solder resist layer 270 covering at least a portion of the second surface 244' of the second dielectric layer 240' and a portion of the third metallization layer 250. In some aspects, Figure 3J Region 380 in the middle can correspond to Figure 2B A portion of the second substrate example 200B depicted in the image.

[0066] Figure 4 A method 400 for manufacturing a substrate (such as a substrate for an IC package incorporating features of a second substrate example 200B or structure 300J) according to various aspects of this disclosure is illustrated. In some aspects, Figures 3A to 3J It can depict substrates at different manufacturing stages according to method 400.

[0067] At operation 410, a first metallization layer (e.g., first metallization layer 220) may be formed on a first surface of the first dielectric layer (e.g., first dielectric layer 210). In some aspects, the first metallization layer may include a first pad structure (e.g., pad structure 226) and a first trace structure (e.g., trace structure 224). In some aspects, the first metallization layer may be formed based on a first conductive layer (e.g., first conductive layer 312) on the first surface of the first dielectric layer.

[0068] In some aspects, method 400 may further include attaching a first dielectric layer to a removable copper foil structure (e.g., structure 300A), wherein the removable copper foil structure may include a first conductive layer and a carrier (e.g., carrier 314) disposed on the first conductive layer. In some aspects, the first dielectric layer 210 may include a dielectric material in which pre-impregnated reinforcing components are embedded. In some aspects, the first conductive layer may comprise a conductive material such as copper.

[0069] At operation 420, a second metallization layer (e.g., second metallization layer 230') may be formed on the second surface of the first dielectric layer. In some aspects, the second metallization layer may include a second pad structure (e.g., pad structure 236') and a second trace structure (e.g., trace structure 234'). In some aspects, the second metallization layer may be formed based on a second conductive layer (e.g., second conductive layer 316) on the second surface of the first dielectric layer. In some aspects, the first dielectric layer may have a second conductive layer formed thereon pre-fabricated before being attached to the removable copper foil structure.

[0070] At operation 430, a conductive pillar (e.g., conductive pillar 290) may be formed, wherein the conductive pillar is coupled to the second pad structure. In some aspects, the conductive pillar may be formed based on performing a masking process and performing a plating process, as referenced. Figure 3D and Figure 3E exemplified.

[0071] At operation 440, a second dielectric layer (e.g., second dielectric layer 240') may be formed on a second surface of the first dielectric layer. In some aspects, a first surface of the second dielectric layer (e.g., surface 242') may face a second surface of the first dielectric layer (e.g., surface 214), and a second metallization layer and conductive pillars may be at least partially embedded in the second dielectric layer. In some aspects, operation 440 may include attaching an RCC layer to the first dielectric layer after forming the second metallization layer and conductive pillars. In some aspects, the RCC layer includes the second dielectric layer and a third conductive layer (e.g., third conductive layer 332) on the second dielectric layer.

[0072] In some aspects, the second dielectric layer 240' may not contain embedded glass fibers. In other aspects, the second dielectric layer 240' may be formed based on ABF, PID, and / or RCC.

[0073] At operation 450, a second via structure (e.g., via structure 284') may be formed. In some aspects, the second via structure may be embedded in a second dielectric layer. In some aspects, the second via structure may have a first end coupled to a conductive post. In some aspects, the second via structure may be formed by forming a second opening (e.g., opening 356) through the second conductive layer and the second dielectric layer to expose at least a portion of the conductive post, and the second via structure is formed based on the second opening.

[0074] In some aspects, operation 450 may further include forming a first via structure (e.g., via structure 282) embedded in a first dielectric layer and having a first end coupled to a first pad structure. In some aspects, the first via structure may have a first end coupled to the first pad structure. In some aspects, the first via structure may be formed based on: removing a carrier after forming a conductive pillar to expose a first conductive layer, forming a first opening (e.g., opening 346) through the first conductive layer and the first dielectric layer to expose at least a portion of a second pad structure, and forming the first via structure based on the first opening. In some aspects, such as Figure 3I As shown, the first metallization layer and the first via structure can be formed based on the same plating process.

[0075] At operation 460, a third metallization layer (e.g., third metallization layer 250) is located on the second surface of the second dielectric layer and has a third pad structure (e.g., pad structure 254). In some aspects, the second via structure may have a second end coupled to the third pad structure. In some aspects, such as Figure 3I As shown, the third metallization layer and the second via structure can be formed based on the same plating process.

[0076] After operating 460, in such Figure 3J As shown in some aspects, a first solder resist layer (e.g., first solder resist layer 260) may be formed covering at least a portion of the first surface of the first dielectric layer and a portion of the first metallization layer. After operation 460, in such... Figure 3J In some aspects shown, a second solder resist layer (e.g., second solder resist layer 270) may be formed covering at least a portion of the second surface of the second dielectric layer and a portion of the third metallization layer.

[0077] In some respects, the width of the conductive post may be smaller than the width of the second pad structure. In some respects, the thickness of the second trace structure or the thickness of the second pad structure may be equal to or less than 6µm. In some respects, the thickness of the conductive post may be equal to or greater than 5µm.

[0078] The technical advantage of method 400 corresponds to the fabrication of a substrate including a metallization layer with reduced thickness; and conductive pillars coupled to pad structures of the metallization layer to increase the overall margin for drilling openings to form a stacked via structure. Therefore, the risk of drilling through openings in the stacked via structure can be reduced without increasing the thickness of the metallization layer. The overall thickness of IC packages incorporated into such a substrate can be reduced. Furthermore, the reliably stacked via structure according to method 400 can reduce the size of the via structure and / or provide better wiring capabilities.

[0079] Figure 5A mobile device 500 according to various aspects of this disclosure is illustrated. In some aspects, the mobile device 500 may be implemented by including one or more IC devices having a package substrate as disclosed herein.

[0080] In some aspects, the mobile device 500 can be configured as a wireless communication device. As shown, the mobile device 500 includes a processor 501. The processor 501 is communicatively coupled to a memory 532 via a link, which can be a die-to-die or chip-to-chip link. The mobile device 500 also includes a display 528 and a display controller 526, wherein the display controller 526 is coupled to the processor 501 and the display 528. The mobile device 500 may include an input device 530 (e.g., a physical or virtual keyboard), a power supply 544 (e.g., a battery), a speaker 536, a microphone 538, and a wireless antenna 542. In some aspects, the power supply 544 may directly or indirectly provide power voltage for some or all of the components of the mobile device 500.

[0081] In some respects, Figure 5 It may include a decoder / decoder (codec) 534 (e.g., an audio and / or voice codec) coupled to processor 501; a speaker 536 and a microphone 538 coupled to codec 534; and a wireless circuit 540 (which may include a modem, RF circuitry, filters, etc.) coupled to wireless antenna 542 and processor 501.

[0082] In some aspects, one or more of the processor 501 (e.g., SoC, application processor (AP)), display controller 526, memory 532, codec 534, and wireless circuit 540 (e.g., baseband interface) include an IC device packaged as an IC package and include a package substrate according to the various aspects described in this disclosure.

[0083] It should be noted that, although Figure 5 Mobile device 500 is described, but similar architectures can be used to implement devices including set-top boxes, music players, video players, entertainment units, navigation devices, personal digital assistants (PDAs), fixed location data units, computers, laptop computers, tablet computers, communication devices, mobile phones, or other similar devices.

[0084] Figure 6 Various electronic devices 610, 620 and 630 that can be incorporated into IC devices 612, 622 and 632 according to aspects of this disclosure are illustrated, and these IC devices can be packaged as IC packages having a packaging substrate described herein.

[0085] For example, mobile phone device 610, laptop computer device 620, and fixed-location terminal device 630 can each generally be considered as user equipment (UE) and may include one or more IC devices (such as IC devices 612, 622, and 632) and a power supply for providing a power supply voltage to power the IC devices. IC devices 612, 622, and 632 may, for example, correspond to being packaged with [features] based on the foregoing reference. Figure 2B and Figures 3A to 3J The example described is an IC device with an IC packaged substrate manufactured using this method.

[0086] Figure 6 The devices 610, 620, and 630 illustrated herein are merely non-limiting examples. Other electronic devices may also feature IC devices on a packaged substrate as described in this disclosure, including but not limited to devices (e.g., electronic devices) comprising: mobile devices, handheld personal communication system (PCS) units, portable data units (such as personal digital assistants), GPS-enabled devices, navigation devices, set-top boxes, music players, video players, entertainment units, fixed-location data units (such as instrument reading devices), communication devices, smartphones, tablet computers, computers, wearable devices, servers, routers, electronic devices implemented in motor vehicles (e.g., autonomous vehicles), Internet of Things (IoT) devices, access points, base stations, or any other device or any combination thereof that stores or retrieves data or computer instructions.

[0087] It should be understood that the various aspects disclosed herein can be described as functional equivalents of structures, materials, and / or devices as described and / or understood by those skilled in the art. For example, in one aspect, the apparatus may include components for performing the various functions discussed above. It should be understood that the foregoing aspects are provided by way of example only, and the claimed aspects are not limited to the specific references and / or illustrations cited as examples.

[0088] Figures 1 to 6 One or more of the components, processes, features, and / or functions illustrated herein may be rearranged and / or combined into a single component, process, feature, or function, or incorporated into several components, processes, or functions. Additional elements, components, processes, and / or functions may also be added without departing from this disclosure. In some specific embodiments, Figures 1 to 6 The corresponding descriptions can be used to manufacture, create, supply, and / or produce integrated devices. In some specific implementations, the equipment may include dies, integrated devices, die packages, ICs, device packages, IC packages, wafers, semiconductor devices, system-in-package (SiP), system-on-a-chip (SoC), and stacked-package (PoP) devices, etc.

[0089] As can be seen in the detailed description above, different features are grouped together in the examples. This manner of disclosure should not be construed as an intention to have more features than those explicitly mentioned in each clause. Rather, the various aspects of this disclosure may include fewer features than those in the individual example clauses disclosed. Therefore, the following clauses should be regarded accordingly as incorporated into the description, where each clause may serve as a separate example. Although each dependent clause may refer in the clause to a specific combination with one of the other clauses, the aspect of that dependent clause is not limited to that specific combination. It should be understood that other example clauses may also include combinations of aspects of a dependent clause with the subject matter of any other dependent or independent clause, or combinations of any feature with other dependent and independent clauses. The various aspects disclosed herein explicitly include these combinations unless explicitly stated or readily inferred that a particular combination is not intended for use (e.g., contradictory aspects, such as defining an element as both an electrical insulator and an electrical conductor). Furthermore, it is contemplated that aspects of a clause may be included in any other independent clause, even if that clause does not directly depend on the independent clause.

[0090] Specific implementation examples are described in the following numbered clauses: Clause 1. A substrate for an integrated circuit (IC) package, the substrate comprising: a first dielectric layer; a first metallization layer located on a first surface of the first dielectric layer, the first metallization layer including a first pad structure and a first trace structure; a second metallization layer located on a second surface of the first dielectric layer, the second metallization layer including a second pad structure and a second trace structure; a conductive pillar coupled to the second pad structure; a second dielectric layer located on the second surface of the first dielectric layer, the first surface of the second dielectric layer facing the second surface of the first dielectric layer, and the second metallization layer and the conductive pillar being at least partially embedded in the second dielectric layer; a second via structure embedded in the second dielectric layer, the second via structure having a first end coupled to the conductive pillar; and a third metallization layer located on the second surface of the second dielectric layer and having a third pad structure, the second via structure having a second end coupled to the third pad structure.

[0091] Clause 2. The substrate according to Clause 1, the substrate further comprising: a first solder resist layer covering at least a portion of the first surface of the first dielectric layer and a portion of the first metallization layer; and a second solder resist layer covering at least a portion of the second surface of the second dielectric layer and a portion of the third metallization layer.

[0092] Clause 3. The substrate according to any one of Clauses 1 to 2, the substrate further comprising: a first via structure embedded in the first dielectric layer, the first via structure having a first end coupled to the second pad structure and a second end coupled to the first pad structure of the first metallization layer.

[0093] Clause 4. The substrate according to any one of Clauses 1 to 3, wherein the width of the conductive pillar is less than the width of the second pad structure.

[0094] Clause 5. The substrate according to any one of Clauses 1 to 4, wherein the thickness of the second trace structure is less than the combined thickness of the second pad structure and the conductive pillar.

[0095] Clause 6. The substrate according to any one of Clauses 1 to 5, wherein: the thickness of the second trace structure or the thickness of the second pad structure is equal to or less than 6 micrometers (µm).

[0096] Clause 7. The substrate according to Clause 6, wherein: the thickness of the second trace structure or the thickness of the second pad structure is in the range of 2µm to 5µm.

[0097] Clause 8. The substrate according to any one of Clauses 1 to 7, wherein: the thickness of the conductive pillar is equal to or greater than 5 micrometers (µm).

[0098] Clause 9. The substrate according to Clause 8, wherein the thickness of the conductive pillar is in the range of 5µm to 30µm.

[0099] Clause 10. The substrate according to any one of Clauses 1 to 9, wherein: no glass fibers are embedded in the second dielectric layer.

[0100] Clause 11. A method of manufacturing a substrate for an integrated circuit (IC) package, the method comprising: forming a first metallization layer on a first surface of a first dielectric layer, the first metallization layer including a first pad structure and a first trace structure; forming a second metallization layer on a second surface of the first dielectric layer, the second metallization layer including a second pad structure and a second trace structure; forming a conductive pillar coupled to the second pad structure; forming a second dielectric layer on the second surface of the first dielectric layer, the first surface of the second dielectric layer facing the second surface of the first dielectric layer, and the second metallization layer and the conductive pillar being at least partially embedded in the second dielectric layer; forming a second via structure embedded in the second dielectric layer, the second via structure having a first end coupled to the conductive pillar; and forming a third metallization layer located on the second surface of the second dielectric layer and having a third pad structure, the second via structure having a second end coupled to the third pad structure.

[0101] Clause 12. The method according to Clause 11, wherein forming the conductive pillar includes performing a masking process and performing a plating process.

[0102] Clause 13. The method according to any one of Clauses 11 to 12, wherein forming the second dielectric layer includes attaching a resin-coated copper layer to the first dielectric layer after forming the second metallization layer and the conductive pillar.

[0103] Clause 14. The method according to any one of Clauses 11 to 13, the method further comprising: attaching the first dielectric layer to a removable copper foil structure, the removable copper foil structure including a first conductive layer on a first surface of the first dielectric layer and a carrier disposed on the first conductive layer; and forming a second conductive layer on a second surface of the first dielectric layer, wherein the first metallization layer is formed based on the first conductive layer, and the second metallization layer is formed based on the second conductive layer.

[0104] Clause 15. The method according to Clause 14, the method further comprising: after forming the conductive pillar, removing the carrier to expose the first conductive layer; forming a first opening through the first conductive layer and the first dielectric layer to expose at least a portion of the second pad structure; and forming a first via structure based on the first opening, the first via structure being embedded in the first dielectric layer and having a first end coupled to the first pad structure.

[0105] Clause 16. The method according to any one of Clauses 14 to 15, wherein forming the second via structure comprises: forming a second opening through the second conductive layer and the second dielectric layer to expose at least a portion of the conductive pillar; and forming the second via structure based on the second opening.

[0106] Clause 17. The method according to any one of Clauses 11 to 16, the method further comprising: forming a first solder resist layer covering at least a portion of the first surface of the first dielectric layer and a portion of the first metallization layer; and forming a second solder resist layer covering at least a portion of the second surface of the second dielectric layer and a portion of the third metallization layer.

[0107] Clause 18. The method according to any one of Clauses 11 to 17, wherein the width of the conductive post is less than the width of the second pad structure.

[0108] Clause 19. The method according to any one of Clauses 11 to 18, wherein: the thickness of the second trace structure or the thickness of the second pad structure is equal to or less than 6 micrometers (µm).

[0109] Clause 20. The method according to any one of Clauses 11 to 19, wherein: the thickness of the conductive post is equal to or greater than 5 micrometers (µm).

[0110] Clause 21. The method according to any one of Clauses 11 to 20, wherein: glass fibers are not embedded in the second dielectric layer.

[0111] Clause 22. An electronic device comprising: an integrated circuit (IC) package, the IC package comprising: a first dielectric layer; a first metallization layer located on a first surface of the first dielectric layer, the first metallization layer including a first pad structure and a first trace structure; a second metallization layer located on a second surface of the first dielectric layer, the second metallization layer including a second pad structure and a second trace structure; a conductive pillar coupled to the second pad structure; a second dielectric layer located on the second surface of the first dielectric layer, the first surface of the second dielectric layer facing the second surface of the first dielectric layer, and the second metallization layer and the conductive pillar being at least partially embedded in the second dielectric layer; a second via structure embedded in the second dielectric layer, the second via structure having a first end coupled to the conductive pillar; and a third metallization layer located on the second surface of the second dielectric layer and having a third pad structure, the second via structure having a second end coupled to the third pad structure.

[0112] Clause 23. The electronic device according to Clause 22, wherein the IC package further comprises: a first IC disposed above and electrically coupled to the first metallization layer; and a second IC disposed below and electrically coupled to the third metallization layer.

[0113] Clause 24. An electronic device according to any one of Clauses 22 to 23, wherein the IC package further comprises: a first solder resist layer covering at least a portion of the first surface of the first dielectric layer and a portion of the first metallization layer; and a second solder resist layer covering at least a portion of the second surface of the second dielectric layer and a portion of the third metallization layer.

[0114] Clause 25. An electronic device according to any one of Clauses 22 to 24, wherein the width of the conductive post is less than the width of the second pad structure.

[0115] Clause 26. An electronic device according to any one of Clauses 22 to 25, wherein the thickness of the second trace structure is less than the combined thickness of the second pad structure and the conductive pillar.

[0116] Clause 27. An electronic device according to any one of Clauses 22 to 26, wherein: the thickness of the second trace structure or the thickness of the second pad structure is equal to or less than 6 micrometers (µm).

[0117] Clause 28. An electronic device according to any one of Clauses 22 to 27, wherein: the thickness of the conductive post is equal to or greater than 5 micrometers (µm).

[0118] Clause 29. An electronic device according to any one of Clauses 22 to 28, wherein: glass fibers are not embedded in the second dielectric layer.

[0119] Clause 30. An electronic device according to any one of aspects 22 to 29, wherein the electronic device includes at least one of: a music player, a video player, an entertainment unit; a navigation device, a communication device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed-location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an Internet of Things (IoT) device, or a device in a motor vehicle.

[0120] Those skilled in the art will understand that information and signals can be represented using any of a variety of different techniques and arts. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be mentioned throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or optical particles, or any combination thereof.

[0121] Furthermore, those skilled in the art will understand that the various exemplary logic blocks, modules, circuits, and algorithm steps described in connection with the aspects disclosed herein can be implemented as electronic hardware, computer software, or a combination of both. To clearly illustrate this interchangeability between hardware and software, various exemplary components, blocks, modules, circuits, and steps have been described above in general terms of their functionality. Whether such functionality is implemented as hardware or software depends on the specific application and the design constraints imposed on the overall system. Those skilled in the art may implement the described functionality in different ways for each specific application, but such specific implementation decisions should not be construed as departing from the scope of this disclosure.

[0122] The various exemplary logic blocks, modules, and circuits described in conjunction with the aspects disclosed herein can be implemented or executed using general-purpose processors, DSPs, ASICs, FPGAs, or other programmable logic devices, discrete gate or transistor logic elements, discrete hardware components, or any combination thereof designed to perform the functions described herein. The general-purpose processor may be a microprocessor, but in alternatives, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration.

[0123] The methods, sequences, and / or algorithms described in conjunction with the aspects disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or a combination of both. The software module may reside in random access memory (RAM), flash memory, read-only memory (ROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disks, removable disks, CD-ROMs, or any other form of storage medium known in the art. Example storage media are coupled to a processor such that the processor can read information from and write information to the storage medium. Alternatively, the storage medium may be integral with the processor. The processor and storage medium may reside in an ASIC. The ASIC may reside in a user terminal (e.g., a UE). Alternatively, the processor and storage medium may reside as discrete components in the user terminal.

[0124] In one or more examples, the described functionality may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functionality may be stored as one or more instructions or code on or transmitted via a computer-readable medium. A computer-readable medium includes both computer storage media and communication media, including any medium that facilitates the transfer of a computer program from one place to another. A storage medium may be any available medium accessible to a computer. By way of example and not limitation, such computer-readable media may include RAM, ROM, EEPROM, CD-ROM or other optical disc storage devices, disk storage devices or other magnetic storage devices, or any other medium that can be used to carry or store the desired program code in the form of instructions or data structures and is accessible to a computer. Furthermore, any connection is appropriately referred to as a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included within the definition of a medium. As used herein, disks and optical discs include: compact optical discs (CDs), laser discs, optical discs, digital versatile discs (DVDs), floppy disks, and Blu-ray discs. Disks typically reproduce data magnetically, while optical discs reproduce data optically using lasers. Combinations of these should also be included within the scope of computer-readable media.

[0125] Furthermore, as used herein, the terms “set,” “group,” etc., are intended to include one or more of the elements. Additionally, as used herein, the terms “having,” “comprising,” “including,” etc., do not exclude the presence of one or more additional elements (e.g., element “having” A may also have B). Furthermore, the phrase “based on” is intended to mean “at least partially based on” unless otherwise explicitly stated. Moreover, as used herein, the term “or” is intended to be open-ended when used in a series and may be used interchangeably with “and / or” unless otherwise explicitly stated (e.g., if used in conjunction with “any” or “only one”), or these alternatives are mutually exclusive (e.g., “one or more” should not be interpreted as “one and more”). Furthermore, although components, functions, actions, and instructions may be described or claimed in the singular form, the plural form may also be considered unless explicitly stated as limited to the singular. Therefore, as used herein, the articles “a,” “an,” “the,” and “the” are intended to include one or more of the elements. Additionally, as used herein, the terms “at least one” and “one or more” include performing or being able to perform “one” component, function, action, or instruction of the described or claimed functionality, and also include performing or being able to perform “two or more” components, functions, actions, or instructions of the described or claimed functionality in combination.

[0126] While the foregoing disclosure illustrates exemplary aspects of this disclosure, it should be noted that various changes and modifications may be made herein without departing from the scope of this disclosure as defined by the appended claims. For example, the functions, steps, and / or actions of the method claims according to the aspects of this disclosure described herein need not be performed in any particular order. Furthermore, no component, function, action, or instruction described or claimed herein should be construed as critical or essential unless expressly stated otherwise.

Claims

1. A substrate for an integrated circuit (IC) package, the substrate comprising: First dielectric layer; A first metallization layer is located on a first surface of the first dielectric layer, and the first metallization layer includes a first pad structure and a first trace structure. The second metallization layer is located on the second surface of the first dielectric layer, and the second metallization layer includes a second pad structure and a second trace structure. A conductive pillar, the conductive pillar being coupled to the second pad structure; A second dielectric layer is located on the second surface of the first dielectric layer, the first surface of the second dielectric layer faces the second surface of the first dielectric layer, and the second metallization layer and the conductive pillar are at least partially embedded in the second dielectric layer. A second via structure is embedded in the second dielectric layer, and the second via structure has a first end coupled to the conductive post; and A third metallization layer is located on a second surface of the second dielectric layer and has a third pad structure, and the second via structure has a second end coupled to the third pad structure.

2. The substrate according to claim 1, further comprising: A first solder resist layer, the first solder resist layer covering at least a portion of the first surface of the first dielectric layer and a portion of the first metallization layer; and A second solder resist layer covers at least a portion of the second surface of the second dielectric layer and a portion of the third metallization layer.

3. The substrate according to claim 1, further comprising: A first via structure is embedded in the first dielectric layer, the first via structure having a first end coupled to the second pad structure and a second end coupled to the first metallization layer.

4. The substrate according to claim 1, wherein the width of the conductive pillar is smaller than the width of the second pad structure.

5. The substrate according to claim 1, wherein the thickness of the second trace structure is less than the combined thickness of the second pad structure and the conductive pillar.

6. The substrate according to claim 1, wherein: The thickness of the second trace structure or the thickness of the second pad structure is equal to or less than 6 micrometers (µm).

7. The substrate according to claim 6, wherein: The thickness of the second trace structure or the thickness of the second pad structure is in the range of 2µm to 5µm.

8. The substrate according to claim 1, wherein: The thickness of the conductive pillar is equal to or greater than 5 micrometers (µm).

9. The substrate according to claim 8, wherein: The thickness of the conductive pillar is in the range of 5µm to 30µm.

10. The substrate according to claim 1, wherein: No glass fibers are embedded in the second dielectric layer.

11. A method of manufacturing a substrate for an integrated circuit (IC) package, the method comprising: A first metallization layer is formed on a first surface of a first dielectric layer, the first metallization layer including a first pad structure and a first trace structure; A second metallization layer is formed on the second surface of the first dielectric layer, the second metallization layer including a second pad structure and a second trace structure; Form conductive pillars coupled to the second pad structure; A second dielectric layer is formed on the second surface of the first dielectric layer, the first surface of the second dielectric layer faces the second surface of the first dielectric layer, and the second metallization layer and the conductive pillar are at least partially embedded in the second dielectric layer; A second via structure is formed embedded in the second dielectric layer, the second via structure having a first end coupled to the conductive pillar; as well as A third metallization layer is formed on the second surface of the second dielectric layer and has a third pad structure, wherein the second via structure has a second end coupled to the third pad structure.

12. The method of claim 11, wherein forming the conductive pillar includes performing a masking process and performing a plating process.

13. The method of claim 11, wherein forming the second dielectric layer includes attaching a resin-coated copper layer to the first dielectric layer after forming the second metallization layer and the conductive pillar.

14. The method according to claim 11, further comprising: The first dielectric layer is attached to a removable copper foil structure, the removable copper foil structure including a first conductive layer located on the first surface of the first dielectric layer and a carrier disposed on the first conductive layer. as well as A second conductive layer is formed on the second surface of the first dielectric layer. The first metallization layer is formed based on the first conductive layer, and the second metallization layer is formed based on the second conductive layer.

15. The method according to claim 14, further comprising: After the conductive pillars are formed, the carrier is removed to expose the first conductive layer; A first opening is formed through the first conductive layer and the first dielectric layer to expose at least a portion of the second pad structure; as well as A first via structure is formed based on the first opening, the first via structure being embedded in the first dielectric layer and having a first end coupled to the first pad structure.

16. The method of claim 14, wherein forming the second via structure comprises: A second opening is formed through the second conductive layer and the second dielectric layer to expose at least a portion of the conductive pillar; as well as The second via structure is formed based on the second opening.

17. The method according to claim 11, further comprising: A first solder resist layer is formed covering at least a portion of the first surface of the first dielectric layer and a portion of the first metallization layer; as well as A second solder resist layer is formed, covering at least a portion of the second surface of the second dielectric layer and a portion of the third metallization layer.

18. The method of claim 11, wherein the width of the conductive post is less than the width of the second pad structure.

19. The method according to claim 11, wherein: The thickness of the second trace structure or the thickness of the second pad structure is equal to or less than 6 micrometers (µm).

20. The method of claim 11, wherein: The thickness of the conductive pillar is equal to or greater than 5 micrometers (µm).

21. The method according to claim 11, wherein: No glass fibers are embedded in the second dielectric layer.

22. An electronic device, the electronic device comprising: An integrated circuit (IC) package, the integrated circuit (IC) package comprising: First dielectric layer; A first metallization layer is located on a first surface of the first dielectric layer, and the first metallization layer includes a first pad structure and a first trace structure. The second metallization layer is located on the second surface of the first dielectric layer, and the second metallization layer includes a second pad structure and a second trace structure. A conductive pillar, the conductive pillar being coupled to the second pad structure; A second dielectric layer is located on the second surface of the first dielectric layer, the first surface of the second dielectric layer faces the second surface of the first dielectric layer, and the second metallization layer and the conductive pillar are at least partially embedded in the second dielectric layer. A second via structure, embedded in the second dielectric layer, having a first end coupled to the conductive pillar; and A third metallization layer is located on a second surface of the second dielectric layer and has a third pad structure, and the second via structure has a second end coupled to the third pad structure.

23. The electronic device of claim 22, wherein the IC package further comprises: A first IC is disposed above the first metallization layer and electrically coupled to the first metallization layer; and The second IC is disposed below the third metallization layer and electrically coupled to the third metallization layer.

24. The electronic device of claim 22, wherein the IC package further comprises: A first solder resist layer, the first solder resist layer covering at least a portion of the first surface of the first dielectric layer and a portion of the first metallization layer; and A second solder resist layer covers at least a portion of the second surface of the second dielectric layer and a portion of the third metallization layer.

25. The electronic device of claim 22, wherein the width of the conductive post is smaller than the width of the second pad structure.

26. The electronic device of claim 22, wherein the thickness of the second trace structure is less than the combined thickness of the second pad structure and the conductive pillar.

27. The electronic device according to claim 22, wherein: The thickness of the second trace structure or the thickness of the second pad structure is equal to or less than 6 micrometers (µm).

28. The electronic device according to claim 22, wherein: The thickness of the conductive pillar is equal to or greater than 5 micrometers (µm).

29. The electronic device according to claim 22, wherein: No glass fibers are embedded in the second dielectric layer.

30. The electronic device of claim 22, wherein the electronic device comprises at least one of: a music player, a video player, an entertainment unit; a navigation device, a communication device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed-location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an Internet of Things (IoT) device, or a device in a motor vehicle.

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