Packaging substrate, chip package, chip packaging structure and its fabrication method

Abstract

This application provides a packaging substrate, a chip package, a chip package structure, and a method for fabricating the same. The packaging substrate includes at least one packaging substrate unit and a dicing area. The packaging substrate unit includes: a core board structure having an upper circuit layer and a lower circuit layer; the lower circuit layer having a pad structure and a stepped groove, the stepped groove being located in the area of ​​the pad structure and its position corresponding to the position of the pad structure; and a solder crawling metal layer located on the sidewall of the stepped groove, the end of which has a certain distance from the dicing area corresponding to the edge of the packaging substrate unit. The chip package and the chip package structure each include the packaging substrate. By setting the stepped groove, the solder crawling height and solder flow during packaging are improved, enhancing the bonding between the packaging substrate and the circuit board. Simultaneously, the problem of cutting burrs caused by the solid metal structure of the circuit layer can be avoided.

Description

Technical Field

[0001] This application relates to the field of semiconductor packaging technology, and in particular to a packaging substrate, a chip package, a chip packaging structure, and a method for preparing the same. Background Technology

[0002] Land Grid Array (LGA) substrates are crucial substrates widely used in electronic packaging. Characterized by pins arranged in a grid array, they offer advantages such as high density and high signal transmission performance. Manufacturing processes involve complex steps including material lamination, drilling, filling with conductive and thermally conductive materials, photolithography to etch metal layers, and electroplating to achieve high-precision circuit routing and connections. Commonly used materials, such as BT resin substrates, offer high heat resistance, dimensional stability, and low dielectric constant, meeting the size and performance requirements of packaging. In terms of design layout, LGA substrates must fully consider circuit layout, signal integrity, and power management to ensure performance in high-speed circuits. They are widely used in multi-chip module (MCM) packaging, enabling efficient interconnection and integration between chips. For example, RF power amplifier modules and RF front-end modules integrating RF antenna switches often employ LGA packaging. The advantages of packaging substrates are that they can achieve high-density circuit wiring and connection, meet the packaging requirements of high pin count chips, have good electrical and mechanical properties, and are suitable for a variety of application scenarios, such as smartphones, computers, and IoT products.

[0003] LGA (Land Grid Array) packaging is a type of integrated circuit packaging where the chip achieves electrical performance through a grid array of pins on the packaging substrate. It offers advantages such as high density and high signal transmission performance, and is widely used. However, existing LGA packages suffer from insufficient side solder creep and poor solder flow during the bonding process between the packaging substrate and the circuit board, which affects the bonding integrity of the product and leads to poor reliability. Summary of the Invention

[0004] The problem to be solved by this application is to provide a packaging substrate, a chip package, a chip packaging structure and a method for preparing the same, so as to improve the solder creep height and solder flow during packaging, and enhance the bonding between the packaging substrate and the circuit board.

[0005] To address the aforementioned problems, this application provides a packaging substrate, which includes at least one packaging substrate unit and a dicing region surrounding the packaging substrate unit. The packaging substrate unit includes:

[0006] Core board structure; The upper circuit layer and the lower circuit layer are located on the upper surface and the lower surface of the core board structure, respectively. The packaging substrate unit corresponding to the lower circuit layer has a pad structure at its edge. The lower circuit layer and the packaging substrate unit corresponding to the core board structure have stepped grooves at their edges. The stepped grooves are located in the area of ​​the pad structure and the position of the stepped grooves corresponds to the position of the pad structure. A solder crawling metal layer is located on the side wall surface of the stepped trough and electrically connected to the pad structure. The end of the solder crawling metal layer at the bottom of the stepped trough has a certain distance from the cutting area corresponding to the edge of the packaging substrate unit.

[0007] In an optional embodiment, the core board structure includes a core board, a first metal layer located on the upper surface of the core board, and a second metal layer located on the lower surface of the core board, wherein the upper circuit layer is located on the upper surface of the first metal layer, and the lower circuit layer is located on the lower surface of the core board; The bottom surface of the stepped trough is the lower surface of the first metal layer.

[0008] In an optional embodiment, the stepped trough has a step, the step surface of which is located on the lower surface of the second metal layer near the lower circuit layer.

[0009] In an optional embodiment, the lower circuit layer includes multiple metal circuit layers; The stepped trough has multiple steps, with at least one step's surface located on the lower surface of the second metal layer near the lower circuit layer, and the surfaces of the remaining steps located on the surfaces of each metal circuit layer.

[0010] In an optional embodiment, the pad structure has multiple pads, which are spaced apart along the edge of the package substrate unit.

[0011] In an optional embodiment, the packaging substrate includes a plurality of packaging substrate units, with adjacent pad structures between two adjacent packaging substrate units, and stepped grooves at corresponding positions between two adjacent packaging substrate units are connected across the cutting channel area.

[0012] In an optional embodiment, the width of the bottom surface of the stepped groove of the two packaging substrate units is greater than the width of the cutting channel area. The first metal layer of the core board structure exposed at the bottom of the stepped groove connecting the two packaging substrate units across the dicing area does not have a solid metal structure in the corresponding dicing area.

[0013] In an optional embodiment, the packaging substrate includes a plurality of packaging substrate units, with adjacent pad structures between two adjacent packaging substrate units, and stepped grooves at corresponding positions between two adjacent packaging substrate units are spaced apart with respect to the cutting channel area.

[0014] In an optional embodiment, the tin-climbing metal layer includes a tin-climbing layer located on the sidewall surface of the stepped trough and a protective layer located on the surface of the tin-climbing layer.

[0015] In an optional embodiment, the thickness of the solder layer is 1 micrometer to 3 micrometers, and the thickness of the pad structure is 12 micrometers to 20 micrometers.

[0016] In an optional embodiment, the tin-climbing layer is a copper tin-climbing layer or a gold tin-climbing layer.

[0017] In an optional embodiment, the protective layer is a nickel protective layer or a gold protective layer.

[0018] In an optional embodiment, a solder resist ink layer is further included, which is disposed on both sides of the core board structure and located on the surfaces of the two outer circuit layers.

[0019] In an optional embodiment, the outer circuit layers on both sides of the core board structure have the same thickness.

[0020] This application also provides a method for preparing a packaging substrate, comprising the following steps: A core board structure is provided, the core board structure including at least one core board structure unit and a cutting track area surrounding the core board structure unit, the core board structure unit including a core board structure and an upper circuit layer and a lower circuit layer respectively disposed on the upper surface and the lower surface of the core board structure, the edge of the core board structure unit corresponding to the lower circuit layer having a pad structure; A stepped retrieval groove is formed, wherein the stepped retrieval groove is located at the edge of the packaging substrate unit corresponding to the lower circuit layer and the core board structure, and the stepped retrieval groove is located in the area of ​​the pad structure and the position of the stepped retrieval groove corresponds to the position of the pad structure. A tin-climbing metal layer is formed, which is located on the side wall surface of the stepped retrieval tank and electrically connected to the pad structure. The end of the tin-climbing metal layer at the bottom of the stepped retrieval tank has a certain distance from the cutting area corresponding to the edge of the packaging substrate unit.

[0021] In an optional embodiment, the core board structure includes a core board, a first metal layer located on the upper surface of the core board, and a second metal layer located on the lower surface of the core board, wherein the upper circuit layer is located on the upper surface of the first metal layer, and the lower circuit layer is located on the lower surface of the second metal layer; The steps for forming the stepped trough include: A first sub-groove is formed at the position corresponding to the pad structure and cut track area of ​​the lower circuit layer, and the bottom surface of the first sub-groove is the lower surface of the second metal layer; A second sub-groove is formed at the bottom of the first sub-groove, penetrating the core plate. The width of the second sub-groove is smaller than that of the first sub-groove, and the width of the second sub-groove is greater than or equal to the width of the cutting channel area. The bottom surface of the second sub-groove is the lower surface of the second metal layer.

[0022] In an optional embodiment, the step of forming the tin-plated metal layer includes: A solder crawling layer is formed on the inner wall surface of the first sub-catch and the second sub-catch, and the solder crawling layer is electrically connected to the pad structure; Remove a portion of the tin-climbing layer and a portion of the first metal layer from the bottom of the second sub-tank corresponding to the cutting channel area, wherein the width of the removed portion of the tin-climbing layer and the portion of the first metal layer is greater than the width of the cutting channel area; A protective layer is formed on the surface of the tin-climbing layer, and the end of the protective layer located at the bottom of the second sub-tank has a certain distance from the cutting channel area corresponding to the edge of the core board structural unit.

[0023] In an optional embodiment, a vacuum lamination followed by etching method is used to remove part of the tin-climbing layer and part of the first metal layer in the area corresponding to the cut track at the bottom of the second sub-tank.

[0024] In an optional embodiment, the first sub-scooping tank is formed by laser processing or machining; The second sub-groove is formed using a laser process; When the first sub-groove is formed by laser process, the second metal layer corresponding to the first sub-groove is the etching barrier required to form the first sub-groove. When the second sub-groove is formed by laser process, the first metal layer corresponding to the second sub-groove is the etching barrier required to form the second sub-groove.

[0025] In an optional embodiment, the first sub-groove and the second sub-groove at corresponding positions between two adjacent core board structural units are connected across the cutting channel area.

[0026] In an optional embodiment, solder resist ink layers are further formed on the surfaces of the upper and lower circuit layers on the side away from the core board structure, respectively.

[0027] This application also provides a chip package, including: A packaging substrate unit includes a core board structure. The upper and lower surfaces of the core board structure have an upper circuit layer and a lower circuit layer, respectively. The lower circuit layer has a pad structure at its edge. The lower circuit layer and the core board structure have a stepped groove. The stepped groove is located in the area of ​​the pad structure, and the position of the stepped groove corresponds to the position of the pad structure. The sidewall surface of the stepped groove has a solder crawling metal layer electrically connected to the pad structure, and the end of the solder crawling metal layer at the bottom of the stepped groove has a certain distance from the sidewall of the packaging substrate unit. The chip structure is disposed on the surface of the upper circuit layer of the packaging substrate unit and is located away from the stepped groove.

[0028] This application also provides a chip packaging structure, including: Circuit board; A chip package, wherein the chip package is one of the chip packages described above; The chip package is disposed on the surface of the circuit board, and the lower circuit layer of the chip package is disposed close to the circuit board. The stepped groove of the chip package contains solder, which is used to connect the chip package and the circuit board.

[0029] The advantages of the technical solution in this application are: (1) This application sets a stepped retrieval tank and sets a solder crawling metal layer on the side wall surface of the stepped retrieval tank, which can increase the fluidity of the solder during soldering in the stepped retrieval tank and optimize the subsequent solder crawling structure formed in the stepped retrieval tank. On the one hand, it can ensure the height of solder crawling, increase the contact area between the solder and the packaging substrate, improve the fluidity of the solder, and reduce the risk of brittle bubbles, so as to enhance the bonding and reliability of the product. On the other hand, when the stepped retrieval tank needs to be made into a deep stepped retrieval tank, the stepped retrieval tank can retain relatively more structural core board structure and / or circuit layer structure on the side wall, so that the packaging substrate is not easy to break.

[0030] (2) By setting several steps corresponding to each circuit layer, this application can increase the diversity of product design. The depth of the stepped scooping groove and the number of steps of the stepped scooping groove can be designed according to the required solder climbing height, so that the cut packaging substrate unit can adapt to substrates with different specifications of connection structure.

[0031] (3) This application sets up a stepped scooping groove that runs through the scooping groove area, and by making the first metal layer exposed at the bottom of the stepped scooping groove not have a metal solid structure in the scooping groove area, the end of the tin-climbing metal layer and the scooping groove area corresponding to the edge of the packaging substrate unit have a certain distance. When the substrate is cut along the scooping groove area in the future, the problem of cutting burrs caused by the metal solid structure of the circuit layer can be avoided, which greatly improves the product quality of the chip package or chip package structure.

[0032] (4) The thickness of the tin climbing layer is less than the thickness of the pad structure, which makes it easy to remove the tin climbing layer in the corresponding cutting area at the bottom of the second sub-tank before forming the protective layer. When forming the protective layer on the surface of the tin climbing layer, it is also easy to ensure that the protective layer does not have a solid structure in the corresponding cutting area at the bottom of the second sub-tank. Attached Figure Description

[0033] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly described below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort. In addition, in the following drawings, the components are not necessarily drawn to scale, and components with similar related characteristics or features may have the same or similar reference numerals.

[0034] Figure 1 This is a schematic diagram of the fabrication process of the packaging substrate in one embodiment of this application. Figure 1 ; Figure 2 This is a schematic diagram of the fabrication process of the packaging substrate in one embodiment of this application. Figure 2 ; Figure 3 This is a schematic diagram of the fabrication process of the packaging substrate in one embodiment of this application. Figure 3 ; Figure 4 This is a schematic diagram of the fabrication process of the packaging substrate in one embodiment of this application. Figure 4 ; Figure 5 This is a schematic diagram of the fabrication process of the packaging substrate in one embodiment of this application. Figure 5 ; Figure 6 This is a schematic diagram of the fabrication process of the packaging substrate in one embodiment of this application. Figure 6 ; Figure 7 This is a schematic diagram of the fabrication process of the packaging substrate in one embodiment of this application. Figure 7 ; Figure 8 This is a schematic diagram of the fabrication process of the packaging substrate in one embodiment of this application. Figure 8 ; Figure 9 This is a schematic diagram of the fabrication process of the packaging substrate in one embodiment of this application. Figure 9 (The solder pad and protective layer are not shown); Figure 10 This is a schematic diagram of the fabrication process of the packaging substrate in one embodiment of this application. Figure 10 (and Figure 10 for Figure 9 (Schematic diagram of the cross-sectional structure of AA). Figure 11 This is a schematic diagram of the fabrication process of the packaging substrate in another embodiment of this application. Figure 11 ; Figure 12 This is a schematic diagram of the structure of a chip package in one embodiment of this application; Figure 13 This is a schematic diagram of the chip packaging structure in one embodiment of this application; Figure 14 This is a schematic diagram of the fabrication process of a packaging substrate according to an embodiment of this application.

[0035] The labels for the attached figures are as follows: 1. Packaging substrate; 101. Packaging substrate unit; 102. Cutting channel area; 10. Core board structure; 11. Core board; 12. First metal layer; 13. Second metal layer; 14. Conductive via; 20. Upper circuit layer; 21. Connecting pad; 22. Insulating layer; 30. Lower circuit layer; 40. Pad structure; 41. Connecting rib; 50. Stepped retrieval groove; 51. Step; 52. First sub-retrieval groove; 53. Second sub-retrieval groove; 60. Solder creeping metal layer; 61. Solder creeping layer; 62. Protective layer; 70. Solder resist ink layer; 80. Solder; 2. Chip structure; 3. Circuit board. Detailed Implementation

[0036] To make the technical problems, technical solutions and beneficial effects to be solved by this application clearer, the following describes this application in further detail with reference to the accompanying drawings and embodiments.

[0037] In the description of this application, it should be noted that the use of terms such as "first" and "second" to define objects (such as elements, components, regions, layers, doping types and / or parts) is merely for the purpose of distinguishing different objects and is not necessarily used to describe a specific order or sequence. Unless the context clearly indicates otherwise, it should be understood that such data can be used interchangeably where appropriate.

[0038] In the description of this application, it should be understood that the singular forms "a," "an," and "the" may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms "composes" and / or "comprises" are used in this specification, the presence of said features, integers, steps, operations, elements, and / or components is identified, but the presence of one or more other features, integers, steps, operations, elements, and / or components is not excluded. The presence or addition of operations, elements, components, and / or groups. Furthermore, when used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0039] In the description of this application, it should also be noted that when a component is referred to as "on another component," "connected to another component," or "in contact with another component," it can mean not only that a component is directly on, directly connected to, or directly in contact with another component, but also that an intermediate component can be inserted between the two components. Furthermore, "connection" includes not only fixed connections but also detachable connections or integral connections. Similarly, when an element is referred to as "electrically connected," "electrically contacted," "electrically coupled," or "electrically coupled to" another element, the two elements can be in direct electrical contact or point coupling, or they can be in electrical contact or point coupling through an intermediate component.

[0040] In the description of this application, it should also be noted that the orientation or positional relationship indicated by directional terms such as "front, back, up, down, left, right", "horizontal, vertical, perpendicular, horizontal" and "top, bottom" are usually based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description. Unless otherwise stated, these directional terms do not indicate or imply that the device or element referred to must have a specific orientation or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on the scope of protection of this application; the directional terms "inner" and "outer" refer to the inner and outer contours relative to the outline of each component itself.

[0041] Furthermore, in the description of this application, spatial relation terms such as "below," "under," "below," "below," "above," "on the upper surface," "above," "upper surface," "lower surface," "bottom surface," etc., can be used to describe the spatial positional relationship between one element or feature shown in the figures and other elements or features. It should be understood that spatial relation terms, in addition to the orientation shown in the figures, also include different orientations of elements or features in use and operation. For example, if an element or feature in the figures is flipped or inverted, an element or feature described as "below" or "below" other elements or features will be oriented "above" other elements or features. Furthermore, elements may also include other orientations (e.g., rotated by an angle or other orientations).

[0042] This application provides a packaging substrate; please refer to [reference needed]. Figures 8-10 The packaging substrate includes at least one packaging substrate unit 101 and a dicing region 102 disposed around the packaging substrate unit 101. The packaging substrate unit 101 includes: Core board structure 10; The upper circuit layer 20 and the lower circuit layer 30 are located on the upper surface and the lower surface of the core board structure 10, respectively. The packaging substrate unit 101 corresponding to the lower circuit layer 30 has a pad structure 40 at its edge. The lower circuit layer 30 and the packaging substrate unit 101 corresponding to the core board structure 10 have stepped grooves 50 at their edges. The stepped grooves 50 are located in the area of ​​the pad structure 40 and the position of the stepped grooves 50 corresponds to the position of the pad structure 40. A solder crawling metal layer 60 is located on the side wall surface of the stepped trough 50 and is electrically connected to the pad structure 40. The end of the solder crawling metal layer 60 located at the bottom of the stepped trough 50 has a certain distance from the cutting channel area 102 corresponding to the edge of the packaging substrate unit 101.

[0043] In actual packaging, because the pad structures 40 are all located at the bottom of the packaging substrate 1, the side soldering height of the packaging substrate 1 is insufficient during the bonding process with the circuit board 3, affecting the bonding of the product and resulting in poor reliability. This application provides a stepped trough 50 with a soldering metal layer 60 on the sidewall surface of the stepped trough 50. This increases the fluidity of the solder 80 during soldering within the stepped trough 50 and optimizes the subsequent soldering structure formed within the stepped trough 50. On the one hand, it ensures the soldering height, increases the contact area between the solder and the packaging substrate 1, improves the fluidity of the solder, and reduces the risk of solder jamming, thereby enhancing the bonding and reliability of the product. On the other hand, when the stepped trough 50 needs to be fabricated as a deep stepped trough 50, the stepped trough 50 can retain relatively more structural core board structure 10 and / or circuit layer entities on the sidewall, making the packaging substrate 1 less prone to breakage.

[0044] In actual use, the stepped scooping groove 50 and the tin-climbing metal layer 60 on the sidewall surface of the stepped scooping groove form the wettable side wings of the packaging substrate 1.

[0045] In one embodiment, the core board structure 10 includes a core board 11, a first metal layer 12 located on the upper surface of the core board 11 and a second metal layer 13 located on the lower surface of the core board 11, an upper circuit layer 20 located on the upper surface of the first metal layer 12 and a lower circuit layer 30 located on the lower surface of the core board 11. The bottom surface of the stepped scooping tank 50 is the lower surface of the first metal layer 12.

[0046] In one embodiment, the stepped trough 50 has a step 51, the step surface of which is located on the lower surface of the second metal layer 13 near the lower circuit layer 30.

[0047] At this time, the lower circuit layer 30 includes a metal circuit layer.

[0048] In another embodiment, the lower circuit layer 30 includes multiple metal circuit layers; The stepped trough 50 has multiple steps 51, at least one step 51 has its step surface located on the lower surface of the second metal layer 13 near the lower circuit layer 30, and the step surfaces of the other steps 51 are located on the surfaces of each metal circuit layer. At the same time, a step can also span multiple metal circuit layers.

[0049] By setting several steps 51 corresponding to each circuit layer, the diversity of product design can be increased. The depth of the stepped trough 50 and the number of steps 51 of the stepped trough 50 can be designed according to the required solder climbing height, so that the cut packaging substrate unit 101 can adapt to substrates with different specifications of connection structure.

[0050] In another embodiment, the upper circuit layer 20 includes multiple metal circuit layers, and the stepped groove 50 can also start from the lower circuit layer 30, pass through the core board structure 10, and extend to the upper circuit layer 20. In this case, the upper circuit layer 20 has at least one metal circuit layer that is furthest from the core board structure 10 without the stepped groove 50, so as to ensure that the packaging substrate is a whole plate structure.

[0051] In one embodiment, the pad structure 40 has a plurality of pad structures 40, which are spaced apart along the edge of the package substrate unit 101.

[0052] In fact, the pad structure 40 is located on the surface of the outermost metal circuit layer of the lower circuit layer 30.

[0053] In one embodiment, the packaging substrate 1 includes a plurality of packaging substrate units 101, with adjacent pad structures 40 between two adjacent packaging substrate units 101, and stepped grooves 50 at corresponding positions between two adjacent packaging substrate units 101 are connected across the cutting channel region 102.

[0054] In one specific embodiment, the pad structures 40 correspondingly disposed on the two packaging substrate units 101 are connected by connecting ribs 41.

[0055] In one specific embodiment, the width of the connecting rib 41 is less than or equal to the width of the pad structure 40.

[0056] In another specific embodiment, two adjacent connecting ribs 41 can also be connected by a central rib.

[0057] In one embodiment, the width of the bottom surface of the stepped groove 50 of the two packaging substrate units 101 is greater than the width of the cutting channel region 102. The first metal layer 12 of the core board structure 10 exposed at the bottom of the stepped groove 50 that connects the two packaging substrate units 101 across the dicing region 102 does not have a solid metal structure in the corresponding dicing region 102.

[0058] This application sets up a stepped trough 50 that runs through the cutting channel region 102, and makes the first metal layer 12 exposed at the bottom of the stepped trough 50 not have a solid metal structure. When the substrate is subsequently cut along the cutting channel region 102, the problem of cutting burrs caused by the solid metal structure of the first metal layer 12 can be avoided.

[0059] Please refer to Figure 11In another embodiment, the packaging substrate 1 includes a plurality of packaging substrate units 101, with adjacent pad structures 40 between two adjacent packaging substrate units 101, and stepped grooves 50 at corresponding positions between two adjacent packaging substrate units 101 are spaced apart about the cutting channel area 102 (two adjacent stepped grooves 50 are not connected through the cutting channel area 102), and the stepped grooves 50 extend into the cutting channel area 102.

[0060] In one embodiment, the solder crawling metal layer 60 includes a solder crawling layer 61 located on the sidewall surface of the stepped retrieval tank 50 and a protective layer 62 located on the surface of the solder crawling layer 61. The protective layer 62 is used to protect the solder crawling metal layer 60 and improve the solder crawling capability of the stepped retrieval tank 50.

[0061] In one embodiment, the thickness of the solder layer 61 is 1 micrometer to 3 micrometers, preferably 2 micrometers, and the thickness of the pad structure 40 is 12 micrometers to 20 micrometers, preferably 15 micrometers.

[0062] In actual use, the thickness of the tin-climbing layer 61 is less than the thickness of the pad structure 40, so that the tin-climbing layer 61 of the cut-out area 102 can be etched away in subsequent processes.

[0063] In one embodiment, the tin-climbing layer 61 is a copper tin-climbing layer or a gold tin-climbing layer.

[0064] In one embodiment, the protective layer 62 is a nickel protective layer or a gold protective layer.

[0065] In one embodiment, a solder resist ink layer 70 is also included, which is disposed on both sides of the core board structure 10 and located on the surface of the two outer circuit layers.

[0066] In one embodiment, the outer circuit layers on both sides of the core board structure 10 have the same thickness. The solder resist ink layers 70 on both sides of the core board structure 10 also have the same thickness.

[0067] Please refer to Figures 1-10 as well as Figure 14 This application also provides a method for preparing a packaging substrate, comprising the following steps: S100. Provide a core board structure 10, the core board structure 10 including at least one core board structure unit and a cutting channel region 102 disposed around the core board structure unit, the core board structure unit including the core board structure 10 and an upper circuit layer 20 and a lower circuit layer 30 respectively disposed on the upper surface and the lower surface of the core board structure 10, the edge of the core board structure unit corresponding to the lower circuit layer 30 having a pad structure 40. S200. A stepped retrieval groove 50 is formed. The stepped retrieval groove 50 is located at the edge of the packaging substrate unit 101 corresponding to the lower circuit layer 30 and the core board structure 10. The stepped retrieval groove 50 is located in the area of ​​the pad structure 40 and the position of the stepped retrieval groove 50 corresponds to the position of the pad structure 40. S300. A solder crawling metal layer 60 is formed. The solder crawling metal layer 60 is located on the side wall surface of the stepped scooping tank 50 and is electrically connected to the pad structure 40. The end of the solder crawling metal layer 60 located at the bottom of the stepped scooping tank 50 has a certain distance from the cutting channel area 102 corresponding to the edge of the packaging substrate unit 101.

[0068] Please refer to Figure 1 and Figure 2 In one embodiment, the core board structure 10 includes a core board 11, a first metal layer 12 located on the upper surface of the core board 11, and a second metal layer 13 located on the lower surface of the core board 11. The upper circuit layer 20 is located on the upper surface of the first metal layer 12, and the lower circuit layer 30 is located on the lower surface of the second metal layer 13. The upper circuit layer 20 and the lower circuit layer 30 are respectively disposed on the upper and lower surfaces of the core board structure 10 by a lamination process.

[0069] In one specific embodiment, the upper circuit layer 20 also has a connection pad 21 for conductive connection with the chip structure 2.

[0070] Please refer to Figure 3 In one embodiment, before forming the stepped groove 50, a solder resist ink layer 70 is formed on the surface of the upper circuit layer 20 and the lower circuit layer 30 on the side away from the core board structure 10, respectively. The solder resist ink layer 70 does not cover the pad structure 40 or connect to the pad 21.

[0071] Please refer to Figure 4 and Figure 5 In one embodiment, the specific steps of forming the stepped trough 50 in step S200 include: A first sub-groove 52 is formed at the position of the pad structure 40 and the cut-and-cover area 102 in the lower circuit layer 30, and the bottom surface of the first sub-groove 52 is the lower surface of the second metal layer 13. A second sub-groove 53 is formed at the bottom of the first sub-groove 52, penetrating the core plate 11. The width of the second sub-groove 53 is smaller than that of the first sub-groove 52, and the width of the second sub-groove 53 is greater than or equal to the width of the cutting channel area 102. The bottom surface of the second sub-groove 53 is the lower surface of the second metal layer 13.

[0072] In fact, the width of the second sub-slot 53 is smaller than that of the first sub-slot 52, so that the second metal layer 13 forms the step 51 of the stepped slot 50 near the lower surface of the lower circuit layer 30.

[0073] In one specific embodiment, the core board structure 10 has a conductive via 14 that connects the upper circuit layer 20 and the lower circuit layer 30.

[0074] Please refer to Figures 6-10 In one embodiment, the specific steps for forming the tin-plated metal layer 60 in step S300 include: Please refer to Figure 6 A solder crawling layer 61 is formed on the inner wall surface of the first sub-catch 52 and the second sub-catch 53, and the solder crawling layer 61 is electrically connected to the pad structure 40. Please refer to Figure 7 Remove part of the tin layer 61 and part of the first metal layer 12 at the bottom of the second sub-tank 53 corresponding to the cutting channel area 102. The width of the removed part of the tin layer 61 and part of the first metal layer 12 is greater than the width of the cutting channel area 102. Please refer to Figures 8-10 A protective layer 62 is formed on the surface of the tin-climbing layer 61, and the end of the protective layer 62 located at the bottom of the second sub-tank 53 has a certain distance from the cutting channel area 102 corresponding to the edge of the core board structure unit.

[0075] In one embodiment, the protective layer 62 at the bottom of the second sub-dip trough 53 extends to the sidewall of the second metal layer 13 and has a certain distance from the cutting channel area 102 corresponding to the edge of the core board structural unit.

[0076] In one specific embodiment, a solder layer 61 is also formed on the surface of the pad structure 40.

[0077] In another embodiment, the metal solid structure of the first metal layer 12 exposed at the bottom of the second sub-dip 53 in the corresponding dicing area 102 may also be removed after the second sub-dip 53 is formed and before the tin-climbing layer 61 is formed.

[0078] In one embodiment, the first sub-groove 52 is formed by laser processing or machining; The second sub-groove 53 is formed by laser processing; When the first sub-drilling groove 52 is formed by laser process, the second metal layer 13 corresponding to the first sub-drilling groove 52 is the etching barrier required to form the first sub-drilling groove 52. When the second sub-groove 53 is formed by laser process, the first metal layer 12 corresponding to the second sub-groove 53 is the etching barrier required to form the second sub-groove 53.

[0079] In one embodiment, the upper and lower circuit layers include an insulating layer 22.

[0080] In fact, the etching barrier is a solid metal structure of the first metal layer 12. This solid metal structure is made of a different material than the insulating layer 22 of the upper circuit layer. During the laser process of forming the first sub-groove 52 and the second sub-groove 53, the solid metal structure can serve as the depth termination layer of the laser.

[0081] In one specific embodiment, the insulating layer 22 includes an insulating layer made of molding compound.

[0082] In one embodiment, a vacuum lamination followed by etching method is used to remove part of the tin layer 61 and part of the first metal layer 12 corresponding to the cutting channel region 102 at the bottom of the second sub-dip 53.

[0083] Please refer to Figure 9 In one embodiment, the first sub-groove 52 and the second sub-groove 53 at corresponding positions between two adjacent core board structural units are connected across the cutting channel region 102.

[0084] Please refer to Figure 8 and Figure 12 This application also provides a chip package, comprising: The packaging substrate unit 101 includes a core board structure 10. The upper and lower surfaces of the core board structure 10 have an upper circuit layer 20 and a lower circuit layer 30, respectively. The edge of the lower circuit layer 30 has a pad structure 40. The lower circuit layer 30 and the core board structure 10 have a stepped groove 50. The stepped groove 50 is located in the area of ​​the pad structure 40 and the position of the stepped groove 50 corresponds to the position of the pad structure 40. The side wall surface of the stepped groove 50 has a solder crawling metal layer 60 that is electrically connected to the pad structure 40, and the end of the solder crawling metal layer 60 at the bottom of the stepped groove 50 has a certain distance from the side wall of the packaging substrate unit 101. Chip structure 2 is disposed on the surface of the upper circuit layer 20 of the packaging substrate unit 101 and is disposed away from the stepped groove 50.

[0085] In one specific embodiment, the upper circuit layer 20 of the packaging substrate unit 101 also has a connection pad 21, and the chip structure 2 is connected to the packaging substrate unit 101 through the connection pad 21.

[0086] Please refer to Figure 12 This application also provides a method for preparing a chip package, comprising the following steps: A packaging substrate 1 is provided, which is one of the packaging substrates described above. A chip structure 2 is provided, which is disposed on the surface of the upper circuit layer 20 of the packaging substrate unit 101 and is disposed away from the stepped groove 50. The chip structure 2 and the packaging substrate 1 are encapsulated. The packaging substrate 1 and the chip structure 2 are cut along the cutting area 102 to form a single chip package having the packaging substrate 1 and the chip structure 2.

[0087] In one specific embodiment, the core board structure 10 includes multiple core board structure units, each corresponding to a multiple packaging substrate unit 101, which are cut to form multiple chip package units.

[0088] Please refer to Figure 8 and Figure 13 This application also provides a chip packaging structure, including: Circuit board 3; Chip package, wherein the chip package is one of the chip packages described above; The chip package is disposed on the surface of the circuit board 3, and the lower circuit layer 30 of the chip package is disposed close to the circuit board 3. The stepped groove 50 of the chip package contains solder 80, which is used to connect the chip package and the circuit board 3.

[0089] It should be noted that, where there is no conflict, the features in the different embodiments of this application described above can be combined with each other. Furthermore, in each of the above embodiments, the focus is on describing the differences from other embodiments; other specific descriptions of the same / similar parts between the embodiments can be referred to (or referenced) interchangeably. In addition, descriptions of well-known components and technologies have been omitted in the above description to avoid unnecessarily obscuring the concepts of this application.

[0090] Although this application has been disclosed above with reference to preferred embodiments, it is not intended to limit this application. Any person skilled in the art can make possible changes and modifications to the technical solutions of this application by utilizing the methods and techniques disclosed above without departing from the spirit and scope of this application. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of this application without departing from the content of the technical solutions of this application shall fall within the protection scope of the technical solutions of this application.

Claims

1. A packaging substrate, characterized in that, The packaged substrate includes at least one packaging substrate unit and a dicing region surrounding the packaging substrate unit, the packaging substrate unit comprising: Core board structure; The upper circuit layer and the lower circuit layer are located on the upper surface and the lower surface of the core board structure, respectively. The packaging substrate unit corresponding to the lower circuit layer has a pad structure at its edge. The lower circuit layer and the packaging substrate unit corresponding to the core board structure have stepped grooves at their edges. The stepped grooves are located in the area of ​​the pad structure and the position of the stepped grooves corresponds to the position of the pad structure. A solder crawling metal layer is located on the side wall surface of the stepped trough and electrically connected to the pad structure. The end of the solder crawling metal layer at the bottom of the stepped trough has a certain distance from the cutting area corresponding to the edge of the packaging substrate unit.

2. The packaging substrate as described in claim 1, characterized in that, The core board structure includes a core board, a first metal layer located on the upper surface of the core board, and a second metal layer located on the lower surface of the core board. The upper circuit layer is located on the upper surface of the first metal layer, and the lower circuit layer is located on the lower surface of the core board. The bottom surface of the stepped trough is the lower surface of the first metal layer.

3. The packaging substrate as described in claim 2, characterized in that, The stepped trough has a step, and the step surface is located on the lower surface of the second metal layer near the lower circuit layer.

4. The packaging substrate as described in claim 2, characterized in that, The lower circuit layer includes multiple metal circuit layers; The stepped trough has multiple steps, with at least one step's surface located on the lower surface of the second metal layer near the lower circuit layer, and the surfaces of the remaining steps located on the surfaces of each metal circuit layer.

5. A packaging substrate as described in claim 1, characterized in that, The pad structure has multiple pads, which are spaced apart along the edge of the packaging substrate unit.

6. A packaging substrate as described in claim 1, characterized in that, The packaging substrate includes multiple packaging substrate units, with adjacent pad structures between two adjacent packaging substrate units, and stepped grooves at corresponding positions between two adjacent packaging substrate units are connected across the cutting channel area.

7. A packaging substrate as described in claim 6, characterized in that, The width of the bottom surface of the stepped groove of the two packaging substrate units is greater than the width of the cutting channel area; The first metal layer of the core board structure exposed at the bottom of the stepped groove connecting the two packaging substrate units across the dicing area does not have a solid metal structure in the corresponding dicing area.

8. A packaging substrate as described in claim 1, characterized in that, The packaging substrate includes multiple packaging substrate units, with adjacent pad structures between two adjacent packaging substrate units, and stepped grooves at corresponding positions between two adjacent packaging substrate units are spaced apart with respect to the cutting channel area.

9. A packaging substrate as described in claim 1, characterized in that, The tin-climbing metal layer includes a tin-climbing layer located on the side wall surface of the stepped trough and a protective layer located on the surface of the tin-climbing layer.

10. A packaging substrate as described in claim 9, characterized in that, The thickness of the tin-climbing layer is 1 micrometer to 3 micrometers, and the thickness of the pad structure is 12 micrometers to 20 micrometers.

11. A packaging substrate as described in claim 9, characterized in that, The tin-climbing layer is a copper tin-climbing layer or a gold tin-climbing layer.

12. A packaging substrate as described in claim 9, characterized in that, The protective layer is a nickel protective layer or a gold protective layer.

13. A packaging substrate as described in claim 1, characterized in that, It also includes a solder resist ink layer, which is disposed on both sides of the core board structure and located on the surface of the two outer circuit layers.

14. A packaging substrate as described in claim 1, characterized in that, The outer circuit layers on both sides of the core board structure have the same thickness.

15. A method for preparing a packaging substrate, characterized in that, Includes the following steps: A core board structure is provided, the core board structure including at least one core board structure unit and a cutting track area surrounding the core board structure unit, the core board structure unit including a core board structure and an upper circuit layer and a lower circuit layer respectively disposed on the upper surface and the lower surface of the core board structure, the edge of the core board structure unit corresponding to the lower circuit layer having a pad structure; A stepped retrieval groove is formed, wherein the stepped retrieval groove is located at the edge of the packaging substrate unit corresponding to the lower circuit layer and the core board structure, and the stepped retrieval groove is located in the area of ​​the pad structure and the position of the stepped retrieval groove corresponds to the position of the pad structure. A tin-climbing metal layer is formed, which is located on the side wall surface of the stepped retrieval tank and electrically connected to the pad structure. The end of the tin-climbing metal layer at the bottom of the stepped retrieval tank has a certain distance from the cutting area corresponding to the edge of the packaging substrate unit.

16. The method for preparing a packaging substrate as described in claim 15, characterized in that, The core board structure includes a core board, a first metal layer located on the upper surface of the core board, and a second metal layer located on the lower surface of the core board. The upper circuit layer is located on the upper surface of the first metal layer, and the lower circuit layer is located on the lower surface of the second metal layer. The steps for forming the stepped trough include: A first sub-groove is formed at the position corresponding to the pad structure and cut track area of ​​the lower circuit layer, and the bottom surface of the first sub-groove is the lower surface of the second metal layer; A second sub-groove is formed at the bottom of the first sub-groove, penetrating the core plate. The width of the second sub-groove is smaller than that of the first sub-groove, and the width of the second sub-groove is greater than or equal to the width of the cutting channel area. The bottom surface of the second sub-groove is the lower surface of the second metal layer.

17. The method for preparing a packaging substrate as described in claim 16, characterized in that, The steps to form the tin-plated metal layer include: A solder crawling layer is formed on the inner wall surface of the first sub-catch and the second sub-catch, and the solder crawling layer is electrically connected to the pad structure; Remove a portion of the tin-climbing layer and a portion of the first metal layer from the bottom of the second sub-tank corresponding to the cutting channel area, wherein the width of the removed portion of the tin-climbing layer and the portion of the first metal layer is greater than the width of the cutting channel area; A protective layer is formed on the surface of the tin-climbing layer, and the end of the protective layer located at the bottom of the second sub-tank has a certain distance from the cutting channel area corresponding to the edge of the core board structural unit.

18. The method for preparing a packaging substrate as described in claim 17, characterized in that, The second sub-tank bottom corresponding to the cutting channel area is removed by vacuum lamination followed by etching.

19. The method for preparing a packaging substrate as described in claim 16, characterized in that, The first sub-groove is formed by laser processing or machining. The second sub-groove is formed using a laser process; When the first sub-groove is formed by laser process, the second metal layer corresponding to the first sub-groove is the etching barrier required to form the first sub-groove. When the second sub-groove is formed by laser process, the first metal layer corresponding to the second sub-groove is the etching barrier required to form the second sub-groove.

20. The method for preparing a packaging substrate as described in claim 16, characterized in that, The first and second sub-grooves at corresponding positions between two adjacent core board structural units are connected across the cutting channel area.

21. A chip packaging structure as described in claim 16, characterized in that, It also includes forming solder resist ink layers on the surfaces of the upper and lower circuit layers on the side away from the core board structure, respectively.

22. A chip package, characterized in that, include: A packaging substrate unit includes a core board structure. The upper and lower surfaces of the core board structure have an upper circuit layer and a lower circuit layer, respectively. The lower circuit layer has a pad structure at its edge. The lower circuit layer and the core board structure have a stepped groove. The stepped groove is located in the area of ​​the pad structure, and the position of the stepped groove corresponds to the position of the pad structure. The sidewall surface of the stepped groove has a solder crawling metal layer electrically connected to the pad structure, and the end of the solder crawling metal layer at the bottom of the stepped groove has a certain distance from the sidewall of the packaging substrate unit. The chip structure is disposed on the surface of the upper circuit layer of the packaging substrate unit and is located away from the stepped groove.

23. A chip packaging structure, characterized in that, include: Circuit board; A chip package, wherein the chip package is the chip package according to claim 22; The chip package is disposed on the surface of the circuit board, and the lower circuit layer of the chip package is disposed close to the circuit board. The stepped groove of the chip package contains solder, which is used to connect the chip package and the circuit board.

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