A square root determination method, electronic device, and computer-readable storage medium
By employing an iterative and integer shifting method for square root calculation, the problem of high-precision and low-latency square root calculation in embedded chips is solved, achieving savings in hardware area and power consumption.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- CHONGQING LANSHAN AUTOMOTIVE ELECTRONICS CO LTD
- Filing Date
- 2026-02-02
- Publication Date
- 2026-05-29
AI Technical Summary
In the absence of a hardware floating-point unit in embedded chips, how can a square root calculation scheme be designed that balances high precision, low latency, and hardware area to meet real-time requirements?
By combining iterative calculation and integer shift operations with a fixed number of iterations and a scaling factor of even numbers, complex circuits and division units are avoided, and square root calculation is achieved.
This ensures the accuracy and real-time performance of square root results, saves hardware area and power consumption, and avoids complex circuit design.
Smart Images
Figure CN122111376A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of chip technology, and in particular to a method for determining square roots, an electronic device, and a computer-readable storage medium. Background Technology
[0002] In the embedded systems field, many core algorithms rely on square root calculations. Typical applications include motor control and vector control and attitude calculation for drones / robots, as well as distance calculation for sensor data processing and navigation. These applications have high requirements for both real-time performance and accuracy in computation.
[0003] Currently, the main methods for calculating square roots include table lookup and hardware floating-point unit (HPU) calculation. Table lookup achieves fast lookup by pre-storing square root values, offering the advantage of speed. However, the accuracy of table lookup is limited by the capacity of the storage table; obtaining high-precision results requires storing a huge data table, which consumes significant storage space and increases hardware cost and area. While using a hardware floating-point unit can achieve higher accuracy, embedded chips are typically limited by cost and area and often lack such units.
[0004] Therefore, given the lack of hardware floating-point units in embedded chips and the strict constraints on computing resources (such as clock speed, memory, and power consumption), designing a square root calculation scheme that balances high precision, low latency, and hardware area has become an urgent technical problem to be solved. Summary of the Invention
[0005] This application discloses a method for determining square roots, an electronic device, and a computer-readable storage medium. Iterative methods help ensure the accuracy of the square root result. By limiting the number of iterations to a fixed number, the square root calculation has a deterministic delay and eliminates the need for complex convergence judgment circuits, thus saving hardware area and overhead. Furthermore, by limiting the scaling exponent to an even number, the subsequent square root result restoration process can be implemented through integer shift operations, avoiding the introduction of complex division units, thereby further saving hardware area and overhead.
[0006] Firstly, embodiments of this application provide a method for determining a square root, which can be applied to an embedded chip. The embedded chip includes at least a multiplier, a subtractor, and a shifter. The method includes: Get the floating-point number to be processed; The floating-point number to be processed is scaled to obtain a first floating-point number within a preset numerical range, and the scaling exponent is stored. The scaling exponent is an even number. The second floating-point number is determined based on the first floating-point number, and the second floating-point number is an initial approximation of the reciprocal of the square root of the first floating-point number; The process is executed N times based on the fixed-point number corresponding to the second floating-point number, and the reciprocal of the target iteration output value corresponding to the last iteration is taken as the square root result of the first floating-point number; the iteration output value corresponding to each iteration is the iterative approximation of the reciprocal of the square root of the first floating-point number; If the floating-point number to be processed is scaled down, a left shift operation is performed on the square root result of the first floating-point number using a shifter based on the restored shift amount to obtain the square root result of the floating-point number to be processed; if the floating-point number to be processed is scaled up, a right shift operation is performed on the square root result of the first floating-point number using a shifter based on the restored shift amount to obtain the square root result of the floating-point number to be processed; wherein, the restored shift amount is determined based on the scaling exponent; Each iteration process includes the following steps: The iterative input values are multiplied by the multiplier to obtain the first intermediate result; where, when this iteration is the first iteration, the iterative input value is the fixed-point number corresponding to the second floating-point number; when this iteration is not the first iteration, the iterative input value is the iterative output value corresponding to the previous iteration; The first intermediate result is multiplied by the fixed-point number corresponding to the first floating-point number using a multiplier to obtain the second intermediate result; The third intermediate result is obtained by subtracting 3 from the second intermediate result using a subtractor. The third intermediate result is multiplied by the iterative input value using a multiplier to obtain the fourth intermediate result; The fourth intermediate result is shifted one bit to the right by a shifter to obtain the iteration output value corresponding to this iteration.
[0007] In this technical solution, on the one hand, iteration helps to ensure the accuracy of the square root result. By limiting the number of iterations to a fixed number, the square root calculation has a deterministic delay, and there is no need to introduce a complex convergence judgment circuit, which helps to save hardware area and hardware costs.
[0008] Secondly, by limiting the scaling exponent to an even number, the subsequent square root result restoration process can be achieved through integer shift operations. This avoids the introduction of complex division units, thereby saving hardware area and hardware costs.
[0009] In addition, by scaling the floating-point number to be processed to the first floating-point number, it is possible to convert the floating-point number to be processed into the first floating-point number within a fixed numerical range (i.e., a preset numerical range). This is to limit the bit width of the initial value of the iterative process calculated based on the first floating-point number (i.e., the fixed-point number corresponding to the second floating-point number) and the bit width of each intermediate result in the iterative process. This is beneficial to realize the calculation by reusing hardware with a fixed bit width, thereby saving hardware area and power consumption.
[0010] In one possible implementation, both the floating-point number to be processed and the first floating-point number are binary floating-point numbers under the target floating-point number format. The binary floating-point number includes an exponent field and a mantissa field. The value of the mantissa field is used to represent the fractional part of the significant digits of the binary floating-point number, and the value of the exponent field is used to represent the bias exponent of the binary floating-point number. The actual exponent of the binary floating-point number is the difference between the bias exponent and the preset bias constant corresponding to the target floating-point number format. The value of the mantissa field of the first floating-point number is the same as the value of the mantissa field of the floating-point number to be processed. The true exponent and scaling index of the first floating-point number are determined based on the parity of the true exponent of the floating-point number to be processed.
[0011] In this technical solution, the storage characteristics of binary floating-point numbers can be utilized to quickly scale and obtain the first floating-point number. Furthermore, the scaling operation only adjusts the exponent and does not modify the mantissa; therefore, the valid digit information of the floating-point number to be processed is completely preserved. This achieves lossless scaling, retains the original precision, avoids precision loss, and ensures that subsequent square root calculations are based on high-fidelity data.
[0012] In one possible implementation, if the true exponent of the floating-point number to be processed is even, then the true exponent of the first floating-point number is 0, and the scaling exponent is equal to the true exponent of the floating-point number to be processed; if the true exponent of the floating-point number to be processed is odd, then the true exponent of the first floating-point number is 1, and the scaling exponent is the difference between the true exponent of the floating-point number to be processed and 1.
[0013] In one possible implementation, the preset numerical range is [1, 4), and the floating-point number to be processed is amplified. Double or reduce The value is 10 times; where K is the scaling exponent, and the restoration shift is K / 2.
[0014] In one possible implementation, determining the second floating-point number based on the first floating-point number includes: shifting the first floating-point number one bit to the right using a shifter to obtain the third floating-point number; and using the difference between the square root reciprocal magic constant and the third floating-point number as the second floating-point number.
[0015] In this technical solution, compared to using complex Taylor expansion or lookup table methods to determine the initial approximate value of the reciprocal of the square root, the initial approximate value of the reciprocal of the square root can be generated more quickly by shifting and subtracting the magic constant of the reciprocal of the square root.
[0016] In one possible implementation, the scaling exponent is an eight-bit binary number; the method further includes: reading the six-bit binary number corresponding to the middle six bits of the scaling exponent as the restore shift amount.
[0017] In one possible implementation, the method further includes: performing a truncation operation on the result of each multiplication by the multiplier, so that the bit width of the corresponding intermediate result is a preset bit width.
[0018] In this technical solution, during the iterative process, the bit width of the product may exceed the preset bit width after each multiplication operation. By performing a truncation operation on the product, the bit width of the corresponding intermediate result is made to be the preset bit width, thus preventing numerical overflow.
[0019] In one possible implementation, N is less than or equal to a preset value.
[0020] In this technical solution, by configuring the number of iterations to a fixed, small value, it is beneficial to make the square root calculation have a deterministic delay, which is particularly in line with the real-time requirements of embedded systems.
[0021] Secondly, embodiments of this application provide a square root determination apparatus, which includes units for implementing the method described in the first aspect.
[0022] Thirdly, embodiments of this application provide an electronic device including an embedded chip; the embedded chip is used to perform the method described in the first aspect.
[0023] In one possible implementation, the embedded chip may integrate a processor and a memory, the memory being used to store computer programs or instructions; the processor being used to retrieve the computer programs or instructions from the memory and to run the computer programs or instructions to perform the method described in the first aspect.
[0024] Fourthly, embodiments of this application provide a computer-readable storage medium storing a computer program or computer instructions, wherein when the computer program or computer instructions are executed by a processor, the method described in the first aspect is executed.
[0025] Fifthly, embodiments of this application provide a computer program product including a computer program or instructions, which, when run on an embedded chip, causes the embedded chip to perform the method described in the first aspect. Attached Figure Description
[0026] Figure 1 This is a flowchart illustrating a method for determining a square root provided in an embodiment of this application; Figure 2 This is a schematic diagram of a hardware implementation process for calculating the square root provided in an embodiment of this application; Figure 3 This is a schematic diagram of the structure of a square root determining device provided in an embodiment of this application; Figure 4This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation
[0027] The terms "first," "second," etc., used in the embodiments of this application are used to distinguish different objects, not to describe a specific order. "At least one" in the embodiments of this application refers to one or more, and "multiple" refers to two or more. "And / or" in the embodiments of this application describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent the following three situations: A exists alone, A and B exist simultaneously, and B exists alone. Here, A and B can be singular or plural.
[0028] In the embodiments of this application, "at least one of the following" or similar expressions refer to any combination of these items, including any combination of a single item or a plurality of items. For example, at least one of a, b, or c can represent the following seven cases: a, b, c, a and b, a and c, b and c, a, b, and c. Each of a, b, and c can be an element or a set containing one or more elements.
[0029] The method for determining the square root proposed in the embodiments of this application is described below. This method can be executed by an embedded chip. The embedded chip includes at least a multiplier, a subtractor, and a shifter, which are reused cyclically in an N-step iteration process to complete the iterative approximation of the reciprocal of the square root.
[0030] Please see Figure 1 , Figure 1 This is a flowchart illustrating a method for determining a square root according to an embodiment of this application. The method for determining a square root may include, but is not limited to, the following steps.
[0031] S101: Get the floating-point number to be processed.
[0032] The floating-point number to be processed can be a binary floating-point number belonging to the target floating-point number format. This application does not limit the target floating-point number format; for example, the target floating-point number format can refer to a floating-point number format that conforms to the IEEE 754 standard or other standards. Here, the floating-point number format refers to the binary encoding specification used to represent real numbers in a computer. The IEEE 754 standard is currently the most widely used floating-point number representation standard.
[0033] A binary floating-point number (such as F0) in the IEEE 754 standard can be represented as follows, where the following expression is the binary encoding of a real number:
[0034] This expression is the binary encoding of the real number F0, where S is the sign bit, indicating positive or negative; M is the mantissa, representing the fractional part of the significant digits; and E is the offset exponent, which is stored and differs from the true exponent. , This is the true exponent. Bias is the bias constant, which varies depending on the floating-point format. The exponent can also be called the index.
[0035] Floating-point formats conforming to the IEEE 754 standard can be further subdivided according to precision as follows: half-precision, single-precision, double-precision, and quadruple-precision. These four formats are the four basic precision formats defined by the IEEE 754 standard for binary floating-point formats. The specific details of the four basic precision formats are shown in Table 1.
[0036] Table 1
[0037] Taking a single-precision, binary floating-point number conforming to the IEEE 754 standard as an example, the corresponding bias constant is 127. The real number 10.2 can be expressed as: In this case, the mantissa is 0.275, the actual exponent is 3, and the stored bias decoder is 130.
[0038] In one possible implementation, after the embedded chip obtains the floating-point number to be processed, it can also perform a validity check on the floating-point number. The floating-point number to be processed that passes the validity check can proceed to the next step of the process, while the floating-point number to be processed that fails the validity check can skip the subsequent process.
[0039] In one possible implementation, the specific method for validating the floating-point number to be processed can be as follows: if the floating-point number to be processed is negative, an error flag is output, and the subsequent process is skipped; if the floating-point number to be processed exceeds a preset upper threshold, an overflow flag is output, and the subsequent process is skipped; if the floating-point number to be processed is below a preset lower threshold, the square root result is output as 0, and the subsequent process is skipped. In this way, anomalies can be detected in advance before entering the subsequent process. For illegal inputs such as negative numbers, excessively small numbers, or excessively large numbers, errors are immediately reported and the process exits, without wasting computational resources. Specifically, if the sign bit of the floating-point number to be processed is 0, it indicates that the floating-point number is positive; if the sign bit of the floating-point number to be processed is 1, it indicates that the floating-point number is negative.
[0040] This application does not limit the specific values or setting methods of the preset upper and lower thresholds. In one possible implementation, the preset upper and lower thresholds can be set by default by the embedded chip, or the user can set or modify their specific values according to actual needs.
[0041] In one possible implementation, the preset upper and lower thresholds can be determined based on the precision requirement of the final square root result. In one possible implementation, if the precision requirement for the integer (or fractional) part of the final square root result is 'a' bits, then the preset upper threshold can be 2a + Bias, and the preset lower threshold can be Bias - 2a. For example, taking a single-precision, binary floating-point number that meets the IEEE 754 standard as an example, assuming the precision requirement for the integer (or fractional) part of the final square root result is 16 bits, then the preset upper threshold is 159, and the preset lower threshold is 95.
[0042] S102: Scale the floating-point number to be processed to obtain a first floating-point number within a preset numerical range, and store the scaling exponent, which is an even number.
[0043] Scaling the floating-point number being processed refers to multiplying or dividing by... The process adjusts the floating-point number to be processed to a value (i.e., the first floating-point number) within a fixed range (i.e., a preset numerical range). The scaling process only modifies the exponent of the floating-point number, leaving the mantissa unchanged, thus ensuring no loss of precision. Simultaneously, the scaling exponent used is stored for subsequent result restoration. Here, K is the scaling exponent.
[0044] By restricting the scaling exponent to even numbers, the subsequent square root result restoration can be achieved through integer shift operations. This avoids introducing complex division units, thus saving hardware area and overhead. This is because the square root operation has a "halving" effect on the exponent, meaning the floating-point number being processed is scaled. Then the square root result of the floating-point number to be processed needs to be scaled. When K is even, K / 2 becomes an integer, allowing binary shift (left or right shift) to perform scaling and restoration, avoiding complex division or floating-point operations.
[0045] In one possible implementation, the preset numerical range is [1, 4), and the floating-point number to be processed is amplified. Double or reduce times.
[0046] In one possible implementation, both the floating-point number to be processed and the first floating-point number are binary floating-point numbers in the target floating-point format. The binary floating-point number includes an exponent field and a mantissa field. The mantissa field represents the fractional part of the significant digits of the binary floating-point number, and the exponent field represents the bias exponent. The actual exponent of the binary floating-point number is the difference between the bias exponent and the preset bias constant corresponding to the target floating-point format. The mantissa field of the first floating-point number has the same value as that of the floating-point number to be processed. The actual exponent and scaling exponent of the first floating-point number can be determined based on the parity of the actual exponent of the floating-point number to be processed. In this way, the storage characteristics of binary floating-point numbers can be utilized to quickly scale the first floating-point number. Furthermore, the scaling operation only adjusts the exponent and does not modify the mantissa, thus preserving the significant digit information of the floating-point number to be processed. This achieves lossless scaling, retains the original precision, avoids precision loss, and ensures that subsequent square root calculations are based on high-fidelity data.
[0047] For details regarding the target floating-point number format, bias exponent, true exponent, and bias constant, please refer to the preceding descriptions. The significant digits of a binary floating-point number refer to the binary values used to represent the precision portion of the floating-point number; the significant digits determine how many bits of valid information the floating-point number can represent. The range of significant digits is [1, 2). For example, the floating-point number to be processed... The significant figures are 1.275.
[0048] In one possible implementation, if the true exponent of the floating-point number to be processed is even, then the true exponent of the first floating-point number is 0, and the scaling exponent is equal to the true exponent of the floating-point number to be processed; if the true exponent of the floating-point number to be processed is odd, then the true exponent of the first floating-point number is 1, and the scaling exponent is the difference between the true exponent of the floating-point number to be processed and 1.
[0049] When the true exponent of the floating-point number to be processed is even, the value range of the first floating-point number obtained after scaling is [1, 2]. When the true exponent of the floating-point number to be processed is odd, the value range of the first floating-point number obtained after scaling is [2, 4]. In one possible implementation, the embedded chip can read the least significant bit value of the stored bias exponent of the floating-point number to be processed, and determine the parity of the true exponent of the floating-point number to be processed by the least significant bit value of the bias exponent, which is faster. For example, taking the bias constant corresponding to the floating-point number to be processed as odd (such as 127) as an example, assuming that the least significant bit value of the bias exponent of the floating-point number to be processed is 0 (i.e., the bias exponent of the floating-point number to be processed is even), in this case, the true exponent of the floating-point number to be processed is odd. Assuming that the least significant bit value of the bias exponent of the floating-point number to be processed is 1 (i.e., the bias exponent of the floating-point number to be processed is odd), in this case, the true exponent of the floating-point number to be processed is even.
[0050] For example, suppose the floating-point number to be processed is In this case, the value of the mantissa field of the first floating-point number is the same as the value of the mantissa field of the floating-point number to be processed, both being 0.275. Furthermore, since the true exponent of the floating-point number to be processed is an odd number 3, and the true exponent of the first floating-point number is 1, and the scaling index is the difference between the true exponent of the floating-point number to be processed (i.e., 3) and 1, the first floating-point number is... And the scaling factor is 2.
[0051] S103: Determine the second floating-point number based on the first floating-point number. The second floating-point number is an initial approximation of the reciprocal of the square root of the first floating-point number.
[0052] The specific implementation of S103 can be as follows: the first floating-point number is shifted right by 1 bit using a shifter to obtain the third floating-point number; and the difference between the magic constant of the square root reciprocal and the third floating-point number is used as the second floating-point number. Compared with using complex Taylor expansion or lookup table methods to determine the initial approximation of the square root reciprocal, the initial approximation of the square root reciprocal can be generated more quickly through shifting and subtraction of the magic constant of the square root reciprocal.
[0053] The square root reciprocal magic constant is a fixed 32-bit hexadecimal constant: 0x5F3759DF, where 0x is the hexadecimal prefix. This empirical constant, derived through extensive experimentation, is used to quickly calculate the initial value of the square root reciprocal of an IEEE 754 32-bit single-precision floating-point number. The corresponding decimal value for the square root reciprocal magic constant is 1597463007.
[0054] Shifting the first floating-point number right by 1 bit involves treating the entire binary storage format of the first floating-point number as an unsigned integer and then performing a logical right shift of 1 bit on that integer.
[0055] S104: Execute N iterations based on the fixed-point number corresponding to the second floating-point number, and use the reciprocal of the target iteration output value corresponding to the last iteration as the square root of the first floating-point number; the iteration output value corresponding to each iteration is an iterative approximation of the reciprocal of the square root of the first floating-point number. Each iteration includes the following steps: ① The iterative input value is multiplied by the iterative input value to obtain the first intermediate result; where, when this iteration is the first iteration, the iterative input value is the fixed-point number corresponding to the second floating-point number; when this iteration is not the first iteration, the iterative input value is the iterative output value corresponding to the previous iteration; ② The first intermediate result is multiplied by the fixed-point number corresponding to the first floating-point number using a multiplier to obtain the second intermediate result; ③ Subtract 3 from the second intermediate result using a subtractor to obtain the third intermediate result; ④ The third intermediate result is multiplied by the iterative input value using a multiplier to obtain the fourth intermediate result; ⑤ Shift the fourth intermediate result one bit to the right using a shifter to obtain the iteration output value corresponding to this iteration.
[0056] The embedded chip in the S104 converts the second floating-point number to a fixed-point form as the starting point for iteration, performing a fixed number of N iterations. This ensures that the iterative approximation of the reciprocal of the square root of the first floating-point number is closer to the true value each time, thus helping to ensure the accuracy of the square root result. Furthermore, by limiting the number of iterations to a fixed number, the square root calculation has a deterministic delay and eliminates the need for complex convergence circuitry, saving hardware area and overhead. During the iteration process, multipliers, subtractors, and shifters are reused to complete the iteration flow, avoiding the use of division; high-precision approximation can be achieved using only multiplication, subtraction, and shifting.
[0057] In one possible implementation, N is a positive integer, and N is less than or equal to a preset value. By configuring the number of iterations to a fixed, small value, it is beneficial to make the square root calculation have a deterministic delay, which is particularly suitable for the real-time requirements of embedded systems. This application does not limit the specific values of N and the preset value; for example, N can be 1 or 2.
[0058] In one possible implementation, a truncation operation is performed on the result of each multiplication operation to ensure that the bit width of the corresponding intermediate result is a preset bit width. For example, an embedded chip can perform a truncation operation on the product of two iterative input values to ensure that the bit width of the first intermediate result is a preset bit width; perform a truncation operation on the product of the first intermediate result and a first floating-point number to ensure that the bit width of the second intermediate result is a preset bit width; and perform a truncation operation on the product of the third intermediate result and the iterative input value to ensure that the bit width of the fourth intermediate result is a preset bit width. In the iterative process, after each multiplication operation, the bit width of the resulting product may exceed the preset bit width. By performing a truncation operation on the product to ensure that the bit width of the corresponding intermediate result is a preset bit width, numerical overflow can be prevented.
[0059] The embodiments of this application do not limit the preset bit width. For example, the preset bit width can be 50 bits or other bit widths.
[0060] The preset bit width can be determined based on the format of the multiplier's input data. For example, if the multiplier's input data is in the uq4.46 format, then the preset bit width can be 50 bits. Here, uqM.N is an unsigned fixed-point representation, where u represents unsigned, q represents fixed-point, M represents the number of bits in the integer part, and N represents the number of bits in the fractional part. This ensures that the output format of the intermediate results meets the multiplier's input format requirements. This allows the same 50-bit multiplier to be reused in the iterative process, saving hardware area and overhead.
[0061] Taking the input data of the multiplier as uq4.46 format and the preset bit width as 50 bits as an example, the specific way to perform the truncation operation is to retain the highest 4 integer bits of the product and the following 46 fractional bits, so that the format of the corresponding intermediate result is uq4.46 format.
[0062] In the embodiments of this application, the multipliers, subtractors and shifters in the iterative process are shared computing units in the hardware implementation. The arithmetic operations required for the iteration are executed in a time-sharing manner within multiple clock cycles by a state machine control, so as to reduce circuit area and power consumption.
[0063] S105: If the floating-point number to be processed is scaled down, then based on the restored shift amount, a left shift operation is performed on the square root result of the first floating-point number through a shifter to obtain the square root result of the floating-point number to be processed; if the floating-point number to be processed is scaled up, then based on the restored shift amount, a right shift operation is performed on the square root result of the first floating-point number through a shifter to obtain the square root result of the floating-point number to be processed. The restored shift amount is determined based on the scaling exponent.
[0064] The restoration shift is K / 2, where K is the scaling exponent.
[0065] As mentioned above, the original floating-point number F0 to be processed is scaled to a first floating-point number FS within a preset numerical range, and the scaling exponent is K, i.e., FS = F0. 2K or FS = F0 / 2K. Calculated... Then, the square root of the floating-point number to be processed needs to be restored by reverse scaling. , The expression is as follows: ,or,
[0066] By setting K to an even number, K / 2 becomes an integer, and the scaling effect can be offset by binary shifting, thus achieving efficient restoration.
[0067] The floating-point number to be processed is reduced to the square root of the first floating-point number based on K / 2 through a shifter (i.e. Performing a left shift operation is equivalent to shifting the left shift position to the right shift position to the left ... Multiply To obtain the square root result of the floating-point number to be processed (i.e. The floating-point number to be processed is amplified, and based on K / 2, a right shift operation is performed on the square root result of the first floating-point number using a shifter, which is equivalent to... Divide by This is used to obtain the square root of the floating-point number to be processed.
[0068] In one possible implementation, the scaling exponent is an eight-bit binary number. The embedded chip can use the six-bit binary number corresponding to the middle six bits of the scaling exponent as the restore shift amount. The actual exponent range of IEEE 754 single-precision binary floating-point numbers is -126 to 127. Since the restore shift amount is K / 2, which is half of the scaling exponent K, and 6 bits can represent the shift range of 0-63, directly reading the middle six bits of the scaling exponent can cover the scaling and restore requirements of most floating-point numbers in embedded scenarios.
[0069] For example, taking an offset constant of 127 as an example, if Es[7]=1, it means that the floating-point number F0 to be processed is scaled down by data_scale=(Es[7:0]-127). In this case, the square root result of the first floating-point number needs to be scaled up by data_scale[6:1]. If Es[7]=0, it means that the floating-point number F0 to be processed is scaled up by data_scale=(127-Es[7:0]) or not scaled up. In this case, the square root result of the first floating-point number needs to be scaled down by data_scale[6:1] or no shift operation needs to be performed. Among them, the scaling index described above is the actual scaling index, Es[7:0] represents the offset scaling index corresponding to the actual scaling index, that is, the offset scaling index is stored, data_scale is the scaling index in the form of an eight-bit binary number, and data_scale[6:1] represents the middle six bits of the scaling index. By reading the highest bit of the offset scaling index, it is possible to quickly determine whether the floating-point number to be processed is scaled down or scaled up.
[0070] By implementing the embodiments of this application, on the one hand, iteration helps to ensure the accuracy of the square root result, and by limiting the number of iterations to a fixed number, the square root calculation has a deterministic delay, and there is no need to introduce a complex convergence judgment circuit, which helps to save hardware area and hardware costs.
[0071] Secondly, by limiting the scaling exponent to an even number, the subsequent square root result restoration process can be achieved through integer shift operations. This avoids the introduction of complex division units, thereby saving hardware area and hardware costs.
[0072] In addition, by scaling the floating-point number to be processed to the first floating-point number, it is possible to convert the floating-point number to be processed into the first floating-point number within a fixed numerical range (i.e., a preset numerical range). This is to limit the bit width of the initial value of the iterative process calculated based on the first floating-point number (i.e., the fixed-point number corresponding to the second floating-point number) and the bit width of each intermediate result in the iterative process. This is beneficial to realize the calculation by reusing hardware with a fixed bit width, thereby saving hardware area and power consumption.
[0073] A schematic diagram of the hardware implementation process for calculating the square root using an embedded chip in this application embodiment can be seen as follows: Figure 2 As shown in the diagram. Here, F0 represents the floating-point number to be processed, F1 represents the first floating-point number, F2 represents the second floating-point number, X0 represents the fixed-point number corresponding to the first floating-point number, X1 represents the fixed-point number corresponding to the second floating-point number, X2 represents the iterative input value corresponding to this iteration, X3 represents the first intermediate result, X4 represents the second intermediate result, X5 represents the third intermediate result, X6 represents the fourth intermediate result, X7 represents the iterative output value corresponding to this iteration, and X8 represents the square root result of the first floating-point number. Figure 2 The specific execution process of each step can be found in the previous description, and will not be repeated here.
[0074] Please see Figure 3 , Figure 3 This is a schematic diagram of a square root determining device provided in an embodiment of this application. Figure 3 As shown, the square root determination device 30 includes an acquisition unit 301 and a processing unit 302. The square root determination device 30 can perform the relevant steps of the embedded chip in the aforementioned method embodiments.
[0075] The acquisition unit is used to acquire the floating-point number to be processed. The processing unit is used to scale the floating-point number to be processed, obtain a first floating-point number within a preset numerical range, and store the scaling exponent, wherein the scaling exponent is an even number. The processing unit is also used to determine a second floating-point number based on the first floating-point number, wherein the second floating-point number is an initial approximation of the reciprocal of the square root of the first floating-point number; The processing unit is also used to execute N iterations based on the fixed-point number corresponding to the second floating-point number, and to take the reciprocal of the target iteration output value corresponding to the last iteration as the square root result of the first floating-point number; the iteration output value corresponding to each iteration is the iterative approximation of the reciprocal of the square root of the first floating-point number; The processing unit is further configured to, if the floating-point number to be processed is scaled down, perform a left shift operation on the square root result of the first floating-point number based on the restored shift amount through a shifter to obtain the square root result of the floating-point number to be processed; if the floating-point number to be processed is scaled up, perform a right shift operation on the square root result of the first floating-point number based on the restored shift amount through a shifter to obtain the square root result of the floating-point number to be processed; wherein, the restored shift amount is determined based on the scaling exponent; Each iteration process includes the following steps: The iterative input values are multiplied by the multiplier to obtain the first intermediate result; where, when this iteration is the first iteration, the iterative input value is the fixed-point number corresponding to the second floating-point number; when this iteration is not the first iteration, the iterative input value is the iterative output value corresponding to the previous iteration; The first intermediate result is multiplied by the fixed-point number corresponding to the first floating-point number using a multiplier to obtain the second intermediate result; The third intermediate result is obtained by subtracting 3 from the second intermediate result using a subtractor. The third intermediate result is multiplied by the iterative input value using a multiplier to obtain the fourth intermediate result; The fourth intermediate result is shifted one bit to the right by a shifter to obtain the iteration output value corresponding to this iteration.
[0076] Specifically, in this case, the operations performed by the acquisition unit and the processing unit can be referred to the description of the embedded chip in the method embodiment, which will not be repeated here.
[0077] Please see Figure 4 , Figure 4 This is a schematic diagram of the structure of an electronic device 40 provided in an embodiment of this application, which can be used to implement the functions of the embedded chip in the above method embodiments. The electronic device 40 may include an embedded chip 401. Optionally, the electronic device 40 may also include one or more of a processor 402 and a memory 403. Figure 4 The components shown by the dashed lines are optional components, meaning that electronic device 40 may not include them. Figure 4 The component shown by the dashed line.
[0078] Embedded chips include at least multipliers, subtractors, and shifters.
[0079] In one possible implementation, the processor and / or memory can be integrated inside the embedded chip, or the processor and / or memory can be integrated outside the embedded chip but inside the electronic device.
[0080] Processors, memory, and embedded chips can be connected via bus 404 or other methods. The bus is... Figure 4The connections between other components are shown in bold lines only and are not intended to be limiting. Buses can be categorized as address buses, data buses, control buses, etc. For ease of illustration, Figure 4 The bus is represented by a single thick line, but this does not mean that there is only one bus or one type of bus.
[0081] The coupling in this application embodiment is an indirect coupling or communication connection between devices, units, or modules, which can be electrical, mechanical, or other forms, used for information exchange between devices, units, or modules. This application embodiment does not limit the specific connection medium between the aforementioned processors, memories, and embedded chips.
[0082] The memory may include read-only memory and random access memory, and provides instructions and data to the processor. A portion of the memory may also include non-volatile random access memory.
[0083] The processor can be a Central Processing Unit (CPU), but it can also be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor can be a microprocessor, which is optional; the processor can also be any conventional processor.
[0084] In one example, when the electronic device adopts Figure 4 When in the form shown, Figure 4 The embedded chip in the device can execute the methods in any of the above method embodiments. The processor in the embedded chip or the processor in the electronic device can execute the methods in any of the above method embodiments.
[0085] In one possible implementation, a memory is used to store computer programs or instructions; a processor is used to invoke the computer programs or instructions stored in the memory to perform the steps executed in the method embodiment.
[0086] In the embodiments of this application, the methods provided in the embodiments of this application can be implemented by running a computer program (including program code) capable of performing the steps involved in the above-described methods on a general-purpose computing device, such as a computer, which includes processing elements and storage elements such as a CPU, random access memory (RAM), and read-only memory (ROM). The computer program can be recorded on, for example, a computer-readable recording medium, loaded into an electronic device through the computer-readable recording medium, and run therein.
[0087] Based on the same inventive concept, the principles and beneficial effects of the devices and electronic devices provided in the embodiments of this application in solving the problem are similar to those of the embedded chips in solving the problem in the method embodiments of this application. Please refer to the principles and beneficial effects of the method embodiments. For the sake of brevity, they will not be repeated here.
[0088] This application also provides a computer-readable storage medium storing a computer program or computer instructions adapted for loading by a processor and executing the methods provided in the above-described method embodiments. The processor may be integrated into an embedded chip.
[0089] This application also provides a computer program product containing a computer program or instructions, which, when run on an embedded chip, causes the embedded chip to execute the method provided in the above-described method embodiments.
[0090] Regarding the modules / units included in the various devices and products described in the above embodiments, they can be software modules / units, hardware modules / units, or a combination of both. For example, for various devices and products applied to or integrated into a chip, all of their modules / units can be implemented using hardware methods such as circuits, or at least some modules / units can be implemented using software programs that run on a processor integrated within the chip, while the remaining (if any) modules / units can be implemented using hardware methods such as circuits; for various devices and products applied to or integrated into a chip module, all of their modules / units can be implemented using hardware methods such as circuits, and different modules / units can be located in the same component (e.g., chip, circuit module, etc.) or different components of the chip module, or at least some modules / units can be implemented using hardware methods such as circuits. The implementation is achieved through a software program that runs on a processor integrated within the chip module. The remaining (if any) modules / units can be implemented using hardware methods such as circuits. For various devices and products applied to or integrated into electronic devices, each of their modules / units can be implemented using hardware methods such as circuits. Different modules / units can be located in the same component (e.g., chip, circuit module, etc.) or different components within the electronic device. Alternatively, at least some modules / units can be implemented using a software program that runs on a processor integrated within the electronic device, while the remaining (if any) modules / units can be implemented using hardware methods such as circuits.
[0091] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that this application is not limited to the described order of actions, as some steps may be performed in other orders or simultaneously according to this application. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions and modules involved are not necessarily essential to this application.
[0092] In the above embodiments, the descriptions of each embodiment have their own emphasis, and any multiple embodiments can be used in combination. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments.
[0093] The steps in the method of this application embodiment can be adjusted, combined, or deleted according to actual needs.
[0094] The modules in the device of this application embodiment can be merged, divided, and deleted according to actual needs.
[0095] Those skilled in the art will understand that all or part of the steps in the various methods of the above embodiments can be implemented by program instructions and related hardware. The program instructions can be stored in a computer-readable storage medium, which may include: flash drive, ROM, RAM, disk or optical disk, etc.
[0096] The above-disclosed embodiments are merely one example of this application and only a part of the embodiments of this application. They should not be construed as limiting the scope of this application.
Claims
1. A method for determining a square root, characterized in that, The method is applied to an embedded chip, wherein the embedded chip includes at least a multiplier, a subtractor, and a shifter; the method includes: Get the floating-point number to be processed; The floating-point number to be processed is scaled to obtain a first floating-point number within a preset numerical range, and the scaling exponent is stored, wherein the scaling exponent is an even number. A second floating-point number is determined based on the first floating-point number, and the second floating-point number is an initial approximation of the reciprocal of the square root of the first floating-point number; The process is executed N times based on the fixed-point number corresponding to the second floating-point number, and the reciprocal of the target iteration output value corresponding to the last iteration is taken as the square root result of the first floating-point number; the iteration output value corresponding to each iteration is the iterative approximation of the reciprocal of the square root of the first floating-point number; If the floating-point number to be processed is scaled down, a left shift operation is performed on the square root result of the first floating-point number based on the restored shift amount through the shifter to obtain the square root result of the floating-point number to be processed; if the floating-point number to be processed is scaled up, a right shift operation is performed on the square root result of the first floating-point number based on the restored shift amount through the shifter to obtain the square root result of the floating-point number to be processed; wherein, the restored shift amount is determined based on the scaling exponent; Each iteration process includes the following steps: The multiplier multiplies the iterative input value to obtain a first intermediate result; wherein, when this iteration is the first iteration, the iterative input value is the fixed-point number corresponding to the second floating-point number; when this iteration is not the first iteration, the iterative input value is the iterative output value corresponding to the previous iteration; The first intermediate result is multiplied by the fixed-point number corresponding to the first floating-point number by the multiplier to obtain the second intermediate result; The subtractor subtracts 3 from the second intermediate result to obtain the third intermediate result; The multiplier multiplies the third intermediate result with the iterative input value to obtain the fourth intermediate result; The fourth intermediate result is shifted one bit to the right by the shifter to obtain the iteration output value corresponding to this iteration.
2. The method according to claim 1, characterized in that, Both the floating-point number to be processed and the first floating-point number belong to binary floating-point numbers under the target floating-point number format. The binary floating-point number includes an exponent field and a mantissa field. The value of the mantissa field is used to represent the fractional part of the significant digits of the binary floating-point number, and the value of the exponent field is used to represent the bias exponent of the binary floating-point number. The actual exponent of the binary floating-point number is the difference between the bias exponent and the preset bias constant corresponding to the target floating-point number format. Wherein, the value of the mantissa field of the first floating-point number is the same as the value of the mantissa field of the floating-point number to be processed; The true exponent of the first floating-point number and the scaling index are determined based on the parity of the true exponent of the floating-point number to be processed.
3. The method according to claim 2, characterized in that, If the true exponent of the floating-point number to be processed is even, then the true exponent of the first floating-point number is 0, and the scaling exponent is equal to the true exponent of the floating-point number to be processed. If the true exponent of the floating-point number to be processed is odd, then the true exponent of the first floating-point number is 1, and the scaling index is the difference between the true exponent of the floating-point number to be processed and 1.
4. The method according to claim 1, characterized in that, The preset numerical range is [1, 4), and the floating-point number to be processed is amplified. Double or reduce The scaling factor is K / 2; where K is the scaling exponent and the restoration shift is K / 2.
5. The method according to claim 1, characterized in that, Determining the second floating-point number based on the first floating-point number includes: The first floating-point number is shifted right by 1 bit using the shifter to obtain the third floating-point number; The difference between the square root reciprocal magic constant and the third floating-point number is taken as the second floating-point number.
6. The method according to any one of claims 1-5, characterized in that, The scaling index is an eight-bit binary number; the method further includes: The six-bit binary number corresponding to the middle six bits of the scaling exponent is read as the restore shift amount.
7. The method according to any one of claims 1-5, characterized in that, The method further includes: The result of each multiplication by the multiplier is truncated so that the bit width of the corresponding intermediate result is a preset bit width.
8. The method according to any one of claims 1-5, characterized in that, N is less than or equal to the preset value.
9. An electronic device, characterized in that, Includes an embedded chip; the embedded chip is used to perform the method as described in any one of claims 1-8.
10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program or computer instructions that, when executed by a processor, cause the method described in any one of claims 1-8 to be performed.