Gicl packaging structure with improved communication

Abstract

This disclosure relates to a GICL package structure with improved communication. Aspects of this disclosure may include, for example, a packaged integrated circuit device comprising two currently isolated integrated circuit dies. Each integrated circuit die includes a conductive coil that can be inductively coupled for wireless communication between the two currently isolated integrated circuit dies. One of the integrated circuit dies is flip-chip mounted to the other, wherein the coils face each other across an insulating layer that includes a routing layer for providing power to the flip-chip mounted integrated circuit die. Other embodiments are disclosed.

Description

Technical Field

[0001] This disclosure relates to integrated circuit packaging structures. Background Technology

[0002] Current-isolated integrated circuits can communicate wirelessly. For example, two current-isolated integrated circuit dies can each have a conductive coil that can be used for communication via inductive coupling. Summary of the Invention

[0003] In an example embodiment, a system includes a first integrated circuit die having a first communication coil and a second integrated circuit die having a second communication coil. The second integrated circuit die is positioned relative to the first integrated circuit die such that the first communication coil faces and is aligned with the second communication coil to allow inductive coupling between the first and second communication coils. An insulating layer is positioned between the first and second integrated circuit dies, and the insulating layer includes a first conductive trace coupled to provide an electrical connection to the second integrated circuit die (e.g., providing signals and / or power to the second integrated circuit die).

[0004] Additional example embodiments of the system include an insulating layer having a polymer layer formed on the first integrated circuit die, wherein the first conductive trace includes a wire bonding pad region. Additionally, the insulating layer may be formed from an interposer circuit board. The insulating layer may also include a second conductive trace coupled to provide a second electrical connection to the first integrated circuit die (e.g., providing signal and / or power to the first integrated circuit die). The first and second conductive traces may be in separate voltage domains, and the insulating layer may provide current isolation between the first and second integrated circuit dies. Furthermore, the insulating layer may leave an exposed portion of the first integrated circuit die, and the electrical connection to the first integrated circuit die may be formed on the exposed portion of the first integrated circuit die. The system may further include a dielectric underfill layer between the second integrated circuit die and the insulating layer, and the first integrated circuit die may include at least a third communication coil, and the second integrated circuit die may include at least a fourth communication coil.

[0005] In another example embodiment, a packaged integrated circuit device includes: a first integrated circuit die having a first conductive coil and a first bonding pad for providing a first electrical connection to the first integrated circuit die (e.g., providing a signal and / or power to the first integrated circuit die); a dielectric layer formed on the first integrated circuit die above the first conductive coil and the first bonding pad, the dielectric layer including a via for providing electrical coupling to the first bonding pad on the first integrated circuit die, and a first conductive trace coupled to the via to provide the first electrical connection to the first integrated circuit die, the dielectric layer further including a first conductive trace for providing electrical coupling to the first bonding pad on the first integrated circuit die. The second integrated circuit die has a second conductive trace for inductive coupling to the first conductive trace, and a second bonding pad for providing a second electrical connection to the second integrated circuit die, wherein the second integrated circuit die is mounted to the first integrated circuit die, wherein the first conductive trace faces and is aligned with the second conductive trace, and wherein the second bonding pad faces and is aligned with the second conductive trace on the dielectric layer to electrically couple the second conductive trace on the dielectric layer to the second bonding pad to provide the second electrical connection to the second integrated circuit die.

[0006] Additional example embodiments of the packaged integrated circuit device may include the dielectric layer comprising a polymer layer, a redistribution layer, an interposer, a circuit board, etc. Furthermore, the dielectric layer may provide current isolation between the first integrated circuit die and the second integrated circuit die, wherein the first bonding pad and the second bonding pad are current-isolated from each other.

[0007] In another example embodiment, a method may include: forming a first conductive coil on a first integrated circuit die; forming an insulating layer on the first integrated circuit die; forming a conductive trace on the insulating layer; forming a second conductive coil on a second integrated circuit die; placing bonding pads on the second integrated circuit die; and coupling the second integrated circuit die to the first integrated circuit die such that the second conductive coil faces and is aligned with the first conductive coil to allow inductive coupling between the first and second conductive coils, and such that the bonding pads on the second integrated circuit die are coupled to the conductive traces on the insulating layer to provide an electrical connection to the second integrated circuit die (e.g., providing signal and / or power to the second integrated circuit die).

[0008] Additional example embodiments of the method include wherein forming the insulating layer on the first integrated circuit die includes forming a polyimide layer on the first integrated circuit die, wherein forming the conductive trace on the insulating layer includes forming a metallization layer on the polyimide layer, and wherein the electrical connection to the second integrated circuit die is configured to route power to the second integrated circuit die. Additionally, the method may include performing a solder reflow operation to couple the second integrated circuit die to the first integrated circuit die, and filling the cavity between the second integrated circuit die and the insulating layer with a non-conductive underfill material. Attached Figure Description

[0009] This disclosure is illustrated by means of examples, embodiments, etc., and is not limited to the drawings, in which similar reference numerals indicate similar elements. Elements in the drawings are shown for simplicity and clarity, and are not necessarily drawn to scale. The drawings, together with the detailed description, are incorporated in and form a part of this specification, and are used to further illustrate examples, embodiments, etc., and to explain various principles and advantages based on this disclosure, in which:

[0010] Figure 1 and Figure 2 This is a cross-sectional view of a packaged electronic device that includes two currently isolated integrated circuit devices.

[0011] Figure 3 Example process flows according to various embodiments are shown;

[0012] Figure 4 This is a flowchart illustrating example methods according to various embodiments. Detailed Implementation

[0013] The following detailed descriptions are provided as examples for illustrative purposes and are not intended to limit the invention or its application and uses. Furthermore, one should not be bound by any express or implied theory presented in the prior art, background art, or the following detailed descriptions.

[0014] For the sake of simplicity and clarity, the drawings show the general construction, and descriptions and details of well-known features and technologies may be omitted to avoid unnecessarily obscuring the invention. Furthermore, the elements in the drawings are not necessarily drawn to scale. For example, the dimensions of some elements or areas in the drawings may be exaggerated relative to other elements or areas to aid in understanding embodiments of the invention.

[0015] The terms “first,” “second,” “third,” “fourth,” etc. (if any) used in this specification and claims are used to distinguish similar elements and are not necessarily used to describe a particular sequence or chronological order. It should be understood that the terms thus used are interchangeable where appropriate so that embodiments of the invention described herein can be operated, for example, in sequences other than those shown or otherwise described herein. Furthermore, the terms “comprise,” “include,” “have,” and any variations thereof are intended to cover a non-exclusive inclusion, such that a process, method, article of manufacture, or apparatus comprising a list of elements is not necessarily limited to those elements but may include other elements not expressly listed or inherent to such process, method, article of manufacture, or apparatus. The term “coupled” as used herein is defined as a direct or indirect connection, either electrically or non-electrically. As used herein, the terms “substantially” and “generally” mean sufficient to achieve the stated purpose in a practically practicable manner, and minor defects (if any) are not significant to the stated purpose.

[0016] Unless otherwise stated, directional references such as “top,” “bottom,” “left,” “right,” “above,” and “below” are not intended to require any preferred orientation, but are for illustrative purposes to refer to the orientation of one or more corresponding figures.

[0017] It should be understood that the steps of the various processes described herein are non-limiting examples of suitable processes according to embodiments and are for illustrative purposes. Systems and apparatus according to the embodiments herein may use any suitable process, including processes that omit the steps described above, processes that perform those steps in a different order, and similar processes, etc. It should also be understood that well-known features may be omitted for clarity.

[0018] Unless otherwise expressly stated, the use of the terms "approximately," "generally," and similar terms with respect to the dimensions, relative positioning, or orientation of various features indicates that the dimensions, positioning, or orientation of those features are subject to the tolerances and / or anticipated process variations of the equipment and processes selected to form the described features. Unless otherwise expressly stated, the use of the terms "approximately," "generally," and similar terms with respect to measurable values ​​or characteristics is subject to the anticipated measurement accuracy of the equipment and methods used to measure those values ​​or characteristics and / or within the tolerance limits specified by the technical standards applicable to the described technology.

[0019] Communication between currently isolated integrated circuit dies can be achieved through conductive communication coils in inductively coupled integrated circuit dies. This type of communication is referred to herein as a currently isolated communication link (GICL). The size of the coils used for the GICL (and / or the amount of signal power) can be affected by the distance between the coils. For example, for a given signal power, a larger distance between inductively coupled coils will result in a larger coil, which in turn can lead to an increase in the overall size of the integrated circuit die.

[0020] The various embodiments described herein improve signal transmission by reducing the distance between coils in an integrated circuit die while maintaining current isolation, thereby allowing for a reduction in coil size and potentially a reduction in the area of ​​the integrated circuit die. The integrated circuit die is mounted as a flip-chip die on a separate integrated circuit die having a high-voltage isolation layer acting as an insulator and a routing layer for wire bonding connections. In some embodiments, the isolation layer may be a passivation layer with a redistribution layer (RDL), and in other embodiments, the isolation layer may be an interposer circuit board with a routing layer. In still other embodiments, the isolation layer may include conductive traces for routing signals and power to the flip-chip mounted integrated circuit die. These and other embodiments are further described below.

[0021] Figure 1 This is a cross-sectional view of a packaged electronic device that includes two currently isolated integrated circuit devices. Figure 1 The packaged electronic device includes a first integrated circuit die 110 and a second integrated circuit die 150 separated by an insulating layer 120. In some embodiments, the insulating layer 120 has high voltage breakdown characteristics (e.g., >5000 volts) to allow the two integrated circuit dies to operate in different voltage domains and to withstand large voltage transients without damaging either integrated circuit die. As an example, but not as a limitation, one integrated circuit die may include a digital control circuit system operating at a relatively low voltage (e.g., less than 10 volts), and the second integrated circuit die may include a high-voltage circuit system (e.g., operating at hundreds of volts) intended to drive an inverter or a motor (e.g., for an electric vehicle).

[0022] like Figure 1 As shown, a first integrated circuit die 110 is mounted to a lead frame segment 186. The first integrated circuit die 110 includes one or more conductive coils 112 and at least one bonding pad 114 formed thereon. In some embodiments, the conductive coils 112 and bonding pads 114 are formed on one or more metallization layers on the first integrated circuit die 110. Figure 1In this example, bonding pad 114 provides power to the first integrated circuit die 110. In some embodiments, bonding pad 114 can provide a signal connection to the first integrated circuit die 110. The bonding pad formed on the integrated circuit die 110 can be used for any combination of signal and power connections. Four conductive coils 112 are shown on the integrated circuit die 110; however, any number of conductive coils may be included. Similarly, a bonding pad 114 is shown on the integrated circuit die 110; however, any number of bonding pads may be included.

[0023] The insulating layer 120 may comprise any material (at any thickness) providing the required amount of dielectric insulation material quality (e.g., >5000V breakdown characteristics). For example, a passivation layer (e.g., a polymer such as polyimide) may be formed on the integrated circuit die 110 to provide the desired characteristics. And, for example, an interposer circuit board may serve as the insulating layer 120. At least one conductive trace is formed on the insulating layer 120. For example, conductive trace 122 is formed on the insulating layer 120 to provide bonding pads for providing electrical connections to the second integrated circuit die 150. Figure 1 In this example, wire 174 is wire-bonded to conductive trace 122 and lead frame segment 184. Furthermore, for example, in some embodiments, conductive trace 124, together with via 173, is formed on insulating layer 120 to provide wire bonding pads for routing power to integrated circuit die 110. Figure 1 In this example, wire 172 is wire-bonded to conductive trace 124 and lead frame segment 182. Furthermore, for example, conductive trace 126 is formed on insulating layer 120.

[0024] The second integrated circuit die 150 includes one or more conductive coils 152 and at least one bonding pad 154, 156 formed thereon. In some embodiments, the conductive coils 152 and the bonding pads 154, 156 are formed on a metallization layer on the second integrated circuit die 150. Figure 1 In this example, bonding pads 154 and 156 can provide signal and power connections to the second integrated circuit die 150. For example, bonding pad 154 can provide power to the second integrated circuit die 150, and bonding pad 156 can provide other signal routing to the integrated circuit die 150. Four conductive coils 152 are shown on the integrated circuit die 150; however, any number of conductive coils may be included. Similarly, two bonding pads 154 and 156 are shown on the integrated circuit die 150; however, any number of bonding pads may be included.

[0025] The second integrated circuit die 150 is flip-chip mounted to the insulating layer 120, with the conductive coils 152 and 112 aligned substantially vertically. In some embodiments, this is performed using a solder reflow operation. Figure 1 In the illustrated embodiment, the distance between the inductively coupled conductive coils 152 and 112 is reduced compared to an embodiment in which the second integrated circuit die 150 is mounted "upright" on top of the conductive coil 152. If the second integrated circuit die 150 were to be mounted upright, the thickness of the integrated circuit die 150 would be included in the distance between the conductive coils 152 and 112, thereby increasing the distance between the inductively coupled conductive coils. In the various flip-chip embodiments described herein, the inductively coupled conductive coils are closer together, potentially allowing for lower signal power, smaller conductive coils, smaller integrated circuit dies, or any combination thereof.

[0026] Figure 1 The packaged integrated circuit device shown also includes an underfill material 170 and a molding material 190. These materials may include any suitable non-conductive material.

[0027] In the Figure 1 In the illustrated embodiment, insulating layer 120 includes conductive traces that provide wire bonding pads to route electrical connections (e.g., signals and / or power) to both integrated circuit dies 110 and 150. For example, in some embodiments, when power is applied to leadframe segment 184, conductive trace 122 may be electrically coupled to bonding pad 154 to provide power to integrated circuit die 150. Similarly, when power is applied to leadframe segment 182, conductive trace 124 may be electrically coupled to bonding pad 114 to provide power to integrated circuit die 110.

[0028] Figure 2 This is a cross-sectional diagram of a packaged electronic device comprising two currently isolated integrated circuit devices. Figure 2 In the illustrated embodiment, the insulating layer 120 leaves an exposed portion of the integrated circuit die 110. The exposed portion 210 occupies the area of ​​the integrated circuit die 110 including the bonding pads 114. Therefore, in the... Figure 2 In the illustrated embodiment, insulating layer 120 provides conductive trace 122 to provide electrical connections to integrated circuit die 150 (e.g., routing signals or power to integrated circuit die 150), but does not provide electrical connections to integrated circuit die 110 (e.g., routing signals or power to integrated circuit die 110). In these embodiments, insulating layer 120 provides current isolation between integrated circuit dies 110 and 150 while routing signals and / or power to only one of the integrated circuit dies.

[0029] Figure 3 Example process flows according to various embodiments are shown. At 310, conductive coils 112 and bonding pads 114 are formed on integrated circuit die 110. In some embodiments, conductive coils 112 are electrically coupled to wireless communication circuitry within integrated circuit die 110. For example, one or more conductive coils of conductive coils 112 may be coupled to transmitter circuitry, receiver circuitry, transceiver circuitry, etc. In some embodiments, bonding pads 114 may be electrically coupled to one or more circuit nodes within integrated circuit die 110 that supply power to circuitry within integrated circuit die 110. In these embodiments, when a voltage is applied to bonding pads 114, power can be supplied to circuitry within integrated circuit die 110, such as control circuitry, transmitter circuitry, receiver circuitry, transceiver circuitry, etc.

[0030] At 320, an insulating layer is formed on the integrated circuit die 110. In some embodiments, a polymer layer is formed on the integrated circuit die 110 to form an insulating layer 120. In other embodiments, an interposer circuit board is attached to the integrated circuit die 110 to form the insulating layer 120. A via 302 is formed in the insulating layer 120, and conductive traces 124, 122, and 126 are formed on the insulating layer 120. As shown at 320, conductive trace 124 on the insulating layer 120 is electrically coupled to a bonding pad 114 on the integrated circuit die 110 to provide an electrical connection between the conductive trace 124 and the integrated circuit die 110. In embodiments where the bonding pad 114 routes power to circuitry within the integrated circuit die 110, a voltage applied to the conductive trace 124 on the insulating layer 120 will provide power to the integrated circuit device 110. Conductive trace 122 is electrically isolated from conductive trace 124.

[0031] In some embodiments, the insulating layer 120 is made of a dielectric material thick enough to provide the desired minimum voltage breakdown characteristics (e.g., >5000V). For example, the insulating layer 120 may be formed of a polyimide layer having the desired thickness (e.g., ~20 μm). Furthermore, for example, the insulating layer may be formed of an interposer circuit board made of an organic material of the desired thickness.

[0032] At 330, an integrated circuit die 110 with insulating layer 120 is individually separated and mounted on a lead frame including lead frame sections 182, 184, and 186. Lead frame sections 182, 184, and 186 are electrically isolated from each other. This allows lead frame section 182 to supply power (or signals) to integrated circuit die 110 and allows lead frame section 184 to supply power (or signals) to integrated circuit die 150, while maintaining current isolation between the two integrated circuit dies.

[0033] At 340, conductive coil 152 and bonding pads 154 and 156 are formed on the second integrated circuit die 150. In some embodiments, conductive coil 152 is electrically coupled to wireless communication circuitry within the integrated circuit die 150. For example, one or more communication coils in communication coil 152 may be coupled to transmitter circuitry, receiver circuitry, transceiver circuitry, etc. In some embodiments, bonding pad 154 is electrically coupled to one or more circuit nodes within the integrated circuit die 150 that supply power to circuitry within the integrated circuit die 150. In these embodiments, when a voltage is applied to bonding pad 154, power can be supplied to circuitry within the integrated circuit die 150, such as control circuitry, transmitter circuitry, receiver circuitry, transceiver circuitry, etc. Metal contacts 314 and 316 are formed on bonding pad 154 and 156, respectively. In some embodiments, metal contacts 314 and 316 are copper bumps or copper balls placed on the respective bonding pads.

[0034] At 350, integrated circuit die 150 is flip-chip mounted to integrated circuit die 110. In some embodiments, the electrical and mechanical mounting of integrated circuit die 110 is achieved via a solder reflow process. As part of this process, communication coils 112 and 152 are aligned and face each other to allow inductive coupling. Additionally, conductive trace 122 is electrically coupled to bonding pad 154 to provide an electrical connection from the conductive trace 122 on insulating layer 120 to circuitry within integrated circuit die 150 (e.g., routing power and / or signals from the conductive trace 122 to the circuitry).

[0035] At 360, a non-conductive underfill material 170 is placed between the integrated circuit die 150 and the insulating layer 120. At 370, wire 172 is wire-bonded to the conductive trace 124 and the lead frame segment 182, wire 174 is wire-bonded to the conductive trace 122 and the lead frame segment 184, and the entire device is overmolded at 190.

[0036] The resulting packaged integrated circuit device shown at 370 includes: a first integrated circuit die 110 having a first conductive coil 112 and a first bonding pad 114 for providing a first electrical connection to the first integrated circuit die; a dielectric layer 120 formed on the first integrated circuit die 110 over the first conductive coil 112 and the first bonding pad 114, the dielectric layer 120 including a via 302 for providing electrical coupling to the first bonding pad 114 on the first integrated circuit die 110, and a first conductive trace 124 coupled to the via 302 to provide the first electrical connection to the first integrated circuit die 110, the dielectric layer 120 further including a second conductive trace 122; and a second integrated circuit. Die 150 has a second conductive coil 152 for inductive coupling to a first conductive coil 112, and a second bonding pad 154 for providing a second electrical connection to the second integrated circuit die 150, wherein the second integrated circuit die 150 is mounted to the first integrated circuit die 110, wherein the first conductive coil 112 faces and is aligned with the second conductive coil 152, and wherein the second bonding pad 154 faces and is aligned with a second conductive trace 122 on a dielectric layer 120 to electrically couple the second conductive trace 122 on the dielectric layer 120 to the second bonding pad 154 to provide a second electrical connection to the second integrated circuit die 150.

[0037] Figure 4 This is a flowchart illustrating example methods according to various embodiments. At 410, a first conductive coil is formed on a first integrated circuit die. The first conductive coil may be a communication coil for inductive coupling to a coil in another integrated circuit die, the other integrated circuit die being current-isolated from the first integrated circuit die. For example, the operation of 410 may involve forming a conductive coil 112 on integrated circuit die 110.

[0038] At 420, an insulating layer is formed on the first integrated circuit die. In some embodiments, the insulating layer is a passivation layer formed of a polymer, and in other embodiments, the insulating layer is an interposer circuit board. The insulating layer insulates the first integrated circuit die from the second integrated circuit die to provide current isolation between the integrated circuit dies, while providing wireless communication between conductive coils in the integrated circuit die via inductive coupling. At 430, a conductive trace is formed on the insulating layer. The conductive trace may be one of a plurality of conductive traces formed in a metallization layer on the insulating layer. In some embodiments, at least one of the conductive traces routes signals and / or power to the second integrated circuit, which is flip-chip mounted to the first integrated circuit die.

[0039] At 440, the first integrated circuit die is mounted on a lead frame. In some embodiments, this includes mounting on a lead frame with electrically isolated lead frame segments. For example, the first integrated circuit die may be mounted on a first lead frame segment isolated from the second and third lead frame segments (e.g., lead frame segments 182, 184).

[0040] At position 450, a second conductive coil is formed on the second integrated circuit die. The second conductive coil may be a communication coil for inductive coupling to a communication coil on the first integrated circuit die. For example, the operation at 450 may form a conductive coil 152 on integrated circuit die 150.

[0041] At 460, a metal contact is placed on the second integrated circuit die, wherein the metal contact is electrically coupled to provide signals and / or power to the second integrated circuit. In some embodiments, the action of 460 corresponds to placing the metal contact 314 on the bonding pad 154.

[0042] At 470, the second integrated circuit die is coupled to the first integrated circuit die such that the second conductive coil faces the first conductive coil and is aligned with the first conductive coil to allow inductive coupling, and such that metal contacts are coupled to conductive traces on the insulating layer to provide electrical connection to the second integrated circuit die (e.g., routing signals and / or power to the second integrated circuit die).

Claims

1. A system, characterized in that, include: The first integrated circuit die has a first communication coil; A second integrated circuit die has a second communication coil, wherein the second integrated circuit die is positioned relative to the first integrated circuit die such that the first communication coil faces the second communication coil and is aligned with the second communication coil to allow inductive coupling between the first communication coil and the second communication coil; as well as An insulating layer is positioned between the first integrated circuit die and the second integrated circuit die, the insulating layer including a first conductive trace coupled to provide a first electrical connection to the second integrated circuit die.

2. The system according to claim 1, characterized in that, The insulating layer includes a second conductive trace coupled to provide a second electrical connection to the first integrated circuit die.

3. The system according to claim 1, characterized in that, The insulating layer leaves an exposed portion of the first integrated circuit die, and the electrical connection to the first integrated circuit die is formed on the exposed portion of the first integrated circuit die.

4. The system according to claim 1, characterized in that, The first integrated circuit die includes at least a third communication coil, and the second integrated circuit die includes at least a fourth communication coil.

5. A packaged integrated circuit device, characterized in that, include: A first integrated circuit die has a first conductive coil and a first bonding pad for providing a first electrical connection to the first integrated circuit die; A dielectric layer, formed on the first integrated circuit die above the first conductive coil and the first bonding pad, the dielectric layer including elements for providing electrical coupling to the first integrated circuit die. The via of the first bonding pad on the first integrated circuit die, and the first conductive trace coupled to the via to provide the first electrical connection to the first integrated circuit die, the dielectric layer further including a second conductive trace; as well as A second integrated circuit die has a second conductive coil for inductive coupling to the first conductive coil, and a second bonding pad for providing a second electrical connection to the second integrated circuit die, wherein the second integrated circuit die is mounted to the first integrated circuit die, wherein the first conductive coil faces and is aligned with the second conductive coil, and wherein the second bonding pad faces and is aligned with the second conductive trace on the dielectric layer to electrically couple the second conductive trace on the dielectric layer to the second bonding pad to provide the second electrical connection to the second integrated circuit die.

6. The packaged integrated circuit device according to claim 5, characterized in that, The dielectric layer provides current isolation between the first integrated circuit die and the second integrated circuit die.

7. The packaged integrated circuit device according to claim 5, characterized in that, The first bonding pad and the second bonding pad are electrically isolated from each other.

8. A method, characterized in that, include: A first conductive coil is formed on the first integrated circuit die; An insulating layer is formed on the first integrated circuit die; Conductive traces are formed on the insulating layer; A second conductive coil is formed on the second integrated circuit die; Place the bonding pads on the second integrated circuit die; as well as The second integrated circuit die is coupled to the first integrated circuit die such that the second conductive coil faces and is aligned with the first conductive coil to allow inductive coupling between the first and second conductive coils, and the bonding pads on the second integrated circuit die are coupled to the conductive traces on the insulating layer to provide an electrical connection to the second integrated circuit die.

9. The method according to claim 8, characterized in that, The coupling of the second integrated circuit die to the first integrated circuit die includes performing a solder reflow operation.

10. The method according to claim 9, characterized in that, Additionally, it includes filling the cavity between the second integrated circuit die and the insulating layer with a non-conductive bottom filler material.

Images