PCB integrated power module

Abstract

This application provides a PCB integrated power module. The PCB integrated power module includes a PCB board, a substrate, and power chips. The power chips include a control electrode, a first power terminal, and a second power terminal. The power chips include a first power chip and a second power chip. The PCB board includes adjacent and mutually insulated first and second metal layers. The gate traces of the first power chips are disposed on the first metal layer and correspondingly connected to the control electrode of the first power chip. The second metal layer has a metal connection region that is not at the same potential as the second power terminal of the first power chip. The area of ​​all the gate traces of the first power chips facing the metal connection region does not exceed 20% of the sum of the areas of all the first power chips.

Description

Technical Field

[0001] This application relates to the field of power semiconductor device technology, and in particular to a PCB integrated power module. Background Technology

[0002] In key high-power application areas such as new energy vehicles, industrial motor drives, and photovoltaic inverters, PCB (Printed Circuit Board) integrated power modules have become core components for achieving efficient system operation due to their high integration, small size, and excellent power density characteristics.

[0003] PCB-integrated power modules combine the processes of traditional power modules and PCB boards, integrating the traditional power module onto a printed circuit board (PCB). Compared to traditional power module bonding processes, the internal electrical connections utilize microvia technology, which offers greater flexibility. Through a stacked design, the module can achieve lower commutation loop inductance. Furthermore, by combining microvia technology with an AMB (Active Metal Brazing Ceramic Substrate) ceramic substrate, integrated modules with superior thermal conductivity compared to traditional power modules can be achieved.

[0004] Unlike traditional power modules that use aluminum wire bonding, copper wire bonding, and copper strip bonding, the electrical connections between the power terminals and signal terminals of a PCB-integrated power module and the power chip are achieved entirely through the copper foil of each PCB layer and the microvia technology between different layers. Therefore, the drive signal copper foil layer is easily affected by the power copper foil layer, negatively impacting the electrical performance of the integrated power module. Summary of the Invention

[0005] The purpose of this application is to provide a PCB integrated power module that can solve at least one technical problem existing in the prior art.

[0006] One aspect of this application provides a PCB-integrated power module. The PCB-integrated power module includes a PCB board, a substrate embedded in the PCB board, and a power chip disposed on the substrate. The power chip includes a control electrode, a first power terminal, and a second power terminal. Specifically, the power chip includes a first power chip and a second power chip; the PCB board includes adjacent and mutually insulated first and second metal layers; the gate traces of the first power chips are disposed on the first metal layer and correspondingly connected to the control electrode of the first power chip; the second metal layer has a metal connection region that is not at the same potential as the second power terminal of the first power chip; and the area of ​​the gate traces of all the first power chips facing the metal connection region does not exceed 20% of the sum of the areas of all the first power chips.

[0007] Furthermore, the first power chip is an upper-bridge power chip, the second power chip is a lower-bridge power chip, and the gate trace of the first power chip is the upper-bridge gate trace of the upper-bridge power chip.

[0008] Furthermore, the metal connection region includes a DC negative connection region, which is connected to the second power terminal of the lower bridge power chip, and the upper bridge gate trace is configured to reduce the area directly opposite the DC negative connection region.

[0009] Furthermore, the upper bridge gate trace includes a first upper bridge gate trace and a second upper bridge gate trace connected to the first upper bridge gate trace. The second upper bridge gate trace is connected to the control electrode of the upper bridge power chip through a micro-hole on the PCB board.

[0010] Furthermore, the upper bridge gate trace includes a first upper bridge gate trace, and the second metal layer also has a second upper bridge gate trace. An insulating region is provided between the second upper bridge gate trace and the DC negative electrode connection region to insulate the second upper bridge gate trace from the DC negative electrode connection region. The first upper bridge gate trace is connected to the control electrode of the upper bridge power chip through the second upper bridge gate trace.

[0011] Furthermore, the PCB board also includes a third metal layer, which is adjacent to and insulated from the second metal layer. The third metal layer is disposed close to the power chip and has a DC positive connection area and an AC connection area. The DC positive connection area is connected to the first power terminal of the upper bridge power chip, and the AC connection area is connected to the second power terminal of the upper bridge power chip and the first power terminal of the lower bridge power chip.

[0012] Furthermore, the upper bridge gate trace includes a first upper bridge gate trace, and the third metal layer also has a second upper bridge gate trace. An insulating region is provided in the area of ​​the second metal layer opposite to the second upper bridge gate trace. The first upper bridge gate trace is connected to the control electrode of the upper bridge power chip through the second upper bridge gate trace.

[0013] Furthermore, the second metal layer is also provided with a third upper bridge gate connection portion, which is insulated from the DC negative terminal connection portion through the insulating region. The first upper bridge gate trace and the second upper bridge gate trace are connected through the third upper bridge gate connection portion.

[0014] Furthermore, the first upper gate trace and the third upper gate connection portion are connected through a first micro-hole on the PCB board, and the second upper gate trace and the third upper gate connection portion are connected through a second micro-hole on the PCB board, wherein the positions of the first micro-hole and the second micro-hole are spatially offset from each other.

[0015] Furthermore, the third upper bridge gate connection portion is directly opposite the middle region of the second upper bridge gate trace.

[0016] Furthermore, the direction of the second upper bridge gate trace is parallel to the current direction of the PCB integrated power module, and the direction of the first upper bridge gate trace is perpendicular to the direction of the second upper bridge gate trace.

[0017] Furthermore, the power chip includes multiple parallel upper-bridge power chips, and the multiple upper-bridge power chips include at least one row. Each row includes two upper-bridge power chips arranged along a first direction, wherein the first direction is parallel to the current direction of the PCB integrated power module. The opposite ends of the second upper-bridge gate traces are respectively connected to the control electrodes of the two upper-bridge power chips in the corresponding row through micro-holes on the PCB. When the at least one row is multiple rows, the multiple rows are spaced apart along a second direction, which is perpendicular to the first direction. The number of second upper-bridge gate traces is the same as the number of rows of upper-bridge power chips.

[0018] Furthermore, the power chip includes a MOSFET chip, wherein the control electrode, the first power terminal, and the second power terminal of the power chip are the gate, drain, and source of the MOSFET chip, respectively; or, the power chip includes a combination of an IGBT chip and an FRD chip, wherein the control electrode, the first power terminal, and the second power terminal of the power chip are the gate, collector, and emitter of the IGBT chip, respectively, and the first power terminal and the second power terminal are also the cathode and anode of the FRD chip.

[0019] The PCB integrated power module of one or more embodiments of this application modifies the design of the gate traces of the first power chip, ensuring that the area of ​​the metal connection regions at non-same potential between the gate traces of all the first power chips and the second power terminals of the first power chips does not exceed 20% of the sum of the areas of all the first power chips. This allows for a reduction in the width of the gate traces. Thinner gate traces mean a smaller area exposed to external electromagnetic interference, i.e., a weaker antenna effect. Furthermore, a smaller gate signal area reduces the area of ​​the metal connection regions at different potentials, thus decreasing the influence of electric fields from adjacent metal layers. In other words, thinner gate traces mean that the gate signal is less susceptible to interference from both electric and magnetic fields. Therefore, the oscillation of the PCB integrated power module can be effectively reduced. Attached Figure Description

[0020] Figure 1 This is a circuit diagram of one phase in a three-phase full-bridge circuit.

[0021] Figure 2 This is a typical turn-on oscillation waveform diagram of a PCB integrated power module with a MOSFET chip packaged in it.

[0022] Figure 3 This is a schematic diagram of the drive circuit of a power module.

[0023] Figure 4 This is a schematic diagram of the gate signal copper foil of the upper and lower bridge arms in the related technology.

[0024] Figure 5 This is a schematic diagram of a parallel plate capacitor formed between adjacent metal layers.

[0025] Figure 6 This is a top view of a PCB integrated power module according to an embodiment of this application.

[0026] Figure 7 For along Figure 6 A cross-sectional view along line AA in the diagram.

[0027] Figure 8 For along Figure 6 A cross-sectional view of the BB line.

[0028] Figure 9 This is a schematic diagram of the power chip arrangement on a substrate according to one embodiment of this application.

[0029] Figure 10 This is a schematic diagram of the wiring of each metal layer of a PCB board according to an embodiment of this application.

[0030] Figure 11 This is a schematic diagram of the wiring of each metal layer of a PCB board according to another embodiment of this application.

[0031] Figure 12 This is a schematic diagram of the wiring of each metal layer of a PCB board according to another embodiment of this application.

[0032] Figure 13 This is a schematic diagram showing that, according to an embodiment of this application, the first upper-bridge gate trace and the second upper-bridge gate trace are connected to the third upper-bridge gate connection portion through micro-holes on the PCB board. Detailed Implementation

[0033] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses consistent with some aspects of this application as detailed in the appended claims.

[0034] With the continuous increase in power level requirements in key high-power applications such as new energy vehicles, industrial motor drives, and photovoltaic inverters, the heat generated by PCB integrated power modules during operation has increased dramatically. The heat generated by integrated power modules in these applications must be effectively dissipated to the outside of the integrated power module. Maintaining a dynamic balance between the heat generation and heat dissipation power of the integrated power module is a crucial prerequisite for ensuring that the junction temperature of its power chip remains stable within the operating junction temperature range during operation. Here, "power chip" typically refers to the bare die of a power semiconductor device. Common types of power semiconductors include Si-based IGBT (Insulated Gate Bipolar Transistor) chips, Si-based FRD (Fast Recovery Diode) chips (usually used in conjunction with Si-based IGBT chips), SiC-based MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) chips, and GaN-based HEMT (High Electron Mobility Transistor) chips. Limited by the operating junction temperature range of power chips and the heat dissipation capacity of integrated power modules, how to reduce the energy loss during the operation of integrated power modules and control the junction temperature within an acceptable range has become a key bottleneck restricting further breakthroughs in the reliability, service life and power density of PCB integrated power modules.

[0035] The heat generated during the operation of an integrated power module can be categorized into three parts based on the stage of generation: the heat generated by the power loss Pon during the turn-on process, the heat generated by the power loss Poff during the turn-off process, and the heat generated by the power loss Pcond during the stable conduction state. Compared to traditional power modules, by optimizing the structure of integrated power modules, they can typically have a smaller stray inductance in the power circuit. Because the turn-on and turn-off speeds of a power module are limited by the stray inductance of the power circuit, a smaller stray inductance means that the integrated power module can turn on and off faster, thereby reducing the heat generated during the turn-on and turn-off processes.

[0036] Figure 1 This paper presents a circuit diagram of one phase in a three-phase full-bridge circuit. A circuit with only one phase in a three-phase full-bridge circuit is called a half-bridge circuit. Figure 1 The half-bridge circuit is illustrated using a MOSFET chip as an example. Figure 1 As shown, the current output from the AC terminal is a sinusoidal alternating current. When the output current is positive, the current path is as shown by the solid arrow in the figure. By controlling the upper bridge MOSFET chip, it is determined whether the output current flows out from the DC+ terminal or the DC- terminal. The output voltage waveform (i.e., the pulse width modulation (PWM) signal) is controlled by the time ratio of these two paths. Similarly, when the output current is negative, the current path is as shown by the dashed arrow in the figure. By controlling the lower bridge MOSFET chip, it is determined whether the output current flows out from the DC+ terminal or the DC- terminal.

[0037] As the turn-on and turn-off speeds of PCB integrated power modules increase, the turn-on and turn-off processes are easily affected by interference, resulting in oscillations. On one hand, due to the high voltage and current change rates during oscillation, the oscillation itself risks damaging the power chip of the integrated power module, and it also generates electromagnetic interference to the drive control circuitry near the integrated power module. On the other hand, oscillations prolong the turn-on and turn-off process, thereby increasing turn-on and turn-off losses and heat generation. Therefore, suppressing or even eliminating oscillations during the turn-on and turn-off processes is crucial for the application of PCB integrated power modules.

[0038] Figure 2 A typical turn-on oscillation waveform of a PCB-integrated power module with a MOSFET chip packaged in it is shown. Figure 2 The diagram shows the gate control signal V of the MOSFET chip. GS The waveform, the drain voltage V of the MOSFET chip DS The curve and the current I flowing through the MOSFET chip DThe curve shows that during the turn-on process, the voltage change rate caused by oscillation is much higher than the original voltage change rate. At the same time, the oscillation of the gate voltage leads to an increase in the length of the Miller plateau and a decrease in the drain voltage oscillation. During this period, the current flowing through the MOSFET chip is already the large current of the load. The integral of the product of voltage and current is the heat generated by the MOSFET chip during the turn-on process. It can be seen that the extended turn-on time caused by oscillation will lead to greater heat generation.

[0039] The most common interference is usually caused by the stable drive signal voltage being affected by the high rate of change of voltage or current in the power path during the turn-on and turn-off processes. This is due to the effect of the electric field or magnetic field, which causes the drive voltage of the power chip gate to change. Figure 3 A schematic diagram of a drive circuit for a power module is shown. (For example...) Figure 3 As shown, the drive circuit switches between positive and negative drive voltages (e.g., -3V and +18V) according to the control signal. In addition to the internal electrical connections of the power module and the parasitic gate resistance within the chip, an external drive resistor is placed in the drive circuit to adjust the switching speed of the MOSFET chip. Figure 3 The resistance of all drive circuits is combined into a single equivalent drive resistance R. G Similarly, in addition to the parasitic gate-source capacitance of the MOSFET chip itself, an additional gate-source capacitance is usually placed in the drive circuit. Figure 3 The capacitor C in GS This is the equivalent capacitance of the two. Capacitance C GS and the stray inductance L of the drive circuit G and driving resistor R G The RLC circuit constitutes the drive loop. When the switching state is changed to switch the drive voltage between positive and negative voltages, the excessively fast switching speed causes a rapid change in the drive voltage. This change in drive voltage acts as an excitation source, generating RLC resonance in the drive loop, leading to oscillations in the gate voltage. Furthermore, in the power loop of the half-bridge topology, the electrical connection between the upper and lower bridge arms between the DC+ and DC- terminals also contains parasitic resistance and inductance. Figure 3 The values ​​in the figure are represented as equivalent resistance (ESR) and stray inductance (L). S And bus capacitor C DC-link Furthermore, during commutation, changes in the gate drive voltage further affect the current in the power circuit. Similarly, changes in the power circuit current act as an excitation source, influencing the equivalent resistance (ESR) and stray inductance (L) in the power circuit. S Parasitic capacitance C of MOSFET chip DS This generates RLC oscillations. The voltage oscillations in the power circuit, in turn, are transmitted through the feedback capacitance C parasitic on the MOSFET chip. GD This causes a voltage change at the gate of the drive circuit. Only when the drive resistance R...G A sufficiently large driving resistor R is needed to suppress ringing, but a large driving resistor R... G This means a slower switching speed. However, a slower switching speed leads to a significant increase in switching losses.

[0040] In summary, due to crosstalk between the drive circuit and the power circuit, the voltage change in the gate voltage after being disturbed may cause oscillation. Therefore, the gate routing layout inside the integrated power module is crucial to the turn-on and turn-off performance of the integrated power module.

[0041] In related technologies, some PCB integrated power module designs do not consider the susceptibility of the gate layout to interference. The resulting oscillations and adverse effects on the switching performance of the integrated power module are often accepted as inherent characteristics of the integrated power module. These designs typically involve large areas of copper plating for the gate signal. Figure 4 A schematic diagram of the gate signal copper foil of the upper and lower bridge arms in the related technology is shown. For example... Figure 4 As shown, the gate signal copper foil of the upper and lower bridge arms is composed of large-area copper foil in two separate sections. The initial intention of this design was to reduce the stray inductance L of the drive circuit between the external driver and the power chip gate caused by the packaging by using a large area of ​​copper. G However, the large copper area of ​​the drive circuit may cause the following problems: First, from the perspective of electric field, the large area of ​​gate signal copper is more susceptible to interference from the potential of other PCB layers; second, from the perspective of magnetic field, the large area of ​​gate signal copper is more susceptible to interference from external magnetic fields, i.e., the antenna effect is obvious. Therefore, the oscillation of the PCB integrated power module in this part of the design is obvious. For oscillations that will not cause failure, if the design chooses to accept the existence of oscillations, then it is necessary to suppress the oscillations from the application perspective. In application, larger parameters such as drive resistors and drive capacitors need to be matched to reduce the turn-on and turn-off speeds, thereby suppressing the amplitude of oscillations. However, slower turn-on and turn-off speeds mean greater losses during turn-on and turn-off, thus necessitating a reduction in the application current and power of the integrated power module. At the same time, slower turn-on and turn-off speeds mean that the switching frequency of the PCB integrated power module application is limited. Lower switching frequencies will bring the following problems: First, larger filter components, increasing the size and cost of the inverter; second, a higher harmonic ratio, posing challenges to the heat dissipation system.

[0042] Furthermore, due to limitations in manufacturing costs and process complexity, the number of copper layers in PCB integrated modules is also limited. Too many lamination layers make the product less cost-competitive, and more complex processes increase production cycles, significantly impacting product reliability and estimated lifespan. PCB integrated power modules typically have only three copper layers above the AMB ceramic substrate chip layer for current transmission. These three copper layers must accommodate the routing of DC+ terminals, AC terminals, DC- terminals, and gate control signals. In such a copper layout design, the optimization of stray inductance must be considered. The most basic design principle is a stacked structure, where the copper path for current flowing from the DC+ terminal into the upper-bridge semiconductor power chip and the path for current flowing from the lower-bridge semiconductor power chip to the DC- terminal are stacked. Because the current directions are opposite and they completely overlap spatially, their mutual inductance is significantly reduced. Therefore, on the third metal layer L3, the closest layer above the AMB ceramic substrate, copper is laid on one side for the DC+ current flowing into the upper bridge power chip circuit, and on the other side, copper is laid for the current flowing out from the upper bridge power chip to the AC terminal and into the lower bridge power chip. The second metal layer L2 is laid with copper for the current flowing from the lower bridge power chip to the DC- terminal. Thus, the DC+ and DC- traces of the power circuit are distributed on the third metal layer L3 and the second metal layer L2, which are spatially stacked. The first metal layer L1 is laid with the gate control signal traces of the upper and lower bridge power chips, as well as the leads of other signal terminals.

[0043] like Figure 5 As shown, due to the large copper area of ​​the gate trace on the first metal layer L1 and the large copper area of ​​the DC- power loop trace on the second metal layer L2, they are spatially aligned and form a standard parallel plate capacitor C with the insulating material between the two layers. L1-L2 When the parallel plate capacitor C L1-L2When the relative potential of the copper layers at both ends changes, a charging and discharging current is generated on the copper layers. Because the voltage between the lower gate trace of the first metal layer L1 and the DC-power circuit of the second metal layer L2 only changes between the turn-on and turn-off gate voltages during commutation, for example, from -3V to 18V, the charging and discharging current caused by the planar capacitor effect is very small and its impact on the gate driving process can be ignored. However, the DC-voltage between the upper gate trace of the first metal layer L1 and the second metal layer L2 will be superimposed with the change in the bus voltage during commutation. For example, when the bus voltage is 800V, the voltage across the planar capacitor will change from -3V to 818V during commutation. Such a large voltage change will inevitably cause a considerable charging and discharging current on the planar capacitor. The gate terminal of the drive circuit is electrically connected to an external driver. However, the driver's current capability is limited, typically below 10A. During switching, in addition to the normal current supply to the power chip, the current provided by the driver must also charge and discharge the plate-plate capacitor due to the aforementioned plate-plate capacitor effect. This effect significantly prolongs the turn-on and turn-off process of the upper bridge, increasing its energy. The charging and discharging current caused by this plate-plate capacitor may also cause a sudden change in the gate voltage of the upper bridge power chip. As mentioned earlier, such excitation will induce RLC resonance in the drive circuit and subsequently in the power circuit. Furthermore, this capacitor itself, along with the parasitic capacitance and inductance of the lower bridge power chip, forms an RLC oscillation path, further complicating the oscillation mechanism.

[0044] In view of this, this application provides an improved PCB integrated power module that can solve at least one of the technical problems mentioned above.

[0045] The PCB integrated power modules of various embodiments of this application will now be described in detail with reference to the accompanying drawings. Unless otherwise specified, the features of the following embodiments and implementation methods can be combined with each other.

[0046] Figure 6 A top view of a PCB-integrated power module according to an embodiment of this application is disclosed. Figure 7 Revealed along Figure 6 A cross-sectional view of line AA in the middle. Figure 8 Revealed along Figure 6 A sectional view along the BB line. (Refer to reference...) Figures 6 to 8 As shown, a PCB integrated power module according to one embodiment of this application includes a PCB board 100, a substrate 200 embedded in the PCB board 100, and a power chip 300 disposed on the substrate 200.

[0047] The substrate 200 may include, for example, a ceramic substrate 200. The power chip 300 includes an upper bridge power chip 301 and a lower bridge power chip 302.

[0048] Figure 9 This diagram illustrates the arrangement of power chips 300 on a substrate 200 according to one embodiment of this application. Figure 9 As shown, in some embodiments, considering the junction temperature tolerance of each bridge arm power chip 300 of the PCB integrated power module, each bridge arm is typically composed of multiple upper bridge power chips 301 connected in parallel and multiple lower bridge power chips 302 connected in parallel to share the current. Therefore, the power chips 300 on the substrate 200 may include multiple upper bridge power chips 301 connected in parallel, and the multiple upper bridge power chips 301 include at least one row, each row including two upper bridge power chips 301 arranged along a first direction, wherein the first direction is parallel to the current direction of the PCB integrated power module. When the at least one row of upper bridge power chips 301 includes multiple rows, the multiple rows are respectively arranged at intervals along a second direction, the second direction being perpendicular to the first direction.

[0049] Correspondingly, the power chip 300 on the substrate 200 may include a plurality of parallel lower-bridge power chips 302. The plurality of lower-bridge power chips 302 include at least one row, and each row includes two lower-bridge power chips 302 arranged along a first direction, wherein the first direction is parallel to the current direction of the PCB integrated power module. When the lower-bridge power chips 302 include at least one row of multiple rows, the multiple rows are arranged at intervals along a second direction, and the second direction is perpendicular to the first direction.

[0050] exist Figure 9 In the example shown, the upper-bridge power chip 301 and the lower-bridge power chip 302 each include six chips connected in parallel, arranged in three rows in the left-right direction, with each row including two chips arranged vertically. It is understood that... Figure 9 This is merely an example of the present application and is intended for ease of description only. It does not constitute a limitation of the present application. In practical applications, the number of upper bridge power chips 301 and lower bridge power chips 302 can be set as needed.

[0051] The power chip 300 includes a control electrode, a first power terminal, and a second power terminal.

[0052] In some embodiments, the power chip 300 of this application may include a MOSFET chip. The control electrode, first power terminal, and second power terminal of the power chip 300 are respectively the gate, drain, and source of the MOSFET chip.

[0053] In the embodiments of this application, a MOSFET chip will be used as an example for illustration and description. However, it is understood that the power chip 300 of this application is not limited to a MOSFET chip. In other embodiments, the power chip 300 of this application may also include a combination of an IGBT chip and an FRD chip, a GaN-based HEMT chip, or other power semiconductor devices with similar functions. For the combination of an IGBT chip and an FRD chip, the control electrode, the first power terminal, and the second power terminal of the power chip 300 are the gate, collector, and emitter of the IGBT chip, respectively, and the first power terminal and the second power terminal are also the cathode and anode of the FRD chip.

[0054] It should be noted that since the MOSFET chip has a built-in body diode, when the power chip 300 includes a MOSFET chip, each power chip 300 does not need to be connected in parallel with an FRD chip; however, when the power chip 300 includes an IGBT chip, each power chip 300 still needs to be connected in parallel with an FRD chip.

[0055] Considering that the drive signal copper layer is easily affected by the power copper layer, which can negatively impact the electrical performance of the PCB integrated power module, the layout design principle of the control electrode of the power chip 300 in the PCB integrated power module of this application is as follows: Principle 1: Adjacent layers (the upper and lower layers) to the control electrode copper layer should avoid having copper layers with different potentials than the control electrode traces. For example, for a MOSFET chip, the only difference between the gate and source is the driving voltage, which can be considered as the same potential. The DC positive (DC+) terminal and the drain DH of the upper-bridge power chip 301 are at the same potential V1; the gate GH, source SH, power (AC) terminal, and drain DL of the lower-bridge power chip 302 are at the same potential V2; the gate GL, source SL, and DC negative (DC-) terminal of the lower-bridge power chip 302 are at the same potential V3.

[0056] Principle 2: When the situation described in Principle 1 cannot be avoided, the area of ​​the control electrode trace copper and the copper of different potentials in adjacent layers should be minimized.

[0057] Principle 3: While controlling the routing of the power traces, it is also necessary to ensure that they do not have a significant negative impact on the current carrying capacity of the power copper foil and the stray inductance of the module.

[0058] Considering the high manufacturing process and cost involved in Principle 1, and weighing the manufacturing process and cost, the layout of the control electrode of the power chip 300 in the PCB integrated power module of this application is mainly designed based on Principles 2 and 3. The layout of the control electrode of the power chip 300 in the PCB integrated power module of this application will be described in detail below.

[0059] The power chip 300 includes a first power chip and a second power chip. The PCB board 100 includes an adjacent and mutually insulated first metal layer L1 and a second metal layer L2. The gate trace of the first power chip is disposed on the first metal layer L1. The gate trace of the first power chip is correspondingly connected to the control electrode of the first power chip. The second metal layer L2 is provided with a metal connection area that is not at the same potential as the second power terminal of the first power chip.

[0060] The area of ​​the gate traces of all the first power chips facing the metal connection area located in the second metal layer L2 does not exceed 20% of the sum of the areas of all the first power chips.

[0061] In one embodiment of this application, the gate trace of the first power chip located in the first metal layer L1 may be configured to be composed of thin strip traces to reduce the width of the gate trace of the first power chip, thereby reducing the area opposite to the metal connection region located in the second metal layer L2.

[0062] Compared to Figure 4 The large-area gate traces of the first power chip in this application are minimized by reducing the area of ​​the metal connection region that is not at the same potential as the second power terminal of the first power chip. This allows for a reduction in the width of the gate traces. Thinner gate traces mean a smaller area exposed to external electromagnetic interference, resulting in a weaker antenna effect. In other words, thinner gate traces mean that the gate signal is less susceptible to interference from both electric and magnetic fields. Furthermore, the smaller gate signal area reduces the area of ​​the adjacent non-equivalent metal connection region, thus reducing the influence of the non-equivalent electric field from the adjacent metal layer. This effectively reduces the oscillation of the PCB-integrated power module.

[0063] In some embodiments, the first power chip described in this application is an upper-bridge power chip 301, and the second power chip is a lower-bridge power chip 302. The gate trace of the first power chip disposed on the first metal layer L1 is the upper-bridge gate trace 310 of the upper-bridge power chip 301, and the upper-bridge gate trace 310 is connected to the control electrode of the upper-bridge power chip 301. That is, the upper-bridge gate trace 310 of the upper-bridge power chip 301 is affected by a metal connection region in an adjacent layer that is not at the same potential as the second power terminal of the upper-bridge power chip 301.

[0064] In some embodiments, the metal connection region of the upper gate trace 310 of the upper bridge power chip 301, which is affected by the second power terminal of the adjacent second metal layer L2 at a different potential from that of the upper gate gate trace 310 of the upper bridge power chip 301, includes a DC negative connection region 132, which is connected to the second power terminal of the lower bridge power chip 302. Since the upper gate trace 310 and the DC negative connection region 132 are at different potentials, in this case, for example, the upper gate trace 310 disposed in the first metal layer L1 can be configured as a thin strip trace, such that the area of ​​the upper gate trace 310 of all the upper bridge power chips 301 disposed in the first metal layer L1 and the DC negative connection region 132 disposed in the second metal layer L2 does not exceed 20% of the sum of the areas of all the upper bridge power chips 301, thereby reducing the influence of the different potentials of the DC negative terminals of the adjacent layers on the gate of the upper bridge power chip 301.

[0065] like Figure 7 and Figure 8 As shown, in some embodiments, the PCB board 100 further includes a third metal layer L3, which is adjacent to and insulated from the second metal layer L2, and is disposed close to the power chip 300. The third metal layer L3 has a DC positive connection area 131 and an AC connection area 133. The DC positive connection area 131 is connected to the first power terminal of the upper bridge power chip 301, and the AC connection area 133 is connected to the second power terminal of the upper bridge power chip 301 and the first power terminal of the lower bridge power chip 302. The third metal layer L3 also has a DC negative connection area 132, which is insulated and separated from both the DC positive connection area 131 and the AC connection area 133.

[0066] The PCB integrated power module of this application has a DC positive connection area 131, a DC negative connection area 132, and an AC connection area 133 on the third metal layer L3, and a DC negative connection area 122 on the second metal layer L2. An upper bridge power chip 301 and a lower bridge power chip 302 are provided on the substrate 200. Through the stacking of the PCB board 100, such as... Figure 7 and Figure 8 As shown, current flows from the DC+ terminal through the DC positive connection region 131 on the third metal layer L3 and through the metal layer on the substrate 200 into the drain DH of the upper bridge power chip 301. The source SH of the upper bridge power chip 301 flows through the AC connection region 133 on the third metal layer L3 and through the metal layer on the substrate 200 into the drain DL of the lower bridge power chip 302. The source SL of the lower bridge power chip 302 is connected to the DC negative connection region 122 on the second metal layer L2 through a micro-hole on the PCB board. Figure 7 and Figure 8It can be seen that the current flow path from the DC+ terminal into the upper bridge power chip 301 and the current flow path from the lower bridge power chip 302 to the DC- terminal are superimposed and their current directions are opposite. They form opposite commutation paths in the second metal layer L2 and the third metal layer L3, which can effectively reduce the stray inductance of the commutation circuit.

[0067] The following will describe in detail several embodiments of the layout of the upper bridge gate trace 310 of the upper bridge power chip 301 provided in this application with reference to the figures.

[0068] Figure 10 This diagram illustrates the wiring of each metal layer of a PCB board 100 according to one embodiment of this application. Figure 10 As shown, in one embodiment of this application, the upper bridge gate trace 310 disposed on the first metal layer L1 may include a first upper bridge gate trace 311 and a second upper bridge gate trace 312 connected to the first upper bridge gate trace 311. The first upper bridge gate trace 311 may be connected to the upper bridge gate pad 330 disposed on the first metal layer L1, and the second upper bridge gate trace 312 may be connected to the control electrode of the upper bridge power chip 301 through a microvia on the PCB board 100.

[0069] The first metal layer L1 of the PCB board 100 of this application is further provided with a lower gate trace 320. The lower gate trace 320 disposed in the first metal layer L1 may include a first lower gate trace 321 and a second lower gate trace 322 connected to the first lower gate trace 321. The first lower gate trace 321 may be connected to the lower gate pad 340 disposed in the first metal layer L1, and the second lower gate trace 322 may be connected to the control electrode of the lower bridge power chip 302 through a microvia on the PCB board 100.

[0070] Optionally, the direction of the second upper-bridge gate trace 312 is parallel to the current direction of the PCB-integrated power module, and the direction of the first upper-bridge gate trace 311 is perpendicular to the direction of the second upper-bridge gate trace 312. The number of second upper-bridge gate traces 312 is the same as the number of rows of upper-bridge power chips 301. The two opposite ends of the second upper-bridge gate traces 312 can be connected to the control electrodes of two corresponding upper-bridge power chips 301 in a row through micro-holes on the PCB board 100.

[0071] Accordingly, the direction of the second lower bridge gate trace 322 is parallel to the current direction of the PCB integrated power module, and the direction of the first lower bridge gate trace 321 is perpendicular to the direction of the second lower bridge gate trace 322. The number of second lower bridge gate traces 322 is the same as the number of rows of lower bridge power chips 302. The two opposite ends of the second lower bridge gate traces 322 can be connected to the control electrodes of two lower bridge power chips 302 in a corresponding row through micro-holes on the PCB board 100.

[0072] from Figure 10 As can be seen from the above, this application can significantly reduce the width and area of ​​the gate trace by changing the gate trace of the upper bridge power chip 301 to a thin strip trace, thereby reducing the area opposite to the DC negative electrode connection region 132 of the adjacent layer, reducing the parallel capacitance effect and external interference.

[0073] For the lower-bridge power chip 302, since the DC negative terminal connection region 132 of the second metal layer L2 is connected to the second power terminal of the lower-bridge power chip 302, that is, the DC negative terminal connection region 132 of the second metal layer L2 and the second power terminal of the lower-bridge power chip 302 are at the same potential, and the control electrode of the lower-bridge power chip 302 is at a potential difference of one driving voltage from the potential of the second power terminal, it can also be considered that the control electrode of the lower-bridge power chip 302 and the second power terminal are at the same potential. Furthermore, the lower-bridge gate trace 320 of the lower-bridge power chip 302 located in the first metal layer L1 and the DC negative terminal connection region 132 located in the adjacent second metal layer L2 are also basically at the same potential. Therefore, the lower-bridge gate trace 320 of the lower-bridge power chip 302 basically does not have the planar capacitance effect of the adjacent layer.

[0074] For the upper bridge chip, the upper bridge gate trace 310 of the upper bridge power chip 301 located in the first metal layer L1 and the DC negative terminal connection region 132 located in the adjacent second metal layer L2 are at different potentials. Therefore, the upper bridge gate trace 310 of the upper bridge power chip 301 will be affected by the planar capacitance effect of the adjacent layer.

[0075] Considering Figure 10 The upper gate trace 310 in the first metal layer L1 includes both the first upper gate trace 311 and the second upper gate trace 312, and there is still a considerable area directly opposite to the DC negative terminal connection region 132 of the second metal layer L2. Therefore, this application provides another layout for the upper gate trace of the upper bridge power chip 301.

[0076] Figure 11 A schematic diagram illustrating the wiring of each metal layer of a PCB board 100 according to another embodiment of this application is shown. Figure 11 As shown, with Figure 10 The difference is that... Figure 10The second upper bridge gate trace 312 of the first metal layer L1 is disposed on the second metal layer L2, that is, in Figure 11 In this configuration, the upper gate trace 310 of the first metal layer L1 includes only the first upper gate trace 311, while the second metal layer L2 also includes a second upper gate trace 312. An insulating region 125 is provided between the second upper gate trace 312 and the DC negative terminal connection region 132 to ensure mutual insulation between them. The first upper gate trace 311 can be connected to the control electrode of the upper bridge power chip 301 via the second upper gate trace 312. Specifically, the first upper gate trace 311 of the first metal layer L1 can be connected to the second upper gate trace 312 of the second metal layer L2 via microvias on the PCB board 100, and the second upper gate trace 312 of the second metal layer L2 can then be connected to the control electrode of the upper bridge power chip 301 via microvias on the PCB board.

[0077] Figure 11 In the illustrated embodiment, by setting the second upper gate trace 312 in the upper gate trace 310 in the second metal layer L2, only the first upper gate trace 311 is opposite to the DC negative connection region 132 of the second metal layer L2. Therefore, the area directly opposite the upper gate trace 310 and the DC negative connection region 132 of the second metal layer L2 can be further reduced.

[0078] However, considering Figure 11 Placing the second upper-bridge gate trace 312 in the second metal layer L2 will occupy the area of ​​the second metal layer L2, which will inevitably have a certain impact on the current carrying capacity of the DC negative terminal connection area 132 of the second metal layer L2 and the stray inductance of the PCB integrated power module. Therefore, this application provides another layout method for the upper-bridge gate trace of the upper-bridge power chip 301.

[0079] Figure 12 This diagram illustrates the wiring of each metal layer of a PCB board 100 according to yet another embodiment of this application. Figure 12 As shown, with Figure 10 The difference is that... Figure 10 The second upper bridge gate trace 312 of the first metal layer L1 is disposed on the third metal layer L3, that is, in Figure 12In this configuration, the upper gate trace 310 of the first metal layer L1 includes only the first upper gate trace 311, while the third metal layer L3 also includes a second upper gate trace 312. Furthermore, an insulating region 125 is provided in the area of ​​the second metal layer L2 opposite to the second upper gate trace 312. The first upper gate trace 311 can be connected to the control electrode of the upper bridge power chip 301 via the second upper gate trace 312. The second metal layer L2 also includes a third upper gate connection portion 313, which is insulated from the DC negative terminal connection portion 132 via the insulating region 125. The first upper gate trace 311 and the second upper gate trace 312 are connected via the third upper gate connection portion 313.

[0080] Figure 13 This illustration shows a schematic diagram of an embodiment of the present application where the first upper-bridge gate trace 311 and the second upper-bridge gate trace 312 are connected to the third upper-bridge gate connection portion 313 via microvias on the PCB board 100. (See attached diagram.) Figure 13 As shown, in some embodiments, the first upper gate trace 311 and the third upper gate connection portion 313 are connected through a first micro-hole 151 on the PCB board 100, and the second upper gate trace 312 and the third upper gate connection portion 313 are connected through a second micro-hole 152 on the PCB board 100. The positions of the first micro-hole 151 and the second micro-hole 152 are spatially offset from each other, thereby improving the reliability of the interconnection.

[0081] Optionally, the third upper bridge gate connection portion 313 is directly opposite the middle region of the second upper bridge gate trace 312.

[0082] Figure 12 The embodiment shown places the second upper-bridge gate trace 312 of the upper-bridge power chip 301 in the third metal layer L3, and performs metal hollowing in the area corresponding to the second upper-bridge gate trace 312 in the second metal layer L2. This allows the second upper-bridge gate trace 312 arranged in the third metal layer L3 to have no or reduced direct facing area with the DC negative terminal connection area 132 of the adjacent second metal layer L2, thereby eliminating or reducing the planar capacitance effect between the second metal layer L2 and the third metal layer L3.

[0083] In addition, the area in the second metal layer L2 corresponding to the second upper bridge gate trace 312 is not completely hollowed out. Instead, a metal island is reserved in the middle area as the third upper bridge gate connection part 313. The first upper bridge gate trace 311 located in the first metal layer L1 and the second upper bridge gate trace 312 located in the third metal layer L3 are connected through the third upper bridge gate connection part 313 located in the second metal layer L2. This cleverly balances the anti-interference capability of the upper bridge gate trace 310 of the upper bridge power chip 301 and the current carrying capacity of the DC negative power trace of the second metal layer L2.

[0084] It is understood that the above description of the PCB-integrated power module of this application uses the example of the PCB board 100 having three layers above the power chip 300. However, the PCB board 100 of the PCB-integrated power module of this application is not limited to having three layers above the power chip 300; it may also include other numbers of layers, such as four layers. Wherever the gate traces of the power chip 300 are affected by the planar capacitance effect of adjacent metal layers, a similar solution described above can be adopted, and will not be elaborated further here.

[0085] Furthermore, it is understood that the above explanation uses the example of the planar capacitance effect of adjacent metal layers on the upper gate trace 310 of the upper bridge power chip 301 as an example. However, this application is not limited to this. In other embodiments, the first power chip described in this application can also be the lower bridge power chip 302, and correspondingly, the second power chip can be the upper bridge power chip 301. That is, if the lower gate trace 320 of the lower bridge power chip 302 is similarly affected by the planar capacitance effect of adjacent layers, it can also adopt a similar layout as the upper gate trace 310 of the upper bridge power chip 301, which will not be elaborated here. In summary, any layout of the gate trace of the power chip 300 based on the principles two and three mentioned above in this application will be covered within the protection scope of this patent application.

[0086] The PCB integrated power module of this application reduces the planar capacitance effect of adjacent layers and external interference by adjusting the layout of the gate traces of the power chip 300. It largely avoids the negative impact of the planar capacitance effect on the turn-on and turn-off of the PCB integrated power module, significantly reduces the turn-on and turn-off time delay, and effectively suppresses oscillation. Furthermore, it has little impact on the current carrying capacity and thermal performance of the DC negative electrode.

[0087] In addition, the PCB integrated power module of this application can maintain the same number of 100 layers on the PCB board and the original number of copper trace layers above the substrate 200, so that the production cost and cycle remain unchanged, the process complexity is not changed, and the product reliability and expected life are not affected.

[0088] The PCB integrated power module provided in the embodiments of this application has been described in detail above. Specific examples have been used to illustrate the PCB integrated power module of this application. The description of the above embodiments is only for helping to understand the core idea of ​​this application and is not intended to limit this application. It should be noted that those skilled in the art can make several improvements and modifications to this application without departing from the spirit and principles of this application, and all such improvements and modifications should fall within the protection scope of the appended claims.

Claims

1. A PCB integrated power module, characterized in that: The system includes a PCB board, a substrate embedded in the PCB board, and a power chip disposed on the substrate. The power chip includes a control electrode, a first power terminal, and a second power terminal. The power chip includes a first power chip and a second power chip. The PCB board includes an adjacent and mutually insulated first metal layer and a second metal layer. The gate trace of the first power chip is disposed on the first metal layer and is connected to the control electrode of the first power chip. The second metal layer has a metal connection region that is not at the same potential as the second power terminal of the first power chip. The area of ​​the gate traces of all the first power chips facing the metal connection region does not exceed 20% of the sum of the areas of all the first power chips.

2. The PCB integrated power module as described in claim 1, characterized in that: The first power chip is an upper-bridge power chip, the second power chip is a lower-bridge power chip, and the gate trace of the first power chip is the upper-bridge gate trace of the upper-bridge power chip.

3. The PCB integrated power module as described in claim 2, characterized in that: The metal connection region includes a DC negative connection region, which is connected to the second power terminal of the lower bridge power chip. The upper bridge gate trace is configured to reduce the area directly opposite the DC negative connection region.

4. The PCB integrated power module as described in claim 3, characterized in that: The upper bridge gate trace includes a first upper bridge gate trace and a second upper bridge gate trace connected to the first upper bridge gate trace. The second upper bridge gate trace is connected to the control electrode of the upper bridge power chip through a micro-hole on the PCB board.

5. The PCB integrated power module as described in claim 3, characterized in that: The upper bridge gate trace includes a first upper bridge gate trace, and the second metal layer also has a second upper bridge gate trace. An insulating region is provided between the second upper bridge gate trace and the DC negative electrode connection region to insulate the second upper bridge gate trace from the DC negative electrode connection region. The first upper bridge gate trace is connected to the control electrode of the upper bridge power chip through the second upper bridge gate trace.

6. The PCB integrated power module as described in claim 3, characterized in that: The PCB board further includes a third metal layer, which is adjacent to and insulated from the second metal layer. The third metal layer is located close to the power chip and has a DC positive connection area and an AC connection area. The DC positive connection area is connected to the first power terminal of the upper bridge power chip, and the AC connection area is connected to the second power terminal of the upper bridge power chip and the first power terminal of the lower bridge power chip.

7. The PCB integrated power module as described in claim 6, characterized in that: The upper bridge gate trace includes a first upper bridge gate trace, and the third metal layer also has a second upper bridge gate trace. An insulating region is provided in the area of ​​the second metal layer opposite to the second upper bridge gate trace. The first upper bridge gate trace is connected to the control electrode of the upper bridge power chip through the second upper bridge gate trace.

8. The PCB integrated power module as described in claim 7, characterized in that: The second metal layer is further provided with a third upper bridge gate connection portion, which is insulated from the DC negative terminal connection portion through the insulating region. The first upper bridge gate trace and the second upper bridge gate trace are connected through the third upper bridge gate connection portion.

9. The PCB integrated power module as described in claim 8, characterized in that: The first upper gate trace and the third upper gate connection portion are connected through a first micro-hole on the PCB board, and the second upper gate trace and the third upper gate connection portion are connected through a second micro-hole on the PCB board, wherein the positions of the first micro-hole and the second micro-hole are spatially offset from each other.

10. The PCB integrated power module as described in claim 9, characterized in that: The third upper bridge gate connection is directly opposite the middle area of ​​the second upper bridge gate trace.

11. The PCB integrated power module as described in any one of claims 4-5 and 7-10, characterized in that: The direction of the second upper bridge gate trace is parallel to the current direction of the PCB integrated power module, and the direction of the first upper bridge gate trace is perpendicular to the direction of the second upper bridge gate trace.

12. The PCB integrated power module as described in claim 11, characterized in that: The power chip includes multiple parallel upper-bridge power chips, which are arranged in at least one row. Each row includes two upper-bridge power chips arranged along a first direction, wherein the first direction is parallel to the current direction of the PCB-integrated power module. The opposite ends of the second upper-bridge gate trace are connected to the control electrodes of the two upper-bridge power chips in the corresponding row through micro-holes on the PCB. In the case where at least one row is multiple rows, the multiple rows are spaced apart along a second direction, which is perpendicular to the first direction, and the number of the second upper bridge gate traces is the same as the number of rows of the upper bridge power chip.

13. The PCB integrated power module as described in claim 1, characterized in that: The power chip includes a MOSFET chip, wherein the control electrode, the first power terminal, and the second power terminal of the power chip are respectively the gate, drain, and source of the MOSFET chip; or, The power chip includes a combination of an IGBT chip and an FRD chip. The control electrode, the first power terminal, and the second power terminal of the power chip are the gate, collector, and emitter of the IGBT chip, respectively, and the first power terminal and the second power terminal are also the cathode and anode of the FRD chip.

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