Multi-channel fan aging automatic control circuit

Abstract

The utility model provides a multichannel fan aging automatic control circuit, which relates to the aging test field and comprises a single chip microcomputer, a multichannel driving control circuit, an interface circuit, an address selection circuit, a signal acquisition circuit, an acquisition channel switching circuit, an ADC acquisition circuit and a communication circuit. According to the fan aging test system, the output voltage is set remotely and uniformly in cooperation with software of the upper computer, aging test of multiple fans is achieved, aging data among the fans are mutually independent, the data are stored in a data report generated by the upper computer in real time, the convenience of the fan aging test is greatly improved, the accuracy of the test data is improved, and the test cost is reduced.

Description

Technical Field

[0001] The utility model relates to the technical field of aging test, in particular to a multi-channel fan aging automatic control circuit. Background Art

[0002] Fan aging detection is a test method to evaluate the stability of fan performance. This test mainly simulates the long-term operation of the fan in actual use to detect the reliability and possible problems of the fan. During the test, it is necessary to monitor the operation of the fan, including parameters such as the temperature of the motor and the speed of the fan blades, and use sensors for real-time data collection. After the test, the test data needs to be analyzed and evaluated to evaluate the reliability and performance of the fan.

[0003] At present, the aging and quality inspection of fans in the market mainly relies on manual methods using DC power supplies. Although this method can evaluate the quality of fans, it still has many shortcomings. First, manually setting the voltage of each power supply makes the operation process cumbersome, especially when dealing with multiple products, multiple DC power supplies need to be configured, resulting in increased costs; second, it is easy to make mistakes when setting the voltage manually, which may cause damage to the fan; in addition, this method is not responsive enough when dealing with product failures, and it is impossible to quickly and accurately diagnose and take protective measures; finally, this method cannot effectively collect and save the aging data of each product, which constitutes an obstacle to subsequent product problem analysis and traceability. Utility Model Content

[0004] In order to overcome the deficiencies in the prior art, the utility model provides a multi-channel fan aging automatic control circuit, which greatly improves the convenience of fan aging testing, while improving the accuracy of test data and reducing testing costs.

[0005] The technical solution adopted by the utility model to solve its technical problems is: a multi-channel fan aging automatic control circuit, the improvement of which is that it includes: a single-chip microcomputer, a multi-channel drive control circuit, an interface circuit, an address selection circuit, a signal acquisition circuit, an acquisition channel switching circuit, an ADC acquisition circuit and a communication circuit, wherein the input end of the multi-channel drive control circuit is connected to the single-chip microcomputer to control the opening and closing of the drive fan, the output end of the multi-channel drive control circuit is connected to the input end of the interface circuit; the output end of the interface circuit is connected to the input end of the signal acquisition circuit; the signal acquisition The output end of the collector circuit is connected to the input end of the acquisition channel switching circuit, and is used to collect the voltage and current of the driving fan during operation; the input end of the acquisition channel switching circuit is also connected to the single-chip microcomputer, and the output end of the acquisition channel switching circuit is connected to the input end of the ADC acquisition circuit, and is used to switch the signal acquisition channel; the ADC acquisition circuit is connected to the single-chip microcomputer, and is used for the single-chip microcomputer to read the converted fan aging data; the address selection circuit is connected to the single-chip microcomputer, and is used for the single-chip microcomputer to identify the current address; the communication circuit is connected to the single-chip microcomputer, and is used for the single-chip microcomputer to communicate with the host computer.

[0006] In the above circuit, the multi-channel drive control circuit includes resistor R36, resistor R37, resistor R38, resistor R39, resistor R40, resistor R41, resistor R42, resistor R43, resistor R44, resistor R45, resistor R46, resistor R47, field effect transistor Q1, field effect transistor Q2, field effect transistor Q3, field effect transistor Q4, transistor Q7, transistor Q8, transistor Q9 and transistor Q10, wherein the resistor One end of the resistor R44, the resistor R45, the resistor R46 and the resistor R47 are respectively connected to the control signal output by the single chip microcomputer, and the other ends of the resistor R44, the resistor R45, the resistor R46 and the resistor R47 are respectively connected to the base of the transistor Q7, the transistor Q8, the transistor Q9 and the transistor Q10, and the emitter of the transistor Q7, the transistor Q8, the transistor Q9 and the transistor Q10 is connected to a low level, and the collector of the transistor Q7 is connected to a low level. The electrode is connected to one end of the resistors R39 and R40, the other end of the resistor R39 is connected to the gate of the field effect transistor Q1, the other end of the resistor R40 is connected to the source of the field effect transistor Q1, the collector of the transistor Q10 is connected to one end of the resistors R36 and R41, the other end of the resistor R36 is connected to the gate of the field effect transistor Q2, the other end of the resistor R41 is connected to the source of the field effect transistor Q2, the collector of the transistor Q9 is connected to one end of the resistors R37 and R42, the other end of the resistor R37 is connected to the gate of the field effect transistor Q3, the other end of the resistor R42 is connected to the source of the field effect transistor Q3, the transistor Q8 is connected to one end of the resistors R38 and R43, the other end of the resistor R38 is connected to the gate of the field effect transistor Q4, and the other end of the resistor R43 is connected to the source of the field effect transistor Q4.

[0007] In the above circuit, the multi-channel drive control circuit also includes a PWM drive circuit, and the PWM drive circuit includes a resistor R48, a resistor R49, a resistor R50, a resistor R51, a resistor R52, a resistor R53, a field effect transistor Q5, a field effect transistor Q6, a transistor Q11 and a transistor Q12, wherein one end of the resistor R52 and the resistor R53 is connected to the PWM waveform output by the single-chip microcomputer, the other end of the resistor R52 is connected to the base of the transistor Q11, and the collector of the transistor Q11 is connected to the collector of the transistor Q11. The electrode is connected to one end of the resistor R48 and the resistor R50, the emitter of the transistor Q11 is connected to a low level, the other end of the resistor R48 and the resistor R50 is connected to the gate of the field effect transistor Q5, the other end of the resistor R53 is connected to the base of the transistor Q12, the collector of the transistor Q12 is connected to one end of the resistor R49 and the resistor R51, the emitter of the transistor Q12 is connected to a low level, and the other end of the resistor R49 and the resistor R51 is connected to the gate of the field effect transistor Q6.

[0008] In the above circuit, the interface circuit includes four parallel thermistors PT1, PT2, PT3 and PT4, one end of the thermistors PT1, PT2, PT3 and PT4 is connected to a DC power supply, and the other end of the thermistors PT1, PT2, PT3 and PT4 is connected to the multi-channel drive control circuit.

[0009] In the above circuit, the address selection circuit includes a 6-bit dip switch S1 and resistors R1, R3, R6, R7, R8 and R10, wherein one end of the resistors R1, R3, R6, R7, R8 and R10 is connected to a high level, and the other ends of the resistors R1, R3, R6, R7, R8 and R10 are connected to the 6-bit dip switch S1. By changing the state of the 6-bit dip switch S1, the signals of the six wires connected to the resistors are changed, and the six signal lines are connected to the single-chip microcomputer to provide address information for the circuit.

[0010] In the above circuit, the signal acquisition circuit includes a voltage acquisition circuit and a current acquisition circuit, wherein the voltage acquisition circuit includes four groups of parallel voltage divider circuits, each group of voltage divider circuits includes two resistors and capacitors; the current acquisition circuit includes four groups of parallel current acquisition units, each group of current acquisition units includes three capacitors and two resistors.

[0011] In the above circuit, the acquisition channel switching circuit includes a voltage acquisition channel switching circuit and a current acquisition channel switching circuit.

[0012] In the above circuit, the ADC acquisition circuit includes a resistor R14, a resistor R18, a capacitor C13, a capacitor C17, a capacitor C20 and an AD conversion chip U2, wherein one end of the resistor R14 and the resistor R18 are connected to the single-chip microcomputer, the other end of the resistor R14 is connected to the capacitor C13, one end of the capacitor C17 and the AD conversion chip U2, and the other end of the capacitor C13 is connected to a low level; the other end of the resistor R18 is connected to the other end of the capacitor C17, one end of the capacitor C20 and the AD conversion chip U2, and the other end of the capacitor C20 is connected to a low level.

[0013] In the above circuit, the communication circuit includes two optocoupler chips U6 and U8 and a communication chip U7. The optocoupler chips U6 and U8 are used to increase the anti-interference ability of the circuit. The communication chip U7 is used to convert the TTL serial port signal of the microcontroller into a 485 communication signal to communicate with the host computer.

[0014] In the above circuit, the communication circuit also includes resistor R54, resistor R55, resistor R56, resistor R57, resistor R58, resistor R59, resistor R60, resistor R61, transistor Q13, transistor Q14 and capacitor C27, wherein the third pin of the optocoupler chip U8 is connected to the collector of the transistor Q14, the base of the transistor Q14 is connected to the microcontroller through the resistor R61, the seventh and eighth pins of the optocoupler chip U8 are connected to the second and third pins of the communication chip U7 and the collector of the transistor Q13 through the resistor R56, the base of the transistor Q13 is connected to the sixth pin of the optocoupler chip U8, and the emitter of the transistor Q13 is connected to a low level.

[0015] The beneficial effects of the utility model are: through the above-mentioned multi-channel fan aging automatic control circuit, in conjunction with the host computer software, the output voltage is remotely and uniformly set, so that one fan and multiple fans can be tested for aging. At the same time, the aging data between the fans are independent of each other, and the data is saved in real time through the host computer to generate data reports, which greatly improves the convenience of the fan aging test, while improving the accuracy of the test data and reducing the test cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a block diagram of a multi-channel fan aging automatic control circuit;

[0017] Figure 2 It is a circuit diagram of a multi-channel drive control circuit in a multi-channel fan aging automatic control circuit;

[0018] Figure 3 It is a circuit diagram of a PWM drive circuit in a multi-channel fan aging automatic control circuit;

[0019] Figure 4 The present invention is a circuit diagram of an interface circuit in a multi-channel fan aging automatic control circuit;

[0020] Figure 5 The present invention is a circuit diagram of an address selection circuit in a multi-channel fan aging automatic control circuit;

[0021] Figure 6 It is a circuit diagram of a signal acquisition circuit in a multi-channel fan aging automatic control circuit;

[0022] Figure 7 It is a circuit diagram of a collection channel switching circuit in a multi-channel fan aging automatic control circuit;

[0023] Figure 8 It is a circuit diagram of an ADC acquisition circuit in a multi-channel fan aging automatic control circuit;

[0024] Fig. 9 The present invention is a circuit diagram of a communication circuit in a multi-channel fan aging automatic control circuit. DETAILED DESCRIPTION

[0025] The utility model is further described below in conjunction with the accompanying drawings and embodiments.

[0026] The following will clearly and completely describe the concept, specific structure and technical effects of the utility model in combination with the embodiments and drawings, so as to fully understand the purpose, characteristics and effects of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, not all of them. Based on the embodiments of the utility model, other embodiments obtained by technicians in this field without creative work are all within the scope of protection of the utility model. In addition, all the connection / connection relationships involved in the patent do not refer to the direct connection of components, but refer to the formation of a better connection structure by adding or reducing connection accessories according to the specific implementation situation. The various technical features in the creation of the utility model can be combined interchangeably without conflicting with each other.

[0027] The utility model provides a multi-channel fan aging automatic control circuit, such as Figure 1 As shown, it includes a single chip microcomputer 10, a multi-channel drive control circuit 20, an interface circuit 30, an address selection circuit 40, a signal acquisition circuit 50, an acquisition channel switching circuit 60, an ADC acquisition circuit 70 and a communication circuit 80, wherein:

[0028] The input end of the multi-channel drive control circuit 20 is connected to the P0.0-P0.3 pins and the P2.5 and P2.6 pins of the single-chip microcomputer 10 to control the opening and closing of the drive fan. The output end of the multi-channel drive control circuit 20 is connected to the input end of the interface circuit 30; the output end of the interface circuit 30 is connected to the input end of the signal acquisition circuit 50; the output end of the signal acquisition circuit 50 is connected to the input end of the acquisition channel switching circuit 60 to acquire the voltage and current during the operation of the drive fan; the input end of the acquisition channel switching circuit 60 is also connected to the P2.1-P2.3 and P3.4-P 3.7 connection, the output end of the acquisition channel switching circuit 60 is connected to the input end of the ADC acquisition circuit 70, which is used to switch the signal acquisition channel; the ADC acquisition circuit 70 is connected to the P3.2-P3.3 and P5.5, P1.6-P1.7 pins of the single-chip microcomputer 10, which is used for the single-chip microcomputer 10 to read the converted fan aging data; the address selection circuit 40 is connected to the P1.0-P1.5 pins of the single-chip microcomputer 10, which is used for the single-chip microcomputer 10 to identify the current address; the communication circuit 80 is connected to the P3.0, P3.1 and P5.4 pins of the single-chip microcomputer 10, which is used for the single-chip microcomputer 10 to communicate with the host computer.

[0029] Through the above-mentioned multi-channel fan aging automatic control circuit, the output voltage can be set uniformly remotely in cooperation with the host computer software to realize aging test of multiple fans. At the same time, the aging data of the fans are independent of each other, and the data is saved in real time through the host computer to generate data reports, which greatly improves the convenience of fan aging test, while improving the accuracy of test data and reducing test costs.

[0030] In an exemplary embodiment, if Figure 2 As shown, the multi-channel drive control circuit 20 includes resistor R36, resistor R37, resistor R38, resistor R39, resistor R40, resistor R41, resistor R42, resistor R43, resistor R44, resistor R45, resistor R46, resistor R47, field effect transistor Q1, field effect transistor Q2, field effect transistor Q3, field effect transistor Q4, transistor Q7, transistor Q8, transistor Q9 and transistor Q10.

[0031] Among them, one end of the resistor R44, the resistor R45, the resistor R46 and the resistor R47 are respectively connected to the control signal output by the single-chip microcomputer, and the other ends of the resistor R44, the resistor R45, the resistor R46 and the resistor R47 are respectively connected to the base of the transistor Q7, the transistor Q8, the transistor Q9 and the transistor Q10, and the emitters of the transistors Q7, Q8, Q9 and Q10 are connected to a low level. The collector of the transistor Q7 is connected to one end of the resistors R39 and R40, and the other end of the resistor R39 is connected to the gate of the field effect transistor Q1. The other end of the resistor R40 is connected to the source of the field effect transistor Q1. The collector of the tube Q10 is connected to one end of the resistors R36 and R41, the other end of the resistor R36 is connected to the gate of the field effect tube Q2, the other end of the resistor R41 is connected to the source of the field effect tube Q2, the collector of the transistor Q9 is connected to one end of the resistors R37 and R42, the other end of the resistor R37 is connected to the gate of the field effect tube Q3, the other end of the resistor R42 is connected to the source of the field effect tube Q3, the transistor Q8 is connected to one end of the resistors R38 and R43, the other end of the resistor R38 is connected to the gate of the field effect tube Q4, and the other end of the resistor R43 is connected to the source of the field effect tube Q4.

[0032] In a possible implementation, in order to control the speed of the fan, Figure 3 As shown, the multi-channel drive control circuit 20 also includes a PWM drive circuit 210, and the PWM drive circuit 210 includes resistors R48, R49, R50, R51, R52, R53, field effect transistors Q5, Q6, transistors Q11 and Q12.

[0033] Among them, one end of the resistor R52 and the resistor R53 is connected to the PWM waveform output by the single-chip microcomputer, the other end of the resistor R52 is connected to the base of the transistor Q11, the collector of the transistor Q11 is connected to one end of the resistor R48 and the resistor R50, the emitter of the transistor Q11 is connected to a low level, the other end of the resistor R48 and the resistor R50 is connected to the gate of the field effect transistor Q5, the other end of the resistor R53 is connected to the base of the transistor Q12, the collector of the transistor Q12 is connected to one end of the resistor R49 and the resistor R51, the emitter of the transistor Q12 is connected to a low level, and the other end of the resistor R49 and the resistor R51 is connected to the gate of the field effect transistor Q6.

[0034] The PWM waveform output by the microcontroller controls the transistors Q11 and Q12 through resistors R52 and R53. The transistors Q11 and Q12 amplify the PWM signal current and then pass through resistors R48 and R49 to connect to the gates of the field effect transistors Q5 and Q6. With the addition of MOS drive, the PWM signal is more stable and has a certain load capacity.

[0035] In an exemplary embodiment, if Figure 4 As shown, the interface circuit 30 includes four parallel thermistors PT1, PT2, PT3 and PT4, one end of the thermistors PT1, PT2, PT3 and PT4 is connected to a DC power supply, and the other end of the thermistors PT1, PT2, PT3 and PT4 is connected to the multi-channel drive control circuit 20.

[0036] The current protection PTC circuit PT1-PT4 is connected to the main field effect transistor drive circuit of Q1-Q4 of the multi-channel fan control drive circuit 20, and is output from the second pin of the J4-J7 interface. The first pin of J4-J7 is connected to the current sampling resistors R27, R33, R34, and R35. The sampling resistors can convert the current in each channel into a voltage signal, which is supplied to the signal acquisition circuit 50 for acquisition. D1-D4 are output indications, etc. The circuit is connected in parallel to the output interface through the current limiting resistors R26, R28, R31, and R32 to indicate the output status.

[0037] In an exemplary embodiment, if Figure 5 As shown, the address selection circuit 40 includes a 6-bit DIP switch S1 and resistors R1, R3, R6, R7, R8 and R10.

[0038] Among them, one end of the resistor R1, the resistor R3, the resistor R6, the resistor R7, the resistor R8 and the resistor R10 is connected to a high level, and the other ends of the resistor R1, the resistor R3, the resistor R6, the resistor R7, the resistor R8 and the resistor R10 are connected to the 6-bit dip switch S1. By changing the state of the 6-bit dip switch S1, the signals of the six wires connected to the resistors are changed, and the six signal lines are connected to the single-chip microcomputer to provide address information for the circuit.

[0039] In an exemplary embodiment, if Figure 6 As shown, the signal acquisition circuit 60 includes a voltage acquisition circuit and a current acquisition circuit.

[0040] The voltage acquisition circuit includes four groups of parallel voltage divider circuits consisting of resistors R19-R20, resistors R22-R23, resistors R24-R25, and resistors R29-R30. Each group of voltage divider circuits includes two resistors and one capacitor, which are used to collect the voltage at the output interface of each channel. For example, the voltage at the connection between the resistor R19 and the resistor R20 is the voltage after voltage division, that is, the voltage reduced in proportion is connected to the acquisition channel switching circuit 60;

[0041] The current acquisition circuit includes four groups of current acquisition units connected in parallel, each group of current acquisition units includes three capacitors and two resistors. The current acquisition circuit acquires the signal output from the sampling resistor through resistors R2-R17. The signal is filtered by capacitors C3-C19 and then sent to the acquisition channel switching circuit 60 for the single-chip microcomputer 10 to select the switching channel.

[0042] In an exemplary embodiment, if Figure 7 As shown, the acquisition channel switching circuit includes a voltage acquisition channel switching circuit and a current acquisition channel switching circuit, wherein:

[0043] U4 is a voltage acquisition channel switching circuit, whose 9th to 11th pins are connected to the single-chip microcomputer 10. The single-chip microcomputer 10 controls U4 to switch and select the channel leading to the ADC acquisition circuit 70 by controlling these pins. The 3rd pin of U4 is connected to the ADC acquisition circuit 70, and the selected channel signal is output from this pin. The 16th pin of U4 is connected to the positive pole of the power supply to power the chip IC. The 7th and 8th pins of U4 are connected to the negative pole of the power supply to provide negative power to the IC. The 6th pin of U4 is connected to the single-chip microcomputer 10 to control the U4 chip to enable the selection. The other pins of U4 are connected to the voltage acquisition circuit to receive the voltage acquisition signal.

[0044] U1 is a current acquisition channel switching circuit, whose pins 9-11 are connected to the microcontroller 10 to switch the acquisition channel, its pin 6 is the selection pin and the microcontroller 10 controls the IC selection, the 16th pin is connected to the positive pole of the power supply, the 8th and 7th pins are connected to the negative pole of the power supply to power the IC, the 3rd and 13th pins are connected to the ADC acquisition circuit 70 to collect the selected current data, and the other pins of U1 are connected to the current acquisition circuit to receive the current signal.

[0045] In an exemplary embodiment, if Figure 8 As shown, the ADC acquisition circuit includes a resistor R14, a resistor R18, a capacitor C13, a capacitor C17, a capacitor C20 and an AD conversion chip U2.

[0046] Among them, one end of the resistor R14 and the resistor R18 are connected to the single-chip microcomputer, the other end of the resistor R14 is connected to the capacitor C13, one end of the capacitor C17 and the AD conversion chip U2, and the other end of the capacitor C13 is connected to a low level; the other end of the resistor R18 is connected to the other end of the capacitor C17, one end of the capacitor C20 and the AD conversion chip U2, and the other end of the capacitor C20 is connected to a low level.

[0047] Resistor R14 and resistor R18 are connected to the acquisition channel switching circuit 60 to receive the selected current data, and then connected to capacitor C13, capacitor C17 and capacitor C20 for capacitor filtering. After filtering, they are connected to pins 7 and 8 of the AD conversion chip U2 for AD conversion.

[0048] Resistor R21 is connected to the acquisition channel switching circuit 60, receives the selected voltage data, and then filters it through capacitor C22, and connects to the 6th pin of the AD conversion chip U2 to perform AD conversion. The 1st pin, the 5th pin, and the 12th to 14th pins of the AD conversion chip U2 are connected to the microcontroller 10, and the microcontroller 10 reads the converted voltage and current data through these pins.

[0049] In an exemplary embodiment, if Fig. 9 As shown, the communication circuit 80 includes two optocoupler chips U6 and U8 and a communication chip U7. The optocoupler chips U6 and U8 are used to increase the anti-interference ability of the circuit. The communication chip U7 is used to convert the TTL serial port signal of the microcontroller into a 485 communication signal to communicate with the host computer.

[0050] In a possible implementation, the communication circuit further includes a resistor R54, a resistor R55, a resistor R56, a resistor R57, a resistor R58, a resistor R59, a resistor R60, a resistor R61, a transistor Q13, a transistor Q14 and a capacitor C27.

[0051] Among them, the third pin of the optocoupler chip U8 is connected to the collector of the transistor Q14, the base of the transistor Q14 is connected to the single-chip microcomputer through the resistor R61, the seventh and eighth pins of the optocoupler chip U8 are connected to the second and third pins of the communication chip U7 and the collector of the transistor Q13 through the resistor R56, the base of the transistor Q13 is connected to the sixth pin of the optocoupler chip U8, and the emitter of the transistor Q13 is connected to a low level.

[0052] Through the above embodiments, the present application collects the voltage and current of the fan during operation through the signal acquisition circuit, so that the single-chip microcomputer knows the current working status of the fan, and the internal program analyzes and calculates and makes corresponding fan control. At the same time, the single-chip microcomputer controls whether the voltage is output on the fan interface by controlling the fan drive control loop. Since 4 channels are integrated on a PCB board, there are 4 groups of control drive circuits and fan output interface circuits, that is, each aging device has 4 channels. More test channels can be expanded through the module address selection circuit, and the data of the aging device communicates with the host computer through the communication circuit. It is worth mentioning that in the embodiment of the present application, only a 4-channel fan drive control loop is used for explanation, but it is not limited to this. Among them, the number of channels of the fan drive control loop can be increased automatically as needed.

[0053] Through the above embodiments, the present application provides a multi-channel fan aging automatic control circuit, which cooperates with the host computer software to remotely and uniformly set the output voltage, so as to realize aging test of multiple fans. At the same time, the aging data between fans are independent of each other, and the data is saved in real time through the host computer to generate data reports, which greatly improves the convenience of fan aging test, while improving the accuracy of test data and reducing testing costs.

[0054] The above is a specific description of the preferred implementation of the utility model, but the invention of the utility model is not limited to the described embodiments. Technical personnel familiar with the field can also make various equivalent deformations or substitutions without violating the spirit of the utility model. These equivalent deformations or substitutions are all included in the scope defined by the claims of this application.

Claims

1. A multi-channel fan aging automatic control circuit, characterized in that: include: Single chip microcomputer, multi-channel drive control circuit, interface circuit, address selection circuit, signal acquisition circuit, acquisition channel switching circuit, ADC acquisition circuit and communication circuit, wherein: The input end of the multi-channel drive control circuit is connected to the single chip microcomputer to control the opening and closing of the drive fan, and the output end of the multi-channel drive control circuit is connected to the input end of the interface circuit; The output end of the interface circuit is connected to the input end of the signal acquisition circuit; The output end of the signal acquisition circuit is connected to the input end of the acquisition channel switching circuit, and is used to acquire the voltage and current of the driving fan during operation; The input end of the acquisition channel switching circuit is also connected to the single chip microcomputer, and the output end of the acquisition channel switching circuit is connected to the input end of the ADC acquisition circuit, for switching the signal acquisition channel; The ADC acquisition circuit is connected to the single chip microcomputer, and is used for the single chip microcomputer to read the converted fan aging data; The address selection circuit is connected to the single chip microcomputer and is used for the single chip microcomputer to identify the current address; The communication circuit is connected to the single chip microcomputer and is used for the single chip microcomputer to communicate with a host computer.

2. The multi-channel fan aging automatic control circuit according to claim 1, characterized in that: The multi-channel drive control circuit includes a resistor R36, a resistor R37, a resistor R38, a resistor R39, a resistor R40, a resistor R41, a resistor R42, a resistor R43, a resistor R44, a resistor R45, a resistor R46, a resistor R47, a field effect transistor Q1, a field effect transistor Q2, a field effect transistor Q3, a field effect transistor Q4, a triode Q7, a triode Q8, a triode Q9 and a triode Q10, wherein: One ends of the resistors R44, R45, R46 and R47 are respectively connected to the control signals output by the single chip microcomputer, the other ends of the resistors R44, R45, R46 and R47 are respectively connected to the bases of the transistors Q7, Q8, Q9 and Q10, the emitters of the transistors Q7, Q8, Q9 and Q10 are connected to a low level, the collector of the transistor Q7 is connected to one ends of the resistors R39 and R40, the other end of the resistor R39 is connected to the gate of the field effect transistor Q1, the other end of the resistor R40 is connected to the source of the field effect transistor Q1, and the transistors The collector of Q10 is connected to one end of the resistors R36 and R41, the other end of the resistor R36 is connected to the gate of the field effect transistor Q2, the other end of the resistor R41 is connected to the source of the field effect transistor Q2, the collector of the transistor Q9 is connected to one end of the resistors R37 and R42, the other end of the resistor R37 is connected to the gate of the field effect transistor Q3, the other end of the resistor R42 is connected to the source of the field effect transistor Q3, the transistor Q8 is connected to one end of the resistors R38 and R43, the other end of the resistor R38 is connected to the gate of the field effect transistor Q4, and the other end of the resistor R43 is connected to the source of the field effect transistor Q4.

3. The multi-channel fan aging automatic control circuit according to claim 2, characterized in that: The multi-channel drive control circuit further includes a PWM drive circuit, which includes a resistor R48, a resistor R49, a resistor R50, a resistor R51, a resistor R52, a resistor R53, a field effect transistor Q5, a field effect transistor Q6, a transistor Q11 and a transistor Q12, wherein: One end of the resistor R52 and the resistor R53 are connected to the PWM waveform output by the single-chip microcomputer, the other end of the resistor R52 is connected to the base of the transistor Q11, the collector of the transistor Q11 is connected to one end of the resistor R48 and the resistor R50, the emitter of the transistor Q11 is connected to a low level, the other end of the resistor R48 and the resistor R50 is connected to the gate of the field effect transistor Q5, the other end of the resistor R53 is connected to the base of the transistor Q12, the collector of the transistor Q12 is connected to one end of the resistor R49 and the resistor R51, the emitter of the transistor Q12 is connected to a low level, and the other end of the resistor R49 and the resistor R51 is connected to the gate of the field effect transistor Q6.

4. The multi-channel fan aging automatic control circuit according to claim 1, characterized in that: The interface circuit includes four parallel thermistors PT1, PT2, PT3 and PT4, one end of the thermistors PT1, PT2, PT3 and PT4 is connected to a DC power supply, and the other end of the thermistors PT1, PT2, PT3 and PT4 is connected to the multi-channel drive control circuit.

5. The multi-channel fan aging automatic control circuit according to claim 1, characterized in that: The address selection circuit includes a 6-bit DIP switch S1 and resistors R1, R3, R6, R7, R8 and R10, wherein: One end of the resistor R1, the resistor R3, the resistor R6, the resistor R7, the resistor R8 and the resistor R10 is connected to a high level, and the other ends of the resistor R1, the resistor R3, the resistor R6, the resistor R7, the resistor R8 and the resistor R10 are connected to the 6-bit dip switch S1. By changing the state of the 6-bit dip switch S1, the signals of the six wires connected to the resistors are changed, and the six signal lines are connected to the single-chip microcomputer to provide address information for the circuit.

6. The multi-channel fan aging automatic control circuit according to claim 1, characterized in that: The signal acquisition circuit includes a voltage acquisition circuit and a current acquisition circuit, wherein: The voltage acquisition circuit includes four groups of voltage divider circuits connected in parallel, and each group of voltage divider circuits includes two resistors and one capacitor; The current collection circuit includes four groups of current collection units connected in parallel, and each group of current collection units includes three capacitors and two resistors.

7. The multi-channel fan aging automatic control circuit according to claim 1, characterized in that: The acquisition channel switching circuit includes a voltage acquisition channel switching circuit and a current acquisition channel switching circuit.

8. The multi-channel fan aging automatic control circuit according to claim 1, characterized in that: The ADC acquisition circuit includes a resistor R14, a resistor R18, a capacitor C13, a capacitor C17, a capacitor C20 and an AD conversion chip U2, wherein: One end of the resistor R14 and the resistor R18 are connected to the single chip microcomputer, the other end of the resistor R14 is connected to one end of the capacitor C13, the capacitor C17 and the AD conversion chip U2, and the other end of the capacitor C13 is connected to a low level; The other end of the resistor R18 is connected to the other end of the capacitor C17, one end of the capacitor C20 and the AD conversion chip U2, and the other end of the capacitor C20 is connected to a low level.

9. The multi-channel fan aging automatic control circuit according to claim 1, characterized in that: The communication circuit includes two optocoupler chips U6 and U8 and a communication chip U7. The optocoupler chips U6 and U8 are used to increase the anti-interference ability of the circuit. The communication chip U7 is used to convert the TTL serial port signal of the single-chip microcomputer into a 485 communication signal to communicate with the host computer.

10. The multi-channel fan aging automatic control circuit according to claim 9, characterized in that: The communication circuit further includes a resistor R54, a resistor R55, a resistor R56, a resistor R57, a resistor R58, a resistor R59, a resistor R60, a resistor R61, a transistor Q13, a transistor Q14 and a capacitor C27, wherein: The third pin of the optocoupler chip U8 is connected to the collector of the transistor Q14, the base of the transistor Q14 is connected to the microcontroller through a resistor R61, the seventh and eighth pins of the optocoupler chip U8 are connected to the second and third pins of the communication chip U7 and the collector of the transistor Q13 through a resistor R56, the base of the transistor Q13 is connected to the sixth pin of the optocoupler chip U8, and the emitter of the transistor Q13 is connected to a low level.

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