Chip testing device based on ATE

Abstract

The utility model discloses a chip testing device based on ATE. The chip testing device comprises a first testing module, an RF switch, a differential clock circuit module and a second testing module. The differential clock circuit module is used for generating a first differential clock signal when the second test module performs Serdes Trim test on the to-be-tested chip; the second test module is used for performing Serdes Trim test on the to-be-tested chip according to the first differential clock signal; the first test module and the second test module are used for performing a first type of test on the to-be-tested chip. According to the device provided by the utility model, the differential clock circuit module is arranged in the device, and the differential clock circuit module is used for generating the differential clock signal, so that the chip can be tested by adopting middle-end and low-end ATE test machines, and all test items of the chip can be completed on the same plate; the chip testing process is simplified, and the testing cost is reduced.

Description

Technical Field

[0001] The utility model belongs to the technical field of chip testing, and in particular relates to a chip testing device based on ATE. Background Art

[0002] With the rapid development of communication technology and the increase in data transmission rate, the traditional parallel data transmission method has some limitations and needs to transmit multiple data bits at the same time. For large-scale data transmission, multiple transmission lines are required, which will lead to complex wiring, high power consumption and other problems. In order to solve these problems, Serdes technology came into being. Serdes can provide higher bandwidth than parallel transmission technology and is widely used in the field of embedded high-speed transmission.

[0003] Because the test of the Serdes physical layer requires the bandwidth of the equipment to be greater than the signal rate, the test index is high and the test port access will affect the signal. Therefore, most manufacturers use instruments and test boards to test Serdes, which is inefficient and only suitable for the product exploration stage to do certain tests on the characteristics and performance of Serdes. The test method based on automatic test equipment (ATE) can realize comprehensive testing of the IO modules, functions, transmission and reception parameters of Serdes products, and can realize mass production testing of high-speed interfaces. However, in the mass production process of the test device, it is necessary not only to ensure the quality of the chip, but also to control the test cost of the chip. In the process of realizing large-scale mass production of domestic high-speed Serdes FPGA chips, the problem of high testing costs is faced.

[0004] Since general mid- and low-end ATE testers cannot meet all the testing requirements of chips, it is necessary to use higher-end, more expensive, and more comprehensive ATE testers, which increases the testing cost.

[0005] The FPGA chip with embedded SerDes is divided into two parts for testing. The FPGA part can be tested using the current low-end and mid-range ATE testers that can meet the pattern depth, but the low-end and mid-range ATE testers cannot meet the testing requirements of the SerDes part.

[0006] A traditional test device tests the chip through a sub-board test solution. It uses two test boards to meet the test requirements in mass production testing. For example, test board 1 implements functional tests such as IO DC testing (including openshort, vih, voh, etc.) and Serdes trim testing. Test board 2 implements Serdes high-speed loopback testing through an ATE tester. The process of testing chips through this device is relatively complicated.

[0007] Another traditional test device is to implement all test functions on a test board. This device needs to be implemented by a high-end ATE test machine, resulting in a high test cost.

[0008] Therefore, the existing ATE test devices either have complicated test procedures or high test costs. Utility Model Content

[0009] The embodiment of the utility model provides a chip testing device based on ATE, which can solve the problems of complex testing process and high testing cost of the existing ATE testing device.

[0010] The present invention provides a chip testing device based on ATE, the device comprising:

[0011] The first test module;

[0012] An RF switch, wherein an input end of the RF switch is connected to an output end of the first test module;

[0013] A differential clock circuit module, wherein the output end of the differential clock circuit module is connected to the input end of the RF switch, and the differential clock circuit module is used to generate a first differential clock signal when the second test module performs a Serdes Trim test on the chip to be tested;

[0014] The second test module, the input end of the second test module is connected to the output end of the RF switch, the first test module and the second test module are used to perform a first type of test on the chip to be tested, and the second test module is also used to perform a Serdes Trim test on the chip to be tested according to the first differential clock signal.

[0015] Illustratively, the first category of tests does not include a Serdes Trim test.

[0016] In a specific embodiment, the differential clock circuit module includes a differential clock module and an attenuation circuit module;

[0017] A differential clock module, the differential clock module is used to generate an original differential clock signal when the second test module performs a SerdesTrim test on the chip to be tested;

[0018] The attenuation circuit module is used to attenuate the original differential clock signal to obtain a first differential clock signal, wherein the amplitude of the first differential clock signal is smaller than that of the original differential clock signal.

[0019] In a specific embodiment, the positive output terminal of the differential clock module is connected to the positive input terminal of the attenuation circuit module, and the negative output terminal of the differential clock module is connected to the negative input terminal of the attenuation circuit module;

[0020] The positive output end of the attenuation circuit module is connected to the first positive input end of the RF switch as the positive output end of the differential clock circuit module, and the negative output end of the attenuation circuit module is connected to the first negative input end of the RF switch as the negative output end of the differential clock circuit module;

[0021] The positive output terminal of the RF switch is connected to the positive input terminal of the second test module; the negative output terminal of the RF switch is connected to the negative input terminal of the second test module.

[0022] In a specific embodiment, the first test module includes: a first ATE tester, a first isolation module, a second isolation module, a first capacitor and a second capacitor;

[0023] The positive input terminal of the first ATE tester is connected to the output terminal of the first isolation module, and the negative input terminal of the first ATE tester is connected to the output terminal of the second isolation module;

[0024] The input end of the first isolation module is connected to the positive output end of the chip to be tested as the positive input end of the first test module, and the input end of the first isolation module is also connected to the input end of the first capacitor;

[0025] The input end of the second isolation module is connected to the negative output end of the chip to be tested as the negative input end of the first test module, and the input end of the second isolation module is also connected to the input end of the second capacitor;

[0026] An output terminal of the first capacitor is connected to a second positive input terminal of the RF switch;

[0027] The output terminal of the second capacitor is connected to the second negative input terminal of the RF switch.

[0028] In a specific embodiment, the second test module includes a second ATE tester, a third isolation module, a fourth isolation module, a third capacitor, and a fourth capacitor;

[0029] The positive input terminal of the second ATE tester is connected to the output terminal of the third isolation module, and the negative input terminal of the second ATE tester is connected to the output terminal of the fourth isolation module;

[0030] The input end of the third isolation module is connected to the output end of the third capacitor;

[0031] The input end of the fourth isolation module is connected to the output end of the fourth capacitor;

[0032] The input end of the third capacitor is connected to the positive output end of the RF switch as the positive input end of the second test module, and the output end of the third capacitor is connected to the positive input end of the chip to be tested;

[0033] The input end of the fourth capacitor is connected to the negative output end of the RF switch as the negative input end of the second test module, and the output end of the fourth capacitor is connected to the negative input end of the chip to be tested.

[0034] In a specific embodiment, the differential clock module includes: a differential crystal oscillator, a fifth capacitor, a sixth capacitor, a seventh capacitor, an eighth capacitor, a ninth capacitor, a magnetic bead, a first resistor and a second resistor;

[0035] The first port of the fifth capacitor is connected to the negative input terminal of the attenuation circuit module as the negative output terminal of the differential clock module;

[0036] The first port of the sixth capacitor is connected to the positive input terminal of the attenuation circuit module as the positive output terminal of the differential clock module;

[0037] A first port of the seventh capacitor is grounded;

[0038] A power pin of the differential crystal oscillator is connected to the second port of the seventh capacitor, the power pin of the differential crystal oscillator is also connected to the first port of the magnetic bead, a negative output pin of the differential crystal oscillator is connected to the second port of the fifth capacitor, a positive output pin of the differential crystal oscillator is connected to the second port of the sixth capacitor, a ground pin of the differential crystal oscillator is grounded, and an output enable pin of the differential crystal oscillator is connected to the first port of the second resistor;

[0039] Two ends of the first resistor are connected in parallel to the positive output pin and the negative output pin of the differential crystal oscillator;

[0040] The second port end of the second resistor is connected to the first port of the magnetic bead;

[0041] The second port of the magnetic bead is connected to the first port of the eighth capacitor;

[0042] The second port of the eighth capacitor is grounded;

[0043] The first port and the second port of the ninth capacitor are respectively connected in parallel to the first port and the second port of the eighth capacitor, and the first port of the ninth capacitor is also connected to the input voltage.

[0044] In a specific embodiment, the attenuation circuit module includes a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor and a twelfth resistor R;

[0045] The first port of the third resistor is connected to the positive output terminal of the differential clock module as the positive input terminal of the attenuation circuit module, and the second port of the third resistor is connected to the first port of the fourth resistor;

[0046] The second port of the fourth resistor is connected to the first positive input terminal of the RF switch as the positive output terminal of the attenuation circuit module;

[0047] A first port of the fifth resistor is connected to the first port of the third resistor, and a second port of the fifth resistor is grounded;

[0048] The first port of the sixth resistor is connected to the second port of the third resistor, and the second port of the sixth resistor is grounded;

[0049] The first port of the seventh resistor is connected to the second port of the fourth resistor, and the second port of the seventh resistor is grounded;

[0050] The first port of the eighth resistor is connected to the negative output terminal of the differential clock module as the negative input terminal of the attenuation circuit module, and the second port of the eighth resistor is connected to the first port of the ninth resistor;

[0051] The second port of the ninth resistor is connected to the first negative input terminal of the RF switch as the negative output terminal of the attenuation circuit module;

[0052] A first port of the tenth resistor is connected to the first port of the eighth resistor, and a second port of the tenth resistor is grounded;

[0053] The first port of the eleventh resistor is connected to the second port of the eighth resistor, and the second port of the eleventh resistor is grounded;

[0054] A first port of the twelfth resistor is connected to a second port of the ninth resistor, and a second port of the twelfth resistor is grounded.

[0055] Compared with the prior art, the beneficial effect of the embodiments of the utility model is as follows: according to the ATE-based chip testing device provided by the utility model, a differential clock circuit module is set in the device, and a differential clock signal is generated by the differential clock circuit module, so that the utility model can use a mid-to-low-end ATE test machine to test the chip, so that all test items of the chip can be completed on the same board, simplifying the chip testing process and reducing the testing cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] Figure 1 It is a structural schematic diagram of a chip testing device;

[0057] Figure 2 is a schematic diagram of the structure of another chip testing device;

[0058] Figure 3 A schematic diagram of the structure of a chip testing device based on ATE provided in an embodiment of the utility model;

[0059] Figure 4 A schematic diagram of a specific structure of a chip testing device based on ATE provided by an embodiment of the utility model;

[0060] Figure 5A schematic diagram of the isolation effect of an isolation module provided by an embodiment of the utility model;

[0061] Figure 6 A schematic diagram of a specific structure of a differential clock module provided by an embodiment of the utility model;

[0062] Figure 7 A schematic diagram of a specific structure of an attenuation circuit module provided in an embodiment of the utility model.

[0063] Reference numerals:

[0064] 1: first test module; 11: first ATE tester; 12: first isolation module; 13: second isolation module; C1: first capacitor; C2: second capacitor; 2: RF switch; 3: differential clock circuit module; 31: differential clock module; 311: differential crystal oscillator; 3111: phase-locked loop; 3112: crystal oscillator; 3113: output driver; 312: magnetic bead; C5: fifth capacitor; C6: sixth capacitor; C7: seventh capacitor; C8: eighth capacitor; C9: ninth capacitor; R1: first resistor; R2: second resistor; 32: attenuation circuit module; R3: third resistor; R4: fourth resistor; R5: fifth resistor; R6: sixth resistor; R7: seventh resistor; R8: eighth resistor; R9: ninth resistor; R10: tenth resistor; R11: eleventh resistor; R12: twelfth resistor; 4: second test module; 41: second ATE tester; 42: third isolation module; 33: fourth isolation module; C3: third capacitor; C4: fourth capacitor. DETAILED DESCRIPTION

[0065] The present invention is further described in detail below in conjunction with specific embodiments, but the implementation methods of the present invention are not limited thereto.

[0066] Figure 1 It is a structural schematic diagram of a chip testing device based on ATE.

[0067] For example, since low-end ATE testers cannot generate differential clock signals, the test device 100 needs to perform board separation testing on the chip to be tested. Figure 1 In the test device, the test device 100 needs to perform chip function test and Serdes trim test on board 1. On board 2, a high-speed loopback test is performed on the chip to be tested through an ATE test machine.

[0068] Exemplarily, it is necessary to perform a Serdes trim test on the chip under test through a differential clock signal.

[0069] Since the board test needs to be performed, after the chip to be tested completes the test items of board one, it needs to be connected to board two for testing. Such a testing process is relatively complicated.

[0070] Figure 2 It is a structural schematic diagram of a chip testing device based on ATE.

[0071] For example, Figure 2 The test device 200 can complete all test items of the chip to be tested, such as functional test, such as IO test, DC test; Serdes test, such as Serdes Trim test and high-speed loopback test.

[0072] For example, to implement a test without separating boards, it is necessary to set up an ultra-high bandwidth high-frequency isolation module with a bandwidth of 20Ghz or 40Ghz in the test device. To perform a Serdes Trim test, the ATE test channel is required to provide the chip with a differential clock signal that meets the test requirements (for example, 0.8V common mode voltage, 50mV amplitude, and 100Mhz frequency). However, only high-end testers have such functions in the mass production stage.

[0073] Therefore, the testing cost of testing the chip using this type of testing device is high.

[0074] In view of this, the present invention provides a chip testing device based on ATE. According to the chip testing device based on ATE provided by the present invention, by setting a differential clock circuit module in the device, the differential clock circuit module generates a differential clock signal, so that the present invention can use a mid-to-low-end ATE tester to test the chip, so that all test items of the chip can be completed on the same board, simplifying the test process of the chip and reducing the test cost.

[0075] Example 1

[0076] Figure 3 The structure diagram of a chip testing device based on ATE provided by an embodiment of the utility model is shown. As an example but not a limitation, the testing device 300 may include a first testing module 1, an RF switch 2, a differential clock circuit module 3 and a second testing module 4.

[0077] First test module 1;

[0078] An RF switch 2, wherein an input end of the RF switch 2 is connected to an output end of the first test module 1;

[0079] The differential clock circuit module 3 , the output end of the differential clock circuit module 3 can be connected to the input end of the second test module 4 .

[0080] The second test module 4 has an input end connected to the output end of the differential clock circuit module 3. The positive output end of the second test module 4 can be connected to the positive input end of the chip to be tested, and the negative output end of the second test module 4 can be connected to the negative input end of the chip to be tested.

[0081] In one example, the first test module 1 and the second test module 4 can be used to perform a first type of test on the chip to be tested. The first type of test may include functional tests such as high-speed loopback test and IO, DC test (including openshort, vih, voh and other tests) in Serdes test. The first type of test does not include Serdes Trim test. The differential clock circuit module 3 can be used to generate a first differential clock signal when the second test module 4 performs a Serdes Trim test on the chip to be tested. The second test module 4 can also be used to perform a Serdes Trim test on the chip to be tested according to the first differential clock signal. The RF switch can be used to switch the output of the signal generated by the first test module 1 and the signal generated by the differential clock circuit module 3 according to the test requirements.

[0082] According to the ATE-based chip testing device provided by the utility model, a differential clock circuit module is set in the device, and a differential clock signal is generated by the differential clock circuit module, so that the utility model can use a mid-to-low-end ATE test machine to test the chip, so that all test items of the chip can be completed on the same board, simplifying the chip testing process and reducing the testing cost.

[0083] Example 2

[0084] Based on Example 1, Figure 4 The schematic diagram shows the specific structure of a chip testing device based on ATE provided by the utility model.

[0085] In some embodiments, see Figure 4 The specific structure of the first test module 1 in the embodiment of the present invention may include a first ATE tester 11, a first isolation module 12, a second isolation module 13, a first capacitor C1 and a second capacitor C2.

[0086] In a possible implementation, the positive input terminal of the first ATE tester 11 may be connected to the output terminal of the first isolation module 12 , and the negative input terminal of the first ATE tester 11 may be connected to the output terminal of the second isolation module 13 .

[0087] The input end of the first isolation module 12 can be connected to the positive output end of the chip to be tested as the positive input end of the first test module 1 , and the input end of the first isolation module 12 can also be connected to the input end of the first capacitor C1 .

[0088] The input end of the second isolation module 13 as the negative input end of the first test module 1 can be connected to the negative output end of the chip to be tested, and the input end of the second isolation module 13 can also be connected to the input end of the second capacitor C2.

[0089] The output end of the first capacitor C1 can be connected to the second positive input end of the RF switch 2 as the positive output end of the first test module 1;

[0090] The output end of the second capacitor C2 can be connected to the second negative input end of the RF switch 2 as the negative output end of the first test module 1 .

[0091] In one example, the first isolation module 12 and the second isolation module 13 can be an ultra-high bandwidth high frequency isolation module. The module is a BIAS-T bias circuit module, which is mainly used for DC bias of high-speed digital circuits or radio frequency signals in the 20Ghz frequency band. The bandwidth of the bias circuit of the module can reach 40M-20Ghz. The S11 within the bandwidth is below -20Db.

[0092] For example, the isolation module can be used to isolate ATE test channels from high-speed signals. Figure 5 The return loss curve of the test fixture at 20 GHz bandwidth in (a), and Figure 5 (b) shows the return loss curve after the isolation module is connected in parallel to the test fixture with a bandwidth of 20 GHz. It can be seen that the isolation module can introduce oscillation of the return loss in the low-frequency part, and has no obvious impact on the test fixture with a bandwidth of 20 GHz in the high-frequency area, thus playing an isolation role.

[0093] In some embodiments, see Figure 4 The specific structure of the differential clock circuit module 3 in the differential clock circuit module 3 may include a differential clock module 31 and an attenuation circuit module 32.

[0094] In a possible implementation, the positive output terminal of the differential clock module 31 may be connected to the positive input terminal of the attenuation circuit module 32 , and the negative output terminal of the differential clock module 31 may be connected to the negative input terminal of the attenuation circuit module 32 .

[0095] The positive output end of the attenuation circuit module 32 can be connected to the first positive input end of the RF switch 2 as the positive output end of the differential clock circuit module 3, and the negative output end of the attenuation circuit module 32 can be connected to the first negative input end of the RF switch 2 as the negative output end of the differential clock circuit module 3.

[0096] The positive output terminal of the RF switch 2 can be connected to the positive input terminal of the second test module 4 ; the negative output terminal of the RF switch 2 can be connected to the negative input terminal of the second test module 4 .

[0097] In one example, the differential clock circuit module 3 can be used to generate an original differential clock signal when the second test module 4 performs a Serdes Trim test on the chip to be tested. The attenuation circuit module 32 can be used to attenuate the original differential clock signal to obtain a first differential clock signal. Since the common mode voltage of the first differential clock signal is still high, the RF switch 2 can be used to filter the common mode voltage of the first differential clock signal to obtain a filtered first differential clock signal with a common mode voltage of 0V.

[0098] Specifically, the common mode voltage of the original differential clock signal is 1.25V, the amplitude is 300mV, and the frequency is 100Mhz.

[0099] Specifically, since the Serdes Trim test requires a clock signal with a common mode voltage of 0.8V, an amplitude of 50mV, and a frequency of 156.25Mhz, and the amplitude of the original signal is relatively large, the attenuation circuit block 22 can be used to attenuate the clock amplitude from the original 300mV to 50mV, thereby achieving the required clock amplitude condition and obtaining the first differential clock signal.

[0100] Optionally, the attenuation value of the signal amplitude can be adjusted according to specific usage requirements.

[0101] In some embodiments, see Figure 4 The specific structure of the second test module 4 in FIG. 4 may include a second ATE tester 41, a third isolation module 42, a fourth isolation module 43, a third capacitor C3 and a fourth capacitor C4.

[0102] In a possible implementation, the positive input terminal of the second ATE tester 41 may be connected to the output terminal of the third isolation module 42 , and the negative input terminal of the second ATE tester 41 may be connected to the output terminal of the fourth isolation module 43 .

[0103] An input end of the third isolation module 42 may be connected to an output end of the third capacitor C3 .

[0104] An input end of the fourth isolation module 43 may be connected to an output end of the fourth capacitor C4 .

[0105] The input end of the third capacitor C3 can be connected to the positive output end of the RF switch 2 as the positive input end of the second test module 4, and the output end of the third capacitor C3 can be connected to the positive input end of the chip to be tested.

[0106] The input end of the fourth capacitor C4 can be connected to the negative output end of the RF switch 2 as the negative input end of the second test module 4, and the output end of the fourth capacitor C4 can be connected to the negative input end of the chip to be tested.

[0107] Exemplarily, the second test module 4 can pull up the common mode voltage of the filtered first differential clock signal with a common mode voltage of 0V to 0.8V through the second ATE test machine 41 channel to achieve the target differential clock signal required for the test. Then, the Serdes Trim test is performed on the chip to be tested according to the target differential clock signal.

[0108] Specifically, the first ATE tester 11, isolation module 12, isolation module 13 and the second ATE tester 41, isolation module 42, isolation module 43 in the first test module 1 are used to perform a high-speed loopback test in a Serdes test on the chip to be tested. Capacitors C1, C2, C3 and C4 are used to perform functional tests such as IO tests and DC tests on the chip to be tested. The differential clock circuit module 3 and the second test module 4 are used to perform a Serdes Trim test on the chip to be tested.

[0109] According to the ATE-based chip testing device provided by the utility model, a differential clock circuit module is set in the device, and a differential clock signal is generated by the differential clock circuit module, so that the utility model can use a mid-to-low-end ATE test machine to test the chip, so that all test items of the chip can be completed on the same board, simplifying the chip testing process and reducing the testing cost.

[0110] Example 3

[0111] Figure 6 The differential clock module 31 may include: a differential crystal oscillator 311, a fifth capacitor C5, a sixth capacitor C6, a seventh capacitor C7, an eighth capacitor C8, a ninth capacitor C9, a magnetic bead 312, a first resistor R1 and a second resistor R2.

[0112] In one possible implementation, see Figure 6 The first port of the fifth capacitor C5 can be connected to the negative input terminal of the attenuation circuit module 32 as the negative output terminal of the differential clock module 31 .

[0113] The first port of the sixth capacitor C6 can be connected to the positive input terminal of the attenuation circuit module 32 as the positive output terminal of the differential clock module 31 .

[0114] A first terminal of the seventh capacitor C7 is grounded.

[0115] The power pin of the differential crystal oscillator 311 can be connected to the second port of the seventh capacitor C7, the power pin of the differential crystal oscillator 311 can also be connected to the first port of the magnetic bead 312, the negative output pin of the differential crystal oscillator 311 can be connected to the second port of the fifth capacitor C5, the positive output pin of the differential crystal oscillator 311 can be connected to the second port of the sixth capacitor C6, the ground pin of the differential crystal oscillator 311 is grounded, and the output enable pin of the differential crystal oscillator 311 can be connected to the first port of the second resistor R2.

[0116] Two ends of the first resistor R1 may be connected in parallel to the positive output pin and the negative output pin of the differential crystal oscillator 311 .

[0117] The second port of the second resistor R2 may be connected to the first port of the magnetic bead 312 .

[0118] The second port of the magnetic bead may be connected to the first port of the eighth capacitor C8.

[0119] A second port of the eighth capacitor C8 is grounded;

[0120] The first port and the second port of the ninth capacitor C9 can be connected in parallel to the first port and the second port of the eighth capacitor C8 respectively, and the first port of the ninth capacitor C9 can also be connected to the input voltage terminal.

[0121] In one example, see Figure 6 The differential crystal oscillator 311 may include a phase-locked loop 3111 , a crystal oscillator 3112 and an output driver 3113 .

[0122] Exemplarily, the crystal oscillator 3112 can be connected in parallel to the phase-locked loop 3111. The input end of the output driver 3113 can be connected to the output end of the phase-locked loop 3111, the positive output end of the output driver 3113 can be used as the positive output pin of the differential crystal oscillator 311, and the negative output end of the output driver 3113 can be used as the negative output pin of the differential crystal oscillator 311.

[0123] Optionally, the differential crystal oscillator 311 may also have a floating pin left floating.

[0124] In a possible implementation, the capacitance specification of the fifth capacitor C5, the sixth capacitor C6, the seventh capacitor C7 and the eighth capacitor C8 may be 0.1 μF. The capacitance specification of the ninth capacitor C9 may be 4.7 μF / 6.3V. The specification of the differential crystal oscillator may be 50 MHz. The resistance value of the first resistor R1 may be 100Ω, and the resistance value of the second resistor R2 may be 4.7 kΩ.

[0125] Embodiment 4,

[0126] Figure 7The schematic diagram of the specific structure of an attenuation circuit module provided by the utility model is shown. The attenuation circuit module 32 may include a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11 and a twelfth resistor R12.

[0127] The first port of the third resistor R3 can be connected to the positive output terminal of the differential clock module 31 as the positive input terminal of the attenuation circuit module 32, and the second port of the third resistor R3 can be connected to the first port of the fourth resistor R4.

[0128] The second port of the fourth resistor R4 can be connected to the first positive input terminal of the RF switch 2 as the positive output terminal of the attenuation circuit module 32 .

[0129] A first port of the fifth resistor R5 may be connected to the first port of the third resistor R3 , and a second port of the fifth resistor R5 is grounded.

[0130] A first port of the sixth resistor R6 may be connected to a second port of the third resistor R3 , and a second port of the sixth resistor R6 is grounded.

[0131] A first port of the seventh resistor R7 may be connected to a second port of the fourth resistor R4, and a second port of the seventh resistor R7 is grounded.

[0132] The first port of the eighth resistor R8 can be connected to the negative output terminal of the differential clock module 31 as the negative input terminal of the attenuation circuit module 32, and the second port of the eighth resistor R8 can be connected to the first port of the ninth resistor R9.

[0133] The second port of the ninth resistor R9 can be connected to the first negative input terminal of the RF switch 2 as the negative output terminal of the attenuation circuit module 32 .

[0134] A first port of the tenth resistor R10 may be connected to a first port of the eighth resistor R8 , and a second port of the tenth resistor R10 is grounded.

[0135] A first port of the eleventh resistor R11 may be connected to a second port of the eighth resistor R8 , and a second port of the eleventh resistor R11 is grounded.

[0136] A first port of the twelfth resistor R12 may be connected to a second port of the ninth resistor R9 , and a second port of the twelfth resistor R12 is grounded.

[0137] The above contents are further detailed descriptions of the present invention in combination with specific preferred implementations, and the specific implementation of the present invention cannot be considered to be limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A chip testing device based on ATE, characterized in that: include: A first test module (1); An RF switch (2), wherein an input end of the RF switch (2) is connected to an output end of the first test module (1); A differential clock circuit module (3), the output end of the differential clock circuit module (3) being connected to the input end of the RF switch (2), and the differential clock circuit module (3) being used to generate a first differential clock signal when the second test module performs a Serdes Trim test on the chip to be tested; A second test module (4), wherein an input end of the second test module (4) is connected to an output end of the RF switch (2), the first test module (1) and the second test module (4) are used to perform a first type of test on the chip to be tested, and the second test module (4) is further used to perform a Serdes Trim test on the chip to be tested according to the first differential clock signal, wherein the first type of test does not include the Serdes Trim test.

2. The device according to claim 1, characterized in that The differential clock circuit module (3) comprises a differential clock module (31) and an attenuation circuit module (32); A differential clock module (31), the differential clock module (31) being used to generate an original differential clock signal when the second test module (4) performs the Serdes Trim test on the chip to be tested; An attenuation circuit module (32), the attenuation circuit module (32) is used to perform attenuation processing on the original differential clock signal to obtain a first differential clock signal, wherein the amplitude of the first differential clock signal is smaller than that of the original differential clock signal.

3. The device according to claim 2, characterized in that The positive output end of the differential clock module (31) is connected to the positive input end of the attenuation circuit module (32), and the negative output end of the differential clock module (31) is connected to the negative input end of the attenuation circuit module (32); The positive output end of the attenuation circuit module (32) is connected to the first positive input end of the RF switch (2) as the positive output end of the differential clock circuit module (3), and the negative output end of the attenuation circuit module (32) is connected to the first negative input end of the RF switch (2) as the negative output end of the differential clock circuit module (3); The positive output terminal of the RF switch (2) is connected to the positive input terminal of the second test module (4); and the negative output terminal of the RF switch (2) is connected to the negative input terminal of the second test module (4).

4. The device according to claim 3, characterized in that The first test module (1) comprises: a first ATE test machine (11), a first isolation module (12), a second isolation module (13), a first capacitor (C1) and a second capacitor (C2); The positive input terminal of the first ATE tester (11) is connected to the output terminal of the first isolation module (12), and the negative input terminal of the first ATE tester (11) is connected to the output terminal of the second isolation module (13); The input end of the first isolation module (12) is connected to the positive output end of the chip to be tested as the positive input end of the first test module (1), and the input end of the first isolation module (12) is also connected to the input end of the first capacitor (C1); The input end of the second isolation module (13) is connected to the negative output end of the chip to be tested as the negative input end of the first test module (1), and the input end of the second isolation module (13) is also connected to the input end of the second capacitor (C2); The output end of the first capacitor (C1) is connected to the second positive input end of the RF switch (2); The output end of the second capacitor (C2) is connected to the second negative input end of the RF switch (2).

5. The device according to claim 4, characterized in that The second test module (4) comprises a second ATE tester (41), a third isolation module (42), a fourth isolation module (43), a third capacitor (C3) and a fourth capacitor (C4); The positive input terminal of the second ATE tester (41) is connected to the output terminal of the third isolation module (42), and the negative input terminal of the second ATE tester (41) is connected to the output terminal of the fourth isolation module (43); The input end of the third isolation module (42) is connected to the output end of the third capacitor (C3); The input end of the fourth isolation module (43) is connected to the output end of the fourth capacitor (C4); The input end of the third capacitor (C3) is connected to the positive output end of the RF switch (2) as the positive input end of the second test module (4), and the output end of the third capacitor (C3) is connected to the positive input end of the chip to be tested; The input end of the fourth capacitor (C4) is connected to the negative output end of the RF switch (2) as the negative input end of the second test module (4), and the output end of the fourth capacitor (C4) is connected to the negative input end of the chip to be tested.

6. The device according to claim 3, characterized in that The differential clock module (31) comprises: a differential crystal oscillator (311), a fifth capacitor (C5), a sixth capacitor (C6), a seventh capacitor (C7), an eighth capacitor (C8), a ninth capacitor (C9), a magnetic bead (312), a first resistor (R1) and a second resistor (R2); The first port of the fifth capacitor (C5) is connected to the negative input terminal of the attenuation circuit module (32) as the negative output terminal of the differential clock module (31); The first port of the sixth capacitor (C6) is connected to the positive input end of the attenuation circuit module (32) as the positive output end of the differential clock module (31); A first port of the seventh capacitor (C7) is grounded; A power pin of the differential crystal oscillator (311) is connected to the second port of the seventh capacitor (C7), the power pin of the differential crystal oscillator (311) is also connected to the first port of the magnetic bead (312), a negative output pin of the differential crystal oscillator (311) is connected to the second port of the fifth capacitor (C5), a positive output pin of the differential crystal oscillator (311) is connected to the second port of the sixth capacitor (C6), a ground pin of the differential crystal oscillator (311) is grounded, and an output enable pin of the differential crystal oscillator (311) is connected to the first port of the second resistor (R2); Two ends of the first resistor (R1) are connected in parallel to the positive output pin and the negative output pin of the differential crystal oscillator (311); The second port of the second resistor (R2) is connected to the first port of the magnetic bead (312); The second port of the magnetic bead (312) is connected to the first port of the eighth capacitor (C8); The second port of the eighth capacitor (C8) is grounded; The first port and the second port of the ninth capacitor (C9) are respectively connected in parallel to the first port and the second port of the eighth capacitor (C8), and the first port of the ninth capacitor (C9) is also connected to the input voltage terminal.

7. The device according to claim 3, characterized in that The attenuation circuit module (32) comprises a third resistor (R3), a fourth resistor (R4), a fifth resistor (R5), a sixth resistor (R6), a seventh resistor (R7), an eighth resistor (R8), a ninth resistor (R9), a tenth resistor (R10), an eleventh resistor (R11) and a twelfth resistor (R12); The first port of the third resistor (R3) is connected to the positive output end of the differential clock module (31) as the positive input end of the attenuation circuit module (32), and the second port of the third resistor (R3) is connected to the first port of the fourth resistor (R4); The second port of the fourth resistor (R4) is connected to the first positive input terminal of the RF switch (2) as the positive output terminal of the attenuation circuit module (32); A first port of the fifth resistor (R5) is connected to a first port of the third resistor (R3), and a second port of the fifth resistor (R5) is grounded; A first port of the sixth resistor (R6) is connected to a second port of the third resistor (R3), and a second port of the sixth resistor (R6) is grounded; A first port of the seventh resistor (R7) is connected to a second port of the fourth resistor (R4), and a second port of the seventh resistor (R7) is grounded; The first port of the eighth resistor (R8) is connected to the negative output end of the differential clock module (31) as the negative input end of the attenuation circuit module (32), and the second port of the eighth resistor (R8) is connected to the first port of the ninth resistor (R9); The second port of the ninth resistor (R9) is connected to the first negative input terminal of the RF switch (2) as the negative output terminal of the attenuation circuit module (32); A first port of the tenth resistor (R10) is connected to a first port of the eighth resistor (R8), and a second port of the tenth resistor (R10) is grounded; A first port of the eleventh resistor (R11) is connected to a second port of the eighth resistor (R8), and a second port of the eleventh resistor (R11) is grounded; A first port of the twelfth resistor (R12) is connected to a second port of the ninth resistor (R9), and a second port of the twelfth resistor (R12) is grounded.

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