Network optical fiber interface circuit of distributed cascade multilevel converter system

Abstract

The utility model discloses a network optical fiber interface circuit of a distributed cascade multilevel converter system, which comprises an optical fiber transceiver, a field programmable logic gate array and a differential signal conversion circuit, and a PECL port of the optical fiber transceiver is connected with an LVDS interface of the field programmable logic gate array through the differential signal conversion circuit. The PECL port of the optical fiber transceiver comprises a PECL sending port and a PECL receiving port, the LVDS interface of the field programmable logic gate array comprises an LVDS sending port and an LVDS receiving port, and the differential signal conversion circuit comprises an LVDS to PECL coupling circuit connected between the LVDS sending port and the PECL receiving port and a PECL to LVDS coupling circuit connected between the PECL sending port and the LVDS receiving port. According to the utility model, the requirement of the communication rate of more than 100Mbps of an optical fiber interface of a distributed cascade multilevel converter system is met.

Description

Technical Field

[0001] The utility model relates to the field of distributed cascade multi-level converter systems, in particular to a network optical fiber interface circuit of a distributed cascade multi-level converter system. Background Art

[0002] Communication rate is the first requirement of the optical fiber interface circuit, which determines the hardware and software design of the optical fiber interface. In addition, reliability and cost are also considered in the design of the optical fiber interface.

[0003] The network communication rate is estimated based on the system switching frequency. In each switching cycle, assuming that the control algorithm executed by the master node requires voltage, current and temperature feedback information of each module, the communication rate P required by the communication network can be approximated as:

[0004] P=N×n n ×n b ×f sw (1)

[0005] In formula (1), P is the communication rate; N is the number of slave nodes in the system; n b The number of bits per data packet; f sw is the system switching frequency; n n The number of data packets that each node needs to transmit.

[0006] Assuming a simple three-phase system as an example, with 3 slave nodes, each node needs to transmit 1 data packet, each data packet is 96 bits, and the switching frequency is 10K, the communication rate P required by the communication network can be obtained to be 2.88Mb / s. Involving a more complex system, such as a three-phase H-bridge cascade 11-level converter variable frequency speed regulation system, assuming that each node has 1 data packet, each data packet is 96 bits, there are a total of 16 nodes, and the switching frequency is 50K, the communication rate P required for the communication network can be obtained to be 76.8Mbps.

[0007] Based on the above theoretical analysis, it can be seen that the current communication rate of the optical fiber interface circuit is mostly within 100Mbps, while the optical fiber interface design of the distributed cascade multilevel converter system should meet the communication rate of more than 100M, so it is difficult to meet its rate requirements. Utility Model Content

[0008] The technical problem to be solved by the utility model is to provide a network optical fiber interface circuit of a distributed cascade multi-level converter system, which meets the requirement of a communication rate of more than 100Mbps for the optical fiber interface of the distributed cascade multi-level converter system.

[0009] The technical solution of the utility model is:

[0010] A network optical fiber interface circuit of a distributed cascade multi-level converter system comprises an optical fiber transceiver, a field programmable logic gate array and a differential signal conversion circuit. The PECL port of the optical fiber transceiver is connected to any LVDS interface of the field programmable logic gate array through the differential signal conversion circuit. The PECL port of the optical fiber transceiver comprises a PECL transmission port and a PECL receiving port. Each LVDS interface of the field programmable logic gate array comprises an LVDS transmission port and an LVDS receiving port. The differential signal conversion circuit comprises an LVDS-to-PECL coupling circuit connected between the LVDS transmission port and the PECL receiving port and a PECL-to-LVDS coupling circuit connected between the PECL transmission port and the LVDS receiving port.

[0011] The LVDS to PECL coupling circuit includes a capacitor C1, a capacitor C2, and two resistors R 1a and two resistors R 2a ;

[0012] The two resistors R 1a and two resistors R 2a In the example, one of the resistors R 1a The inner end and one of the resistors R 2a The inner ends are connected in series with each other, and another resistor R 1a The inner end and another resistor R 2a The inner ends of the two series circuits are connected in series, and then the two series circuits are connected in parallel to the power supply Vcc and the ground terminal, and the two resistors R 1a The external ends are connected to the power supply Vcc, and the two resistors R 2a The outer ends of are grounded;

[0013] The two differential signal ends of the LVDS transmission port are connected to one end of the capacitor C1 and one end of the capacitor C2 respectively, and the other end of the capacitor C1 and one of the differential signal ends of the PECL receiving port are connected to one of the resistors R 1a and one of the resistors R 2a In the series circuit between the two terminals, the other end of capacitor C2 and the other differential signal end of the PECL receiving port are connected to another resistor R 1a and another resistor R 2a On the series line between.

[0014] The PECL to LVDS coupling circuit includes two resistors R 1b , two resistors R 2b , two resistors R 1c , two resistors R 2c and two resistors R 3c ;

[0015] The two resistors R 1b and two resistors R 2b In the example, one of the resistors R 1b The inner end and one of the resistors R 2b The inner end is connected in series with another resistor R 1b The inner end and another resistor R 2b The inner ends of the two series circuits are connected in series, and then the two series circuits are connected in parallel to the power supply Vcc and the ground terminal, and the two resistors R 1b The external ends are connected to the power supply Vcc, and the two resistors R 2b The outer ends of are grounded;

[0016] Two resistors R 1c , two resistors R 2c and two resistors R 3c In the example, one of the resistors R 1c 、One of the resistors R 2c and one of the resistors R 3c Connect in series, another resistor R 1c , another resistor R 2c and another resistor R 3c The two series circuits are then connected in parallel to the power supply Vcc and the ground terminal, and the two resistors R 1c The external ends are connected to the power supply Vcc, and the two resistors R 3c The outer ends of are grounded;

[0017] One of the differential signal ends of the PECL transmit port is connected to one of the resistors R 1b and one of the resistors R 2b The series circuit between the two resistors R 1c and one of the resistors R 2c The other differential signal end of the PECL transmitting port is connected to another resistor R 1b and another resistor R 2b The series circuit between them is connected to another resistor R 1c and another resistor R 2c On the series line between

[0018] One of the differential signal terminals of the LVDS receiving port is connected to one of the resistors R 2c and one of the resistors R 3c The other differential signal end of the LVDS receiving port is connected to another resistor R 2c and another resistor R 3c On the series line between.

[0019] The LVDS to PECL coupling circuit also includes two resistors R4, a resistor R5 and a resistor R6. The two differential signal ends of the LVDS transmitting port are respectively connected to one end of the two resistors R4 in a one-to-one correspondence. The resistors R5 and R6 are connected in parallel with each other and the two parallel ends are respectively connected to the other ends of the two resistors R4 in a one-to-one correspondence. One end of the capacitor C1 and one end of the capacitor C2 are respectively connected to the other ends of the two resistors R4 in a one-to-one correspondence.

[0020] The PECL to LVDS coupling circuit further includes a resistor R7, and the resistor R7 is connected between two differential signal terminals of the LVDS receiving port.

[0021] Advantages of the utility model:

[0022] The optical fiber transceiver of the utility model adopts an optical fiber transceiver with a PECL port, which can achieve a communication rate of 155Mbps, integrates transmission and reception, has strong anti-interference ability and high reliability;

[0023] The field programmable logic gate array of the utility model has multiple LVDS interfaces, and the LVDS interface can support a data transmission rate of up to 640Mbps. Compared with the single-ended I / O standard, the LVDS interface maintains signal integrity and has lower electromagnetic interference and lower power consumption;

[0024] The differential signal conversion circuit of the utility model combines the advantages of DC coupling and AC coupling, realizes the coupled communication of the PECL port and the LVDS interface, and ensures the reliability of signal transmission. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 It is a circuit diagram of the utility model.

[0026] Figure numerals: 1-field programmable gate array FPGA, 2-optical fiber transceiver, 11-LVDS transmission port 11, 12-LVDS receiving port, 21-PECL transmission port, 22-PECL receiving port. DETAILED DESCRIPTION

[0027] The following will be combined with the drawings in the embodiments of the utility model to clearly and completely describe the technical solutions in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments in the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.

[0028] See Figure 1, a network optical fiber interface circuit of a distributed cascade multi-level converter system, comprising an optical fiber transceiver 2 (model HFBR_5204T), a field programmable logic gate array FPGA 1 (Cyclone series, model EP1C6144C6) and a differential signal conversion circuit, wherein the PECL port of the optical fiber transceiver 2 is connected to any LVDS interface of the FPGA 1 through the differential signal conversion circuit, the PECL port of the optical fiber transceiver 2 comprises a PECL transmission port 21 and a PECL receiving port 22, each LVDS interface of the FPGA 1 comprises an LVDS transmission port 11 and an LVDS receiving port 12, and the differential signal conversion circuit comprises an LVDS to PECL coupling circuit connected between the LVDS transmission port 11 and the PECL receiving port 22 and a PECL to LVDS coupling circuit connected between the PECL transmission port 21 and the LVDS receiving port 12;

[0029] The LVDS to PECL coupling circuit includes capacitor C1, capacitor C2, and two resistors R 1a , two resistors R 2a , two resistors R4 (120Ω), resistor R5 (170Ω) and resistor R6 (100Ω);

[0030] Two resistors R 1a and two resistors R 2a In the example, one of the resistors R 1a The inner end and one of the resistors R 2a The inner ends are connected in series with each other, and another resistor R 1a The inner end and another resistor R 2a The inner ends of the two series circuits are connected in series, and then the two series circuits are connected in parallel to the power supply Vcc and the ground terminal, and the two resistors R 1a The external ends are connected to Vcc (5V), and two resistors R 2a The outer ends of are grounded;

[0031] The two differential signal ends of the LVDS transmission port 11 are respectively connected to one end of the two resistors R4 in a one-to-one correspondence, the resistors R5 and R6 are connected in parallel and the two parallel ends are respectively connected to the other ends of the two resistors R4 in a one-to-one correspondence, and one end of the capacitor C1 and one end of the capacitor C2 are respectively connected to the other ends of the two resistors R4 in a one-to-one correspondence, and the other end of the capacitor C1 and one of the differential signal ends of the PECL receiving port 22 are both connected to one of the resistors R 1a and one of the resistors R 2a In the series circuit between the two terminals, the other end of the capacitor C2 and the other differential signal end of the PECL receiving port 22 are connected to another resistor R 1a and another resistor R 2a On the series line between

[0032] The PECL to LVDS coupling circuit includes two resistors R 1b , two resistors R 2b , two resistors R 1c , two resistors R 2c , two resistors R 3c and resistor R7 (100Ω);

[0033] Two resistors R 1b and two resistors R 2b In the example, one of the resistors R 1b The inner end and one of the resistors R 2b The inner end is connected in series with another resistor R 1b The inner end and another resistor R 2b The inner ends of the two series circuits are connected in series, and then the two series circuits are connected in parallel to the power supply Vcc and the ground terminal, and the two resistors R 1b The external ends are connected to the power supply Vcc, and the two resistors R 2b The outer ends of are grounded;

[0034] Two resistors R 1c , two resistors R 2c and two resistors R 3c In the example, one of the resistors R 1c 、One of the resistors R 2c and one of the resistors R 3c Connect in series, another resistor R 1c , another resistor R 2c and another resistor R 3c The two series circuits are then connected in parallel to the power supply Vcc and the ground terminal, and the two resistors R 1c The external ends are connected to the power supply Vcc, and the two resistors R 3c The outer ends of are grounded;

[0035] One of the differential signal terminals of the PECL transmission port 21 is connected to one of the resistors R 1b and one of the resistors R 2b The series circuit between the two resistors R 1c and one of the resistors R 2c In the series line between the two terminals, the other differential signal terminal of the PECL transmission port 21 is connected to another resistor R 1b and another resistor R 2b The series circuit between them is connected to another resistor R 1c and another resistor R 2c On the series line between

[0036] The resistor R7 is connected between two differential signal terminals of the LVDS receiving port 12, and one of the differential signal terminals of the LVDS receiving port 12 is connected to one of the resistors R 2c and one of the resistors R 3c In the series line between the two terminals, another differential signal terminal of the LVDS receiving port 12 is connected to another resistor R 2c and another resistor R 3c On the series line between.

[0037] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A network optical fiber interface circuit for a distributed cascade multilevel converter system, characterized in that: The invention comprises an optical fiber transceiver, a field programmable logic gate array and a differential signal conversion circuit. The PECL port of the optical fiber transceiver is connected to any LVDS interface of the field programmable logic gate array through the differential signal conversion circuit. The PECL port of the optical fiber transceiver comprises a PECL transmission port and a PECL receiving port. Each LVDS interface of the field programmable logic gate array comprises an LVDS transmission port and an LVDS receiving port. The differential signal conversion circuit comprises an LVDS-to-PECL coupling circuit connected between the LVDS transmission port and the PECL receiving port and a PECL-to-LVDS coupling circuit connected between the PECL transmission port and the LVDS receiving port.

2. The network optical fiber interface circuit of a distributed cascade multi-level converter system according to claim 1, characterized in that: The LVDS to PECL coupling circuit includes a capacitor C1, a capacitor C2, and two resistors R 1a and two resistors R 2a ; The two resistors R 1a and two resistors R 2a In the example, one of the resistors R 1a The inner end and one of the resistors R 2a The inner ends are connected in series with each other, and another resistor R 1a The inner end and another resistor R 2a The inner ends of the two series circuits are connected in series, and then the two series circuits are connected in parallel to the power supply Vcc and the ground terminal, and the two resistors R 1a The external ends are connected to the power supply Vcc, and the two resistors R 2a The outer ends of are grounded; The two differential signal ends of the LVDS transmission port are connected to one end of the capacitor C1 and one end of the capacitor C2 respectively, and the other end of the capacitor C1 and one of the differential signal ends of the PECL receiving port are connected to one of the resistors R 1a and one of the resistors R 2a In the series circuit between the two terminals, the other end of capacitor C2 and the other differential signal end of the PECL receiving port are connected to another resistor R 1a and another resistor R 2a On the series line between.

3. The network optical fiber interface circuit of a distributed cascade multi-level converter system according to claim 1, characterized in that: The PECL to LVDS coupling circuit includes two resistors R 1b , two resistors R 2b , two resistors R 1c , two resistors R 2c and two resistors R 3c ; The two resistors R 1b and two resistors R 2b In the example, one of the resistors R 1b The inner end and one of the resistors R 2b The inner end is connected in series with another resistor R 1b The inner end and another resistor R 2b The inner ends of the two series circuits are connected in series, and then the two series circuits are connected in parallel to the power supply Vcc and the ground terminal, and the two resistors R 1b The external ends are connected to the power supply Vcc, and the two resistors R 2b The outer ends of are grounded; Two resistors R 1c , two resistors R 2c and two resistors R 3c In the example, one of the resistors R 1c , one of the resistors R 2c and one of the resistors R 3c Connect in series, another resistor R 1c , another resistor R 2c and another resistor R 3c The two series circuits are then connected in parallel to the power supply Vcc and the ground terminal, and the two resistors R 1c The external ends are connected to the power supply Vcc, and the two resistors R 3c The outer ends of are grounded; One of the differential signal ends of the PECL transmit port is connected to one of the resistors R 1b and one of the resistors R 2b The series circuit between the two resistors R 1c and one of the resistors R 2c The other differential signal end of the PECL transmitting port is connected to another resistor R 1b and another resistor R 2b The series circuit between them is connected to another resistor R 1c and another resistor R 2c On the series line between One of the differential signal terminals of the LVDS receiving port is connected to one of the resistors R 2c and one of the resistors R 3c The other differential signal end of the LVDS receiving port is connected to another resistor R 2c and another resistor R 3c On the series line between.

4. The network optical fiber interface circuit of a distributed cascade multi-level converter system according to claim 2, characterized in that: The LVDS to PECL coupling circuit also includes two resistors R4, a resistor R5 and a resistor R6. The two differential signal ends of the LVDS transmitting port are respectively connected to one end of the two resistors R4 in a one-to-one correspondence. The resistors R5 and R6 are connected in parallel with each other and the two parallel ends are respectively connected to the other ends of the two resistors R4 in a one-to-one correspondence. One end of the capacitor C1 and one end of the capacitor C2 are respectively connected to the other ends of the two resistors R4 in a one-to-one correspondence.

5. The network optical fiber interface circuit of a distributed cascade multi-level converter system according to claim 3, characterized in that: The PECL to LVDS coupling circuit further includes a resistor R7, and the resistor R7 is connected between two differential signal terminals of the LVDS receiving port.

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