Display panel

Abstract

The utility model relates to a display panel. The display panel includes: a base substrate including a display area and an aperture area having an aperture defined in the aperture area; a light emitting element in the display area, and the light emitting element includes: a pixel electrode on the base substrate; a light emitting layer on the pixel electrode; and a common control layer on the pixel electrode; a heating wire surrounding the hole in the hole region; and a signal transmission line connected to the heating wire, and the signal transmission line is electrically insulated from the light emitting element. The common control layer is spaced apart from the heating wire.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0037563 filed in the Korean Intellectual Property Office on March 22, 2023, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0003] Aspects of embodiments of the present disclosure relate to a display panel and a method of manufacturing the display panel. More particularly, aspects of embodiments of the present disclosure relate to a display panel including a hole defined therethrough and a method of manufacturing the display panel. Background Art

[0004] Electronic devices that provide images to users (such as televisions, mobile phones, computers (e.g., tablet computers), navigation units, and gaming units) include display panels for generating and displaying images. In addition to the display panel, the electronic device also includes electronic modules such as cameras, optical sensors, etc.

[0005] In recent years, research has been ongoing on methods of reducing the bezel area to provide a wider display area to users. As an example, an electronic module may be disposed under a display panel, and a hole may be defined through the display panel to improve driving efficiency of the electronic module.

[0006] The above information disclosed in this Background section is for enhancement of understanding of the background of the present disclosure and therefore, the above information may contain information that does not constitute the prior art. Utility Model Content

[0007] One or more embodiments of the present disclosure relate to a display panel and a method of manufacturing the display panel, reducing damage that may be caused to components of the display panel and interrupting the continuity of a common layer disposed adjacent to a hole.

[0008] According to one or more embodiments of the present disclosure, a display panel includes: a base substrate including a display area and a hole area, the hole area having a hole defined in the hole area; a light emitting element in the display area, and the light emitting element includes: a pixel electrode on the base substrate; a light emitting layer on the pixel electrode; and a common control layer on the pixel electrode; a heating line surrounding the hole in the hole area; and a signal transmission line connected to the heating line, and the signal transmission line is electrically insulated from the light emitting element. The common control layer is spaced apart from the heating line.

[0009] In an embodiment, the heating line may have a line width smaller than a line width of the signal transmission line.

[0010] In an embodiment, the heating line may include at least one of molybdenum (Mo), copper (Cu), tungsten (W), gold (Au), silver (Ag), indium tin oxide (ITO), indium zinc oxide (IZO), and indium tin gallium oxide (ITGO).

[0011] In an embodiment, the heating line may include the same material as that of the pixel electrode.

[0012] In an embodiment, the heating line may include the same material as that of the signal transmission line.

[0013] In an embodiment, the heating wire may have a closed loop shape corresponding to an outer line of the hole.

[0014] In an embodiment, the common control layer may further include a protruding portion adjacent to an end portion of the common control layer facing the heating line.

[0015] In an embodiment, the signal transmission line may be positioned at the same layer as that of the pixel electrode.

[0016] In an embodiment, the signal transmission line may extend from the heating line via the display area, and the signal transmission line may be spaced apart from the pixel electrode in the display area.

[0017] In an embodiment, a portion of the signal transmission line may overlap the common control layer, and an end portion of the signal transmission line may not overlap the common control layer.

[0018] In an embodiment, the display panel may further include a pixel defining layer on the pixel electrode and defining a light emitting opening overlapping the pixel electrode. The signal transmission line may overlap the pixel defining layer, and the heating line may not overlap the pixel defining layer.

[0019] In an embodiment, the common control layer may include at least one of a hole control layer and an electron control layer on the light emitting layer.

[0020] In an embodiment, the display panel may further include a dam surrounding the hole in the hole region, and the heating line may be spaced apart from the dam.

[0021] In an embodiment, the dam may include: a first dam; and a second dam located closer to the hole than the first dam. The heating wire may be located between the first dam and the second dam in the hole region.

[0022] In an embodiment, the display panel may further include a blocking portion contacting a rear surface of the heating line, and the blocking portion may have a thermal conductivity lower than that of the heating line.

[0023] In an embodiment, the blocking portion may surround the hole corresponding to the position of the heating wire.

[0024] In an embodiment, the blocking portion may cover at least a portion of a side surface of the heating wire.

[0025] In an embodiment, the blocking portion may include titanium (Ti), lead (Pb), aluminum oxide (AlO x ), polyimide (PI), silicon oxide (SiO x ) and silicon nitride (SiN x ) at least one of.

[0026] According to one or more embodiments of the present disclosure, a method for manufacturing a display panel includes: providing a preliminary display panel, the preliminary display panel including: a pixel electrode in a display area; a heating line in a hole area; and a signal transmission line connected to the heating line; forming a preliminary common control layer on the pixel electrode and the heating line; applying a pulse voltage to the signal transmission line to generate heat in the heating line; and using the heat to remove a portion of the preliminary common control layer on the heating line to form a common control layer spaced apart from the heating line.

[0027] In an embodiment, the providing the preliminary display panel may include forming the pixel electrode, the heating line, and the signal transmission line simultaneously with each other through the same process.

[0028] According to one or more embodiments of the present disclosure, the display panel may include a heating line disposed in the hole region, and a portion of the common control layer formed on the heating line may be removed by heat generated in the heating line. Therefore, the continuity of the common control layer may be blocked in the hole region. Therefore, since no additional structure that blocks the continuity of the common control layer is required in the hole region, the margin in the hole region may be reduced, and the display area may be expanded.

[0029] According to one or more embodiments of the present disclosure, the heating line may be formed together with the pixel electrode through the same process, and thus, an additional process for forming the heating line may not be required. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The above and other aspects and features of the present disclosure will be more clearly understood from the following detailed description of illustrative, non-limiting embodiments with reference to the accompanying drawings, in which:

[0031] Figure 1 is a perspective view of an electronic device according to an embodiment of the present disclosure;

[0032] Figure 2 is an exploded perspective view of an electronic device according to an embodiment of the present disclosure;

[0033] Figure 3 is a plan view of a display panel according to an embodiment of the present disclosure;

[0034] Figure 4 is an enlarged plan view of a region of a portion of a display panel according to an embodiment of the present disclosure;

[0035] Figure 5A and Figure 5B It is along Figure 4 A cross-sectional view of the display panel taken along line II';

[0036] Fig. 6A and Figure 6B It is along Figure 4 A cross-sectional view of the display panel taken along line II';

[0037] Fig. 7A and Figure 7B is along Figure 4 A cross-sectional view of the display panel taken along line II-II';

[0038] Figure 8 is an enlarged plan view of a region of a portion of a display panel according to an embodiment of the present disclosure;

[0039] Fig. 9A and Fig. 9B is an enlarged plan view of a region of a portion of a display panel according to an embodiment of the present disclosure;

[0040] FIG. 10A to FIG. 10C is a plan view illustrating a method of manufacturing a display panel according to one or more embodiments of the present disclosure; and

[0041] FIG. 11A to FIG. 11D is a cross-sectional view illustrating a method of manufacturing a display panel according to one or more embodiments of the present disclosure. DETAILED DESCRIPTION

[0042] Hereinafter, embodiments will be described in more detail with reference to the accompanying drawings, wherein the same reference numerals always refer to the same elements. However, the present disclosure may be implemented in various different forms and should not be construed as being limited to the embodiments shown herein. On the contrary, these embodiments are provided as examples so that the present disclosure will be thorough and complete, and will fully convey the aspects and features of the present disclosure to those skilled in the art. Therefore, processes, elements and techniques that are not necessary for a complete understanding of the aspects and features of the present disclosure for those of ordinary skill in the art may not be described. Unless otherwise noted, throughout the drawings and descriptions, the same reference numerals represent the same elements, and therefore, their redundant descriptions may not be repeated.

[0043] When a certain embodiment can be implemented differently, the specific process order may be different from the described order. For example, two processes described successively may be performed simultaneously or substantially simultaneously, or may be performed in the reverse order of the described order.

[0044] In the accompanying drawings, for the sake of clarity, the relative size, thickness and ratio of elements, layers and zones may be exaggerated and / or simplified. For ease of explanation, spatial relative terms such as "under ... ", "under ... ", "under ... ", "above ... " and "on " may be used herein to describe the relationship between an element or feature and another element (multiple elements) or feature (multiple features) as shown in the figure. It will be understood that, in addition to the orientation depicted in the figure, spatial relative terms are intended to cover different orientations of the device in use or operation. For example, if the device in the figure is turned over, the element described as "under" or "under" or "below" other elements or features will then be oriented to "above" the other elements or features. Therefore, the example terms "under ... " and "under ... " can cover both above and below. The device can be oriented in addition (for example, rotated 90 degrees or at other orientations), and the spatial relative descriptors used in this article should be interpreted accordingly.

[0045] In the figure, the x-axis, y-axis and z-axis are not limited to the three axes of the rectangular coordinate system, and can be interpreted in a broader sense. For example, the x-axis, y-axis and z-axis can be perpendicular to each other or substantially perpendicular to each other, or can represent different directions that are not perpendicular to each other.

[0046] It will be understood that, although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the spirit and scope of the present disclosure, the first element, component, region, layer or part described below may be referred to as a second element, component, region, layer or part.

[0047] It will be understood that when an element or layer is referred to as being "on," "connected to," or "coupled to" another element or layer, the element or layer may be directly on, directly connected to, or directly coupled to the other element or layer, or there may be one or more intervening elements or layers. Similarly, when a layer, region, or element is referred to as being "electrically connected to" another layer, region, or element, the layer, region, or element may be directly electrically connected to the other layer, region, or element, and / or may be indirectly electrically connected via one or more intervening layers, regions, or elements therebetween. Furthermore, it will be understood that when an element or layer is referred to as being "between" two elements or layers, the element or layer may be the only element or layer between the two elements or layers, or there may also be one or more intervening elements or layers.

[0048] The terms used in this article are for the purpose of describing specific embodiments, and are not intended to limit the present disclosure. Unless the context clearly states otherwise, as used in this article, the singular "one" and "one (kind / person)" are intended to also include plural forms. It will also be understood that when used in this specification, the terms "include", "comprise", "contain", "contain", "have", "have" and "have" illustrate the existence of stated features, integers, steps, operations, elements and / or components, but do not exclude the existence or addition of one or more other features, integers, steps, operations, elements, components and / or their groups. As used in this article, the term "and / or" includes any combination and all combinations of one or more related listed items. For example, the statement "A and / or B" means A, B, or A and B. When a statement such as "at least one of ... " is placed after a column of elements, what is modified is the entire column of elements, rather than the individual elements in the column. For example, the expressions "at least one of a, b, and c" and "at least one selected from the group consisting of a, b, and c" mean only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

[0049] As used herein, the terms "substantially," "approximately," and similar terms are used as terms of approximation rather than terms of degree, and are intended to account for the inherent variation in measurements or calculations that one of ordinary skill in the art would recognize. Additionally, when describing embodiments of the present disclosure, the use of "may" refers to "one or more embodiments of the present disclosure." As used herein, the term "using" and variations thereof may be considered synonymous with the term "utilizing" and variations thereof, respectively.

[0050] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. It will also be understood that, unless expressly defined as such herein, terms (such as those defined in general dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and / or this specification, and should not be interpreted in an idealized or overly formal sense.

[0051] Figure 1 is a perspective view of an electronic device DD according to an embodiment of the present disclosure. Figure 2 is an exploded perspective view of an electronic device DD according to an embodiment of the present disclosure.

[0052] The electronic device DD can be activated in response to an electrical signal, and can display an image IM. The electronic device DD may include various embodiments for providing the image IM to the user. As an example, the electronic device DD may be applied to large electronic devices (such as televisions and outdoor billboards, etc.) and small and medium-sized electronic devices (such as monitors, mobile phones, computers (e.g., tablet computers), navigation units (e.g., navigation devices), and game units (e.g., game consoles), etc.). However, the present disclosure is not limited thereto, and the electronic device DD may be applied to other suitable electronic devices that display images. In the present embodiment, for convenience, a mobile phone is shown as a representative example of the electronic device DD.

[0053] Reference Figure 1 , when viewed in a plane (e.g., in a plan view), the electronic device DD may have a rectangular shape whose short sides extend in a first direction DR1 and whose long sides extend in a second direction DR2 that crosses (e.g., intersects) the first direction DR1. However, the shape of the electronic device DD is not limited to the rectangular shape, and the electronic device DD may have various suitable shapes such as other polygonal shapes, a circular shape, or an elliptical shape.

[0054] The electronic device DD may display an image IM through a display surface IS toward a third direction DR3, the third direction DR3 being perpendicular or substantially perpendicular to a plane defined by the first direction DR1 and the second direction DR2. A normal direction of the display surface IS may be parallel or substantially parallel to the third direction DR3. The display surface IS of the electronic device DD may correspond to a front surface of the electronic device DD. The image IM displayed by the electronic device DD may include a static image as well as a video. Figure 1 A clock window and application icons are illustrated as representative examples of the image IM.

[0055] The front (or upper) surface and the rear (or lower) surface of each component (e.g., each unit, layer, component, etc.) of the electronic device DD may be defined relative to the direction in which the image IM is displayed. The front surface and the rear surface may be opposite to each other in the third direction DR3, and the normal direction of each of the front surface and the rear surface may be parallel to or substantially parallel to the third direction DR3. The spacing distance between the front surface and the rear surface of each component in the third direction DR3 may correspond to the thickness of the component in the third direction DR3.

[0056] As used in the present disclosure, the expressions "when viewed in a plane" and "in a plan view" may refer to a state viewed in the third direction DR3. As used in the present disclosure, the expressions "when viewed in a cross section" and "in a cross-sectional view" may refer to a state viewed in the first direction DR1 or the second direction DR2. In addition, the directions indicated by the first direction DR1, the second direction DR2, and the third direction DR3 are relative to each other, and therefore, the directions indicated by the first direction DR1, the second direction DR2, and the third direction DR3 may be modified in various ways to other suitable directions.

[0057] The electronic device DD may be flexible. The term "flexible" as used herein refers to the property of being able to bend from a fully bent structure to a structure that is bent at a scale of a few nanometers. For example, the electronic device DD may be a curved electronic device or a foldable electronic device. However, the present disclosure is not limited thereto, and the electronic device DD may be rigid.

[0058] As a representative example, Figure 1 The electronic device DD including a flat display surface IS is illustrated. However, the shape of the display surface IS of the electronic device DD is not limited thereto or thereby, and the display surface IS may also include a curved surface bent from a flat surface.

[0059] The display surface IS of the electronic device DD may include a display portion AA-DD and a non-display portion NAA-DD. The display portion AA-DD may be a portion that displays an image IM within the front surface of the electronic device DD, and a user may view the image IM through the display portion AA-DD. In the present embodiment, a display portion AA-DD having a quadrilateral shape in a plane (e.g., in a plan view) is shown as a representative example, however, the display portion AA-DD may have various suitable shapes according to the desired design of the electronic device DD.

[0060] The non-display portion NAA-DD may be a portion within the front surface of the electronic device DD that does not display the image IM. The non-display portion NAA-DD may have a suitable color (e.g., a predetermined color) and may block light. The non-display portion NAA-DD may be disposed adjacent to the display portion AA-DD. As an example, the non-display portion NAA-DD may be disposed outside the display portion AA-DD and may surround the display portion AA-DD (e.g., surrounding the periphery of the display portion AA-DD), but the present disclosure is not limited thereto. The non-display portion NAA-DD may be defined as being adjacent to only one side of the display portion AA-DD, or may be defined in a side surface of the electronic device DD instead of the front surface. According to an embodiment, the non-display portion NAA-DD may be omitted as needed or desired.

[0061] According to an embodiment, the display portion AA-DD of the electronic device DD may include a sensing area SA-DD defined therein. The sensing area SA-DD may correspond to Figure 2 The electronic module EM (e.g., electronic component or sensor) EM overlaps the area. Figure 2 ) can receive a signal from the outside, or can provide a signal to the outside through the sensing area SA-DD. As a representative example, Figure 1 One sensing area SA-DD provided in the display part AA-DD is illustrated, however, the present disclosure is not limited thereto or thereby. According to an embodiment, the sensing area SA-DD may be provided in plural in the display part AA-DD.

[0062] According to an embodiment, the electronic device DD may sense an external input applied to the electronic device DD from the outside. The external input may include various suitable external inputs provided from the outside, such as pressure, temperature, and light, etc. The external input may include a proximity input (e.g., a hovering input) applied when an object or a part of a user's body (e.g., a finger) approaches the electronic device DD at a suitable distance (e.g., a predetermined distance) and a touch input (e.g., a touch of a user's hand or an object such as a pen).

[0063] Reference Figure 1 and Figure 2 , the electronic device DD may include a window WP and a housing HU. The window WP and the housing HU may be coupled (e.g., connected or attached) to each other to provide an exterior of the electronic device DD and to provide an interior space for accommodating components of the electronic device DD. The electronic device DD may include a display panel DP, an anti-reflection member ARP, and an electronic module EM disposed between the window WP and the housing HU.

[0064] The electronic module EM may be disposed below the display panel DP. The electronic module EM may be disposed to overlap the display panel DP. The electronic module EM may be an electronic component or a sensor that outputs or receives an optical signal. For example, the electronic module EM may include a camera module (e.g., a camera) that captures an image of an external object, a proximity sensor that uses an optical signal to identify an external object approaching it, or an infrared emission sensor that outputs an optical signal.

[0065] The display panel DP may display an image IM in response to an electrical signal. The display panel DP may be a light-emitting type display panel. For example, the display panel DP may be an organic light-emitting display panel, an inorganic light-emitting display panel, or a quantum dot light-emitting display panel. Hereinafter, for convenience, as a representative example of the display panel DP, an organic light-emitting display panel will be described in more detail.

[0066] The display panel DP may include a display area DA and a non-display area NDA defined as being adjacent to the display area DA. When viewed in a plane (e.g., in a plan view), the non-display area NDA may surround the display area DA (e.g., surround the periphery of the display area DA). The display area DA may display an image IM in response to an electrical signal. The non-display area NDA may not display the image IM. A driving circuit, a line, and a pad for driving a light emitting element disposed in the display area DA may be disposed in the non-display area NDA.

[0067] The display panel DP may include a hole area HA defined within the display area DA. The hole area HA may overlap with the sensing area SA-DD. The hole area HA may overlap with the electronic module EM. In the present disclosure, the expression "one area / portion overlaps with another area / portion" should not be interpreted as being limited to having the same size or the same shape as each other.

[0068] At least a portion of the hole area HA may be surrounded by the display area DA (e.g., its periphery is surrounded by the display area DA). The hole area HA may be completely surrounded by the display area DA (e.g., its periphery is completely surrounded by the display area DA), but the present disclosure is not limited thereto. According to an embodiment, a portion of the hole area HA may be in contact with the display area DA, and another portion of the hole area HA may be in contact with the non-display area NDA.

[0069] The hole HH may be defined to pass through (eg, may penetrate) the display panel DP in the hole area HA. ​​The hole HH may be formed to pass through at least a portion of a component of the display panel DP disposed in the hole area HA.

[0070] The electronic module EM may overlap the hole HH. At least a portion of the electronic module EM may be exposed to the outside through the hole HH. At least a portion of the electronic module EM may be inserted into the hole HH.

[0071] The anti-reflection member ARP may be disposed between the display panel DP and the window WP. The anti-reflection member ARP may reduce reflection of external light incident from outside the electronic device DD to the anti-reflection member ARP. In other words, the anti-reflection member ARP may reduce the reflectivity of the electronic device DD relative to external light. The anti-reflection member ARP may include a polarizer, a retarder, a destructive interference structure, or a plurality of color filters that reduce the reflectivity of the electronic device DD relative to external light.

[0072] The portion of the anti-reflection member ARP overlapping the hole area HA may have a relatively high light transmittance. As an example, the anti-reflection member ARP may include a transmissive portion overlapping the hole area HA. ​​However, the present disclosure is not limited thereto or thereby, and the anti-reflection member ARP may be provided with a through hole defined through the anti-reflection member ARP and overlapping the hole area HA.

[0073] The window WP may be disposed on the anti-reflection member ARP. The window WP may protect the display panel DP and the anti-reflection member ARP disposed under the window WP.

[0074] The window WP may include an optically transparent insulating material. As an example, the window WP may include glass, sapphire or a plastic material. The window WP may have a single-layer structure or a multi-layer structure. The window WP may also include a functional layer such as an anti-fingerprint layer, a phase control layer and / or a hard coating layer disposed on an optically transparent substrate.

[0075] The front surface FS of the window WP may correspond to the display surface IS of the electronic device DD. The front surface FS of the window WP may include a transmissive area TA and a bezel area BZA.

[0076] The transmission area TA of the window WP may be an optically transparent area. The transmission area TA of the window WP may correspond to the display portion AA-DD of the electronic device DD. The transmission area TA may overlap at least a portion of the display area DA of the display panel DP. The window WP may transmit the image IM provided from the display panel DP through the transmission area TA, and the user may view the image IM.

[0077] The transmission area TA of the window WP may overlap the hole area HA. ​​A portion of the transmission area TA overlapping the hole area HA may be defined as a sensing area SA. The sensing area SA may correspond to a sensing area SA-DD of the electronic device DD. The sensing area SA of the window WP may overlap the electronic module EM.

[0078] The sensing area SA overlapping the electronic module EM may be optically transparent and may have a relatively high light transmittance. Since the hole HH overlapping the electronic module EM is formed by removing components of the display panel DP, the electronic module EM may easily receive an optical signal incident to the electronic module EM from the outside through the sensing area SA and the hole HH, or may output the optical signal to the outside through the sensing area SA and the hole HH.

[0079] The frame area BZA of the window WP may be obtained by depositing, coating or printing a material having a suitable color (e.g., a predetermined color) on a transparent substrate. The frame area BZA may correspond to the non-display portion NAA-DD of the electronic device DD. The frame area BZA may overlap at least a portion of the non-display area NDA of the display panel DP. Because the frame area BZA of the window WP covers the non-display area NDA of the display panel DP, components of the display panel DP disposed in the non-display area NDA may be prevented or substantially prevented from being seen from the outside.

[0080] The housing HU may be disposed below the display panel DP. The housing HU may protect the display panel DP and the anti-reflection member ARP contained therein. The housing HU may prevent or substantially prevent foreign matter and / or moisture from entering the display panel DP and the anti-reflection member ARP. The housing HU may include a material having a relatively high strength, and may absorb an impact applied thereto from the outside of the housing HU. According to an embodiment, the housing HU may be provided in a form obtained by coupling a plurality of containing members to each other.

[0081] The electronic device DD may further include an input sensor disposed on the display panel DP. The input sensor may be disposed directly on the display panel DP and may be in contact with the display panel DP without a separate adhesive layer, but the present disclosure is not limited thereto or thereby. In some embodiments, the input sensor may be coupled to the display panel DP via an adhesive layer. The input sensor may obtain coordinate information of an external input applied thereto from outside the electronic device DD. The input sensor may be driven in various suitable ways such as a capacitive method, a resistive method, an infrared method, or a pressure method, but is not particularly limited thereto.

[0082] Figure 3 is a plan view of a display panel DP according to an embodiment of the present disclosure. Figure 3Components of the display panel DP when viewed in a plane (eg, in a plan view) are schematically illustrated.

[0083] Reference Figure 3 The display panel DP may include a base substrate SUB, pixels PX, a plurality of signal lines SL1 to SLm, DL1 to DLn, EL1 to ELm, CSL1, CSL2 and PL electrically connected to the pixels PX, a scan driver SDV, a data driver DDV, an emission driver EDV and a plurality of pads PD.

[0084] The base substrate SUB may provide a base surface of the display panel DP on which elements and lines are disposed. The base substrate SUB may include a display area DA and a non-display area NDA corresponding to the display area DA and the non-display area NDA of the display panel DP, respectively. As a representative example, Figure 3 The base substrate SUB is illustrated as having a rectangular shape parallel to or substantially parallel to each of the first direction DR1 and the second direction DR2 when viewed in a plane (e.g., in a plan view), but the shape of the base substrate SUB is not limited thereto or thereby. Figure 1 )'s desired design, the base substrate SUB can be manufactured in various suitable shapes.

[0085] The base substrate SUB may include a hole area HA, and at least a portion of the hole area HA may be surrounded by the display area DA (e.g., its periphery is surrounded by the display area DA). The pixel PX may be spaced apart from the hole area HA and may be disposed in the display area DA. The hole HH may be defined as passing through (e.g., may penetrate) the display panel DP in the hole area HA. ​​The hole HH may be formed to pass through the base substrate SUB. Due to the hole HH, the hole area HA may have a relatively higher transmittance than the transmittance of the display area DA in which the pixel PX is disposed.

[0086] Some of the signal lines SL1 to SLm, DL1 to DLn, EL1 to ELm, CSL1, CSL2, and PL may extend in the display area DA via the hole area HA. ​​Therefore, some of the signal lines may include a curve extending along the boundary of the hole HH, but are not limited thereto or thereby. According to an embodiment, a separate bridge pattern distinguished from the signal line arranged adjacent to the hole area HA may be provided in the hole area HA, and the bridge pattern may be electrically connected to the signal line. The signal lines SL1 to SLm, DL1 to DLn, EL1 to ELm, CSL1, CSL2, and PL may pass through the hole area HA in various suitable ways and are not particularly limited.

[0087] Since some of the signal lines SL1 to SLm, DL1 to DLn, EL1 to ELm, CSL1, CSL2, and PL extend through the hole area HA and transmit electrical signals, the pixels PX spaced apart from each other due to the hole HH interposed therebetween may be electrically connected to each other. In other words, the electrical signal may be supplied to the entire display area DA without being interrupted by the hole HH.

[0088] Each of the pixels PX may include a pixel driving circuit including a plurality of transistors (e.g., a switching transistor and / or a driving transistor, etc.) and at least one capacitor, and a light emitting element connected to the pixel driving circuit. Each of the pixels PX may be arranged in the display area DA and may emit light in response to an electrical signal applied thereto.

[0089] Each of the scan driver SDV, the data driver DDV, and the emission driver EDV may be disposed in the non-display area NDA of the display panel DP, but the present disclosure is not limited thereto. According to an embodiment, at least one of the scan driver SDV, the data driver DDV, and the emission driver EDV may be disposed to overlap with the display area DA, and thus, the size of the non-display area NDA may be reduced.

[0090] The data driver DDV may be manufactured in the form of an integrated circuit chip defined as a driving chip and may be mounted in the non-display area NDA of the display panel DP, but the present disclosure is not limited thereto. According to an embodiment, the data driver DDV may be mounted on a separate flexible circuit board connected to the display panel DP.

[0091] The signal lines SL1 to SLm, DL1 to DLn, EL1 to ELm, CSL1, CSL2, and PL may include a plurality of scan lines SL1 to SLm, a plurality of data lines DL1 to DLn, a plurality of emission lines EL1 to ELm, first and second control lines CSL1 and CSL2, and a power line PL. Here, each of "m" and "n" is a natural number greater than 0.

[0092] The scan lines SL1 to SLm may extend in a first direction DR1 or a direction opposite to the first direction DR1 and may be connected to a scan driver SDV. The data lines DL1 to DLn may extend in a second direction DR2 or a direction opposite to the second direction DR2 and may be electrically connected to a data driver DDV. The emission lines EL1 to ELm may extend in the first direction DR1 and may be electrically connected to an emission driver EDV.

[0093] The power line PL may extend in the second direction DR2 and may be disposed in the non-display area NDA. The power line PL may be electrically connected to the pixel PX via a connection line connected to the pixel PX and may apply a voltage (eg, a predetermined voltage) to the pixel PX.

[0094] The first control line CSL1 may be electrically connected to the scan driver SDV. The second control line CSL2 may be connected to the emission driver EDV.

[0095] The pad PD may be disposed adjacent to the lower end of the non-display area NDA. The pad PD may be disposed closer to the lower end of the display panel DP than the data driver DDV (e.g., compared to the data driver DDV). The pad PD may be arranged along the first direction DR1. The pad PD may be connected to a circuit board including a timing controller for controlling operations of the scan driver SDV, the data driver DDV, and the emission driver EDV, and a voltage generator for generating voltages.

[0096] Each of the pads PD may be connected to a corresponding signal line among the signal lines SL1 to SLm, DL1 to DLn, EL1 to ELm, CSL1, CSL2, and PL. As an example, the data lines DL1 to DLn, the power line PL, and the first and second control lines CSL1 and CSL2 may be electrically connected to the pads PD.

[0097] The scan driver SDV may generate a plurality of scan signals in response to the scan control signal. The scan signals may be applied to the pixels PX via the scan lines SL1 to SLm. The data driver DDV may generate a plurality of data voltages corresponding to the image signals in response to the data control signal. The data voltages may be applied to the pixels PX via the data lines DL1 to DLn. The emission driver EDV may generate a plurality of emission signals in response to the emission control signal. The emission signals may be applied to the pixels PX via the emission lines EL1 to ELm.

[0098] The pixel PX may receive a data voltage in response to a scan signal. The pixel PX may emit light having a brightness corresponding to the data voltage in response to an emission signal, and thus, an image may be displayed. The emission time of the pixel PX may be controlled by the emission signal. Therefore, the display panel DP may display an image through the display area DA using the pixel PX.

[0099] Figure 4 is an enlarged plan view of a region of a portion of the display panel DP according to an embodiment of the present disclosure. Figure 4 Components of the display panel DP corresponding to the display area DA including the hole area HA and the non-display area NDA adjacent to the display area DA are schematically illustrated.

[0100] Reference Figure 4, the display panel DP may include at least one dam DM1 and DM2 disposed in the hole area HA. ​​As a representative example, Figure 4 A plurality of dams DM1 and DM2 disposed in the hole area HA are illustrated. The dams DM1 and DM2 may include a first dam DM1 and a second dam DM2. However, the number of dams DM1 and DM2 disposed in the hole area HA is not particularly limited thereto.

[0101] The first dam DM1 and the second dam DM2 may be disposed to be spaced apart from each other. The first dam DM1 may be disposed closer to the display area DA in which the pixels PX are arranged than the second dam DM2. The second dam DM2 may be disposed closer to the hole HH than the first dam DM1. In other words, the second dam DM2 may be disposed between the first dam DM1 and the hole HH.

[0102] When viewed in a plane (e.g., in a plan view), the first dam DM1 and the second dam DM2 may be disposed to surround the hole HH (e.g., around the periphery of the hole HH). The first dam DM1 and the second dam DM2 may have a closed loop shape. The first dam DM1 and the second dam DM2 may have a shape corresponding to the outer line of the hole HH. As an example, when viewed in a plane (e.g., in a plan view), the hole HH may have a circular shape, and each of the first dam DM1 and the second dam DM2 may have a ring shape, but the present disclosure is not limited thereto or thereby.

[0103] The first dam DM1 and the second dam DM2 may protrude in the thickness direction (eg, the third direction DR3) of the display panel DP. The first dam DM1 and the second dam DM2 may define an organic layer MN (eg, see FIG. 5 ) in which an encapsulation layer TFE described in more detail below is formed. Figure 5A ) area, and the continuity of the organic layer MN can be blocked in the hole area HA.

[0104] The hole HH may be defined in the hole area HA. Figure 4 A structure in which one hole HH is defined in the hole area HA is illustrated, but the present disclosure is not limited thereto or thereby, and the hole HH may be provided in plural in one hole area HA. ​​According to an embodiment, the hole area HA may be provided in plural, the hole areas HA may be spaced apart from each other in the display area DA, and the hole HH may be defined in each of the hole areas HA.

[0105] The display panel DP may include heating lines HTL and signal transmission lines STL connected to the heating lines HTL.

[0106] The heating line HTL may be disposed adjacent to the hole HH. As an example, when viewed in a plane (eg, in a plan view), the heating line HTL may be disposed between the first dam DM1 and the second dam DM2. However, the position of the heating line HTL is not particularly limited as long as the heating line HTL is disposed adjacent to the hole HH around the hole HH.

[0107] When viewed in a plane (e.g., in a plan view), the heating wire HTL may surround the hole HH (e.g., around the periphery of the hole HH). The heating wire HTL may have a closed loop shape to surround the hole HH (e.g., around the periphery of the hole HH). The heating wire HTL may have a shape corresponding to the outer line of the hole HH. As an example, when viewed in a plane (e.g., in a plan view), the hole HH may have a circular shape, and the heating wire HTL may have a ring shape, but the present disclosure is not limited thereto.

[0108] The signal transmission line STL may extend from the heating line HTL. The signal transmission line STL may be provided integrally with the heating line HTL. The signal transmission line STL may be provided in plurality, and the signal transmission line STL may be connected to the same heating line HTL. As an example, the signal transmission line STL may be connected to the left and right sides of the heating line HTL, respectively.

[0109] The signal transmission line STL may extend from the heating line HTL to the outside of the non-display area NDA. As an example, the signal transmission line STL may extend from the hole area HA to the non-display area NDA via the display area DA. In the display area DA, the signal transmission line STL may be disposed to be spaced apart from the pixel PX. The signal transmission line STL may be electrically insulated from the pixel PX and may not exert an influence on the driving of the pixel PX.

[0110] exist Figure 4 In the embodiment, the signal transmission line STL extends parallel to or substantially parallel to one direction, but the shape of the signal transmission line STL is not particularly limited as long as the signal transmission line STL extends to be spaced apart from the pixel PX in the display area DA. As an example, the signal transmission line STL may include a bent portion that is disposed to be spaced apart from the pixel PX when viewed in a plane (e.g., in a plan view).

[0111] In the manufacturing process of the display panel DP, the heating line HTL may be used to remove the common control layer EL (eg, see Figure 5A In other words, the heating line HTL may be formed in the hole area HA to be connected to the common control layer EL (eg, referring to Figure 5A ) corresponds to the removed area.

[0112] The heating line HTL may have a suitable wiring resistance (e.g., a predetermined wiring resistance), and when current flows through the heating line HTL, heat may be generated by the wiring resistance. Due to the heat generated from the heating line HTL, the common control layer EL (e.g., referring to FIG. 1 ) may be removed from an area corresponding to an area in which the heating line HTL is disposed. Figure 5A ). Therefore, the common control layer EL can be blocked in the hole area HA (for example, refer to Figure 5A Since the continuity of the common control layer EL is blocked in the hole area HA, foreign matter, moisture and / or oxygen from outside the hole HH can be prevented or substantially prevented from entering the display area DA via the common control layer EL.

[0113] The signal transmission line STL may receive a voltage from the outside and may supply a voltage to the heating line HTL so that current flows through the heating line HTL and generates heat. Fig. 11B ) is electrically connected to the power supply device, so a point to which the power supply device is connected can be provided by extending the signal transmission line STL from the heating line HTL to the area in which the common control layer EL is not deposited. In other words, a portion of the signal transmission line STL may be spaced apart from the common control layer EL and may be exposed to the outside in the non-display area NDA, and therefore, the signal transmission line STL may be electrically connected to the power supply device via its exposed portion.

[0114] Each of the heating line HTL and the signal transmission line STL may include a conductive material. Each of the heating line HTL and the signal transmission line STL may include a suitable material that may be formed in a wiring form.

[0115] The heating line HTL and the signal transmission line STL may have the same material as each other. The heating line HTL and the signal transmission line STL may be formed simultaneously or substantially simultaneously with each other through the same process, but the present disclosure is not limited thereto or thereby. According to an embodiment, the heating line HTL and the signal transmission line STL may include materials different from each other. As an example, the heating line HTL may include a material having a wiring resistance higher than that of the signal transmission line STL.

[0116] The heating line HTL may include a material having high thermal conductivity and a high melting point. As an example, the heating line HTL may include: a metal material such as molybdenum (Mo), copper (Cu), tungsten (W), gold (Au) or silver (Ag); or a metal oxide such as indium tin oxide (ITO), indium zinc oxide (IZO) or indium tin gallium oxide (ITGO). Because the heating line HTL includes a material having high thermal conductivity, heat can be easily transferred to the common control layer EL in the process of removing the common control layer EL. In addition, because the heating line HTL includes a material having a high melting point, the heating line HTL will not be damaged even if the temperature rises due to heat. There is no particular limitation on the material included in the heating line HTL, as long as the material can be manufactured as a wiring and can generate heat (e.g., a predetermined heat) by an electric current.

[0117] The heating line HTL and the signal transmission line STL may have line widths different from each other. The line widths of the heating line HTL and the signal transmission line STL may be controlled to generate a wiring resistance difference between the heating line HTL and the signal transmission line STL. Although the heating line HTL and the signal transmission line STL receive the same voltage, high heat may be selectively generated in the heating line HTL by using the wiring resistance difference.

[0118] The heating line HTL may have a first line width W1, and the signal transmission line STL may have a second line width W2 greater than the first line width W1. As an example, the second line width W2 may be twice the first line width W1, however, the present disclosure is not limited thereto or thereby.

[0119] The first line width W1 may have a size of about several micrometers. As an example, the first line width W1 may be equal to or less than about 10 micrometers (μm). However, the size of the first line width W1 is not limited thereto or thereby as long as the first line width W1 generates heat due to wiring resistance.

[0120] The second line width W2 of the signal transmission line STL may be equal to or less than the distance between the pixel electrodes included in the pixel PX. As an example, the second line width W2 may be equal to or less than about 20 micrometers (μm). However, the second line width W2 of the signal transmission line STL is not limited thereto or thereby, as long as the signal transmission line STL has a line width greater than that of the heating line HTL and is disposed to be spaced apart from the pixel electrode.

[0121] Because the heating line HTL has a first line width W1 smaller than the second line width W2 of the signal transmission line STL, heat required to remove the common control layer EL can be generated in response to current supplied thereto from the signal transmission line STL. Because the signal transmission line STL has a second line width W2 larger than the first line width W1 of the heating line HTL, the wiring resistance of the signal transmission line STL can be relatively low, and current can be easily transferred to the heating line HTL.

[0122] Figure 5A and Figure 5B It is along Figure 4 A cross-sectional view of the display panel DP taken along line II'. Figure 5A and Figure 5B Descriptions that are redundant with the above description may not be repeated.

[0123] Reference Figure 5A The display panel DP may include a base substrate SUB, a transistor TR, a light emitting element OL, a plurality of insulating layers 10 to 40 (eg, 10, 20, 30, and 40), a pixel defining layer PDL, and an encapsulation layer TFE. The transistor TR and the light emitting element OL electrically connected to the transistor TR may form a pixel PX (eg, referring to Figure 4 ).

[0124] The base substrate SUB may be a rigid substrate, however, the present disclosure is not limited thereto. According to an embodiment, the base substrate SUB may be a foldable, rollable or bendable flexible substrate. The base substrate SUB may include a glass substrate, a metal substrate, a polymer substrate or an organic / inorganic composite material substrate. The base substrate SUB may include a synthetic resin layer. As an example, the synthetic resin layer may include at least one of acrylic resin, methacrylic resin, polyisoprene resin, vinyl resin, epoxy resin, urethane resin, cellulose resin, siloxane resin, polyamide resin, perylene resin and polyimide resin. However, the materials that can be used for the base substrate SUB are not limited thereto or are not limited thereby.

[0125] The transistor TR and the insulating layers 10 to 40 may be disposed on the base substrate SUB. The transistor TR and the insulating layers 10 to 40 may be formed by forming an insulating layer, a semiconductor layer, and a conductive layer on the base substrate SUB by a coating or deposition process; and selectively patterning the insulating layer, the semiconductor layer, and the conductive layer by several photolithography processes.

[0126] The insulating layers 10 to 40 may include a first insulating layer 10, a second insulating layer 20, a third insulating layer 30, and a fourth insulating layer 40. The first insulating layer 10 to the fourth insulating layer 40 may include an inorganic layer or an organic layer. As an example, the inorganic layer may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. The organic layer may include a phenolic polymer, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluorine polymer, a paraxylene polymer, a vinyl alcohol polymer, or a suitable blend thereof. However, the materials used for the first insulating layer 10 to the fourth insulating layer 40 are not limited thereto or thereby. The structure of the insulating layer stacked on the base substrate SUB is not limited thereto or thereby.

[0127] The transistor TR may include a semiconductor pattern SP and a gate electrode GE. The semiconductor pattern SP may be disposed on a base substrate SUB. According to an embodiment, a buffer layer may be further disposed between the semiconductor pattern SP and the base substrate SUB, and a bonding force between the semiconductor pattern SP and the base substrate SUB may be improved by the buffer layer.

[0128] The semiconductor pattern SP may include a silicon semiconductor. As an example, the semiconductor pattern SP may include a crystalline silicon semiconductor, a polycrystalline silicon semiconductor, or an amorphous silicon semiconductor, but the present disclosure is not limited thereto. The semiconductor pattern SP may include an oxide semiconductor. The semiconductor pattern SP may include various suitable materials as long as the semiconductor pattern SP has semiconductor properties, and is therefore not particularly limited.

[0129] The semiconductor pattern SP may include a source region Sa, a drain region Da, and a channel region Aa. The semiconductor pattern SP may include a plurality of regions distinguished from each other according to conductivity. As an example, the semiconductor pattern SP may have different electrical properties depending on whether it is doped, whether it is doped with an N-type dopant or a P-type dopant, or whether the metal oxide is reduced. A portion of the semiconductor pattern SP having a relatively high conductivity may be used as an electrode or a signal line, and may correspond to the source region Sa and / or the drain region Da of the transistor TR. A non-doped portion or a non-reduced portion having a relatively low conductivity may correspond to the channel region Aa (or active region) of the transistor TR.

[0130] The first insulating layer 10 may be disposed on the base substrate SUB and may cover the semiconductor pattern SP of the transistor TR. The first insulating layer 10 may include an inorganic layer having a single-layer structure or a multi-layer structure.

[0131] The gate electrode GE may be disposed on the first insulating layer 10. When viewed in a plane (eg, in a plan view), the gate electrode GE may overlap the channel region Aa. The gate electrode GE may be used as a mask in a process of doping the semiconductor pattern SP.

[0132] The second insulating layer 20 may be disposed on the first insulating layer 10 and may cover the gate electrode GE. The second insulating layer 20 may include an inorganic layer having a single-layer structure or a multi-layer structure.

[0133] The source electrode SE and the drain electrode DE may be disposed on the second insulating layer 20. The source electrode SE may be connected to the source region Sa of the semiconductor pattern SP via a contact hole defined by passing through (e.g., penetrating) the first insulating layer 10 and the second insulating layer 20. The drain electrode DE may be connected to the drain region Da of the semiconductor pattern SP via a contact hole defined by passing through (e.g., penetrating) the first insulating layer 10 and the second insulating layer 20. The source electrode SE and the drain electrode DE may be disposed on the second insulating layer 20 to be spaced apart from each other.

[0134] The third insulating layer 30 may be disposed on the second insulating layer 20 and may cover the source electrode SE and the drain electrode DE. The fourth insulating layer 40 may be disposed on the third insulating layer 30.

[0135] According to an embodiment, the fourth insulating layer 40 may include an organic layer. The fourth insulating layer 40 including the organic layer may cover particles present on the surface of the third insulating layer 30 and / or step differences between components disposed thereunder, and may provide a flat or substantially flat surface. In addition, the fourth insulating layer 40 may relieve stress between components disposed thereunder and thereon.

[0136] The light emitting element OL may be disposed in the display area DA. The light emitting element OL may be disposed on the fourth insulating layer 40. The light emitting element OL may include an organic light emitting element, a quantum dot light emitting element, a micro LED light emitting element, or a nano LED light emitting element. According to the embodiment, the light emitting element OL may include various suitable embodiments as long as light is generated and / or the amount of light is controlled according to an electrical signal.

[0137] The light emitting element OL may include a pixel electrode AE, a light emitting layer EML, a common control layer EL, and a common electrode CE. According to an embodiment, the pixel electrode AE ​​may be an anode electrode, and the common electrode CE may be a cathode electrode.

[0138] The pixel electrode AE ​​may be disposed on the fourth insulating layer 40. The pixel electrode AE ​​may be electrically connected to the drain electrode DE via a contact hole defined by passing through (e.g., penetrating) the third insulating layer 30 and the fourth insulating layer 40. In some embodiments, a connection electrode may be further disposed between the light emitting element OL and the drain electrode DE, and the light emitting element OL may be electrically connected to the drain electrode DE through the connection electrode.

[0139] The pixel defining layer PDL may be disposed on the fourth insulating layer 40. The pixel defining layer PDL may be provided with a light emitting opening PO defined therethrough to expose at least a portion of the pixel electrode AE. The portion of the pixel electrode AE ​​exposed through the light emitting opening PO may correspond to a light emitting region.

[0140] The pixel defining layer PDL may include a polymer resin. As an example, the pixel defining layer PDL may include a polyacrylate resin or a polyimide resin. The pixel defining layer PDL may include an inorganic material, or may include an inorganic material in addition to the polymer resin. As an example, the pixel defining layer PDL may include silicon nitride (SiN x ), silicon oxide (SiO x ) or silicon oxynitride (SiO x N y ).

[0141] The pixel defining layer PDL may include a light absorbing material. The pixel defining layer PDL may include a black colorant. The black colorant may include a black pigment or a black dye. The black colorant may include a metal material such as chromium, a metal oxide, or carbon black. However, the pixel defining layer PDL is not limited thereto or thereby.

[0142] The light emitting layer EML may be disposed on the pixel electrode AE. The light emitting layer EML may be disposed in a region corresponding to the light emitting opening PO. In other words, the light emitting opening PO may be provided in plurality, the plurality of light emitting openings PO may be spaced apart from each other in the pixel defining layer PDL, and the pixel PX (e.g., referring to Figure 4 ) may be provided to each of the light emitting openings PO in the form of light emitting patterns spaced apart (eg, separated) from each other when viewed in a plane (eg, in a plan view). However, the light emitting layer EML is not limited thereto or thereby.

[0143] The light emitting layer EML may provide light having a desired color (eg, a predetermined color). The light emitting layer EML may emit light having at least one of red, green, and blue, but the present disclosure is not limited thereto. The light emitting layer EML may generate white light by a combination of light emitting materials that generate red, green, and blue, respectively.

[0144] The light-emitting layer EML may include an organic light-emitting material and / or an inorganic light-emitting material. For example, the light-emitting layer EML may include a fluorescent material, a phosphorescent material, an organic metal complex light-emitting material, or a quantum dot. The light-emitting layer EML may have a multilayer structure. As an example, the light-emitting layer EML may include a main light-emitting layer and an auxiliary light-emitting layer disposed on the main light-emitting layer. The main light-emitting layer and the auxiliary light-emitting layer may have different thicknesses from each other according to the wavelength of light emitted from the light-emitting layer EML, and the resonance distance of the light-emitting element OL may be controlled by providing an auxiliary light-emitting layer. In addition, since an auxiliary light-emitting layer may be provided, the color purity of the light emitted from the light-emitting layer EML may be improved.

[0145] The common control layer EL may be disposed between the pixel electrode AE ​​and the common electrode CE adjacent to the light emitting layer EML. As a representative example, Figure 5A A structure in which a common control layer EL is disposed between the light emitting layer EML and the common electrode CE is illustrated, but the present disclosure is not limited thereto or thereby. According to an embodiment, the common control layer EL may be disposed between the pixel electrode AE ​​and the light emitting layer EML, or the common control layer EL may be provided in plurality to be disposed above and below the light emitting layer EML. As an example, the common control layer EL may include at least one of a hole control layer and an electron control layer.

[0146] The common control layer EL may be spread over the pixels PX (eg, see Figure 4 ) are commonly arranged. The common control layer EL may be arranged on the upper surface of the pixel defining layer PDL. The common control layer EL may extend from the display area DA and may be arranged in the hole area HA. ​​The continuity of the common control layer EL may be blocked in the area in which the heating line HTL is arranged. As an example, the heating line HTL may be arranged in the hole area HA, and the common control layer EL may be arranged to be spaced apart from the heating line HTL in the hole area HA. ​​Therefore, the continuity of the common control layer EL may be blocked in the hole area HA. ​​Because the continuity of the common control layer EL is blocked, foreign matter, moisture and oxygen from the outside of the hole HH may be prevented or substantially prevented from entering the display area DA through the common control layer EL.

[0147] The common electrode CE may be disposed on the light emitting layer EML. The common electrode CE may be commonly disposed throughout the pixels PX to provide a common voltage. The common electrode CE may extend from the display area DA and may be disposed to overlap the hole area HA.

[0148] The first voltage may be applied to the pixel electrode AE ​​via the transistor TR, and the common voltage may be applied to the common electrode CE via a signal line for applying the common voltage. The holes and electrons injected into the light emitting layer EML may be recombined with each other to generate excitons, and when the excitons return from an excited state to a ground state, the light emitting element OL may emit light through the display area DA.

[0149] Each of the pixel electrode AE ​​and the common electrode CE may be a transmissive electrode, a transflective electrode or a reflective electrode. The transmissive electrode may include a transparent metal oxide, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (ITZO), etc. The transflective electrode or the reflective electrode may include silver (Ag), magnesium (Mg), copper (Cu), aluminum (Al), platinum (Pt), palladium (Pd), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), ytterbium (Yb), tungsten (W), a suitable compound thereof, or a suitable mixture thereof (e.g., AgMg, AgYb or MgYb).

[0150] The encapsulation layer TFE may be disposed on the light emitting element OL and may encapsulate the light emitting element OL. The encapsulation layer TFE may include at least one insulating layer. The encapsulation layer TFE may include a plurality of inorganic layers IOL1 and IOL2 and at least one organic layer MN disposed between the inorganic layers IOL1 and IOL2. The first inorganic layer IOL1 may be disposed on the common electrode CE. The organic layer MN and the second inorganic layer IOL2 may be sequentially disposed on the first inorganic layer IOL1.

[0151] The first inorganic layer IOL1 and the second inorganic layer IOL2 may protect the light emitting element OL from moisture and / or oxygen. The first inorganic layer IOL1 and the second inorganic layer IOL2 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. However, the materials used for the first inorganic layer IOL1 and the second inorganic layer IOL2 are not limited thereto or thereby.

[0152] The organic layer MN may protect the light emitting element OL from foreign substances such as dust particles. The organic layer MN may include an acrylic resin, but the present disclosure is not limited thereto.

[0153] The hole HH may be defined by components of the display panel DP disposed in the hole area HA. ​​The hole HH may be defined by the base substrate SUB, the insulating layers 10 to 40 disposed on the base substrate SUB, the common control layer EL, and the inorganic layers IOL1 and IOL2.

[0154] The first dam DM1 and the second dam DM2 may be disposed between the hole HH and the display area DA in the hole area HA. ​​Each of the first dam DM1 and the second dam DM2 may have a multi-layer structure. As an example, each of the first dam DM1 and the second dam DM2 may include dam portions L1, L2, and L3 stacked in the third direction DR3. As a representative example, Figure 5A A structure in which each of the first dam DM1 and the second dam DM2 includes a first dam portion L1, a second dam portion L2, and a third dam portion L3 is illustrated However, the stack structure of the first dam DM1 and the second dam DM2 is not limited thereto or thereby.

[0155] The first dam portion L1 may be disposed on the third insulating layer 30. In a process of forming the fourth insulating layer 40, the first dam portion L1 may be formed simultaneously or substantially simultaneously with the fourth insulating layer 40. The first dam portion L1 may include the same material as that of the fourth insulating layer 40, but the present disclosure is not limited thereto or thereby.

[0156] The second dam portion L2 may be disposed on the first dam portion L1. In the process of forming the pixel defining layer PDL, the second dam portion L2 may be formed simultaneously or substantially simultaneously with the pixel defining layer PDL. The second dam portion L2 may include the same material as that of the pixel defining layer PDL, but the present disclosure is not limited thereto or thereby.

[0157] The third dam portion L3 may be disposed on the second dam portion L2. The third dam portion L3 may be formed by depositing an additional layer after forming the pixel defining layer PDL, but the present disclosure is not limited thereto or thereby. According to an embodiment, the third dam portion L3 may include the same material as that of the second dam portion L2, and the second dam portion L2 and the third dam portion L3 may be formed simultaneously or substantially simultaneously with each other, but the present disclosure is not limited thereto or thereby.

[0158] The first dam DM1 and the second dam DM2 may have the same or substantially the same height as each other in the third direction DR3 , but the present disclosure is not limited thereto or thereby. According to an embodiment, the first dam DM1 and the second dam DM2 may have different heights from each other.

[0159] The organic layer MN of the encapsulation layer TFE may extend from the display area DA to the hole area HA, and the area in which the organic layer MN is formed may be defined by at least one of the first dam DM1 and the second dam DM2. At least one of the first dam DM1 and the second dam DM2 may be spaced apart from the organic layer MN. As an example, from among the dams DM1 and DM2, the second dam DM2 disposed relatively adjacent to the hole HH (e.g., relatively closer to the hole HH) may be spaced apart from the organic layer MN.

[0160] The organic layer MN may be formed by curing a liquid organic resin, and the dams DM1 and DM2 may prevent or substantially prevent the liquid organic resin from flowing through the hole area HA. ​​The dams DM1 and DM2 may block the continuity of the organic layer MN in the hole area HA. ​​Since the continuity of the organic layer MN is blocked, a path through which external contaminants may enter the display area DA from the hole area HA may be blocked (e.g., may be easily blocked).

[0161] The organic layer MN may be formed to be spaced apart from the hole HH by the dams DM1 and DM2. Therefore, a cross section of the organic layer MN may not be exposed through the hole HH, and thus, moisture and / or oxygen introduced through the hole HH may be prevented or substantially prevented from flowing into the organic layer MN. As a result, moisture and / or oxygen may be prevented or substantially prevented from entering the organic layer MN through the hole HH, and thus moisture and / or oxygen may be prevented from entering the light emitting element OL disposed in the display area DA. Thus, the reliability of the display panel DP may be improved.

[0162] The first inorganic layer IOL1 and the second inorganic layer IOL2 of the encapsulation layer TFE may extend from the display area DA to the hole area HA. ​​The first inorganic layer IOL1 and the second inorganic layer IOL2 may cover the dams DM1 and DM2 and may contact each other on the dams DM1 and DM2. Therefore, the first inorganic layer IOL1 and the second inorganic layer IOL2 in the hole area HA may encapsulate the organic layer MN disposed between the first inorganic layer IOL1 and the second inorganic layer IOL2.

[0163] The heating line HTL may be disposed on the third insulating layer 30. The heating line HTL may be disposed on the third insulating layer 30 between the first dam DM1 and the second dam DM2. The heating line HTL may be spaced apart from the fourth insulating layer 40 and the dams DM1 and DM2. However, the position of the heating line HTL is not particularly limited thereto as long as the heating line HTL is disposed adjacent to the hole HH and the upper surface of the heating line HTL is exposed without being covered by the insulating layer.

[0164] The continuity of the common control layer EL may be blocked by the heating line HTL. The area from which the common control layer EL is removed may correspond to the area in which the heating line HTL is disposed. The common control layer EL may be sublimated or evaporated by the heat generated by the heating line HTL and may be removed. Therefore, the common control layer EL may include portions spaced apart from each other in the hole area HA due to the heating line HTL interposed therebetween. The common electrode CE, the first inorganic layer IOL1, and the second inorganic layer IOL2 may be disposed on the heating line HTL that is not covered by the common control layer EL and is exposed.

[0165] The heating line HTL may be formed simultaneously or substantially simultaneously with the pixel electrode AE ​​in the process of forming the pixel electrode AE. The heating line HTL may include the same material as that of the pixel electrode AE. The heating line HTL may have a stacking structure that is the same as or substantially the same as that of the pixel electrode AE. As an example, the pixel electrode AE ​​may have a three-layer structure of ITO / Ag / ITO, and the heating line HTL may have the same three-layer structure. Since the heating line HTL may be formed in the process of forming the pixel electrode AE, an additional process for forming the heating line HTL may be omitted.

[0166] However, the present disclosure is not limited thereto or thereby, and the heating line HTL may be formed by a process separate from the process of the pixel electrode AE. Because the heating line HTL may be formed by a process separate from the process of the pixel electrode AE, the heating line HTL may be formed of a conductive material different from the conductive material of the pixel electrode AE. In other words, because the heating line HTL may be formed by a separate process, the heating line HTL may be designed to include one or more materials suitable for removing the common control layer EL, and the material used for the heating line HTL may not be specifically limited.

[0167] Reference Figure 5B , in some embodiments, the common control layer EL may further include a protrusion PR. The protrusion PR may be formed adjacent to the inner surface of the common control layer EL adjacent to the heating line HTL. The protrusion PR may be disposed adjacent to one end of the common control layer EL facing the heating line HTL. In a process of removing a portion of the common control layer EL by heat generated by the heating line HTL, the material for the common control layer EL may be squeezed out from the heating line HTL, and therefore, the protrusion PR may be formed adjacent to the removed portion of the common control layer EL. The thickness of the common control layer EL in which the protrusion PR is formed may be greater than the thickness of the common control layer EL in which the protrusion PR is not formed.

[0168] In some embodiments, the display panel DP may further include a structure in the hole area HA to block the continuity of the common control layer EL. As an example, the display panel DP may have an undercut structure, a reverse tapered structure, or a groove structure defined in the hole area HA, and thus, the display panel DP may block the continuity of the common control layer EL using the heating line HTL.

[0169] Fig. 6A and Figure 6B It is along Figure 4 A cross-sectional view of the display panel DP taken along line II' of FIG. Fig. 6A and Figure 6B Redundant description of elements shown in FIG. 1 that are identical or substantially identical to those described above.

[0170] Reference Fig. 6A In some embodiments, the display panel DP may further include a blocking portion BP disposed below the heating line HTL. When viewed in a plane (e.g., in a plan view), the blocking portion BP may have a shape corresponding to the shape of the heating line HTL. The blocking portion BP may be in contact with a rear surface (or bottom surface) of the heating line HTL. The blocking portion BP may be formed by a separate deposition process before forming the heating line HTL.

[0171] The blocking portion BP may include a suitable material having a lower thermal conductivity than the heating line HTL. For example, the blocking portion BP may include a material such as titanium (Ti), lead (Pb), or aluminum oxide (AlO). x ), an inorganic material such as polyimide (PI), or an organic material such as silicon oxide (SiO x ) or silicon nitride (SiN x ) of inorganic materials.

[0172] The blocking portion BP may be disposed under the heating line HTL, and when the heating line HTL generates heat, the heat generated by the heating line HTL may be reduced from being transferred to other components of the display panel DP except for a portion of the common control layer EL to be removed. In other words, the blocking portion BP may prevent or substantially prevent the display panel DP from being damaged due to the heat generated by the heating line HTL, and may protect the display panel DP.

[0173] The side surface of the heating line HTL may be exposed without being covered by the blocking portion BP. As an example, the side surface of the blocking portion BP may be aligned with the side surface of the heating line HTL, but the present disclosure is not limited thereto or thereby.

[0174] Reference Figure 6B In some embodiments, the blocking portion BPa may cover the rear surface of the heating line HTL and at least a portion of the side surface of the heating line HTL. The blocking portion BPa may be in contact with the rear surface and the side surface of the heating line HTL. Fig. 6A ) and the structure of BPa are not particularly limited as long as a portion of the common control layer EL is removed by the heating line HTL and the display panel DP is protected.

[0175] Fig. 7A and Figure 7B It is along Figure 4 A cross-sectional view of the display panel DP taken along line II-II'. Fig. 7A and Figure 7B Redundant description of elements shown in FIG. 1 that are identical or substantially identical to those described above.

[0176] Reference Fig. 7A and Figure 7B In some embodiments, the display panel DP may further include at least one dam DM3 or DM4 disposed in the non-display area NDA. Fig. 7A and Figure 7B The third dam DM3 and the fourth dam DM4 provided in the non-display area NDA are illustrated.

[0177] The third and fourth dams DM3 and DM4 may be disposed outside the display area DA. As an example, when viewed in a plane (eg, in a plan view), the third and fourth dams DM3 and DM4 may be disposed to surround the display area DA (eg, to surround the periphery of the display area DA).

[0178] Each of the third dam DM3 and the fourth dam DM4 may have the same shape as the first dam DM1 (eg, refer to Figure 5A The third dam DM3 and the fourth dam DM4 may be formed by the same stack structure as the first dam DM1 (eg, referring to Figure 5A ) is formed by the same process as the process of the present invention, but the present disclosure is not limited thereto or thereby.

[0179] Reference Figure 4 , Fig. 7A and Figure 7B The signal transmission line STL may be connected to the heating line HTL and may extend to the non-display area NDA via the display area DA. One end of the signal transmission line STL may be disposed in the non-display area NDA.

[0180] Unlike the heating line HTL which is exposed without being covered by the fourth insulating layer 40 and the pixel defining layer PDL, at least a portion of the signal transmission line STL may overlap with the fourth insulating layer 40 and the pixel defining layer PDL. Because the common control layer EL is removed from the region corresponding to the heating line HTL, the heating line HTL may not overlap with the common control layer EL, but a portion of the signal transmission line STL may overlap with the common control layer EL.

[0181] The end of the signal transmission line STL may not overlap with the common control layer EL. In other words, the end of the signal transmission line STL may not overlap with the common control layer EL and may be exposed in the process of depositing the common control layer EL without being covered by the common control layer EL. Because the end of the signal transmission line STL is exposed without being covered by the common control layer EL, a point to which a power supply device is connected may be provided so that the heating line HTL generates heat.

[0182] like Fig. 7A As shown in FIG. 1 , in some embodiments, the signal transmission line STL may be disposed on the third insulating layer 30. The signal transmission line STL may be formed by contacting the pixel electrode AE ​​(eg, referring to FIG. 1 ). Figure 5A ) is formed by a process different from the process of forming the pixel electrode AE. The signal transmission line STL may be disposed at a layer different from the layer of the pixel electrode AE ​​(for example, disposed in a layer different from the layer of the pixel electrode AE ​​or disposed on a layer different from the layer of the pixel electrode AE). When the heating line HTL is formed by a process different from the process of forming the pixel electrode AE, the signal transmission line STL formed simultaneously or substantially simultaneously with the heating line HTL may also be formed by a process different from the process of forming the pixel electrode AE. However, the present disclosure is not limited thereto or thereby, as long as the signal transmission line STL is connected to the heating line HTL.

[0183] Reference Figure 7B In some embodiments, the signal transmission line STL can be connected to the pixel electrode AE ​​(for example, referring to Figure 5A ) are formed simultaneously or substantially simultaneously. The signal transmission line STL may be disposed at the same layer as the layer of the pixel electrode AE ​​(e.g., disposed in the same layer as the layer of the pixel electrode AE ​​or disposed on the same layer as the layer of the pixel electrode AE). As an example, the signal transmission line STL may be disposed on the fourth insulating layer 40. The heating line HTL is formed by contacting with the pixel electrode AE ​​(e.g., referring to Figure 5A ), the signal transmission line STL formed simultaneously or substantially simultaneously with the heating line HTL may also be formed together with the pixel electrode AE ​​by the same process. However, the present disclosure is not limited thereto or thereby, as long as the signal transmission line STL is connected to the heating line HTL.

[0184] Some of the dam portions included in the third dam DM3 and the fourth dam DM4 may be formed simultaneously or substantially simultaneously in the same process as the process of forming the fourth insulating layer 40. In this case, the signal transmission line STL may extend to the end of the non-display area NDA via an area between the dam portions included in the third dam DM3 and the fourth dam DM4, but the present disclosure is not limited thereto.

[0185] Figure 8 is an enlarged plan view of a region of a portion of the display panel DP according to an embodiment of the present disclosure. Figure 8 Some of the components of the display panel DP in the hole area HA are schematically illustrated and may not be repeated. Figure 8 Redundant description of elements that are identical or substantially identical to those described above.

[0186] Reference Figure 8, the display panel DP may include a plurality of heating lines HTL1 and HTL2. As an example, the heating lines HTL1 and HTL2 may include a first heating line HTL1 and a second heating line HTL2. However, the number of heating lines HTL1 and HTL2 provided in the display panel DP is not limited thereto or thereby.

[0187] Each of the first heating line HTL1 and the second heating line HTL2 may be disposed in the hole area HA. ​​As an example, when viewed in a plane (e.g., in a plan view), the first heating line HTL1 and the second heating line HTL2 may be disposed between the first dam DM1 and the second dam DM2. The first heating line HTL1 may be disposed closer to the second dam DM2 than the second heating line HTL2 (e.g., compared to the second heating line HTL2). In other words, the first heating line HTL1 may be disposed between the second dam DM2 and the second heating line HTL2. However, the positions of the first heating line HTL1 and the second heating line HTL2 are not particularly limited as long as the first heating line HTL1 and the second heating line HTL2 are arranged around the hole HH.

[0188] The first heating wire HTL1 and the second heating wire HTL2 may surround the hole HH (e.g., around the periphery of the hole HH). The first heating wire HTL1 and the second heating wire HTL2 may have a closed loop shape surrounding the hole HH (e.g., around the periphery of the hole HH). The first heating wire HTL1 and the second heating wire HTL2 may have a shape corresponding to the outer line of the hole HH. As an example, when viewed in a plane (e.g., in a plan view), the hole HH may have a circular shape, and each of the first heating wire HTL1 and the second heating wire HTL2 may have a torus shape, but the present disclosure is not limited thereto or thereby. According to an embodiment, the first heating wire HTL1 and the second heating wire HTL2 may have closed loop shapes different from each other, or the first heating wire HTL1 and the second heating wire HTL2 may have a shape different from the shape of the outer line of the hole HH.

[0189] The signal transmission line STL may extend from the first heating line HTL1 and the second heating line HTL2. The first heating line HTL1 and the second heating line HTL2 may be connected to the same signal transmission line STL, but the present disclosure is not limited thereto or thereby. According to an embodiment, the signal transmission line STL connected to the first heating line HTL1 and the signal transmission line STL connected to the second heating line HTL2 may be distinguished from each other.

[0190] The first heating line HTL1 and the second heating line HTL2 may include a suitable material having high thermal conductivity and a high melting point. As an example, the first heating line HTL1 and the second heating line HTL2 may include: a metal material such as molybdenum (Mo), copper (Cu), tungsten (W), gold (Au) or silver (Ag); or a metal oxide such as indium tin oxide (ITO), indium zinc oxide (IZO) or indium tin gallium oxide (ITGO).

[0191] The first heating line HTL1 and the second heating line HTL2 may include the same conductive material as each other. The first heating line HTL1 and the second heating line HTL2 may be formed simultaneously or substantially simultaneously with each other through the same process, but the present disclosure is not limited thereto or thereby. According to an embodiment, the first heating line HTL1 and the second heating line HTL2 may include different conductive materials from each other.

[0192] The first heating line HTL1 and the second heating line HTL2 may have the same or substantially the same line width as each other, but the present disclosure is not limited thereto or thereby. According to an embodiment, the first heating line HTL1 and the second heating line HTL2 may have different line lengths from each other, and by considering the line length difference between the first heating line HTL1 and the second heating line HTL2, the line width of the first heating line HTL1 and the line width of the second heating line HTL2 may be designed to be different from each other.

[0193] Each of the first heating line HTL1 and the second heating line HTL2 may have a line width smaller than that of the signal transmission line STL. The line width of each of the heating lines HTL1 and HTL2 and the signal transmission line STL may be variously adjusted as needed or desired to generate a wiring resistance difference between the heating lines HTL1 and HTL2 and the signal transmission line STL.

[0194] The signal transmission line STL may have a wiring resistance smaller than that of the heating lines HTL1 and HTL2, and the signal transmission line STL may apply (e.g., may easily apply) current to the heating lines HTL1 and HTL2. The wiring resistance of each of the heating lines HTL1 and HTL2 may be greater than that of the signal transmission line STL, and each of the heating lines HTL1 and HTL2 may generate a signal for removing the common control layer EL (e.g., referring to FIG. 1 ) in response to the current applied thereto from the signal transmission line STL. Figure 5A )’s heat.

[0195] Fig. 9A and Fig. 9B is an enlarged plan view of a region of a portion of the display panel DP according to an embodiment of the present disclosure. Fig. 9A and Fig. 9B The components of the display panel DP in the hole area HA are schematically illustrated and may not be repeated. Fig. 9A and Fig. 9B Redundant description of elements shown in FIG. 1 that are identical or substantially identical to those described above.

[0196] Fig. 9A and Fig. 9B A structure in which one first dam DM1 is disposed in the hole area HA is illustrated, but the present disclosure is not limited thereto or thereby, and a plurality of dams may be disposed in the hole area HA.

[0197] Reference Fig. 9A The heating line HTLa may be disposed closer to the hole HH in the hole area HA than the first dam DM1 (eg, compared to the first dam DM1). The position of the heating line HTLa is not particularly limited as long as the heating line HTLa is disposed adjacent to and around the hole HH.

[0198] The heating wire HTLa may surround the hole HH (e.g., around the periphery of the hole HH). The heating wire HTLa may have a closed loop shape surrounding the hole HH (e.g., around the periphery of the hole HH). The heating wire HTLa may have a suitable shape different from the shape of the outer line corresponding to the hole HH. As an example, when viewed in a plane (e.g., in a plan view), the hole HH may have a circular shape, and the heating wire HTLa may have a quadrilateral ring shape. The shape of the heating wire HTLa is not particularly limited as long as the heating wire HTLa has a closed loop shape surrounding the hole HH (e.g., around the periphery of the hole HH).

[0199] When viewed from a plane (e.g., a plan view), the signal transmission line STL may include a bent portion. As an example, the signal transmission line STL may include a portion extending in a first direction DR1 and a portion extending in a second direction DR2. The signal transmission line STL may have a line width sufficient to apply current, and therefore, current may be applied to the heating line HTLa without heat being concentrated at the bent portion. The shape of the signal transmission line STL in a plane (e.g., in a plan view) is not particularly limited as long as the signal transmission line STL is connected to the heating line HTLa.

[0200] The shape of the hole defined in the display panel DP may be variously modified as needed or desired. Fig. 9B In some embodiments, the hole HH-1 may have an elliptical shape, but the present disclosure is not limited thereto. According to an embodiment, the hole HH-1 may have a polygonal shape such as a quadrilateral shape. However, the shape of the hole HH-1 is not particularly limited as long as the hole HH-1 is defined to pass through the display panel DP.

[0201] The heating wire HTLb may have a shape that is the same as or substantially the same as the shape of the outer line corresponding to the hole HH-1. As an example, when viewed in a plane (e.g., in a plan view), the hole HH-1 may have an elliptical shape, and the heating wire HTLb may have an elliptical ring shape. However, the present disclosure is not limited to or thereby, and when the hole HH-1 has a quadrilateral shape when viewed in a plane (e.g., in a plan view), the heating wire HTLb may have a quadrilateral ring shape surrounding the hole HH-1 (e.g., surrounding the periphery of the hole HH-1).

[0202] A method for manufacturing a display panel according to one or more embodiments of the present disclosure may include: a process for providing a preliminary display panel including pixel electrodes, heating lines and signal transmission lines; a process for forming a preliminary common control layer on the preliminary display panel; a process for applying a pulse voltage to the signal transmission line to generate heat in the heating line; and a process for removing the preliminary common control layer (for example, a portion of the preliminary common control layer) disposed on the heating line using the heat generated from the heating line to form a common control layer.

[0203] According to an embodiment, the pixel electrodes, the heating lines, and the signal transmission lines disposed on the preliminary display panel may be formed simultaneously or substantially simultaneously with each other through the same process. FIG. 10A to FIG. 10C This is described in more detail.

[0204] FIG. 10A to FIG. 10C is a plan view illustrating a method of manufacturing a display panel according to one or more embodiments of the present disclosure. FIG. 10A to FIG. 10C FIG. 1 illustrates a plan view of a preliminary display panel DP-P during various processes of a method for manufacturing the display panel.

[0205] Fig. 10A The figure shows the process of forming pixel electrodes AE1, AE2 and AE3 (for example, referring to Fig. 10B )Preliminary display panel DP-P before. Fig. 10A , preliminary dams DM1-P and DM2-P may be provided in the hole area HA. ​​The preliminary dams DM1-P and DM2-P may correspond to the dams DM1 and DM2 (for example, referring to Figure 5A As an example, the preliminary dams DM1-P and DM2-P may correspond to the first dam portion L1 (eg, referring to Figure 5A ).

[0206] Fig. 10A The diagram shows the formation of holes HH in the hole area HA (for example, see Figure 4 ) before the preliminary display panel DP-P. The encapsulation layer TFE (for example, referring to Figure 5A) and remove the encapsulation layer TFE and the portion of the preliminary display panel DP-P in the hole area HA to form the hole HH.

[0207] The fourth insulating layer 40 may be disposed on the preliminary display panel DP-P. The fourth insulating layer 40 may provide a substrate on which the pixel electrodes AE1, AE2, and AE3 (eg, referring to Fig. 10B ) of the substrate surface. The fourth insulating layer 40 may be disposed entirely throughout the display area DA. The fourth insulating layer 40 may be disposed in at least a portion of the non-display area NDA. As an example, an end portion of the fourth insulating layer 40 may be disposed in the non-display area NDA.

[0208] The fourth insulating layer 40 may be spaced apart from the hole area HA. ​​Therefore, at least a portion of the upper surface of the third insulating layer 30 disposed below the fourth insulating layer 40 in the hole area HA may be exposed without being covered by the fourth insulating layer 40. Since the fourth insulating layer 40 including the organic layer is disposed to be spaced apart from the hole area HA, moisture may be prevented or substantially prevented from entering through the hole HH formed by a subsequent process.

[0209] Reference Fig. 10B , pixel electrodes AE1, AE2, and AE3 may be formed on the fourth insulating layer 40 of the preliminary display panel DP-P. The pixel electrodes AE1, AE2, and AE3 may be formed by depositing and patterning a conductive layer. The pixel electrodes AE1, AE2, and AE3 may correspond to the above-mentioned light emitting elements OL (e.g., referring to Figure 5A ) of the pixel electrode AE ​​(for example, refer to Figure 5A ).

[0210] The pixel electrodes AE1, AE2, and AE3 may be spaced apart from each other on the fourth insulating layer 40. The regions in which the pixel electrodes AE1, AE2, and AE3 are disposed may correspond to regions in which the pixels PX (eg, referring to Figure 4 ) area.

[0211] The pixel electrodes AE1, AE2, and AE3 may include a first pixel electrode AE1, a second pixel electrode AE2, and a third pixel electrode AE3. The first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3 may be a configuration of light-emitting elements that emit light of different colors from each other. As an example, the first pixel electrode AE1 may be a pixel electrode of a light-emitting element for emitting a first color light, the second pixel electrode AE2 may be a pixel electrode of a light-emitting element for emitting a second color light different from the first color light, and the third pixel electrode AE3 may be a pixel electrode of a light-emitting element for emitting a third color light different from the first color light and the second color light.

[0212] The first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3 may have sizes different from each other. Among the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3, the first pixel electrode AE1 may have the largest size. The sizes of the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3 may be designed by considering the size of the light emitting area and the color of the light emitted from the light emitting area, but the present disclosure is not limited thereto or thereby. In an embodiment, the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3 may have the same or substantially the same size as each other.

[0213] The heating line HTL and the signal transmission line STL may be formed by the same process as the pixel electrodes AE1, AE2 and AE3. As an example, the heating line HTL, the signal transmission line STL and the pixel electrodes AE1, AE2 and AE3 may be formed by patterning the same conductive layer. Therefore, the heating line HTL and the signal transmission line STL may be disposed at the same layer as the pixel electrodes AE1, AE2 and AE3 (for example, disposed in the same layer as the pixel electrodes AE1, AE2 and AE3 or disposed on the same layer as the pixel electrodes AE1, AE2 and AE3). The heating line HTL and the signal transmission line STL may include the same material as the pixel electrodes AE1, AE2 and AE3, however, the present disclosure is not limited thereto or thereby. According to an embodiment, the heating line HTL and the signal transmission line STL may be formed by a process different from the process of forming the pixel electrodes AE1, AE2 and AE3. As an example, after the heating line HTL and the signal transmission line STL are formed on the third insulating layer 30, the pixel electrodes AE1, AE2 and AE3 may be formed on the fourth insulating layer 40.

[0214] The heating line HTL may be disposed in the hole area HA. ​​As an example, the heating line HTL may be disposed between the preliminary dams DM1-P and DM2-P in the hole area HA. ​​The heating line HTL may be spaced apart from the fourth insulating layer 40. The heating line HTL may have a closed loop shape. A hole HH to be formed in a subsequent process may be formed in an inner region of the heating line HTL (for example, refer to Figure 4 ).

[0215] The signal transmission line STL may extend from the heating line HTL to the outside of the display area DA. An end of the signal transmission line STL may be exposed without being covered by the fourth insulating layer 40. A portion of the signal transmission line STL extending through the display area DA may overlap the fourth insulating layer 40.

[0216] The signal transmission line STL may be disposed between the pixel electrodes AE1, AE2, and AE3 in the display area DA. In other words, the signal transmission line STL may be spaced apart from the pixel electrodes AE1, AE2, and AE3 in the display area DA. The signal transmission line STL may be designed to have a line width equal to or less than the distance between the pixel electrodes AE1, AE2, and AE3. Therefore, the signal transmission line STL may be electrically insulated from the pixel electrodes AE1, AE2, and AE3.

[0217] The signal transmission line STL may include a bent portion. Since the signal transmission line STL is formed between the pixel electrodes AE1, AE2, and AE3, the signal transmission line STL may include a bent portion according to the shape and arrangement of the pixel electrodes AE1, AE2, and AE3. Even if the signal transmission line STL includes a bent portion, since the signal transmission line STL has a line width sufficient to apply current, current may be applied to the heating line HTL without heat being concentrated at the bent portion.

[0218] Reference Fig. 10C , a pixel defining layer PDL may be formed on the preliminary display panel DP-P on which the pixel electrodes AE1, AE2, and AE3 are formed. The pixel defining layer PDL may be disposed on the fourth insulating layer 40 (eg, referring to Fig. 10B )superior.

[0219] The pixel defining layer PDL may be provided with a plurality of light emitting openings P-O1, P-O2, and P-O3 defined therethrough. The light emitting openings P-O1, P-O2, and P-O3 may be formed to penetrate the pixel defining layer PDL. The light emitting openings P-O1, P-O2, and P-O3 may correspond to the light emitting openings PO described above (e.g., referring to Figure 5A ).

[0220] The light emitting openings P-O1, P-O2, and P-O3 may overlap the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3, respectively. At least a portion of each of the pixel electrodes AE1, AE2, and AE3 may be exposed through a corresponding opening of the light emitting openings P-O1, P-O2, and P-O3 overlapping therewith. The portions of the pixel electrodes AE1, AE2, and AE3 exposed through the light emitting openings P-O1, P-O2, and P-O3 may be defined as light emitting regions.

[0221] The light emitting openings P-O1, P-O2, and P-O3 may have various suitable opening sizes according to the sizes of the pixel electrodes AE1, AE2, and AE3. As an example, among the light emitting openings P-O1, P-O2, and P-O3, the first light emitting opening P-O1 overlapping the first pixel electrode AE1 having the largest size may have the largest opening size.

[0222] The pixel defining layer PDL may be spaced apart from the hole area HA. ​​Therefore, the heating line HTL may be exposed without being covered by the pixel defining layer PDL. Therefore, a preliminary common control layer EL-P (eg, referring to Fig. 11B ) may be in contact with the heating line HTL in the hole area HA and may receive heat from the heating line HTL.

[0223] The end of the signal transmission line STL may be exposed without being covered by the pixel definition layer PDL. The end of the signal transmission line STL may be exposed without being covered by the fourth insulating layer 40 (eg, referring to Fig. 10B ) and the end covered by the pixel defining layer PDL may provide a point to which the power supply device is connected, and a voltage may be applied to the heating line HTL through this point. The end of the signal transmission line STL may not overlap with the pixel defining layer PDL, but the portion of the signal transmission line STL extending through the display area DA may overlap with the pixel defining layer PDL.

[0224] The manufacturing method of the display panel according to one or more embodiments of the present disclosure may include a process of forming a common control layer spaced apart from the heating line from the preliminary common control layer. The common control layer may be formed by generating heat in the heating line to remove a portion of the preliminary common control layer formed on the pixel electrode and the heating line corresponding to the heating line. FIG. 11A to FIG. 11D This is described in more detail.

[0225] FIG. 11A to FIG. 11D is a cross-sectional view illustrating a method of manufacturing a display panel according to one or more embodiments of the present disclosure. FIG. 11A to FIG. 11D The diagrams illustrate cross sections of the preliminary display panel DP-P during various processes of the method for manufacturing the display panel.

[0226] Fig.11A The diagram shows the deposition of a preliminary common control layer EL-P (eg, Fig. 11B ) to form a common control layer EL (for example, refer to Fig.11D ) process. Fig. 11B A preliminary display panel DP-P is illustrated on which a preliminary common control layer EL-P is deposited.

[0227] Reference Fig.11A and Fig. 11B , a deposition material EL-M may be deposited on the preliminary display panel DP-P on which the pixel electrode AE ​​and the heating line HTL are formed to form a preliminary common control layer EL-P. The preliminary common control layer EL-P may be disposed on the pixel electrode AE, the light emitting layer EML, and the pixel defining layer PDL.

[0228] The preliminary common control layer EL-P may be disposed in the hole area HA. ​​The preliminary common control layer EL-P may be disposed between the dams DM1 and DM2 and may contact the heating line HTL. A voltage may be applied to the heating line HTL to generate heat, and thus a portion of the preliminary common control layer EL-P contacting the heating line HTL may be removed.

[0229] Fig. 11C The process of applying voltage to the signal transmission line STL is shown in the figure. The end of the signal transmission line STL may be spaced apart from the fourth insulating layer 40, the pixel defining layer PDL, and the preliminary common control layer EL-P. The end of the signal transmission line STL may be exposed to the outside. The power supply device VD may be provided on the end of the signal transmission line STL, and may apply voltage to the signal transmission line STL.

[0230] A pulse voltage may be applied to the signal transmission line STL. An instantaneous pulse voltage of about 10 microseconds to about 100 microseconds may be applied to the signal transmission line STL. The signal transmission line STL may transmit a voltage to a heating line HTL (e.g., referring to Fig.11D As a result, heat may be generated in the heating line HTL due to wiring resistance. The heating line HTL may have a line width smaller than that of the signal transmission line STL, and thus, sufficient heat may be generated in the heating line HTL to selectively remove the preliminary common control layer EL-P.

[0231] Since the voltage is directly applied to the signal transmission line STL to generate heat in the heating line HTL, the voltage can be prevented or substantially prevented from affecting other conductors in the preliminary display panel DP-P. In the case where the heating line HTL is heated by an induction current method rather than a pulse voltage application method, current may flow through other conductors or lines in the preliminary display panel DP-P. However, according to an embodiment of the present disclosure, since the voltage is directly applied to the signal transmission line STL without using an induction current method, the voltage can be applied to the heating line HTL without affecting other conductors or lines in the preliminary display panel DP-P. In addition, the signal transmission line STL and the heating line HTL can be connected to the pixel PX (for example, refer to Figure 4 ) are electrically insulated, and therefore, the signal transmission line STL and the heating line HTL may not affect the electrical characteristics of the pixel PX.

[0232] By applying a voltage to the signal transmission line STL, heat can be generated in the heating line HTL. The heating line HTL can generate enough heat to sublimate or evaporate the preliminary common control layer EL-P. In the case where the preliminary common control layer EL-P to be removed is spaced apart (e.g., separated) from the heating line HTL as a heat source and an additional layer is interposed between the common control layer EL-P and the heating line HTL, the heating line HTL may be required to generate more heat. However, according to one or more embodiments of the present disclosure, the preliminary common control layer EL-P may be in contact with the heating line HTL, and therefore, the portion of the preliminary common control layer EL-P in contact with the heating line HTL can be effectively removed by the heat generated from the heating line HTL.

[0233] Fig.11D The diagram shows the initial public control layer EL-P (for example, see Fig. 11C ) is a process for forming the common control layer EL. Due to the heat generated in the heating line HTL, a portion of the preliminary common control layer EL-P corresponding to the area where the heating line HTL is disposed may sublime or evaporate. Therefore, the continuity of the common control layer EL may be blocked in the area where the heating line HTL is disposed. In other words, the continuity of the common control layer EL may be blocked in the hole area HA. ​​Because the continuity of the common control layer EL is blocked, the heat from the hole HH (for example, referring to Figure 4 ) External foreign matter, moisture and / or oxygen enter the display area DA through the common control layer EL.

[0234] According to one or more embodiments of the present disclosure, the continuity of the common control layer EL can be blocked using a heating line HTL disposed in the hole area HA. ​​Therefore, the process of blocking the continuity of the common control layer EL using an expensive laser process can be omitted in the manufacturing method of the display panel, and thus the process cost can be reduced. In addition, because a portion of the preliminary common control layer EL-P is removed using the heating line HTL, a structure (such as an undercut structure, a reverse tapered spacer, or a groove structure) that can be used to block the continuity of the common control layer EL can be omitted. Therefore, the margin of the hole area HA can be reduced, and the display area DA can be increased.

[0235] The foregoing is an explanation of some embodiments of the present disclosure and should not be interpreted as limiting it. Although some embodiments have been described, it will be readily understood by those skilled in the art that various modifications may be made in the embodiments without departing from the spirit and scope of the present disclosure. It will be understood that, unless otherwise described, the description of the features or aspects in each embodiment should generally be considered to be applicable to other similar features or aspects in other embodiments. Therefore, as is apparent to those of ordinary skill in the art, unless otherwise specifically stated, the features, characteristics and / or elements described in conjunction with a particular embodiment may be used alone or in combination with the features, characteristics and / or elements described in conjunction with other embodiments. Therefore, it is to be understood that the foregoing is an explanation of various example embodiments and should not be interpreted as being limited to the specific embodiments disclosed herein, and various modifications to the disclosed embodiments and other example embodiments are intended to be included in the spirit and scope of the present disclosure as defined in the appended claims and their equivalents.

Claims

1. A display panel, It is characterized in that The display panel comprises: a base substrate including a display region and an aperture region having apertures defined therein; a light emitting element in the display area, wherein the light emitting element comprises: A pixel electrode, on the base substrate; a light-emitting layer, on the pixel electrode; and A common control layer, on the pixel electrode; a heating wire surrounding the hole in the hole region; and a signal transmission line connected to the heating line, and the signal transmission line is electrically insulated from the light emitting element, Wherein, the common control layer is spaced apart from the heating line.

2. The display panel according to claim 1, It is characterized in that The heating line has a line width smaller than a line width of the signal transmission line.

3. The display panel according to claim 1, It is characterized in that The heating wire has a closed loop shape corresponding to an outer line of the hole.

4. The display panel according to claim 1, It is characterized in that The common control layer further includes a protruding portion adjacent to an end portion of the common control layer facing the heating line.

5. The display panel according to claim 1, It is characterized in that The signal transmission line is positioned at the same layer as that of the pixel electrode.

6. The display panel according to claim 1, It is characterized in that The signal transmission line extends from the heating line through the display area, and the signal transmission line is spaced apart from the pixel electrode in the display area.

7. The display panel according to claim 1, It is characterized in that A portion of the signal transmission line overlaps the common control layer, and an end portion of the signal transmission line does not overlap the common control layer.

8. The display panel according to claim 1, It is characterized in that The display panel further comprises a dam surrounding the hole in the hole region, Wherein, the heating line is spaced apart from the dam.

9. The display panel according to claim 8, It is characterized in that The dam comprises: First Dam; and a second dam positioned closer to the hole than the first dam, and Wherein the heating wire is positioned between the first dam and the second dam in the hole area.

10. The display panel according to claim 1, It is characterized in that The display panel further includes a blocking portion contacting a rear surface of the heating line, wherein the blocking portion has a thermal conductivity lower than a thermal conductivity of the heating line.

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