Display panel

Abstract

A display panel is provided. The display panel includes an opening area in a plan view, a display area surrounding at least a portion of the opening area, and an intermediate area between the opening area and the display area; a light emitting diode disposed on the substrate in the display area and including a pixel electrode, a counter electrode, and an intermediate layer; a support layer disposed on the substrate in the intermediate region; an organic insulating layer disposed on the substrate and the support layer, and having a recess corresponding to the support layer; a metal layer disposed on the organic insulating layer and having a protruding tip; and a cap layer including a first cap portion covering an upper surface and a side surface of the metal layer and a second cap portion disposed in the groove. The functional layer extends to the intermediate region and includes a dummy functional layer. The display panel includes a display area having an area for arranging various types of components, and has improved reliability.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0039081 filed on March 24, 2023, and Korean Patent Application No. 10-2023-0050895 filed on April 18, 2023, in the Korean Intellectual Property Office (KIPO), the entire contents of which are incorporated herein by reference. Technical Field

[0002] Embodiments relate to a display panel. Background Art

[0003] Recently, the use of display panels has been diversified. Display panels have become thinner and lighter, and the range of use of display panels has expanded.

[0004] As the area occupied by the display region in the display panel has increased, various functions connected to or related to the display panel have been added. As a method of increasing the display region and adding various functions, research has been conducted to arrange various components in a portion of the display region. Utility Model Content

[0005] The purpose of the present invention is to provide a display panel including a display area having an area for arranging various types of components, the display panel having improved reliability. However, this purpose is only an example and does not limit the scope of the disclosure.

[0006] Additional aspects will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the disclosed embodiments.

[0007] According to an embodiment, the display panel may include: an opening area in a plan view, a display area surrounding at least a portion of the opening area, and an intermediate area between the opening area and the display area; a light emitting diode arranged on a substrate in the display area and including a pixel electrode, a counter electrode, and an intermediate layer arranged between the pixel electrode and the counter electrode and including a functional layer and an emission layer; a support layer arranged on the substrate in the intermediate area; an organic insulating layer arranged on the substrate and the support layer and having a groove corresponding to the support layer; a metal layer arranged on the organic insulating layer and having a protruding tip protruding toward the groove; and a cover layer including a first cover portion covering an upper surface and a side surface of the metal layer and a second cover portion arranged in the groove. The functional layer may extend to the intermediate area and may include a dummy functional layer arranged on the second cover portion.

[0008] The organic insulating layer may cover at least a portion of the support layer.

[0009] The first cover portion and the second cover portion may be spaced apart from each other.

[0010] A first distance from the upper surface of the substrate to an edge of the second cover portion may be greater than a second distance from the upper surface of the substrate to an edge of the dummy functional layer.

[0011] The dummy functional layer may expose an edge of the second cover portion.

[0012] The dummy functional layer may be spaced apart from the organic insulating layer.

[0013] A first angle formed by a first virtual line and the upper surface of the substrate may be smaller than a second angle formed by a second virtual line and the upper surface of the substrate, the first virtual line extending from the edge of the second cover portion to the edge of the tip of the protrusion, and the second virtual line extending from the edge of the dummy functional layer to the edge of the tip of the protrusion.

[0014] The capping layer and the pixel electrode may include the same material.

[0015] The support layer may comprise metal.

[0016] The display panel may further include a thin film transistor arranged in the display area and including a semiconductor layer and a gate electrode. The support layer and the wire arranged on the interlayer insulating layer covering the gate electrode may be arranged on the same layer.

[0017] The display panel may further include: an inorganic insulating layer disposed on the substrate and continuously extending from the display area to the intermediate area. The support layer may be disposed on the inorganic insulating layer.

[0018] According to an embodiment, the display panel may include: an opening area in a plan view, a display area surrounding at least a portion of the opening area, and an intermediate area between the opening area and the display area; a light emitting diode arranged on a substrate in the display area and including a pixel electrode, a counter electrode, and an intermediate layer arranged between the pixel electrode and the counter electrode and including a functional layer and an emission layer; an inorganic insulating layer arranged on the substrate and extending continuously from the display area to the intermediate area; a supporting layer arranged on the inorganic insulating layer in the intermediate area and including a metal; an organic insulating layer arranged on the inorganic insulating layer and the supporting layer and having a groove corresponding to the supporting layer; a metal layer arranged on the organic insulating layer and having a protruding tip protruding toward the groove; and a cap layer including a first cap portion covering an upper surface and a side surface of the metal layer and a second cap portion arranged in the groove. The cap layer and the pixel electrode may include the same material.

[0019] The second cover portion may expose at least a portion of the organic insulating layer.

[0020] The organic insulating layer may cover at least a portion of the support layer.

[0021] The functional layer may extend to the intermediate region, and may include a dummy functional layer disposed on the second cover portion.

[0022] The dummy functional layer may expose an edge of the second cover portion.

[0023] A first distance from the upper surface of the substrate to an edge of the second cover portion may be greater than a second distance from the upper surface of the substrate to an edge of the dummy functional layer.

[0024] A first angle formed by a first virtual line and the upper surface of the substrate may be smaller than a second angle formed by a second virtual line and the upper surface of the substrate, the first virtual line extending from the edge of the second cover portion to the edge of the tip of the protrusion, and the second virtual line extending from the edge of the dummy functional layer to the edge of the tip of the protrusion.

[0025] The display panel may further include a thin film transistor arranged in the display area and including a semiconductor layer and a gate electrode. The support layer and the wire arranged on the interlayer insulating layer covering the gate electrode may be arranged on the same layer.

[0026] The support layer and the wires may comprise the same material.

[0027] According to the utility model, a functional layer including an organic material can be separated in a middle area by a groove structure, and impurities introduced through a via hole of a substrate can be prevented from flowing into an organic light emitting diode through the functional layer, so that a display panel can include a display area having areas for arranging various types of components and has improved reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The above and other aspects, features and advantages of the disclosed embodiments will become more apparent through the following description in conjunction with the accompanying drawings, in which:

[0029] Figure 1 is a schematic perspective view of an electronic device according to an embodiment;

[0030] Figure 2 According to the embodiment along Figure 1 A schematic cross-sectional view of the display panel taken along line II';

[0031] Figure 3 is a schematic plan view of a display panel according to an embodiment;

[0032] Figure 4A is a schematic diagram of an equivalent circuit of a pixel included in a display panel according to an embodiment;

[0033] Figure 4B is a schematic diagram of an equivalent circuit of a pixel included in a display panel according to an embodiment;

[0034] Figure 5 is a schematic plan view of a portion of a display panel according to an embodiment;

[0035] Figure 6 According to the embodiment along Figure 5 A schematic cross-sectional view of a portion of the display panel taken along line III-III';

[0036] Fig. 7A is a schematic cross-sectional view of a portion of a display panel according to an embodiment, and schematically indicates Figure 6 The enlarged area V;

[0037] Figure 7B is a schematic cross-sectional view of a portion of a display panel according to an embodiment, and schematically indicates Figure 6 A magnified region V of

[0038] FIG. 8A to FIG. 8E are schematic cross-sectional views illustrating processes of a method of manufacturing a display panel according to an embodiment. DETAILED DESCRIPTION

[0039] In the following description, for the purpose of explanation, many specific details are set forth to provide a thorough understanding of the various embodiments or implementations disclosed. As used herein, "embodiment" and "implementation" are interchangeable words as non-limiting examples of the apparatus or method disclosed herein. However, it is apparent that various embodiments may be practiced without these specific details or with one or more equivalent arrangements. Here, various embodiments need not be exclusive, nor need they be limited to disclosure. For example, the specific shape, configuration (construction) and characteristics of an embodiment may be used or implemented in another embodiment.

[0040] Now will refer to embodiment in detail, examples of embodiment are shown in the accompanying drawings, and the same reference numerals in the accompanying drawings always represent the same elements. In this regard, the embodiment can have different forms and should not be construed as being limited to the description set forth herein. Therefore, the embodiment is described below only by reference to the accompanying drawings to explain the aspects of the description. Throughout the disclosure, the expression "at least one of a, b and c" means only a, only b, only c, both a and b, both a and c, both b and c, all of a, b and c or its variants.

[0041] Although the disclosure provides various modifications and alternative forms, its embodiments are shown in the drawings by way of example and will be described in detail herein. The effects and characteristics of the disclosure and methods for implementing the disclosure will become apparent by reference to the drawings and embodiments described in detail below. However, the disclosure is not limited to the embodiments disclosed below and may be implemented in various forms.

[0042] Hereinafter, the disclosed embodiments will be described in detail by referring to the accompanying drawings. In the description with reference to the accompanying drawings, the same reference numerals are given to the same or substantially the same elements, and the description will not be repeated.

[0043] The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting. It is also noted that, as used herein, the terms "substantially," "about," and other similar terms are used as terms of approximation rather than terms of degree, and as such, are used to account for the inherent deviations in measured, calculated, and / or provided values ​​that one of ordinary skill in the art would recognize.

[0044] It will be understood that although the terms "first," "second," etc. may be used herein to describe various components, these components should not be limited by these terms. These components are only used to distinguish one component from another. Therefore, without departing from the disclosed teachings, the first element discussed below may be referred to as the second element.

[0045] As used herein, the singular expressions "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0046] It will also be understood that the terms “comprises” and variations thereof, “includes” and variations thereof, and / or “having” and variations thereof used herein specify the presence of stated features, components, elements, features, integers, steps, operations and / or groups thereof, but do not preclude the presence or addition of one or more other features, components, elements, features, integers, steps, operations and / or groups thereof.

[0047] It will be understood that when a layer, region, or element is referred to as being formed "on" another layer, region, or element, the layer, region, or element may be formed directly or indirectly on the other layer, region, or element. For example, there may be intervening layers, regions, or elements. However, when an element or layer is referred to as being "directly on," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. For this purpose, the term "connected" may refer to a physical connection, an electrical connection, and / or a fluid connection with or without intervening elements.

[0048] When a component is described herein as “connecting” another component to or “connected to” another component, the components may be connected to each other as separate elements, or the components may be integrated with each other.

[0049] In the embodiments below, it will be understood that when an element, region or layer is referred to as being connected to another element, region or layer, the element, region or layer may be directly and / or indirectly connected to the other element, region or layer. For example, it will be understood in this specification that when an element, region or layer is referred to as being in contact with or electrically connected to another element, region or layer, the element, region or layer may be directly and / or indirectly in contact with or electrically connected to the other element, region or layer. In addition, when an element is referred to as being "in contact with" or "in contact with" another element, etc., the element may be "electrically in contact with" or "physically in contact with" the other element; or "indirectly in contact with" or "directly in contact with" the other element.

[0050] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. In this specification, the expression "A and / or B" may refer to A, B, or A and B. In addition, the expression "at least one of A and B" may refer to A, B, or A and B. The terms "and" and "or" may be used in conjunction or disjunction and may be understood to be equivalent to "and / or".

[0051] For descriptive purposes, spatially relative terms such as "below," "lower," "above," "upper," "higher," "side," etc. may be used herein to describe the relationship of one element to another (additional) element as shown in the accompanying drawings. Spatially relative terms are intended to cover different orientations of the device in use, operation, and / or manufacture in addition to the orientation depicted in the accompanying drawings. For example, if the device in the accompanying drawings is turned over, an element described as "below" or "beneath" other elements or features will subsequently be oriented to be "above" the other elements or features. Thus, the example term "below" can cover both above and below. In addition, the device can be oriented otherwise (e.g., rotated 90 degrees or at other orientations), and as such, the spatially relative descriptors used herein are interpreted accordingly.

[0052] In the following examples, the x-axis, y-axis, and z-axis are not limited to the three axes of the rectangular coordinate system and can be interpreted in a broader sense. For example, the x-axis, y-axis, and z-axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other.

[0053] Unless otherwise specified, the illustrated embodiments will be understood to provide example features of the disclosure. Therefore, unless otherwise specified, the features, components, modules, layers, films, panels, regions and / or aspects, etc. (hereinafter, individually or collectively referred to as "elements") of the various embodiments may be further combined, separated, interchanged and / or rearranged without departing from the disclosure.

[0054] The display surface may be parallel to the surface defined by the x-direction and the y-direction. The normal direction of the display surface (i.e., the thickness direction of the display device) may refer to the z-direction. In this specification, the expression "when viewed from the top or in a plan view" may refer to the situation when viewed in the z-direction. In the following, the front surface (or top surface) and the rear surface (or bottom surface) of each layer or unit may be distinguished by the z-direction. However, the directions indicated by the x-direction, the y-direction, and the z-direction may be relative concepts and converted relative to each other, for example, converted to the opposite direction.

[0055] When the embodiments can be implemented differently, the specific process order can be performed differently from the described order. For example, two consecutively described processes can be performed substantially simultaneously or in the reverse order of the described order.

[0056] For ease of explanation, the dimensions of the elements in the drawings may be exaggerated. For example, for ease of explanation, the dimensions and thickness of the elements in the drawings are randomly indicated, and therefore, the disclosure is not necessarily limited to the illustrations of the drawings. In addition, the use of cross-hatching and / or shading is generally provided in the drawings to clarify the boundaries between adjacent elements. Thus, unless otherwise specified, the presence or absence of cross-hatching or shading does not convey or indicate any preference or requirement for the specific material, material properties, size, ratio, commonality between the elements shown, and / or any other characteristics, attributes, properties, etc. of the elements.

[0057] Various embodiments are described herein with reference to schematically illustrated cross-sections and / or exploded illustrations as embodiments and / or intermediate structures. Thus, variations in the shapes of the illustrations due to, for example, manufacturing techniques and / or tolerances are expected. Therefore, the embodiments disclosed herein should not necessarily be interpreted as being limited to specific illustrated shapes of regions, but will include deviations in shapes due to, for example, manufacturing. In this way, the regions shown in the drawings may be schematic in nature, and the shapes of these regions may not reflect the actual shapes of the regions of the device, and thus need not be intended to be limiting.

[0058] Unless otherwise defined or implied herein, all terms (including technical and scientific terms) used have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. It will also be understood that terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and should not be interpreted in an idealized or overly formal sense unless clearly defined in the specification.

[0059] Figure 1 is a schematic perspective view of an electronic device 1 according to the embodiment.

[0060] Reference Figure 1, the electronic device 1 may include a device for displaying a video or a still image, and may be used not only as a display screen for portable electronic devices such as mobile phones, smart phones, tablet personal computers (PCs), mobile communication terminals, electronic notebooks, electronic books, portable multimedia players (PMPs), navigation devices, ultra-mobile PCs (UMPCs), etc., but may also be used as a display screen for various products such as televisions, notebook computers, monitors, broadcast panels, Internet of Things (IOT) devices, etc. The electronic device 1 according to the embodiment may also be used for wearable devices such as smart watches, watch phones, glasses-type displays, head-mounted displays (HMDs), etc. The electronic device 1 according to the embodiment may also be used as a central information display (CID) on a vehicle's dashboard or a central dashboard or instrument panel of a vehicle, an interior mirror display that replaces a side mirror of a vehicle, a display set on the rear surface of a front seat, or an entertainment device for a rear seat of a vehicle. The electronic device 1 may be bendable, foldable, or rollable. For ease of explanation, Figure 1 It is shown that the electronic device 1 according to the embodiment is used as a smartphone, but the disclosure is not limited thereto.

[0061] The electronic device 1 may have a rectangular shape in a plan view. Figure 1 As shown in , the electronic device 1 may have a rectangular shape having a short side in the x direction and a long side in the y direction in a plan view. The y direction may intersect the x direction. The corner where the short side in the x direction and the long side in the y direction meet each other may be formed with a curvature (e.g., a predetermined curvature or a selectable curvature), or may be formed with a right angle. However, the electronic device 1 in the plan view is not limited thereto, and may have other polygonal shapes, elliptical shapes, amorphous shapes, etc.

[0062] The electronic device 1 may include an opening area OA (or a first area) and a display area DA (or a second area) at least partially surrounding the opening area OA. The electronic device 1 may include an intermediate area IA between the opening area OA and the display area DA and a peripheral area PA arranged adjacent to the display area DA (or surrounding the display area DA). Each of the intermediate area IA and the peripheral area PA may correspond to a non-display area and does not emit light.

[0063] The opening area OA may be arranged at a portion (eg, an inner portion) of the display area DA. Figure 1As shown in , the opening area OA may be arranged at the upper left side of the display area DA. However, the disclosure is not limited thereto, and the opening area OA may be arranged at various sides of the display area DA (such as, the upper middle side, the upper right side, etc. of the display area DA, or a combination thereof). The expressions "left", "right", "upper" or "lower" relative to the disclosed plan view may be directions relative to the electronic device 1 viewed in a direction perpendicular to the electronic device 1. For example, the expression "left" may be a direction opposite to the x direction, the expression "right" may be an x ​​direction, the expression "upper" may be a y direction, and the expression "lower" may be a direction opposite to the y direction. Figure 1 It is shown that one opening area OA is arranged in the display area DA. However, according to another embodiment, a plurality of opening areas OA may be arranged in the display area DA.

[0064] Figure 2 According to the embodiment along Figure 1 Schematic cross-sectional view of the display panel 10 taken along line II′.

[0065] Reference Figure 2 , the electronic device 1 may include a display panel 10 and a component 70 disposed in an opening area OA of the display panel 10. The display panel 10 and the component 70 may be accommodated in a housing HS.

[0066] The display panel 10 may include a display layer 20 , an input sensing layer 40 , an optical function layer 50 , and a cover window 60 .

[0067] The display layer 20 may include a display element (or emission element) that emits light and displays an image and a pixel circuit that is respectively connected to the display element and applies an electrical signal to the display element. The display element may include a light emitting diode (eg, an organic light emitting diode including an organic emission layer, etc.).

[0068] The input sensing layer 40 may obtain coordinate information based on an external input (e.g., a touch event). The input sensing layer 40 may include a sensing electrode (or a touch electrode) and a trace electrically connected to the sensing electrode (or a touch electrode). The input sensing layer 40 may be arranged on the display layer 20. The input sensing layer 40 may sense an external input by using a mutual capacitance method, a self capacitance method, etc., or a combination thereof.

[0069] The input sensing layer 40 may be formed on the display layer 20 (e.g., directly formed on the display layer 20), or may be bonded to the display layer 20 through an adhesive layer (not shown) such as an optically clear adhesive (OCA), etc. after being separately formed. For example, a process of forming the input sensing layer 40 may be sequentially performed after a process of forming the display layer 20, and an adhesive layer may not be disposed between the input sensing layer 40 and the display layer 20. Figure 2It is shown that the input sensing layer 40 is disposed between the display layer 20 and the optical functional layer 50. However, the disclosure is not limited thereto, and according to another embodiment, the input sensing layer 40 may be disposed on the optical functional layer 50.

[0070] The optical functional layer 50 may include an anti-reflection layer. The anti-reflection layer may reduce the reflectivity of light (external light) incident from the outside toward the display panel 10 through the cover window 60. The anti-reflection layer may include a phase retarder, a polarizer, etc. or a combination thereof. The phase retarder may include a film-type phase retarder, a liquid crystal coating type phase retarder, etc. The polarizer may include a film-type polarizer, a liquid crystal coating type polarizer, etc. The film-type polarizer may include an elongated synthetic resin film, etc., and the liquid crystal coating type polarizer may include liquid crystals arranged in a shape (e.g., a certain shape or a selectable shape), etc.

[0071] According to another embodiment, the anti-reflection layer may include a black matrix, a color filter, etc., or a combination thereof. The color filter may be arranged corresponding to the color of the light emitted from each of the light-emitting diodes of the display layer 20. According to another embodiment, the anti-reflection layer may include a destructive interference structure. The destructive interference structure may include a first reflective layer and a second reflective layer arranged in different layers. The first reflected light and the second reflected light reflected from the first reflective layer and the second reflective layer, respectively, may destructively interfere, and the reflectivity of the external light may be reduced.

[0072] The optical function layer 50 may include a lens layer (not shown). The lens layer may improve the extraction efficiency of light emitted from the display layer 20, or may reduce chromatic aberration. The lens layer may include a layer having a concave lens shape or a convex lens shape, or / and may include a plurality of layers having different refractive indices. The optical function layer 50 may include both an anti-reflection layer and a lens layer or one of the anti-reflection layer and the lens layer.

[0073] The display panel 10 may include an opening 10H. Figure 2 , the display layer 20 may include a first opening 20H, the input sensing layer 40 may include a second opening 40H, the optical function layer 50 may include a third opening 50H, and the first opening 20H, the second opening 40H, and the third opening 50H may overlap each other in a plan view.

[0074] The first opening 20H may penetrate from the top surface of the display layer 20 to the bottom surface of the display layer 20 , the second opening 40H may penetrate from the top surface of the input sensing layer 40 to the bottom surface of the input sensing layer 40 , and the third opening 50H may penetrate from the top surface of the optical function layer 50 to the bottom surface of the optical function layer 50 .

[0075] The openings 10H (eg, first opening 20H, second opening 40H, third opening 50H) of the display panel 10 may be arranged in the opening area OA and overlap each other in a plan view. The sizes (or diameters) of the first opening 20H, second opening 40H, and third opening 50H may be the same or different from each other.

[0076] According to another embodiment, at least one of the display layer 20, the input sensing layer 40, and the optical function layer 50 may not include an opening. For example, one or both of the display layer 20, the input sensing layer 40, and the optical function layer 50 may not include an opening.

[0077] The cover window 60 may be arranged on the optical functional layer 50. The cover window 60 may be bonded to the optical functional layer 50 by an adhesive layer OCA (such as OCA, etc.) arranged between the optical functional layer 50 and the cover window 60. The cover window 60 may include a glass material, a plastic material, etc. For example, the cover window 60 may be an ultra-thin glass window. For example, the cover window 60 may include polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, cellulose acetate propionate, etc. or a combination thereof.

[0078] The opening area OA may be a component area (e.g., a sensor area, a camera area, a speaker area, etc., or a combination thereof) in which a component 70 for adding various functions to the electronic device 1 is arranged. The component 70 may be arranged below the display panel 10 and overlap the opening 10H of the display panel 10 in a plan view.

[0079] The component 70 may include an electronic component. For example, the component 70 may include an electronic component that uses light, sound, etc. For example, the electronic component may include a sensor that uses light, such as an infrared sensor, a camera that receives light or captures an image, a sensor that measures distance or recognizes fingerprints by outputting and sensing light, sound, etc., a small lamp that outputs light, a speaker that outputs sound, etc. The electronic component that uses light may use light of various wavelength ranges such as visible light, infrared light, ultraviolet light, etc., or a combination thereof. The opening area OA may correspond to a transmission area through which light or / and sound output from the component 70 to the outside or traveling from the outside toward the electronic component is transmitted.

[0080] According to another embodiment, when the electronic device 1 is a smart watch, a vehicle dashboard, etc., the component 70 may be a component including a clock hand, a pointer, etc. indicating information (eg, vehicle speed, etc.). Figure 1 Differently, the cover window 60 may include an opening arranged in the opening area OA, and the component 70 such as a pointer may be exposed to the outside. According to another embodiment, when the electronic device 1 includes a component 70 such as a speaker, the cover window 60 may include an opening corresponding to the opening area OA.

[0081] Figure 3 is a schematic plan view of a display panel 10 according to an embodiment.

[0082] Reference Figure 3 , the display panel 10 may include an opening area OA, a display area DA, an intermediate area IA, and a peripheral area PA.

[0083] The display panel 10 may include a plurality of pixels P arranged in a display area DA. The pixel P may be the smallest area for emitting light, and may be an area for emitting red light, green light, or blue light. The display panel 10 may display an image using light emitted from a light emitting diode of each pixel P.

[0084] Each pixel P may include a light emitting diode. For example, each pixel P may include an organic light emitting diode as a display element. According to another embodiment, the display panel 10 may include an inorganic light emitting diode. Hereinafter, a pixel P including an organic light emitting diode as a display element is described as an embodiment. The pixel P arranged in the display area DA may refer to an organic light emitting diode OLED (see Figure 4A ) are arranged in the display area DA.

[0085] In a plan view, the intermediate area IA may surround the opening area OA. The intermediate area IA may be an area in which a light-emitting display element (such as an organic light-emitting diode, etc.) is not arranged, and a signal line that provides a signal to a pixel P arranged adjacent to (or around) the opening area OA may be arranged in the intermediate area IA. For example, when the data line DL and / or the scan line SL extend in the display area DA along the y direction and / or the x direction, a portion of the data line DL and / or the scan line SL may meander in the intermediate area IA along an edge of the opening 10H formed in the opening area OA of the display panel 10.

[0086] A scanning signal is provided to each pixel P (see, for example, Figure 4B A scan driver 2100 for providing Sn, Sn', Sn-1, Sn+1), a data driver 2200 for providing a data signal to each pixel P, and a first main power line (not shown) and a second main power line (not shown) for providing a first power voltage and a second power voltage, respectively, may be arranged in the peripheral area PA. Figure 3 The data driver 2200 is shown to be disposed adjacent to one side of the substrate 100. However, the disclosure is not limited thereto, and according to another embodiment, the data driver 2200 may be disposed on a printed circuit board (PCB) electrically connected to a pad (also referred to as a "pad" or "pad") disposed on one side of the display panel 10.

[0087] Figure 4A and Figure 4B is a schematic diagram of an equivalent circuit of a pixel P included in the display panel 10 according to an embodiment.

[0088] Reference Figure 4A , the pixel P may include a pixel circuit PC electrically connected to a scan line SL, a data line DL, and a driving voltage line PL, and an organic light emitting diode OLED electrically connected to the pixel circuit PC. The pixel circuit PC may include a first transistor T1, a second transistor T2, and a storage capacitor Cst. The second transistor T2 may be a switching transistor. The second transistor T2 may be electrically connected to the scan line SL and the data line DL, and may transmit a data signal Dm provided through the data line DL to the first transistor T1 in response to a scan signal Sn provided through the scan line SL.

[0089] The storage capacitor Cst may be electrically connected to the second transistor T2 and the driving voltage line PL, and may store a voltage corresponding to a difference between a voltage received from the second transistor T2 and a first power voltage ELVDD (or driving voltage) supplied from the driving voltage line PL.

[0090] The first transistor T1 may be a driving transistor. The first transistor T1 may be electrically connected to the driving voltage line PL and the storage capacitor Cst, and may control a driving current I flowing from the driving voltage line PL to the organic light emitting diode OLED according to the value of the voltage stored in the storage capacitor Cst. d The organic light emitting diode OLED can emit light according to the driving current I d Light of a certain brightness (e.g., a certain brightness or a selectable brightness).

[0091] The counter electrode (eg, cathode) of the organic light emitting diode OLED may receive the second power voltage ELVSS (or common voltage). The organic light emitting diode OLED may receive the driving current I from the first transistor T1. d To emit light.

[0092] Reference Figure 4B , the pixel circuit PC may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7, a storage capacitor Cst, and a boosting capacitor Cbt. According to an embodiment, the pixel circuit PC may not include the boosting capacitor Cbt, and hereinafter, the pixel circuit PC including the boosting capacitor Cbt will be described.

[0093] Some of the first transistor T1 to the seventh transistor T7 may be n-channel metal oxide semiconductor field effect transistors (n-channel MOSFET) (NMOS transistors), and the other transistors may be p-channel metal oxide semiconductor field effect transistors (p-channel MOSFET) (PMOS transistors). For example, the third transistor T3 and the fourth transistor T4 may be NMOS transistors, and the other transistors (e.g., the first transistor T1, the second transistor T2, the fifth transistor T5 to the seventh transistor T7) may be PMOS transistors. According to another embodiment, the third transistor T3, the fourth transistor T4, and the seventh transistor T7 may be NMOS transistors, and the other transistors (e.g., the first transistor T1, the second transistor T2, the fifth transistor T5, and the sixth transistor T6) may be PMOS transistors. According to another embodiment, only one of the first transistor T1 to the seventh transistor T7 may be an NMOS transistor, and the other transistors may be PMOS transistors.

[0094] The first to seventh transistors T1 to T7, the storage capacitor Cst, and the boosting capacitor Cbt may be electrically connected to the signal lines SL1, SL2, SLp, EL, SLn, and DL. The signal lines may include a first scan line SL1 transmitting a first scan signal Sn, a second scan line SL2 transmitting a second scan signal Sn', a previous scan line SLp transmitting a previous scan signal Sn-1, an emission control line EL transmitting an emission control signal En, a next scan line SLn transmitting a next scan signal Sn+1, and a data line DL transmitting a data signal Dm.

[0095] The driving voltage line PL can transmit the first power voltage ELVDD to the first transistor T1, and the initialization voltage line VIL can transmit the initialization voltage Vint to the first transistor T1, and connect the first gate electrode of the first transistor T1 and the pixel electrode of the organic light emitting diode OLED (see, for example, Figure 6 210) initialization.

[0096] The first transistor T1 may be a driving transistor. The first gate electrode (or first control electrode) of the first transistor T1 may be electrically connected to the storage capacitor Cst, the first electrode of the first transistor T1 may be electrically connected to the driving voltage line PL through the fifth transistor T5, and the second electrode of the first transistor T1 may be electrically connected to the pixel electrode of the organic light emitting diode OLED through the sixth transistor T6. One of the first electrode and the second electrode of the first transistor T1 may be a source electrode, and the other of the first electrode and the second electrode of the first transistor T1 may be a drain electrode. The first transistor T1 may receive the data signal Dm according to the switching operation of the second transistor T2, and supply the driving current I to the organic light emitting diode OLED. d .

[0097] The second transistor T2 may be a switching transistor. The second gate electrode (or second control electrode) of the second transistor T2 may be electrically connected to the first scan line SL1, the first electrode of the second transistor T2 may be electrically connected to the data line DL, and the second electrode of the second transistor T2 may be electrically connected to the first electrode of the first transistor T1 and may be electrically connected to the driving voltage line PL through the fifth transistor T5. One of the first electrode and the second electrode of the second transistor T2 may be a source electrode, and the other of the first electrode and the second electrode of the second transistor T2 may be a drain electrode. The second transistor T2 may be turned on in response to a first scan signal Sn transmitted through the first scan line SL1, and may perform a switching operation of transmitting a data signal Dm transmitted through the data line DL to the first electrode of the first transistor T1.

[0098] The third transistor T3 may be a compensation transistor for compensating for the threshold voltage of the first transistor T1. A third gate electrode (or compensation control electrode) of the third transistor T3 may be electrically connected to the second scan line SL2. A first electrode of the third transistor T3 may be electrically connected to the lower electrode CE1 of the storage capacitor Cst and the first gate electrode of the first transistor T1 through the first node N1.

[0099] The first node N1 may be a region electrically connected to the first gate electrode of the first transistor T1 , the first electrode of the third transistor T3 , the second electrode of the fourth transistor T4 , and the fourth electrode CE4 of the boosting capacitor Cbt.

[0100] The first electrode of the third transistor T3 may be electrically connected to the fourth transistor T4. The second electrode of the third transistor T3 may be electrically connected to the second electrode of the first transistor T1, and may be electrically connected to the pixel electrode of the organic light emitting diode OLED through the sixth transistor T6. One of the first electrode and the second electrode of the third transistor T3 may be a source electrode, and the other of the first electrode and the second electrode of the third transistor T3 may be a drain electrode.

[0101] The third transistor T3 may be turned on in response to the second scan signal Sn′ transmitted through the second scan line SL2 , and may electrically connect the first gate electrode and the second electrode of the first transistor T1 to each other to diode-connect the first transistor T1 .

[0102] The fourth transistor T4 may be a first initialization transistor that initializes the first gate electrode of the first transistor T1. The fourth gate electrode (or fourth control electrode) of the fourth transistor T4 may be electrically connected to the previous scan line SLp. The first electrode of the fourth transistor T4 may be electrically connected to the initialization voltage line VIL. The second electrode of the fourth transistor T4 may be electrically connected to the lower electrode CE1 of the storage capacitor Cst, the first electrode of the third transistor T3, and the first gate electrode of the first transistor T1. One of the first electrode and the second electrode of the fourth transistor T4 may be a source electrode, and the other of the first electrode and the second electrode of the fourth transistor T4 may be a drain electrode. The fourth transistor T4 may be turned on in response to the previous scan signal Sn-1 received through the previous scan line SLp, and may perform an initialization operation of initializing the voltage of the first gate electrode of the first transistor T1 by transmitting the initialization voltage Vint to the first gate electrode of the first transistor T1.

[0103] The fifth transistor T5 may be an operation control transistor. A fifth gate electrode (or a fifth control electrode) of the fifth transistor T5 may be electrically connected to the emission control line EL, a first electrode of the fifth transistor T5 may be electrically connected to the driving voltage line PL, and a second electrode of the fifth transistor T5 may be electrically connected to the first electrode of the first transistor T1 and the second electrode of the second transistor T2. One of the first electrode and the second electrode of the fifth transistor T5 may be a source electrode, and the other of the first electrode and the second electrode of the fifth transistor T5 may be a drain electrode.

[0104] The sixth transistor T6 may be an emission control transistor. A sixth gate electrode (or a sixth control electrode) of the sixth transistor T6 may be electrically connected to the emission control line EL, a first electrode of the sixth transistor T6 may be electrically connected to the second electrode of the first transistor T1 and the second electrode of the third transistor T3, and a second electrode of the sixth transistor T6 may be electrically connected to the second electrode of the seventh transistor T7 and the pixel electrode of the organic light emitting diode OLED. One of the first electrode and the second electrode of the sixth transistor T6 may be a source electrode, and the other of the first electrode and the second electrode of the sixth transistor T6 may be a drain electrode.

[0105] The fifth transistor T5 and the sixth transistor T6 may be turned on at the same time in response to the emission control signal En received through the emission control line EL, and the first power supply voltage ELVDD may be transmitted to the organic light emitting diode OLED, driving the current I d Can flow in organic light emitting diodes OLED.

[0106] The seventh transistor T7 may be a second initialization transistor that initializes the pixel electrode of the organic light emitting diode OLED. The seventh gate electrode (or the seventh control electrode) of the seventh transistor T7 may be electrically connected to the next scan line SLn. The first electrode of the seventh transistor T7 may be electrically connected to the initialization voltage line VIL. The second electrode of the seventh transistor T7 may be electrically connected to the second electrode of the sixth transistor T6 and the pixel electrode of the organic light emitting diode OLED. The seventh transistor T7 may be turned on in response to the next scan signal Sn+1 received through the next scan line SLn, and may initialize the pixel electrode of the organic light emitting diode OLED. Figure 4B It is shown that the seventh transistor T7 may be electrically connected to the next scan line SLn. However, according to another embodiment, the seventh transistor T7 may be electrically connected to the emission control line EL and may be driven according to the emission control signal En.

[0107] The storage capacitor Cst may include a lower electrode CE1 and an upper electrode CE2. The lower electrode CE1 of the storage capacitor Cst may be electrically connected to the first gate electrode of the first transistor T1, and the upper electrode CE2 of the storage capacitor Cst may be electrically connected to the driving voltage line PL. The storage capacitor Cst may store a voltage corresponding to a difference between a voltage of the first gate electrode of the first transistor T1 and the first power supply voltage ELVDD.

[0108] The boosting capacitor Cbt may include a third electrode CE3 and a fourth electrode CE4. The third electrode CE3 may be electrically connected to the second gate electrode of the second transistor T2 and the first scan line SL1, and the fourth electrode CE4 may be electrically connected to the first node N1. When the first scan signal Sn supplied through the first scan line SL1 is turned off, the boosting capacitor Cbt may increase the voltage of the first node N1, and when the voltage of the first node N1 is increased, a black grayscale may be vividly displayed.

[0109] According to an embodiment, Figure 4B It is shown that the third transistor T3 and the fourth transistor T4 are NMOS transistors and the first transistor T1, the second transistor T2, the fifth transistor T5 to the seventh transistor T7 are PMOS transistors. The first transistor T1, which can directly affect the brightness of the display panel 10, can include a semiconductor layer including polysilicon with high reliability, and a display device with high resolution can be implemented.

[0110] The oxide semiconductor may have high carrier mobility and low leakage current, and the voltage drop may not be significant even when the driving time is increased. For example, even during low-frequency driving, the color change of the image due to the voltage drop may be almost invisible. Therefore, low-frequency driving may be possible. As described above, the oxide semiconductor may have a low leakage current, and at least one of the third transistor T3 and the fourth transistor T4 electrically connected to the gate electrode of the first transistor T1 may include an oxide semiconductor to prevent leakage current from flowing through the first gate electrode of the first transistor T1, and also reduce power consumption.

[0111] Figure 5 is a schematic plan view of a portion of a display panel 10 according to the embodiment.

[0112] The pixels P may be arranged in the display area DA, and the intermediate area IA may be arranged between the opening area OA and the display area DA. The pixels P may be arranged in the display area DA and surround the opening area OA and the intermediate area IA.

[0113] The position of the pixel P may correspond to the position of the organic light emitting diode OLED. The pixel P being arranged in the display area DA may mean that the organic light emitting diode OLED is arranged in the display area DA.

[0114] In a plan view, pixels P arranged adjacent to the opening area OA may be spaced apart from each other with the opening area OA interposed between the pixels P. The pixels P may be spaced apart from each other in an upper or lower direction relative to the opening area OA or in a left or right direction relative to the opening area OA.

[0115] Organic insulating layer (see e.g. Figure 6 The grooves GV of the substrate (see, for example, FIG. 1 ) may be arranged in the intermediate area IA and spaced apart from each other in the x direction and / or the y direction. Each groove GV may be arranged in a plan view (eg, when approximately aligned with the substrate (see, for example, FIG. 1 ) Figure 6 When viewed in a vertical direction from the upper surface of 100), the upper surface of the device has a closed loop shape. Figure 5 As shown in , the grooves GV can form concentric circles. Figure 6 , Fig. 7A and Figure 7B A detailed description thereof is given.

[0116] At least one partition wall PW may be disposed in the intermediate area IA. The partition wall PW may have a closed loop shape in a plan view. According to an embodiment, Figure 5 It is shown that one partition wall (or bank) PW may be disposed in the intermediate area IA. However, according to another embodiment, two partition walls PW may be disposed in the intermediate area IA and spaced apart from each other.

[0117] The groove GV may be disposed between the display area DA and the partition wall PW and / or between the partition wall PW and the opening area OA. Figure 5 It is shown that two grooves GV can be arranged between the display area DA and the partition wall PW and two grooves GV can be arranged between the partition wall PW and the opening area OA. However, the disclosure is not limited to this. According to another embodiment, three or more grooves GV can be arranged between the display area DA and the partition wall PW. Three or more grooves GV can be arranged between the partition wall PW and the opening area OA.

[0118] The substrate of the display panel 10 (see for example Figure 6 The substrate 100 may include a via hole 100H corresponding to the opening area OA, and the opening area OA may correspond to the via hole 100H of the substrate. For example, the groove GV may be arranged between the partition wall PW and the opening area OA, which may mean that the groove GV may be arranged between the partition wall PW and the via hole 100H.

[0119] Figure 6 According to the embodiment along Figure 5 A schematic cross-sectional view of a portion of the display panel 10 taken along line III-III', Fig. 7A is a schematic cross-sectional view of a portion of a display panel 10 according to an embodiment, and schematically shows Figure 6 Region V.

[0120] Fig. 7A The structures of the groove GV, the support layer SPL, the metal layer ML, the cover layer CVL, etc. arranged in the first area A1 between the display area DA and the partition wall PW are schematically shown. However, the groove GV, the support layer SPL, the metal layer ML, and the cover layer CVL arranged in the second area A2 between the partition wall PW and the opening area OA may have the same structure.

[0121] Reference Figure 6 The display panel 10 may include a display area DA, an opening area OA, and an intermediate area IA between the opening area OA and the display area DA. The display panel 10 may include a substrate 100 on which elements of the display panel 10 are arranged, and the substrate 100 may include a display area DA, an opening area OA, and an intermediate area IA between the opening area OA and the display area DA.

[0122] The pixel circuit PC may be disposed on the display area DA of the substrate 100 , and an organic light emitting diode OLED electrically connected to the pixel circuit PC may be disposed on the pixel circuit PC.

[0123] The substrate 100 may include a glass material, a polymer resin, etc. For example, the substrate 100 may include a polymer resin including polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, cellulose acetate propionate, etc. or a combination thereof. The substrate 100 including the polymer resin may be flexible, rollable, foldable or bendable. The substrate 100 may have a multilayer structure including a layer including a polymer resin and an inorganic layer (not shown).

[0124] The first buffer layer 101a and the second buffer layer 101b may be disposed on the upper surface of the substrate 100. The first buffer layer 101a and the second buffer layer 101b may prevent impurities from penetrating into the first semiconductor layer Act1 of the pixel circuit PC. The first buffer layer 101a and the second buffer layer 101b may include an inorganic insulating material such as silicon nitride, silicon oxynitride, silicon oxide, etc. or a combination thereof, and may include a single layer or multiple layers including the inorganic insulating material.

[0125] The bottom metal layer BML may be disposed between the first buffer layer 101a and the second buffer layer 101b. The bottom metal layer BML may block external light from reaching the first thin film transistor TFT1 and / or the second thin film transistor TFT2. According to an embodiment, a constant voltage or signal may be applied to the bottom metal layer BML and damage to the pixel circuit PC due to electrostatic discharge may be prevented. Figure 6 It is shown that one bottom metal layer BML can be arranged under the pixel circuit PC. However, the disclosure is not limited thereto, and according to another embodiment, the display panel 10 may include a plurality of bottom metal layers BML. The bottom metal layer BML may include a metal. For example, the bottom metal layer BML may include Al, Pt, Pd, Ag, Mg, Au, Ni, Nd, Ir, Cr, Ca, Mo, Ti, W, Cu, etc. or an alloy thereof, and may include a single layer or multiple layers.

[0126] The pixel circuit PC may be disposed on the second buffer layer 101b. The pixel circuit PC may include a plurality of transistors and a storage capacitor Cst. According to an embodiment, the pixel circuit PC may include a first thin film transistor TFT1 and a second thin film transistor TFT2.

[0127] The first thin film transistor TFT1 may include a first semiconductor layer Act1 on the second buffer layer 101b and a first gate electrode G1 overlapping the channel region of the first semiconductor layer Act1 in a plan view. The first semiconductor layer Act1 may include a silicon-based semiconductor material (e.g., polycrystalline silicon, etc.). The first semiconductor layer Act1 may include a channel region and an impurity region arranged at a side of the channel region. One of the impurity regions arranged at one side of the channel region may be a source region, and the other of the impurity regions arranged at the other side of the channel region may be a drain region.

[0128] The first gate insulating layer 103 may be disposed between the first semiconductor layer Act1 and the first gate electrode G1. The first gate insulating layer 103 may include an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, etc. or a combination thereof, and may have a single layer or multi-layer structure.

[0129] The first gate electrode G1 may include a conductive material including Mo, Al, Cu, Ti, etc. or a combination thereof, and may have a single-layer or multi-layer structure.

[0130] The storage capacitor Cst may include a lower electrode CE1 and an upper electrode CE2 overlapping each other in a plan view. According to an embodiment, the lower electrode CE1 of the storage capacitor Cst may include the first gate electrode G1 of the first thin film transistor TFT1. For example, the first gate electrode G1 of the first thin film transistor TFT1 may be integrated with the lower electrode CE1 of the storage capacitor Cst.

[0131] The upper electrode CE2 of the storage capacitor Cst may include a conductive material such as Mo, Al, Cu, Ti, etc. or an alloy thereof, and may have a single-layer or multi-layer structure.

[0132] The first interlayer insulating layer 105 may be disposed between the lower electrode CE1 and the upper electrode CE2 of the storage capacitor Cst, and the second interlayer insulating layer 107 may be disposed on the upper electrode CE2 of the storage capacitor Cst. Each of the first interlayer insulating layer 105 and the second interlayer insulating layer 107 may include an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, etc. or a combination thereof, and may have a single-layer or multi-layer structure.

[0133] The second semiconductor layer Act2 of the second thin film transistor TFT2 may be arranged on the second interlayer insulating layer 107. The second semiconductor layer Act2 may include an oxide-based semiconductor material. For example, the second semiconductor layer Act2 may include a Zn oxide-based material (e.g., Zn oxide, In-Zn oxide, Ga-In-Zn oxide, etc. or a combination thereof). According to an embodiment, the second semiconductor layer Act2 may include a semiconductor including In-Ga-Zn-O (IGZO), In-Sn-Zn-O (ITZO), In-Ga-Sn-Zn-O (IGTZO), etc., wherein metals such as In, Ga, Sn, etc. or alloys thereof are included in ZnO.

[0134] According to an embodiment, the second thin film transistor TFT2 may have a double gate structure including a lower gate electrode G3a and an upper gate electrode G3b overlapping the channel region of the second semiconductor layer Act2 in a plan view. According to another embodiment, the lower gate electrode G3a may be omitted.

[0135] The lower gate electrode G3a and the upper electrode CE2 of the storage capacitor Cst may be disposed at the same layer. For example, the lower gate electrode G3a may be disposed between the first interlayer insulating layer 105 and the second interlayer insulating layer 107. The lower gate electrode G3a and the upper electrode CE2 of the storage capacitor Cst may include the same material.

[0136] The upper gate electrode G3b may be arranged on the second semiconductor layer Act2, and the second gate insulating layer 109 is disposed between the second semiconductor layer Act2 and the upper gate electrode G3b. The upper gate electrode G3b may include a conductive material such as Mo, Al, Cu, Ti, etc. or an alloy thereof, and may have a single-layer or multi-layer structure. The second gate insulating layer 109 may include an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, etc. or a combination thereof, and may have a single-layer or multi-layer structure.

[0137] The third interlayer insulating layer 110 may be disposed on the upper gate electrode G3b. The third interlayer insulating layer 110 may include an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, etc. or a combination thereof, and may have a single layer or multi-layer structure.

[0138] Figure 6 It is shown that the upper electrode CE2 of the storage capacitor Cst and the lower gate electrode G3a of the second thin film transistor TFT2 can be arranged at the same layer. However, the disclosure is not limited thereto. According to another embodiment, the upper electrode CE2 of the storage capacitor Cst and the second semiconductor layer Act2 of the second thin film transistor TFT2 can be arranged at the same layer.

[0139] The first thin film transistor TFT1 and the second thin film transistor TFT2 may be electrically connected to each other through a connection electrode CM. The connection electrode CM may be disposed on the third interlayer insulating layer 110. One side of the connection electrode CM may be electrically connected to the first gate electrode G1 of the first thin film transistor TFT1, and the other side of the connection electrode CM may be electrically connected to the second semiconductor layer Act2 of the second thin film transistor TFT2.

[0140] The connection electrode CM may include a conductive material such as Mo, Al, Cu, Ti, etc. or an alloy thereof, and may have a single layer or a multilayer structure. For example, the connection electrode CM may have a multilayer structure including Ti / Al / Ti layers.

[0141] The first planarization layer 111 may be disposed on the connection electrode CM. According to an embodiment, the first planarization layer 111 may include an organic insulating material. In an embodiment, the first planarization layer 111 may include an acrylic material, benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), etc. or a combination thereof.

[0142] Signal lines such as data lines DL may be disposed on the first planarization layer 111 and may be covered by the second planarization layer 113 . Figure 6 It is shown that the data line DL may be formed on the first planarization layer 111. However, the disclosure is not limited thereto. The data line DL and the connection electrode CM may be disposed on the same layer, for example, on the third interlayer insulating layer 110.

[0143] The data line DL may include a conductive material such as Mo, Al, Cu, Ti, etc. or an alloy thereof, and may have a single layer or a multi-layer structure. For example, the data line DL may have a multi-layer structure including Ti / Al / Ti layers.

[0144] The second planarization layer 113 may include an organic insulating layer. In an embodiment, the second planarization layer 113 may include an acrylic material, BCB, polyimide, HMDSO, etc., or a combination thereof.

[0145] The organic light emitting diode OLED may include a pixel electrode 210 , an intermediate layer 220 on the pixel electrode 210 , and an opposing electrode 230 on the intermediate layer 220 .

[0146] The pixel electrode 210 may be arranged on the second planarization layer 113. The pixel electrode 210 may include a reflective layer (not shown) containing Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, etc. or an alloy thereof. According to an embodiment, the pixel electrode 210 may further include a conductive oxide layer (not shown) arranged on and / or below the reflective layer. The conductive oxide layer may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2 O 3 ), indium gallium oxide (IGO), aluminum zinc oxide (AZO), etc. or a combination thereof. According to an embodiment, the pixel electrode 210 may have a triple-layer structure of ITO / Ag / ITO layers.

[0147] In a plan view, an edge of the pixel electrode 210 may overlap with the bank layer 115. The bank layer 115 may include a pixel opening overlapping with a portion of the pixel electrode 210 in a plan view. The bank layer 115 may include an organic insulating material such as an acrylic material, BCB, polyimide, HMDSO, etc., or a combination thereof. According to an embodiment, the bank layer 115 may include a light shielding material. The light shielding material may include: a resin or paste containing carbon black, carbon nanotubes, and a black dye; metal particles such as Ni, Al, Mo, etc., and alloys thereof; metal oxide particles (e.g., chromium oxide, etc.); metal nitride particles (e.g., chromium nitride, etc.); or a combination thereof.

[0148] In a plan view, the intermediate layer 220 may include an emission layer 222 overlapping the pixel electrode 210 through the emission opening of the bank layer 115. The emission layer 222 may include a high molecular weight or low molecular weight organic material that emits red, green, or blue light. According to an embodiment, the emission layer 222 may include an inorganic material, a quantum dot, or the like, or a combination thereof.

[0149] The intermediate layer 220 may include a first functional layer 221 and / or a second functional layer 223. The first functional layer 221 may include a hole transport layer (HTL) and / or a hole injection layer (HIL), etc. The second functional layer 223 may include an electron transport layer (ETL) and / or an electron injection layer (EIL), etc.

[0150] According to an embodiment, the emission layer 222 may be patterned corresponding to the pixel electrode 210, and the first functional layer 221 and / or the second functional layer 223 may be integrally disposed over a surface (eg, the entire surface) of the display area DA. The first functional layer 221 and the second functional layer 223 may extend to the intermediate area IA.

[0151] The counter electrode 230 may include a conductive material having a low work function. For example, the counter electrode 230 may include a (semi) transparent layer (not shown) containing Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, etc. or an alloy thereof. According to an embodiment, the counter electrode 230 may further include a layer (including a conductive material such as ITO, IZO, ZnO, In 2 O 3 etc. or a combination thereof).

[0152] The encapsulation layer 300 may be disposed on the organic light emitting diode OLED and may encapsulate the organic light emitting diode OLED. The encapsulation layer 300 may include an inorganic encapsulation layer, an organic encapsulation layer, etc. or a combination thereof. According to an embodiment, Figure 6 It is shown that the encapsulation layer 300 may include a first inorganic encapsulation layer 310 , a second inorganic encapsulation layer 330 , and an organic encapsulation layer 320 between the second inorganic encapsulation layer 330 and the first inorganic encapsulation layer 310 .

[0153] The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may include aluminum oxide (Al 2 O 3 ), titanium oxide (TiO), tantalum oxide (TA 2 O 5 ), hafnium oxide (HfO 2 )、ZnO、SiO x 、SiN x At least one inorganic material of SiON and SiON. The first inorganic encapsulating layer 310 and the second inorganic encapsulating layer 330 may include a single layer or a multi-layer.

[0154] The organic encapsulation layer 320 may include a polymer material. According to an embodiment, the organic encapsulation layer 320 may include acryl-based resin, epoxy-based resin, polyimide, polyethylene, etc. or a combination thereof. According to an embodiment, the organic encapsulation layer 320 may include acrylate, etc.

[0155] The insulating layer including the inorganic insulating material stacked on the substrate 100 may be an inorganic insulating layer IL. Figure 6 , the inorganic insulating layer IL may include a first buffer layer 101a to a third interlayer insulating layer 110. However, the disclosure is not limited thereto. According to another embodiment, some of the first buffer layer 101a, the second buffer layer 101b, the first gate insulating layer 103, the first interlayer insulating layer 105, the second interlayer insulating layer 107, the second gate insulating layer 109, and the third interlayer insulating layer 110 may be omitted.

[0156] exist Figure 6 In the intermediate area IA, the display panel 10 according to the embodiment may include a substrate 100, an inorganic insulating layer IL, a support layer SPL, an organic insulating layer OL including a groove GV, a metal layer ML, and a cover layer CVL.

[0157] The edge of the second planarization layer 113 may be arranged in the intermediate area IA. For example, the edge of the second planarization layer 113 may be arranged between the display area DA and the groove GV arranged most adjacent to the display area DA. The intermediate area IA may include a first area A1 from the edge of the second planarization layer 113 to the partition wall PW and a second area A2 from the partition wall PW to the via hole 100H.

[0158] At least a portion of the inorganic insulating layer IL of the display area DA may extend toward the via hole 100H of the substrate 100. For example, at least a portion of the inorganic insulating layer IL may be disposed in the display area DA and the intermediate area IA. For example, an edge of the inorganic insulating layer IL toward the opening area OA and an edge of the substrate 100 defining the via hole 100H may be disposed on substantially the same vertical line.

[0159] The supporting layer SPL may be arranged on the inorganic insulating layer IL. The supporting layer SPL may include a plurality of supporting layers SPL spaced apart from each other in the x-direction and / or the y-direction. The supporting layer SPL may include a metal. The supporting layer SPL may include a conductive material such as Mo, Al, Cu, Ti, etc. or an alloy thereof, and may have a single layer or a multilayer structure. For example, the supporting layer SPL may have a multilayer structure of Ti / Al / Ti layers.

[0160] The support layer SPL and the line arranged on the insulating layer covering the gate electrode of the transistor arranged in the display area DA may be formed by the same process, may be arranged on the same layer, and may include the same material. For example, the support layer SPL and the connection electrode CM arranged on the third interlayer insulating layer 110 covering the upper gate electrode G3b of the second thin film transistor TFT2 may be arranged on the same layer and may include the same material.

[0161] The thickness of the support layer SPL may be in the range of about 30% to about 80% of the thickness of the organic insulating layer OL. According to an embodiment, the thickness of the support layer SPL may be in the range of about 3 μm to about 10 μm. According to an embodiment, the thickness of the support layer SPL may be in the range of about 5 μm to about 8 μm.

[0162] The organic insulating layer OL may be arranged on the inorganic insulating layer IL. For example, the organic insulating layer OL may be arranged on the third interlayer insulating layer 110. The organic insulating layer OL may cover at least a portion of the support layer SPL. The organic insulating layer OL may cover at least a portion of the side surface of the support layer SPL. According to an embodiment, the thickness of the organic insulating layer OL may be in the range of about 5 μm to about 20 μm. According to an embodiment, the thickness of the organic insulating layer OL may be in the range of about 9 μm to about 13 μm. The organic insulating layer OL and the first planarization layer 111 covering the connection electrode CM may be formed by the same process. The organic insulating layer OL and the first planarization layer 111 may include the same material and may be arranged at the same layer. The organic insulating layer OL and the first planarization layer 111 may be connected to each other.

[0163] The organic insulating layer OL may include a groove GV. The groove GV may be formed by removing a portion of the organic insulating layer OL in a thickness direction (e.g., z direction) of the display panel 10. The z direction may intersect with the x direction and the y direction. Through the groove GV, the organic insulating layer OL may expose at least a portion of the upper surface of the supporting layer SPL. The depth of the groove GV may correspond to a depth obtained by subtracting the thickness of the supporting layer SPL from the thickness of the organic insulating layer OL.

[0164] The metal layer ML may be disposed on the organic insulating layer OL. The metal layer ML may include a protrusion tip TP. The protrusion tip TP may be a portion of the metal layer ML, and the portion may protrude toward the groove GV. The protrusion tip TP may be a portion of the metal layer ML and may not contact the organic insulating layer OL. In a plan view, the protrusion tip TP may overlap the groove GV.

[0165] The metal layer ML and the data line DL may be formed by the same process. The metal layer ML and the data line DL may be arranged in the same layer and may include the same material. The metal layer ML may include a conductive material such as Mo, Al, Cu, Ti, etc. or an alloy thereof, and may have a single layer or a multilayer structure. For example, the metal layer ML may have a multilayer structure of Ti / Al / Ti.

[0166] The display panel 10 according to the embodiment may include a supporting layer SPL and an organic insulating layer OL, the supporting layer SPL being arranged on the inorganic insulating layer IL, the organic insulating layer OL covering at least a portion of a side surface of the supporting layer SPL and the inorganic insulating layer IL, and exposing at least a portion of an upper surface of the supporting layer SPL through the groove GV.

[0167] In the ashing process after forming the metal layer ML, the organic insulating layer OL can be separated by removing only a portion of the thickness of the organic insulating layer OL. By providing the support layer SPL, the organic insulating layer OL can be disconnected by removing only a portion of the thickness of the organic insulating layer OL except the thickness of the support layer SPL. Therefore, the ashing time can be reduced.

[0168] In addition, by reducing the ashing time, the length of the protrusion tip TP of the metal layer ML can be reduced. The length of the protrusion tip TP can be reduced to a range of about 0.1 μm to about 0.5 μm. As the length of the protrusion tip TP is reduced, the number of protrusion tips TP in the same area can be increased accordingly. Therefore, the reliability of the display device can be improved and the invalid area can be reduced. The cover layer CVL can be arranged on the metal layer ML. The cover layer CVL can cover the upper surface of the metal layer ML (see, for example Fig. 7A and Figure 7B US) and side surfaces (see e.g. Fig. 7A and Figure 7BThe capping layer CVL may cover a portion of the organic insulating layer OL. The capping layer CVL may be disposed in the groove GV.

[0169] The cover layer CVL may include a first cover portion C1 covering the upper surface US and the side surface SS of the metal layer ML and a second cover portion C2 arranged in the groove GV. In the case where the display panel includes a plurality of metal layers ML, the first cover portion C1 may cover the side surface of each of the metal layers ML. The second cover portion C2 may contact a portion of the upper surface of the support layer SPL and a portion of the side surface of the organic insulating layer OL defining the groove GV. The first cover portion C1 and the second cover portion C2 may be spaced apart from each other.

[0170] The capping layer CVL may include a metal. The capping layer CVL and the pixel electrode 210 may include the same material. The capping layer CVL and the pixel electrode 210 may be formed by the same process. According to an embodiment, the capping layer CVL may have a three-layer structure of ITO / Ag / ITO layers.

[0171] The functional layer 220f of the intermediate layer 220 in the display area DA may extend to the intermediate area IA. The functional layer 220f may include a first functional layer 221 and / or a second functional layer 223. The functional layer 220f may be arranged on the cover layer CVL in the intermediate area IA. The dummy functional layer 220d separated from the functional layer 220f by the protrusion tip TP may be arranged in the groove GV. The dummy functional layer 220d may be spaced apart from the functional layer 220f. The functional layer 220f including an organic material may be separated in the intermediate area IA by the structure of the groove GV, and impurities (such as moisture, etc.) introduced through the via 100H of the substrate 100 may be prevented from flowing into the organic light emitting diode OLED through the functional layer 220f.

[0172] Fig. 7A By zooming in Figure 6 The region V of FIG. 1 schematically illustrates the arrangement of the second cover portion C2 of the cover layer CVL and the dummy function layer 220d. The dummy function layer 220d may be arranged on the second cover portion C2.

[0173] Reference Fig. 7A , a first distance dc from the upper surface of the substrate 100 to the edge Ec of the second cover portion C2 may be greater than a second distance df from the upper surface of the substrate 100 to the edge Ef of the dummy function layer 220d. For example, the edge Ec of the second cover portion C2 may be arranged farther from the substrate 100 than the edge Ef of the dummy function layer 220d. The second cover portion C2 may cover the groove with a larger area than the dummy function layer 220d (see, for example, Figure 6 of GV).

[0174] Regarding the relationship with the protrusion tip TP, a vertical distance between an edge Ec of the second cover portion C2 and a lower surface LS of the protrusion tip TP may be smaller than a vertical distance between an edge Ef of the dummy functional layer 220d and the lower surface LS of the protrusion tip TP.

[0175] A first angle θ1 formed by a virtual line L1 extending from an edge Ec of the second cover portion C2 to an edge Et of the protrusion tip TP and the upper surface of the substrate 100 may be smaller than a second angle θ2 formed by a virtual line L2 extending from an edge Ef of the dummy functional layer 220d to an edge Et of the protrusion tip TP and the upper surface of the substrate 100.

[0176] The dummy functional layer 220d may expose the edge Ec of the second cover portion C2. The relationship between the second cover portion C2 of the cover layer CVL and the dummy functional layer 220d may be due to the difference in step coverage between the cover layer CVL and the functional layer 220f. The step coverage may indicate the deposition capability of a portion having a step difference. The difference in step coverage may be affected by the difference between the materials included in the cover layer CVL and the functional layer 220f.

[0177] According to an embodiment, the step coverage of the capping layer CVL may be greater than the step coverage of the functional layer 220f. The second capping portion C2 may cover the defined groove of the organic insulating layer OL with a larger area than the dummy functional layer 220d (see, for example, Figure 6 The dummy functional layer 220f may not contact the organic insulating layer OL. The organic insulating layer OL adjacent to the groove GV may be disconnected from the dummy functional layer 220f. Therefore, the penetration path of oxygen etc. into the organic light emitting diode OLED may be blocked.

[0178] The second cover portion C2 may expose at least a portion of the organic insulating layer OL. The second cover portion C2 may expose a portion of a side surface of the organic insulating layer OL disposed adjacent to the metal layer ML among the side surfaces defining the groove GV. In the case where heat is applied in a subsequent process after forming the organic insulating layer OL and the second cover portion C2, moisture present in the organic insulating layer OL may be released without degassing the moisture. According to an embodiment, the second cover portion C2 may expose at least a portion of the organic insulating layer OL, and a degassing path for moisture may be obtained.

[0179] Figure 7B is a schematic cross-sectional view of a portion of a display panel 10 according to an embodiment, and schematically shows Figure 6 Region V.

[0180] Reference Figure 7B, the metal layer ML may not be parallel to the upper surface of the substrate 100. The support layer SPL may be arranged only on a portion of the organic insulating layer IL, and the upper surface of the organic insulating layer OL covering the support layer SPL and the inorganic insulating layer IL may have a slope. The end of the metal layer ML arranged on the organic insulating layer OL and overlapping the support layer SPL in the z direction may have an ascending slope in the z direction. The first cover portion C1 of the cap layer CVL arranged on the metal layer ML, the functional layer 220f, the counter electrode 230, and the metal layer ML may have the same slope.

[0181] The metal layer ML may include a conductive material such as Mo, Al, Cu, Ti, etc. or an alloy thereof, and may have a single layer or a multilayer structure. According to an embodiment, the metal layer ML may have a multilayer structure including a first layer M1, a second layer M2, and a third layer M3. The first layer M1 and the third layer M3 may include Ti, etc., and the second layer M2 may include Al, etc. The protrusion tip TP of the metal layer ML may extend more in the first layer M1 and the third layer M3 than in the second layer M2.

[0182] According to an embodiment, the first cover portion C1 of the cover layer CVL may cover the upper surface US and the side surface SS of the metal layer ML. The side surface SS of the metal layer ML may include the side surface of the first layer M1, the side surface of the second layer M2, and the side surface of the third layer M3. The first cover portion C1 may extend from the upper surface US of the metal layer ML to the side surface of the third layer M3, the side surface of the second layer M2, and the side surface of the first layer M1. According to an embodiment, as Figure 7B As shown in FIG. 1 , a portion of the first cover portion C1 may be disconnected at the side surface SS of the metal layer ML. Since the third layer M3 is thinner than the second layer M2 in the direction toward the groove (see, for example, Figure 6 The first cover portion C1 further protrudes in the direction of GV), and thus the first cover portion C1 may not be deposited on the lower surface of the third layer M3.

[0183] Likewise, the functional layer 220f and a portion of the counter electrode 230 may be disconnected at the side surface SS of the metal layer ML. Not only the functional layer 220f may be disconnected from the dummy functional layer 220d, but also a portion of the functional layer 220f may be disconnected at the side surface SS of the metal layer ML. The introduction of external impurities such as moisture may be further effectively prevented.

[0184] FIG. 8A to FIG. 8E 2 is a schematic cross-sectional view illustrating a method of manufacturing the display panel 10 according to a process sequence according to an embodiment.

[0185] Reference Fig. 8A, an inorganic insulating layer IL and a support layer SPL may be formed on the substrate 100. The support layer SPL and the connection electrode CM arranged in the display area DA may be simultaneously formed by the same process. The support layer SPL and the connection electrode CM may include the same material.

[0186] Reference Figure 8B , an organic insulating layer OL covering the support layer SPL may be formed on the substrate 100. The organic insulating layer OL may cover the upper surface and the side surface of the support layer SPL. The organic insulating layer OL and the first planarization layer 111 in the display area DA may be simultaneously formed by the same process. The organic insulating layer OL and the first planarization layer 111 may include the same material.

[0187] Reference Figure 8C , a metal layer ML may be formed on the organic insulating layer OL. In a plan view, the metal layer ML may overlap at least a portion of the support layer SPL. The metal layer ML and the data line DL arranged in the display area DA may be simultaneously formed by the same process. The metal layer ML and the data line DL may include the same material.

[0188] Reference Fig.8D , a groove GV may be formed in the organic insulating layer OL. The groove GV may be formed in a position corresponding to the support layer SPL. The groove GV may expose the upper surface of the support layer SPL. The groove GV may expose a portion of the lower surface of the metal layer ML.

[0189] Reference Fig. 8E , a cap layer CVL covering the upper surface and the side surface of the metal layer ML may be formed. The cap layer CVL may contact the metal layer ML, the support layer SPL, and the organic insulating layer OL. The cap layer CVL and the pixel electrode 210 in the display area DA may be formed simultaneously by the same process. The cap layer CVL and the pixel electrode 210 may include the same material.

[0190] The support layer SPL, the organic insulating layer OL, the metal layer ML, and the capping layer CVL disposed in the intermediate area IA and the structures in the display area DA may be respectively formed by the same process, and the process of manufacturing the display panel 10 may become simplified.

[0191] As described above, according to the disclosed embodiments, the display panel 10 including the display area DA in which various types of components are arranged and having improved reliability may be implemented. However, the scope of the disclosure is not limited to these effects as described above.

[0192] The above description is an example of the disclosed technical features, and a person skilled in the art will be able to make various modifications and changes.Therefore, the above disclosed embodiments can be implemented individually or in combination with each other.

[0193] Therefore, the embodiments disclosed in the disclosure are not intended to limit the disclosed technical spirit, but to describe the disclosed technical spirit, and the scope of the disclosed technical spirit is not limited by these embodiments. The disclosed protection scope should be interpreted by the claims, and should be interpreted as all technical spirits within the equivalent scope are included in the disclosed scope.

Claims

1. A display panel, It is characterized in that The display panel comprises: an opening area in a plane, a display area surrounding at least a portion of the opening area, and an intermediate area between the opening area and the display area; A light emitting diode, arranged on a substrate in the display area, and comprising: a pixel electrode; a counter electrode; and an intermediate layer, arranged between the pixel electrode and the counter electrode, and comprising a functional layer and an emission layer; a support layer disposed on the substrate in the intermediate region; an organic insulating layer, arranged on the substrate and the supporting layer, and having a groove corresponding to the supporting layer; a metal layer disposed on the organic insulating layer and having a protrusion tip protruding toward the groove; and The cover layer includes: a first cover portion covering the upper surface and the side surface of the metal layer; and a second cover portion arranged in the groove, Wherein, the functional layer extends to the middle region and includes a dummy functional layer arranged on the second cover part.

2. The display panel according to claim 1, It is characterized in that The organic insulating layer covers at least a portion of the supporting layer.

3. The display panel according to claim 1, It is characterized in that The first cover portion and the second cover portion are spaced apart from each other.

4. The display panel according to claim 1, It is characterized in that A first distance from an upper surface of the substrate to an edge of the second cover portion is greater than a second distance from the upper surface of the substrate to an edge of the dummy functional layer.

5. The display panel according to claim 1, It is characterized in that The dummy functional layer exposes an edge of the second cover portion.

6. The display panel according to claim 1, It is characterized in that A first angle formed by a first virtual line and the upper surface of the substrate is smaller than a second angle formed by a second virtual line and the upper surface of the substrate, the first virtual line extending from the edge of the second cover portion to the edge of the tip of the protrusion, and the second virtual line extending from the edge of the dummy functional layer to the edge of the tip of the protrusion.

7. The display panel according to claim 1, It is characterized in that The display panel further includes: a thin film transistor, arranged in the display region and comprising a semiconductor layer and a gate electrode, The support layer and the wires arranged on the interlayer insulating layer covering the gate electrode are arranged on the same layer.

8. The display panel according to claim 1, It is characterized in that The display panel further includes: an inorganic insulating layer, arranged on the substrate and extending continuously from the display area to the middle area, Wherein, the support layer is arranged on the inorganic insulating layer.

9. A display panel, It is characterized in that The display panel comprises: an opening area in a plane, a display area surrounding at least a portion of the opening area, and an intermediate area between the opening area and the display area; A light emitting diode, arranged on a substrate in the display area, and comprising: a pixel electrode; a counter electrode; and an intermediate layer, arranged between the pixel electrode and the counter electrode, and comprising a functional layer and an emission layer; an inorganic insulating layer, arranged on the substrate and continuously extending from the display area to the middle area; a support layer disposed on the inorganic insulating layer in the intermediate region and comprising a metal; an organic insulating layer, arranged on the inorganic insulating layer and the supporting layer, and having a groove corresponding to the supporting layer; a metal layer disposed on the organic insulating layer and having a protrusion tip protruding toward the groove; and The cover layer includes: a first cover portion covering the upper surface and the side surface of the metal layer; and a second cover portion arranged in the groove, Wherein, the cover layer and the pixel electrode include the same material.

10. The display panel according to claim 9, It is characterized in that The second cover portion exposes at least a portion of the organic insulating layer.

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