Low-cost laser pulse signal peak detection circuit

Abstract

The utility model discloses a low-cost laser pulse signal peak detection circuit, which relates to the field of detection circuits, and comprises a digital logic control part, an analog part and a digital part, the analog part comprises a plurality of subunits, each subunit comprises a peak detection circuit part and a low-speed ADC (Analog to Digital Converter) part, each subunit is connected with the digital part through a main switch WSEL, and the peak detection circuit part is composed of an error amplifier sharing a differential input tube, a peak level sampling read-out buffer, a holding capacitor Ch, a plurality of subswitches, a bias current source, a reset voltage source V1 and an output buffer drive circuit. According to the utility model, peak value measurement and quantification of narrow pulse width echo signals are realized by combining the peak value holding circuit and the low-speed ADC circuit, and the cost area and the power consumption of a laser ranging system are reduced.

Description

Technical Field

[0001] The utility model relates to the field of peak detection circuits, in particular to a low-cost laser pulse signal peak detection circuit. Background Art

[0002] The principle of laser TOF ranging mainly includes the laser emitting laser pulses. The echo signal after reflection from the target is received by the photodetector. The echo time is obtained by processing the photocurrent signal and the target distance information is calculated. The echo signal amplitude will affect the moment when the echo crosses the threshold and cause wandering error. In order to obtain the grayscale information of the echo, it is necessary to measure the peak voltage of the echo signal.

[0003] The existing peak detection scheme used in the field of nanosecond-level modulated narrow pulse TOF laser ranging is mainly realized by high-speed ADC combined with high-precision delay passive devices. The sampling of the peak moment of this scheme is fixed relative to the time of echo threshold determination. In laser ranging of complex target scenes, the pulse width of the target echo will change significantly, so the error of peak detection is large. At the same time, the hardware scale of this scheme is large. In the ranging of scenes such as woods, shrubs, house windows, and overhead cables, the target has the characteristics of multiple echo reflections, and multiple echoes need to be collected for one laser measurement. Therefore, the peak detection scheme based on high-speed ADC sampling has poor scalability and cannot realize peak detection of multi-echo targets. The utility model designs a low-cost laser pulse signal peak detection circuit. Utility Model Content

[0004] The utility model aims to solve the shortcomings in the prior art and proposes a low-cost laser pulse signal peak detection circuit.

[0005] In order to achieve the above purpose, the utility model adopts the following technical solutions:

[0006] A low-cost laser pulse signal peak detection circuit comprises a digital logic control part, an analog part and a digital part, wherein the analog part comprises a plurality of subunits, each of the subunits comprises a peak detection circuit part and a low-speed ADC part, each of the subunits is connected to the digital part through a main switch WSEL, the peak detection circuit part is composed of an error amplifier and a peak level sampling readout buffer of a shared differential input tube, a holding capacitor Ch, a plurality of sub-switches, a bias current source, a reset voltage source V1 and an output buffer driving circuit, wherein the error amplifier and the readout buffer of the shared differential input tube are composed of a tail current source I1, differential input NMOS field effect transistors M1 and M2, error amplifier load PMOS field effect transistors M3 and M4, and readout buffer load PMOS field effect transistors M7 and M8, wherein the sub-switches comprise S1, S2, S3, S4, S7, S8 and S9.

[0007] Preferably, the basic modules of the low-speed ADC respectively include:

[0008] Sample and hold circuit: samples and holds the input signal;

[0009] DAC: adjusts the output voltage according to the output of the control logic;

[0010] Comparator: amplifies the voltage output by the DAC and outputs the comparison result;

[0011] Control logic: adjusts the output voltage of the DAC and outputs data according to the output of the comparator.

[0012] Preferably, the sub-switches S3, S4, S7 are set to be in a reset state when they are closed (other switches are opened), and the level of the holding capacitor Ch is reset to an initial (reset) level V1.

[0013] Preferably, when the sub-switches S1, S2, and S8 are closed (other switches are open), they are in a write state. At this time, the circuit is configured as a two-stage amplifier with unity gain negative feedback as an error amplifier, the first stage is a classic five-tube amplifier, and the second stage is a simple inverting amplifier including a pull-up current source and a holding capacitor Ch. The error amplifier can unidirectionally charge the holding capacitor Ch to realize the functions of peak detection and holding, wherein M1 and M2 are differential input pair tubes of the first stage; M3 and M4 are active loads of the first stage amplifier as current mirrors; and M6 is the input tube of the second stage amplifier, which is used to charge the holding capacitor Ch.

[0014] Preferably, the switches S3, S4, and S9 are closed (other switches are disconnected) to form a read state, at which time the pulse input signal is disconnected, and the circuit is configured as a unit negative feedback two-stage amplifier with a sampling capacitor Ch as input as a readout buffer, wherein the differential input pair of the first stage is shared with the error amplifier, and the second stage amplifier is used to provide a larger load capacity and a larger output swing.

[0015] Compared with the prior art, the utility model has the following advantages:

[0016] The utility model realizes the peak value measurement and quantification of the narrow pulse width echo signal by combining the peak value holding circuit with the low-speed ADC circuit, thereby reducing the cost, area and power consumption of the laser ranging system. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 This is a schematic diagram of a low-cost laser pulse signal peak detection circuit proposed by the utility model.

[0018] Figure 2 This is a working timing diagram of the utility model.

[0019] Figure 3 It is the application structure diagram in the utility model.

[0020] Figure 4 This is the circuit structure diagram of the peak detection circuit.

[0021] Figure 5 This is a working principle diagram of ADC in the present invention. DETAILED DESCRIPTION

[0022] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all of the embodiments. Example

[0023] The utility model adopts a solution combining a peak detection circuit with a low-speed ADC, including a digital logic control part, such as Figure 1 As shown, it is divided into an analog part and a digital part. The analog part includes multiple sub-units, each of which includes a peak detection circuit part (PDH module in the figure) and a low-speed ADC part (ADC module in the figure). Each of the sub-units is connected to the digital part through a main switch WSEL, and is used to control the state switching of the utility model circuit through digital control logic.

[0024] The PDH circuit is composed of an error amplifier and a peak level sampling readout buffer that share a differential input tube, a sampling and holding capacitor, a switch tube, a bias current source, a reset reference voltage source, and an output buffer drive circuit. The error amplifier and the readout buffer that share a differential input tube are composed of a tail current source I1, differential input NMOS field effect transistors M1 and M2, error amplifier load PMOS field effect transistors M3 and M4, and readout buffer load PMOS field effect transistors M7 and M8.

[0025] The system architecture diagram of ADC is as follows Figure 5 As shown, the basic modules and functions are described as follows: sample and hold circuit: sample and hold the input signal; DAC: adjust the output voltage according to the output of the control logic; comparator: amplify the voltage output by the DAC and output the comparison result; control logic: adjust the output voltage of the DAC according to the output of the comparator and output the data.

[0026] like Figure 4 In the reset state, Figure 4 The switches S3, S4, and S7 are closed (conducted) (other switches are open). At this time, the level of the sampling and holding capacitor Ch is reset to the initial (reset) level V1. After the reset state ends, the PDH circuit switches to the write state. In the write state, the main function of the circuit is to detect and hold the peak value of the pulse input voltage. Figure 4 The switches S1, S2, and S8 are closed (conducting) (other switches are open). By selecting the switches, the core circuit is configured as a two-stage amplifier with unity gain negative feedback as an error amplifier. The first stage is a classic five-tube amplifier, and the second stage is a simple inverting amplifier containing a pull-up current source and a peak holding capacitor. The error amplifier can charge the holding capacitor unidirectionally to realize the peak detection and holding function. Among them, M1 and M2 are the differential input pair of tubes of the first stage; M3 and M4 are the active loads of the first stage amplifier as current mirrors; M6 is the input tube of the second stage amplifier, which is used to charge the peak holding capacitor Ch.

[0027] In the utility model, the circuit operation sequence of each sub-unit is as follows: Figure 2 As shown, there are three states, namely reset (RST), write state (Write) and read state (Read). The reset state is controlled by rst_phase, and the high level is valid. During reset, the read and write control signal rd_phase must be in the write state of low level. In the reset state, all the capacitors storing the peak amplitude in the analog circuit part are reset to the initial level. In order to meet the capacitor full discharge reset, the reset state duration needs to be greater than 50ns.

[0028] Keep rd_phase at 0, and switch to the write state when rst_phase jumps from 1 to 0. At this time, the first PDH subunit has been selected and can receive and store the echo peak. After the first echo ends, the falling edge of the echo is used to trigger the digital circuit part to control the write selection signal WSEL to switch to the next PDH subunit.

[0029] Keep rst_phase at 0, and after rd_phase jumps from 0 to 1, enter the read state. In the read state, the four PDH subunits simultaneously output four echo peaks. The output buffer circuit has a 2x amplification, so the VOUT voltage is twice the peak amplitude maintained by the PDH unit. In the read state, when ADC_SOC jumps from 0 to 1, it enters the sampling state. When ADC_SOC jumps from 1 to 0, it indicates that the sampling is completed and the ADC performs data quantization. When ADC_EOC jumps from 0 to 1, it indicates that the quantization is completed and the ADC output is valid.

[0030] The utility model adopts the FPGA solution as follows Figure 3 As shown. The input analog pulse Vpulse is coupled to "VIN" through a 10nF capacitor, and the input operating point of "VIN" is generated on-chip. FPGA, as the control unit of PDH, generates "rst_phase", "rd_phase", "ADCLK" and "WTRIG" to control the working state and peak level readout of PDH, and controls the ADC to collect the readout level VOUT of PDH, and finally inputs the quantized data DIN into FPGA for data storage and processing.

[0031] When in use, in the reset state, the RST signal is high and the Rpwn signal is low. The voltage value of the sampling capacitor in the peak detection circuit is reset to a fixed level. At this time, all switches from the input signal to the peak detection circuit are closed. In the write state, the RST signal is low, Rpwn is low, and the switch WSEL <0> When the pulse signal VIN arrives in the write state, WTRIG is triggered when the falling edge of the first echo signal of VIN arrives, and the switch WSEL is turned on through the digital control logic. <0> Turn off and switch WSEL <1> When the falling edge of the second echo signal of VIN arrives, WTRIG is triggered, and the switch WSEL is turned on through the digital control logic. <1> Turn off and switch WSEL <2> When the falling edge of the third echo signal of VIN arrives, WTRIG is triggered, and the switch WSEL is turned on through the digital control logic. <2> Turn off and switch WSEL <3> When the falling edge of the fourth echo signal of VIN arrives, WTRIG is triggered, and the switch WSEL is turned on through the digital control logic. <3> In the read state, the RST signal is at a low level, and the Rpwn signal is at a high level. In the read state, the SAR ADC quantizes the peak voltage collected by the peak detection circuit and outputs Data1, Data2, Data3, and Data4 respectively. The utility model circuit can realize the peak detection and quantization of the serial four-echo.

[0032] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can make equivalent replacements or changes within the technical scope disclosed by the present invention according to the technical scheme and the utility model concept of the present invention, which should be covered by the protection scope of the present invention.

Claims

1. A low-cost laser pulse signal peak detection circuit, including a digital logic control part, characterized in that: The analog part includes an analog part and a digital part. The analog part includes a plurality of sub-units. Each of the sub-units includes a peak detection circuit part and a low-speed ADC part. Each of the sub-units is connected to the digital part through a main switch WSEL. The peak detection circuit part is composed of an error amplifier and a peak level sampling readout buffer of a shared differential input tube, a holding capacitor Ch, a plurality of sub-switches, a bias current source, a reset voltage source V1, and an output buffer driving circuit. The error amplifier and the readout buffer of the shared differential input tube are composed of a tail current source I1, differential input NMOS field effect transistors M1 and M2, error amplifier load PMOS field effect transistors M3 and M4, and readout buffer load PMOS field effect transistors M7 and M8. The sub-switches include S1, S2, S3, S4, S7, S8, and S9.

2. A low-cost laser pulse signal peak detection circuit according to claim 1, characterized in that: The basic modules of the low-speed ADC include: Sample and hold circuit: samples and holds the input signal; DAC: adjusts the output voltage according to the output of the control logic; Comparator: amplifies the voltage output by the DAC and outputs the comparison result; Control logic: adjusts the output voltage of the DAC and outputs data according to the output of the comparator.

3. The low-cost laser pulse signal peak detection circuit according to claim 1, characterized in that: The sub-switches S3, S4, and S7 are set to be closed, and the other switches are opened to be in a reset state, and the level of the holding capacitor Ch is set to be reset to an initial level V1.

4. The low-cost laser pulse signal peak detection circuit according to claim 1, characterized in that: The sub-switches S1, S2, and S8 are set to be closed, and the other switches are opened in the write state. At this time, the circuit is configured as a two-stage amplifier with unity gain negative feedback as an error amplifier, the first stage is a classic five-tube amplifier, and the second stage is a simple inverting amplifier including a pull-up current source and a holding capacitor Ch. The error amplifier can unidirectionally charge the holding capacitor Ch to realize the functions of peak detection and holding, wherein M1 and M2 are the differential input pair of tubes of the first stage; M3 and M4 are the active loads of the first-stage amplifier as current mirrors; M6 is the input tube of the second-stage amplifier, which is used to charge the holding capacitor Ch.

5. The low-cost laser pulse signal peak detection circuit according to claim 1, characterized in that: The switches S3, S4, and S9 are set to be closed, and the other switches are opened to be in the reading state. At this time, the pulse input signal is disconnected, and the circuit is configured as a unit negative feedback two-stage amplifier with a sampling capacitor Ch as an input as a readout buffer, wherein the differential input pair of the first stage is shared with the error amplifier, and the second stage amplifier is used to provide a larger load capacity and a larger output swing.

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