Chip packaging structure
The chip packaging structure addresses poor current sharing by connecting power device terminals through specific wires to distinct substrate areas, reducing parasitic inductance and improving current sharing and reliability in high-power applications.
Patent Information
- Application Number
- CN202420028570.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-01-04
- Publication Date
- 2024-12-17
- Estimated Expiration
- 2034-01-04
AI Technical Summary
Current semiconductor technologies face challenges in achieving high-power output due to poor current sharing among multiple chips connected in parallel, leading to inconsistent gate voltages and parasitic inductances that affect the performance and reliability of power devices.
A chip packaging structure that electrically connects the input and output terminals of power devices through first and second connecting wires, with the second ends connected to distinct metal areas on a packaging substrate, reducing parasitic inductance and improving current sharing by increasing circuit paths and reducing impedance.
Enhances current sharing consistency, reduces junction temperature differences, improves output capacity, and increases the long-term reliability of power devices by eliminating potential differences and thermal stress, while maintaining thermal performance.
Smart Images
Figure CN222190715U_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a chip packaging structure. Background Art
[0002] Power chips are usually used in electric drive controllers for new energy vehicles. Industry applications are increasingly demanding high-power applications. The power output capacity of a single chip is limited, and high-power output can only be achieved by connecting multiple chips in parallel. However, in related technologies, the current sharing of multiple chips in parallel is poor. Utility Model Content
[0003] In order to overcome the problems existing in the related art, the present disclosure provides a chip packaging structure.
[0004] According to a first aspect of an embodiment of the present disclosure, a chip packaging structure is provided, the chip packaging structure comprising a plurality of power devices, a plurality of first connection wires, a packaging substrate and a second connection wire, wherein:
[0005] The first input and output terminals of each of the plurality of power devices are respectively electrically connected to the first terminals of the respective first connecting wires, and the first input and output terminals are electrically connected together through the second connecting wires;
[0006] The second end of each of the first connecting wires is electrically connected to the first metal area of the packaging substrate;
[0007] The second input and output terminals of each of the power devices are electrically connected to the second metal region of the packaging substrate, wherein the first metal region is not electrically connected to the second metal region.
[0008] Optionally, the width of the first metal area is greater than 3 mm.
[0009] Optionally, the width of the first metal area is greater than 4.5 mm.
[0010] Optionally, a width of an electrical connection surface between the second end of the first connecting line and the first metal area is greater than 3 mm.
[0011] Optionally, a width of an electrical connection surface between the second end of the first connection line and the first metal region is the same as a width of the power device.
[0012] Optionally, the first connecting wire and the second connecting wire are strips or bonding wires.
[0013] Optionally, the packaging substrate is an active metal brazing substrate.
[0014] Optionally, the power device is a power MOSFET.
[0015] Optionally, the plurality of first connecting lines are parallel.
[0016] Optionally, the second connecting line is located above the first input and output terminals.
[0017] By adopting the above technical solution, since the first input and output terminals of each power device in the multiple power devices are respectively electrically connected to the first ends of their respective first connecting lines, the first input and output terminals are electrically connected together through the second connecting lines, the second ends of the first connecting lines are electrically connected to the first metal area of the packaging substrate, and the second input and output terminals of the power devices are electrically connected to the second metal area of the packaging substrate, wherein the first metal area is not electrically connected to the second metal area. Therefore, by using the second connecting line to electrically connect the first input and output terminals together, the circuit path is increased and the value of the parasitic inductance is reduced, the impedance of the first input and output terminals of different power devices is reduced, and the potential difference between the first input and output terminals of different power devices is reduced, thereby improving the consistency of the gate voltage of each power device, and ultimately significantly improving the current sharing.
[0018] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS
[0019] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the present disclosure.
[0020] Figure 1 It is a schematic diagram of a packaging structure of multiple power devices in parallel in the related technology.
[0021] Figure 2 yes Figure 1 Equivalent circuit diagram of the package structure shown.
[0022] Figure 3 is a schematic diagram showing a chip packaging structure according to an exemplary embodiment of the present disclosure.
[0023] Figure 4 It is a cross-sectional schematic diagram of a chip packaging structure according to an embodiment of the present disclosure. DETAILED DESCRIPTION
[0024] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present disclosure. Instead, they are merely examples of devices and methods consistent with some aspects of the present disclosure as detailed in the appended claims.
[0025] It should be noted that all actions of acquiring signals, information or data in the present disclosure are carried out in compliance with the relevant data protection laws and policies of the country where the device is located and with the authorization given by the owner of the corresponding device.
[0026] Figure 1 It is a schematic diagram of the packaging structure of multiple power devices in parallel in the related art. Power device 1, power device 2 and power device 3 are three SiC MOSFET chips. Strip 4, strip 5 and strip 6 are power copper bars, which are used to connect the source electrode on the upper surface of SiCMOSFET and the power output source end respectively. Strip 4, strip 5 and strip 6 are arranged in parallel, and power device 1, power device 2 and power device 3 are placed in the same row. The parasitic inductance between strip 4, strip 5 and strip 6 will cause the source electrodes of power device 1, power device 2 and power device 3 to not be of the same potential, thereby causing driving inconsistency, and ultimately resulting in poor current sharing, and the uneven current degree is usually more than 30%.
[0027] Figure 2 yes Figure 1 The equivalent circuit diagram of the package structure shown. Among them, parasitic inductances L8, L9, L10 and L13 are common paths for all power devices Q1, Q2 and Q3, and have nothing to do with the current sharing. Parasitic inductances L6 and L7 are caused by the physical spacing of the drain of the power device. Since the drain of the power device is connected to the upper copper layer of the active metal brazing (AMB) substrate through silver sintering, this part of the copper layer is usually wider, so the actual parasitic inductance values of parasitic inductances L6 and L7 are small, about 0.2~0.3nH, and have little effect on current sharing. And due to thermal coupling, considering that at least 2~3mm spacing must be left between power devices, this part of the parasitic inductance cannot be further reduced in actual production. Parasitic inductances L1, L2 and L3 are the parasitic inductances of clip 1, clip 5 and clip 6. The parasitic inductances are determined by the physical size of the clips. In parallel applications, only L1 = L2 = L3 is needed to achieve ideal current sharing. There is no special requirement for the size of this part. Parasitic inductances L4 and L5 are Figure 1 The parasitic inductance caused by the distances LL1 and LL2 in the physical space can lead to inconsistent gate-level drive voltages of SiC MOSFETs, that is, inconsistent voltages on capacitors C1, C2, and C3, which ultimately leads to poor current sharing.
[0028] Figure 3 Schematic diagram of a chip packaging structure according to an exemplary embodiment of the present disclosure. The chip packaging structure can be applied to the functional development of similar power electronic products such as motor controllers, new energy vehicles, traction locomotives, and photovoltaics, especially to the development of power devices. Figure 3 As shown, the chip packaging structure according to the embodiment of the present disclosure may include a plurality of power devices 101 to 10 n (denoted by reference numeral 10), a plurality of first connecting lines 201 to 20 n (collectively denoted by reference numeral 20 ), a packaging substrate 40 and a second connection line 30 .
[0029] The plurality of power devices 101 to 10 n The first input and output terminals of each power device are respectively electrically connected to the first ends of their respective first connecting wires, and the first input and output terminals are electrically connected together through the second connecting wire 30. In addition, the plurality of first connecting wires 201 to 20 n The second connection line 30 may be located above the first input and output terminals.
[0030] Each of the first connecting lines 201 to 20 n The second end is electrically connected to the first metal region 401 of the packaging substrate 40 .
[0031] Each of the power devices 101 to 10 n The second input-output terminal is electrically connected to the second metal area 402 of the packaging substrate 40, wherein the first metal area 401 is not electrically connected to the second metal area 402.
[0032] Power Devices 101 to 10 n It can be a power MOSFET or other power devices. Taking power MOSFET as an example, the first input and output terminal of the power device can be the source of the power MOSFET or the drain of the power MOSFET; the second input and output terminal of the power device can be the drain of the power MOSFET or the source of the power MOSFET.
[0033] The second connection line 30 and the first connection lines 201 to 20 n It can be in the form of strips, bonding wires, or other forms.
[0034] The packaging substrate 40 may be any type of packaging substrate, such as an AMB substrate. Taking the AMB substrate as an example, the first metal region 401 and the second metal region 402 of the packaging substrate 40 may be located on the same surface (e.g., the upper surface) of the packaging substrate 40, and the first metal region 401 and the second metal region 402 may be two different regions on the upper surface of the AMB substrate.
[0035] By adopting the above technical solution, since the first input and output terminals of each power device in the plurality of power devices are respectively electrically connected to the first ends of the respective first connecting wires, the first input and output terminals are electrically connected together through the second connecting wires, the second ends of the first connecting wires are electrically connected to the first metal area of the packaging substrate, and the second input and output terminals of the power devices are electrically connected to the second metal area of the packaging substrate, wherein the first metal area is not electrically connected to the second metal area. Therefore, by using the second connecting wires to electrically connect the first input and output terminals together, the circuit path is increased and the Figure 2 The values of parasitic inductances L4 and L5 shown in the figure reduce the impedance of the first input and output terminals of different power devices, reduce the potential difference of the first input and output terminals of different power devices, thereby improving the consistency of the gate voltage of each power device, and finally significantly improving the current sharing. In addition, the chip packaging structure according to the embodiment of the present disclosure does not need to sacrifice the thermal performance of the power device; by improving the current sharing, the junction temperature of the worst power device is reduced, and the output capacity of the power device is improved (because the output capacity of multiple power devices packaged in parallel is usually determined by the worst power device); by improving the current sharing, the temperature difference of different power devices is reduced, so that the temperature balance is achieved between the power devices, the thermal stress of the worst power device is reduced, the failure risk is reduced, and the long-term operation reliability of the power device is improved; the consistency of the driving potential is improved, the adverse effects of the circulating current between the drives of different power devices are eliminated, the mutual interference and failure risk of the drives are reduced, and the long-term operation reliability of the power devices is improved. In addition, the chip packaging structure according to the embodiment of the present disclosure has a wide applicability, not only suitable for strip-type connections, but also suitable for bonding wire connections, not only suitable for Kelvin connections, but also suitable for non-Kelvin connections. For Kelvin connections, differences in source potential of power devices can also lead to inconsistent gate voltages. This is because physically, there is a physical connection between the power loop and the source of the drive loop. Inconsistent source potentials can cause unbalanced currents at the drive source end. The chip packaging structure according to the embodiment of the present disclosure can eliminate this gate voltage inconsistency.
[0036] Next, taking the power device 10 as a power MOSFET and the package substrate 40 as an AMB substrate as an example, the chip packaging structure according to the embodiment of the present disclosure is described. The first input and output terminals of the power device 10 are electrically connected to the first end of the first connecting wire 20, for example, they can be electrically connected by a welding process or other connection methods. The first input and output terminals of each power device 10 are electrically connected together through a second connecting wire 30. The second end of the first connecting wire 20 is electrically connected to the first metal area 401 of the package substrate 40, for example, it can be electrically connected by a welding process or other connection methods. The second input and output terminals of the power device 10 are electrically connected to the second metal area 402 of the package substrate 40, for example, it can be electrically connected by a silver sintering process or other connection methods. The first metal area 401 is not electrically connected to the second metal area 402. The first input and output terminal of the power device 10 can be a source, which can be located on the upper surface of the power device 10. The second input and output terminal of the power device 10 can be a drain, which can be located on the lower surface of the power device 10. The first metal region 401 can be used as a power source terminal, and the second metal region 402 can be used as a power drain terminal. The first metal region 401 and the second metal region 402 can both be regions on the upper surface of the AMB substrate.
[0037] In some embodiments, the width of the first metal region 401 is greater than 3 mm, preferably greater than 4.5 mm. Figure 3 The width marked with the label y in .
[0038] By widening the width of the first metal region 401 and combining the common connection of the first input and output terminals (that is, each first input and output terminal is electrically connected together through the second connecting line 30), the current uniformity can be effectively improved, thereby reducing the junction temperature of the worst power device, improving the output capacity of the power device, reducing the temperature difference between different power devices, reducing the thermal stress of the worst power device, reducing the risk of failure, improving the reliability of long-term operation of the power device, improving the consistency of the driving potential, eliminating the adverse effects of the circulating current between different power device drivers, and reducing the mutual interference and failure risk of the drivers.
[0039] In some embodiments, the first connection lines 201 to 20 n The width of the electrical connection surface between the second end of the first metal area 401 and the first metal area 401 is greater than 3 mm. n The width of the electrical connection surface between the second end of the first metal region 401 and the power devices 101 to 10 n The same width.
[0040] The first connecting line 201 to 20 n The electrical connection surface between the second end of and the first metal region 401 refers to Figure 3 An area filled with diagonal lines.
[0041] In addition, in the chip packaging structure disclosed in the present invention, the first connecting lines 201 to 20 n The width of the electrical connection surface between the second end of the first metal region 401 and the first input and output ends are electrically connected together through the second connection line 30. Alternatively, the first connection lines 201 to 20 n The width of the electrical connection surface between the second end of the first metal region 401 and the first input and output ends are electrically connected together through the second connection line 30, and the width of the first metal region 401 is widened. Alternatively, the first input and output ends are electrically connected together through the second connection line 30, and the width of the first metal region 401 is widened.
[0042] By widening the first connecting lines 201 to 20 n The second end of the first metal region 401 is electrically connected to the surface of the first metal region 401, and combined with the common connection of the first input and output terminals (that is, the first input and output terminals are electrically connected together through the second connecting line 30), and more preferably further combined with the widening of the width of the first metal region 401, it can effectively improve the current uniformity, thereby reducing the junction temperature of the worst power device, improving the output capacity of the power device, reducing the temperature difference between different power devices, reducing the thermal stress of the worst power device, reducing the risk of failure, improving the reliability of long-term operation of the power device, improving the consistency of the driving potential, eliminating the adverse effects of the circulating current between the drivers of different power devices, and reducing the mutual interference and failure risk of the drivers.
[0043] Figure 4 It is a cross-sectional schematic diagram of a chip packaging structure according to an embodiment of the present disclosure. Figure 4 In the example, the package substrate takes the AMB substrate as an example, and the power device takes the power MOSFET as an example. Figure 4 As shown, the first connecting line 20 is a connecting line between the upper surface source of the power device 10 and the upper surface copper layer 401 of the AMB substrate 40. The first connecting line 20 is connected to the upper surface source of the power device 10 through a welding process. The first connecting line 20 is connected to the upper surface copper layer 401 of the AMB substrate 40 through a welding process. The power device 10 is a SiC MOSFET power device. The lower surface drain of the power device 10 is connected to the upper surface copper layer 401 of the AMB substrate 40 through a silver sintering process (for example, a welding layer 400). The AMB substrate 40 includes an upper surface copper layer 401, a lower surface copper layer 402 and an intermediate medium 403. The intermediate medium 403 is generally a Si3N4 material. The bottom of the AMB substrate 40 is connected to the heat sink 80 through a welding process (for example, a welding layer 70).
[0044] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the present disclosure. The present disclosure is intended to cover any variations, uses or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The description and examples are to be considered as exemplary only, and the true scope and spirit of the present disclosure are indicated by the following claims.
[0045] It should be understood that the present disclosure is not limited to the exact structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.
Claims
1. A chip packaging structure, characterized in that: The chip packaging structure includes a plurality of power devices, a plurality of first connection wires, a packaging substrate, and a second connection wire, wherein: The first input and output terminals of each of the plurality of power devices are respectively electrically connected to the first terminals of the respective first connecting wires, and the first input and output terminals are electrically connected together through the second connecting wires; The second end of each of the first connecting wires is electrically connected to the first metal area of the packaging substrate; The second input and output terminals of each of the power devices are electrically connected to the second metal region of the packaging substrate, wherein the first metal region is not electrically connected to the second metal region.
2. The chip packaging structure according to claim 1, characterized in that: The width of the first metal area is greater than 3 mm.
3. The chip packaging structure according to claim 1, characterized in that: The width of the first metal area is greater than 4.5 mm.
4. The chip packaging structure according to any one of claims 1 to 3, characterized in that: The width of the electrical connection surface between the second end of the first connecting line and the first metal area is greater than 3 mm.
5. The chip packaging structure according to any one of claims 1 to 3, characterized in that: The width of the electrical connection surface between the second end of the first connection line and the first metal area is the same as the width of the power device.
6. The chip packaging structure according to claim 1, characterized in that: The first connection line and the second connection line are strips or bonding wires.
7. The chip packaging structure according to claim 1, characterized in that: The packaging substrate is an active metal brazing substrate.
8. The chip packaging structure according to claim 1, characterized in that: The power device is a power MOSFET.
9. The chip packaging structure according to claim 1, characterized in that: The plurality of first connection lines are parallel.
10. The chip packaging structure according to claim 1, characterized in that: The second connecting line is located above the first input and output terminals.