Voltage stabilizing circuit
By using two current mirror circuits and level adjustment modules in the voltage stabilization circuit, the problems of complex circuits and unstable output voltages in the prior art are solved, and the circuit structure is simplified and the output voltage stability is improved.
Patent Information
- Application Number
- CN202421127532.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-05-22
- Publication Date
- 2024-12-31
- Estimated Expiration
- 2034-05-22
AI Technical Summary
The existing voltage-regulating circuits are complex and the output voltage is unstable, which affects the overall performance of the circuit.
A voltage stabilization circuit structure is adopted that includes two current mirror circuits and a level adjustment module, wherein the current mirror circuit ensures stability of the output voltage through proportional control and level adjustment modules.
It realizes simplification of the circuit structure and cost reduction, while ensuring the stability of the output voltage and improving overall performance.
Smart Images
Figure CN222281121U_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of integrated circuit design, and in particular to a voltage stabilizing circuit. Background Art
[0002] The performance of power supply is becoming more and more demanding with the widespread application of portable electronic products. As an important input voltage management module, linear regulated power supply is widely used in chip design due to its low noise, low cost, fast transient characteristics and other characteristics.
[0003] Typical voltage stabilization circuits in the prior art, such as Figure 1 As shown, the current i1 flows into the output end of the load unit 120 through the ninth transistor MN1, the eleventh transistor MN3, the seventh transistor MP4, and the eighth transistor MP5, and the current i2 flows into the output end of the load unit 120 through the tenth transistor MN2 and the twelfth transistor MN4, wherein the ninth transistor MN1 and the eleventh transistor MN3 form a pair of current mirrors, the seventh transistor MP4 and the eighth transistor MP5 form a pair of current mirrors, and the tenth transistor MN2 and the twelfth transistor MN4 form a pair of current mirrors, wherein the ratio of the current mirrors formed by the ninth transistor MN1 and the eleventh transistor MN3, the tenth transistor MN2 and the twelfth transistor MN4 are all set to 1:K; the ratio of the current mirror formed by the seventh transistor MP4 and the eighth transistor MP5 is set to 1:1. When the line loss compensation unit 130 is not connected, the reference voltage VREF=VFB, i1=i2, the current flowing through the eighth transistor MP5 is K×i1, and the current flowing through the twelfth transistor MN4 is K×i2, then the output voltage VOUTpad of the linear regulator is at this time VREF×(1+R1 / R2). When the load current is large, the actual output voltage expression is: VOUT=VOUTpad-Iout×Rw.
[0004] The above voltage stabilizing circuit is not only complex in circuit, but also the output voltage is related to the input reference voltage, which affects the stability of the output voltage. Summary of the invention
[0005] In order to solve the deficiencies in the prior art, the purpose of the present application is to provide a voltage stabilizing circuit with a simple structure and good output stability.
[0006] To achieve the above object, the present application provides a voltage stabilizing circuit, comprising: a first transistor, a level adjustment module, a first current mirror circuit, and a second current mirror circuit, wherein:
[0007] A first transistor, a source connected to the common end of the second current mirror circuit, a gate connected to the output end of the second current mirror circuit and one end of the level adjustment module, and a drain configured as a voltage stabilization output end and connected to the input end of the first current mirror circuit;
[0008] The first current mirror circuit has a common end connected to the other end of the level adjustment module and grounded, and an output end connected to the input end of the second current mirror circuit.
[0009] Furthermore, the second current mirror circuit comprises:
[0010] A second transistor, having a source connected to the source of the third transistor and the source of the first transistor, a drain connected to the output end of the first current mirror circuit, and a gate connected to the drain and the output end of the first current mirror;
[0011] The third transistor has a gate connected to the gate of the second transistor and a drain connected to the other end of the level adjustment module.
[0012] Furthermore, the first current mirror circuit comprises:
[0013] a fourth transistor, whose source is connected to one end of the level adjustment module, whose drain is configured as a voltage output node and connected to the drain of the first transistor, and whose gate is connected to the drain;
[0014] A fifth transistor has a source connected to the other end of the level adjustment module, a drain connected to the input end of the second current mirror circuit, and a gate connected to the gate of the fourth transistor.
[0015] Further,
[0016] The first current mirror circuit includes a fourth transistor and a fifth transistor; the second current mirror circuit includes a second transistor and a third transistor;
[0017] a fourth transistor, whose source is connected to the source of the fifth transistor and one end of the level adjustment module, whose drain is configured as a voltage-stabilizing output end and connected to the drain of the first transistor, and whose gate is connected to the drain;
[0018] a fifth transistor, having a drain connected to the drain of the second transistor and a gate connected to the gate of the fourth transistor;
[0019] The second transistor has a source connected to the source of the third transistor and the source of the first transistor, a drain connected to the output end of the first current mirror circuit, and a gate connected to the drain and the drain of the fifth transistor; the third transistor has a gate connected to the gate of the second transistor, and a drain connected to the other end of the level adjustment module.
[0020] Further,
[0021] A voltage adjustment module is also included between the voltage stabilization output terminal and the drain of the fourth transistor.
[0022] Furthermore, the impedance adjustment module includes: an impedance, and an adjustable impedance connected in series with the impedance.
[0023] Furthermore, the impedance is a resistor or a transistor.
[0024] Furthermore, the level adjustment module is a current source or a resistor.
[0025] Compared with the prior art, the voltage stabilizing circuit of the present application has the following beneficial effects:
[0026] The voltage stabilizing circuit of the present application uses only two current mirror circuits, has a simple circuit structure, is low in cost, can output a stable output voltage, and has good stability.
[0027] Other features and advantages of the present application will be set forth in the following description, and in part will become apparent from the description, or may be understood by practicing the present application. BRIEF DESCRIPTION OF THE DRAWINGS
[0028] The accompanying drawings are used to provide a further understanding of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the present application and do not constitute a limitation of the present application. In the accompanying drawings:
[0029] Figure 1 It is a structural schematic diagram of a voltage stabilizing circuit in the prior art;
[0030] Figure 2 This is a schematic diagram of the structure of the voltage stabilizing circuit of Example 1 of the present application;
[0031] Figure 3 This is a schematic diagram of the structure of the voltage stabilizing circuit of Example 2 of the present application;
[0032] Figure 4 This is a schematic diagram of the structure of the voltage stabilizing circuit of Example 3 of the present application. DETAILED DESCRIPTION
[0033] The embodiments of the present application will be described in more detail below with reference to the accompanying drawings. Although certain embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be construed as being limited to the embodiments described herein. Instead, these embodiments are provided to provide a more thorough and complete understanding of the present application. It should be understood that the drawings and embodiments of the present application are only for exemplary purposes and are not intended to limit the scope of protection of the present application.
[0034] It should be understood that the various steps described in the method implementation of the present application can be performed in different orders and / or performed in parallel. In addition, the method implementation may include additional steps and / or omit the steps shown. The scope of the present application is not limited in this respect.
[0035] The term "including" and its variations used herein are open inclusions, i.e., "including but not limited to". The term "based on" means "based at least in part on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". The relevant definitions of other terms will be given in the following description.
[0036] It should be noted that the modifications of "one" and "plurality" mentioned in this application are illustrative rather than restrictive, and those skilled in the art should understand that unless otherwise clearly indicated in the context, it should be understood as "one or more". "Plurality" should be understood as two or more.
[0037] Hereinafter, embodiments of the present application will be described in detail with reference to the accompanying drawings.
[0038] Example 1
[0039] An embodiment of the present application provides a voltage stabilization circuit for improving the output stability of voltage.
[0040] Figure 2 Schematic diagram of the structure of the voltage stabilizing circuit of Example 1 of the present application, such as Figure 2 As shown, the voltage stabilizing circuit of Embodiment 1 of the present application includes:
[0041] The first current mirror circuit 100 has its input terminal connected to the drain of the transistor M1 and the regulated output terminal Vout of the regulated power supply, its output terminal connected to the input terminal of the second current mirror circuit 200, and its common terminal grounded.
[0042] The second current mirror circuit 200 has its input end connected to the output end of the first current mirror circuit 100 , its output end connected to one end of the level adjustment module 300 and the gate of the transistor M1 , and its common end connected to the source of the transistor M1 .
[0043] The other end of the level adjustment module 300 is grounded.
[0044] In this embodiment, the current After passing through the first current mirror circuit 100 and the second current mirror circuit 200, the current source The constant current generated Compare, Control The node voltage stabilizes the regulated output voltage Vout.
[0045] Example 2
[0046] An embodiment of the present application provides a voltage stabilization circuit for improving the output stability of voltage.
[0047] Figure 3 Schematic diagram of the structure of the voltage stabilizing circuit of Example 2 of the present application, such as Figure 3 As shown, the voltage stabilizing circuit of Embodiment 2 of the present application includes:
[0048] The source of the first transistor M1, the source of the second transistor M2, and the source of the third transistor M3 are connected;
[0049] The gate of the first transistor M1 is connected to the drain of the third transistor M3 and the negative electrode of the current source S1;
[0050] The drain of the first transistor M1 is connected to the voltage-stabilized output terminal Vout, the gate and drain of the fourth transistor M4, and the gate of the fifth transistor M5;
[0051] The source of the fourth transistor M4, the source of the fifth transistor M5, and the positive electrode of the current source S1 are grounded;
[0052] The drain of the fifth transistor M5 is connected to the gate, drain and gate of the second transistor M2 and the third transistor M3.
[0053] In the implementation of the present application, the second transistor M2 and the third transistor M3 constitute the second current mirror circuit 200 in Embodiment 1, and the fourth transistor M4 and the fifth transistor M5 constitute the first current mirror circuit 100 .
[0054] In the implementation of the present application, the current source S1 is used as the level adjustment module 300 to pull down the drain level of the third transistor M3. It is understandable that a resistor can also be used as the level adjustment module 300 to pull down the drain level of the third transistor M3.
[0055] In the embodiment of the present application, the drain-source voltage of the fourth transistor M4 is the voltage of the regulated output terminal Vout, and the current By current and the ratio of the first current mirror circuit 100 to the second current mirror circuit 200, so the current The current flowing through the fourth transistor M4 is constant, so the voltage at the voltage-regulated output terminal Vout does not change with the supply voltage VDD and the output current, and has good stability.
[0056] Example 3
[0057] An embodiment of the present application provides a voltage stabilization circuit for improving the output stability of voltage.
[0058] Figure 4 Schematic diagram of the structure of the voltage stabilizing circuit of Example 3 of the present application, as shown in Figure 4 As shown, in the voltage stabilizing circuit of Example 3 of the present application, the second transistor M2 and the third transistor M3 form a second current mirror circuit 200, and the fourth transistor M4 and the fifth transistor M5 form a first current mirror circuit 100. The difference from Example 2 is that a voltage output module is added between the voltage stabilizing output terminal Vout (the drain of the first transistor M1) and the drain of the fourth transistor M4 to adjust the voltage of the voltage stabilizing output terminal Vout.
[0059] In the embodiment of the present application, the voltage output module is composed of an impedance Z and an adjustable impedance Z1 connected in series.
[0060] In the embodiment of the present application, the impedance Z may be a resistor or a transistor.
[0061] The above description is only a partial embodiment of the present application and an explanation of the technical principles used. Those skilled in the art should understand that the scope of disclosure involved in the present application is not limited to the technical solution formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the above disclosed concept. For example, the above features are replaced with the technical features with similar functions disclosed in this application (but not limited to) by each other to form a technical solution.
[0062] In addition, although each operation is described in a specific order, this should not be construed as requiring these operations to be performed in the specific order shown or in a sequential order. Under certain circumstances, multitasking and parallel processing may be advantageous. Similarly, although some specific implementation details are included in the above discussion, these should not be construed as limiting the scope of the application. Some features described in the context of a separate embodiment can also be implemented in a single embodiment in combination. On the contrary, the various features described in the context of a single embodiment can also be implemented in multiple embodiments individually or in any suitable sub-combination mode.
[0063] Although the subject matter has been described in language specific to structural features and / or methodological logical actions, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or actions described above. On the contrary, the specific features and actions described above are merely example forms of implementing the claims.
Claims
1. A voltage stabilizing circuit, characterized in that: include: A first transistor, a level adjustment module, a first current mirror circuit, and a second current mirror circuit, wherein: A first transistor, a source connected to the common end of the second current mirror circuit, a gate connected to the output end of the second current mirror circuit and one end of the level adjustment module, and a drain configured as a voltage stabilization output end and connected to the input end of the first current mirror circuit; The first current mirror circuit has a common end connected to the other end of the level adjustment module and grounded, and an output end connected to the input end of the second current mirror circuit.
2. The voltage stabilizing circuit according to claim 1, characterized in that: The second current mirror circuit comprises: A second transistor, having a source connected to the source of the third transistor and the source of the first transistor, a drain connected to the output end of the first current mirror circuit, and a gate connected to the drain and the output end of the first current mirror; The third transistor has a gate connected to the gate of the second transistor and a drain connected to the other end of the level adjustment module.
3. The voltage stabilizing circuit according to claim 1, characterized in that: The first current mirror circuit comprises: a fourth transistor, whose source is connected to one end of the level adjustment module, whose drain is configured as a voltage output node and connected to the drain of the first transistor, and whose gate is connected to the drain; A fifth transistor has a source connected to the other end of the level adjustment module, a drain connected to the input end of the second current mirror circuit, and a gate connected to the gate of the fourth transistor.
4. The voltage stabilizing circuit according to claim 1, characterized in that: The first current mirror circuit includes a fourth transistor and a fifth transistor; The second current mirror circuit comprises: a second transistor and a third transistor; a fourth transistor, whose source is connected to the source of the fifth transistor and one end of the level adjustment module, whose drain is configured as a voltage-stabilizing output end and connected to the drain of the first transistor, and whose gate is connected to the drain; a fifth transistor, having a drain connected to the drain of the second transistor and a gate connected to the gate of the fourth transistor; The second transistor has a source connected to the source of the third transistor and the source of the first transistor, a drain connected to the output end of the first current mirror circuit, and a gate connected to the drain and the drain of the fifth transistor; the third transistor has a gate connected to the gate of the second transistor, and a drain connected to the other end of the level adjustment module.
5. The voltage stabilizing circuit according to claim 4, characterized in that: A voltage adjustment module is also included between the voltage stabilization output terminal and the drain of the fourth transistor.
6. The voltage stabilizing circuit according to claim 5, characterized in that: The voltage adjustment module includes: an impedance and an adjustable impedance connected in series with the impedance.
7. The voltage stabilizing circuit according to claim 6, characterized in that: The impedance is a resistor or a transistor.
8. The voltage stabilizing circuit according to any one of claims 1 to 7, characterized in that: The level adjustment module is a current source or a resistor.