Bridge chip hybrid bonding packaging structure
Through the hybrid bonding process between Bridge chip and device layer, multi-dimensional interconnection is achieved, which solves the problems of large size, high cost and low integration in the existing technology, improves the integration and yield of the packaging structure, and expands the integration and development of the packaging structure. The scope of application is reduced and process costs are reduced.
Patent Information
- Application Number
- CN202421005687.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-05-09
- Publication Date
- 2024-12-31
- Estimated Expiration
- 2034-05-09
Smart Images
Figure CN222281991U_ABST
Abstract
Description
Technical Field
[0001] The utility model belongs to the field of semiconductor integrated circuit manufacturing and relates to a Bridge chip hybrid bonding packaging structure. Background Art
[0002] With the development of technology, supercomputing ecosystems such as artificial intelligence (AI) and high performance computing (HPC) are widely used. The packaging of supercomputing ecosystems requires integrating data center CPUs, GPUs, and memory into an integrated design. Figure 1 As shown, a hybrid bonding packaging structure includes a first device layer 01, a SOC chip 011, a second device layer 02, a functional chip 021, a first transfer layer 03 (Active Interposerwafer), a second transfer layer 031, a PCB board 04, a first conductive bump 05, a second conductive bump 051 and a packaging layer 06, which adopts a system-level packaging technology (SoIC 3D stacking technology), wherein the bonding scheme of SoIC adopts a hybrid bonding technology, and uses a copper-to-copper connection (Cu-Cu Interconnect) technology to connect the first device layer 01 with the SOC chip 011 to the transfer wafer (Active Interposer wafer) (i.e., the first transfer layer 03), can achieve chip interconnection with a pitch of 10μm or less, provides excellent bonding pitch and scalability, and connects chips more closely together, thereby achieving faster and shorter connections. However, since the dielectric layer of the hybrid bonding interface uses an oxide layer, the cost of the process is relatively high, and since a transfer wafer is used for transfer, the size of the packaging structure is large and the integration is low, which limits the scope of use of the packaging structure.
[0003] Therefore, there is an urgent need to find a Bridge chip hybrid bonding packaging structure that can reduce the size and process cost of the system-level packaging structure and improve the integration of the system-level packaging structure. Summary of the invention
[0004] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a Bridge chip hybrid bonding packaging structure to solve the problems of large size, high process cost and low integration of the system-level packaging structure in the prior art.
[0005] To achieve the above-mentioned and other related purposes, the utility model provides a Bridge chip hybrid bonding packaging structure, including:
[0006] The first device layer comprises a first chip having at least one upper surface provided with a plurality of first electrodes spaced apart from each other;
[0007] A bridge chip, comprising a first transfer electrode disposed on a lower surface and a second transfer electrode disposed on an upper surface, wherein the first transfer electrode is electrically connected to at least one of the first electrodes;
[0008] A second device layer includes a second chip having a second electrode on at least one lower surface, wherein the second electrode is electrically connected to the second transfer electrode;
[0009] An encapsulation layer, covering at least the exposed side walls of the first device layer and the second device layer and the exposed surface of the Bridge chip;
[0010] a conductive column, penetrating the packaging layer above the first device layer and having a bottom end electrically connected to the first electrode;
[0011] a rewiring layer, located on the upper surface of the packaging layer and electrically connected to the top of the conductive pillar;
[0012] The conductive bump is located on the upper surface of the rewiring layer and is electrically connected to the pad in the rewiring layer.
[0013] Optionally, the first chip further includes a first chip body and a first dielectric layer covering an upper surface of the first chip body, and the first electrode penetrates the first dielectric layer.
[0014] Optionally, the first chip includes a SOC chip.
[0015] Optionally, the devices in the Bridge chip include active devices and passive devices.
[0016] Optionally, a second dielectric layer is provided on the lower surface of the Bridge chip, and the first transfer electrode passes through the second dielectric layer.
[0017] Optionally, the material at the hybrid bonding interface between the first device layer and the Bridge chip is the same.
[0018] Optionally, the material of the first switching electrode is the same as that of the first electrode.
[0019] Optionally, the material of the second electrode is the same as that of the second switching electrode.
[0020] Optionally, upper surfaces of the packaging layer, the conductive pillars and the second device layer are flush.
[0021] Optionally, the rewiring layer includes at least one alternately stacked conductive interconnect layer and dielectric layer, the conductive bump is electrically connected to the conductive interconnect layer on the top layer of the rewiring layer, and the conductive column is electrically connected to the conductive interconnect layer on the bottom layer of the rewiring layer.
[0022] As described above, the Bridge chip hybrid bonding packaging structure of the utility model replaces the transfer wafer for transfer interconnection between multiple chips in the packaging structure with the Bridge chip, and the Bridge chip is bonded to the first device layer and the second device layer for transfer through a hybrid bonding process, so that the chips can be stacked in multiple layers, and multi-dimensional interconnection of multiple chips is achieved, thereby improving the integration and yield of the packaging structure, reducing the size of the packaging structure, and expanding the application field of the packaging structure. In addition, since the hybrid bonding interface between the Bridge chip and the first device layer and the second device layer can be transformed from nitride and oxide dielectric layers to organic dielectric layers, the cost of the process is reduced, and it has a high industrial utilization value. BRIEF DESCRIPTION OF THE DRAWINGS
[0023] Figure 1 Shown is a schematic cross-sectional structure diagram of a hybrid bonding packaging structure.
[0024] Figure 2 Shown is a schematic cross-sectional structure diagram of the Bridge chip hybrid bonding packaging structure of the present invention.
[0025] Description of Figure Numbers
[0026] 01 First device layer
[0027] 011 SOC chip
[0028] 02 Second device layer
[0029] 021 Functional Chip
[0030] 03 First transfer layer
[0031] 031 Second transfer layer
[0032] 04 PCB board
[0033] 05 First conductive bump
[0034] 051 Second conductive bump
[0035] 06 Encapsulation layer
[0036] 1 First device layer
[0037] 11 First Chip
[0038] 111 First chip body
[0039] 112 first dielectric layer
[0040] 12. First electrode
[0041] 121 First extraction electrode
[0042] 2 Bridge chip
[0043] 21 First transfer electrode
[0044] 22 Second transfer electrode
[0045] 23. Second dielectric layer
[0046] 3 Second device layer
[0047] 31 Second Chip
[0048] 311 Second chip body
[0049] 312 third dielectric layer
[0050] 32. Second electrode
[0051] 321 Second extraction electrode
[0052] 4 Encapsulation layer
[0053] 5 Conductive pillars
[0054] 6 Rewiring Layers
[0055] 7 Conductive bumps DETAILED DESCRIPTION
[0056] The following is an explanation of the implementation of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific implementations, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.
[0057] See also Figure 2 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the utility model in a schematic manner, and the drawings only show the components related to the utility model rather than the number, shape and size of the components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.
[0058] Embodiment 1
[0059] This embodiment provides a Bridge chip hybrid bonding packaging structure, such as Figure 2As shown, it is a schematic diagram of the cross-sectional structure of the hybrid bonding packaging structure of the Bridge chip, comprising: a first device layer 1, a Bridge chip 2, a second device layer 3, a packaging layer 4, a conductive column 5, a rewiring layer 6 and a conductive bump 7, wherein the first device layer 1 comprises a first chip 11 having at least one upper surface provided with a plurality of first electrodes 12 arranged at intervals; the Bridge chip 2 comprises a first transfer electrode 21 arranged on the lower surface and a second transfer electrode 22 arranged on the upper surface, the first transfer electrode 21 being electrically connected to at least one of the first electrodes 12; the second device layer 3 comprises at least one A second chip 31 is provided with a second electrode 32 on the lower surface, and the second electrode 32 is electrically connected to the second transfer electrode 22; the packaging layer 4 at least covers the exposed side walls of the first device layer 1 and the second device layer 3 and the exposed surface of the Bridge chip 2; the conductive column 5 passes through the packaging layer 4 above the first device layer 1 and the bottom end is electrically connected to the first electrode 12; the rewiring layer 6 is located on the upper surface of the packaging layer 4 and is electrically connected to the top of the conductive column 5; the conductive bump 7 is located on the upper surface of the rewiring layer 6 and is electrically connected to the pad in the rewiring layer 6.
[0060] As an example, the first chip 11 further includes a first chip body 111 and a first dielectric layer 112 covering an upper surface of the first chip body 111 , and the first electrode 12 penetrates the first dielectric layer 112 .
[0061] Specifically, the first dielectric layer 112 is used to protect the first electrode 12 in the first chip 11. Under the condition of ensuring the performance of the packaging structure, the thickness and shape of the first dielectric layer 112 can be selected according to actual conditions, and are not limited here; the shape and thickness of the first chip body 111 can be selected according to actual conditions, and are not limited here. In this embodiment, the shape of the first dielectric layer 112 is the same as the shape of the first chip body 111 in the first chip 11.
[0062] Specifically, the material of the first dielectric layer 112 includes epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphosilicate glass, fluorine-containing glass or other suitable insulating materials.
[0063] Specifically, the method of forming the first dielectric layer 112 includes chemical vapor deposition, physical vapor deposition, coating or other suitable methods.
[0064] As an example, the first chip 11 includes a SOC chip or other suitable chips to be integrated. In this embodiment, only the SOC chip is selected as the first chip 11 in the first device layer 1 .
[0065] Specifically, while ensuring the function of the packaging structure, the number of the first chips 11 in the first device layer 1 can be selected according to actual conditions, and is not limited here; the thickness, size and shape of each first chip 11 in the first device layer 1 can be selected according to actual conditions, and are not limited here. In this embodiment, the first device layer 1 is provided with two different first chips 11, and the thickness of the first chips 11 is the same.
[0066] Specifically, the first electrode 12 includes a first lead-out electrode 121 and a first chip electrode. The first lead-out electrode 121 penetrates the first dielectric layer 112 so as to lead out the first chip electrode.
[0067] Specifically, the upper surface of the first lead-out electrode 121 is flush with the upper surface of the first dielectric layer 112. Under the condition of ensuring the packaging structure, the cross-sectional size and cross-sectional shape of the first lead-out electrode 121 can be selected according to actual conditions and are not limited here. The cross-sectional area here refers to the cross-sectional area parallel to the upper surface of the first dielectric layer 112.
[0068] Specifically, the material of the first extraction electrode 121 includes copper, aluminum, nickel, gold, silver, titanium, tantalum or other suitable conductive materials.
[0069] As an example, the devices in the Bridge chip 2 (bridge chip) include active devices and passive devices. For example, the Bridge chip 2 may contain only active devices that cooperate with the circuits in the packaging structure, or may contain only passive devices that cooperate with the circuits in the packaging structure, or may contain both active devices and passive devices that cooperate with the circuits in the packaging structure.
[0070] Specifically, while ensuring the performance of the packaging structure, the thickness and size of the Bridge chip 2 can be selected according to actual conditions and are no longer restricted here; the number of the first transfer electrodes 21 can be selected according to actual conditions and are no longer restricted here; the number of the second transfer electrodes 22 can be selected according to actual conditions and are no longer restricted here.
[0071] As an example, a second dielectric layer 23 is disposed on the lower surface of the Bridge chip 2 , and the first switching electrode 21 penetrates the second dielectric layer 23 .
[0072] Specifically, the second dielectric layer 23 is used to protect the first transfer electrode 21 in the Bridge chip 2. Under the condition of ensuring the performance of the packaging structure, the thickness and shape of the second dielectric layer 23 can be selected according to actual conditions and are not limited here.
[0073] Specifically, the material of the second dielectric layer 23 includes epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphosilicate glass, fluorine-containing glass or other suitable insulating materials.
[0074] Specifically, the method of forming the second dielectric layer 23 includes chemical vapor deposition, physical vapor deposition, coating or other suitable methods.
[0075] As an example, the material at the hybrid bonding interface between the first device layer 1 and the Bridge chip 2 is the same, that is, the material of the first dielectric layer 112 is the same as the material of the second dielectric layer 23 , and the material of the first lead-out electrode 121 is the same as the material of the first transfer electrode 21 .
[0076] Specifically, the material of the first switching electrode 21 includes copper, aluminum, nickel, gold, silver, titanium, tantalum or other suitable conductive materials.
[0077] Specifically, under the condition of ensuring the performance of the packaging structure, the cross-sectional size and cross-sectional shape of the first transfer electrode 21 can be selected according to actual conditions, and are not limited here. The cross section here refers to the cross section parallel to the lower surface of the second dielectric layer 23.
[0078] As an example, the material of the first switching electrode 21 is the same as the material of the first electrode 12 .
[0079] Specifically, the lower surface of the first transfer electrode 21 is flush with the lower surface of the second dielectric layer 23, and the first chip 11 is bonded to the Bridge chip 2 through a hybrid bonding process to form an electrical connection between the first lead-out electrode 121 and the first transfer electrode 21, that is, the first electrode 12 is electrically connected to the first transfer electrode 21 through a hybrid bonding process.
[0080] Specifically, the second chip 31 further includes a second chip body 311 and a third dielectric layer 312 covering the lower surface of the second chip body 311 , and the second electrode 32 penetrates the third dielectric layer 312 .
[0081] Specifically, the third dielectric layer 312 is used to protect the second electrode 32 in the second chip 31. Under the condition of ensuring the performance of the packaging structure, the thickness and shape of the third dielectric layer 312 can be selected according to actual conditions, and are not limited here; the thickness and shape of the second chip body 311 can be selected according to actual conditions, and are not limited here. In this embodiment, the shape of the third dielectric layer 312 is the same as the shape of the second chip body 311 in the second chip 31.
[0082] Specifically, the material of the third dielectric layer 312 includes epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphosilicate glass, fluorine-containing glass or other suitable insulating materials.
[0083] Specifically, the method of forming the third dielectric layer 312 includes chemical vapor deposition, physical vapor deposition, coating or other suitable methods.
[0084] Specifically, the second electrode 32 includes a second lead-out electrode 321 and a second chip electrode. The second lead-out electrode 321 penetrates the third dielectric layer 312 to lead out the second chip electrode.
[0085] As an example, the second transfer electrode 22 and the second electrode 32 are made of the same material, that is, the second transfer electrode 22 and the second lead-out electrode 321 are made of the same material. In this embodiment, the second transfer electrode 22 and the second lead-out electrode 321 are both made of copper.
[0086] Specifically, the second transfer electrode 22 and the second electrode 32 are electrically connected through a hybrid bonding process, and the second transfer electrode 22 and the second lead-out electrode 321 are bonded together through a hybrid bonding process.
[0087] Specifically, the encapsulation layer 4 is used to protect the first device layer 1, the Bridge chip 2 and the second device layer 3. The material of the encapsulation layer 4 includes epoxy resin, silicone, PI, PBO, BCB, silicon oxide, phosphosilicate glass, fluorine-containing glass or other suitable insulating materials.
[0088] Specifically, the method of forming the encapsulation layer 4 includes chemical vapor deposition, physical vapor deposition, coating or other suitable methods.
[0089] Specifically, the conductive pillar 5 includes copper, aluminum, nickel, gold, silver, titanium, tantalum or other suitable conductive materials.
[0090] Specifically, the method of forming the conductive pillar 5 includes chemical vapor deposition, physical vapor deposition, electroplating, chemical plating, evaporation, atomic layer deposition, magnetron sputtering or other suitable methods.
[0091] Specifically, under the condition of ensuring the performance of the packaging structure, the cross-sectional shape and cross-sectional size of the conductive pillar 5 can be selected according to actual conditions, and are not limited here. The cross section here refers to the cross section parallel to the upper surface of the packaging layer 4.
[0092] As an example, the upper surfaces of the packaging layer 4 , the conductive pillars 5 and the second device layer 3 are flush.
[0093] Specifically, under the condition of ensuring the performance of the packaging structure, the packaging layer 4 may also cover the upper surface of the second device layer 3 , that is, the upper surface of the packaging layer 4 is higher than the upper surface of the second device layer 3 .
[0094] As an example, the rewiring layer 6 includes at least one alternately stacked conductive interconnect layer and a dielectric layer, the conductive bump 7 is electrically connected to the conductive interconnect layer on the top layer of the rewiring layer 6, and the conductive column 5 is electrically connected to the conductive interconnect layer on the bottom layer of the rewiring layer 6.
[0095] Specifically, under the condition of ensuring the performance of the packaging structure, the number and thickness of the dielectric layer and the conductive interconnect layer can be selected according to actual conditions and are not limited here.
[0096] Specifically, the material of the dielectric layer includes epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphosilicate glass, fluorine-containing glass or other suitable insulating materials.
[0097] Specifically, the method of forming the dielectric layer includes chemical vapor deposition, physical vapor deposition, coating or other suitable methods.
[0098] Specifically, the conductive interconnect layer is made of copper, aluminum, nickel, gold, silver, titanium, tantalum or other suitable conductive materials. In this embodiment, the conductive interconnect layer and the conductive pillar are both made of copper.
[0099] Specifically, the method of forming the conductive interconnect layer includes chemical vapor deposition, physical vapor deposition, electroplating, chemical plating, evaporation, atomic layer deposition, magnetron sputtering or other suitable methods.
[0100] Specifically, the conductive bump 7 is used to form a connection with an external circuit, and the material of the conductive bump 7 includes copper, nickel, gold, silver, titanium, tin or other suitable conductive materials. In this embodiment, a copper column is selected as the main body of the conductive bump 7, and tin is set on the top of the copper column to facilitate welding with the external circuit, that is, a copper bump is used as the conductive bump 7.
[0101] Specifically, the Bridge chip 2 is used to replace the transfer wafer to transfer between multiple chips, thereby improving the yield of packaging, reducing the size of the packaging structure, and expanding the application field of the packaging structure.
[0102] Specifically, since the Bridge chip 2 is bonded to the first chip 11 located below the Bridge chip 2 through a hybrid bonding method, and the Bridge chip 2 is bonded to the second chip 31 located above the Bridge chip 2 through a hybrid bonding method, the chips can be stacked in multiple layers to achieve multi-dimensional interconnection of multiple chips, thereby improving the integration of the packaging structure.
[0103] Specifically, since the Bridge chip 2 is bonded to the first device layer 1 and the second device layer 3 through a hybrid bonding process, and the material of the bonding interface is changed from nitride and oxide dielectric layers to organic dielectric layers, the overall process cost can be reduced.
[0104] The Bridge chip hybrid bonding packaging structure of this embodiment uses the Bridge chip 2 to replace the transfer wafer to transfer between multiple chips, so that the chips can be stacked in multiple layers, and the multi-dimensional interconnection of multiple chips is realized, which improves the integration and yield of the packaging structure, reduces the size of the packaging structure, and expands the application field of the packaging structure. In addition, since the Bridge chip 2 is bonded to the device layers located on the upper and lower sides of the Bridge chip 2 by hybrid bonding, its bonding interface can be transformed from nitride and oxide dielectric layers to organic dielectric layers, which reduces the cost of the process.
[0105] In summary, the Bridge chip hybrid bonding packaging structure of the present invention improves the packaging structure, uses the Bridge chip to replace the transfer wafer in the packaging structure to perform transfer interconnection between multiple chips, and the Bridge chip and the transfer chip are bonded by a hybrid bonding process, so that the chips can be stacked in multiple layers, and multi-dimensional interconnection of multiple chips is realized, which improves the integration and yield of the packaging structure, reduces the size of the packaging structure, and expands the application field of the packaging structure. At the same time, since the hybrid bonding interface between the Bridge chip and the first device layer and the second device layer can be transformed from nitride and oxide dielectric layers to organic dielectric layers, the cost of the process is reduced. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has a high industrial utilization value.
[0106] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the technology may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed in the present invention shall still be covered by the claims of the present invention.
Claims
1. A Bridge chip hybrid bonding packaging structure, characterized in that: include: The first device layer includes a first chip having at least one upper surface provided with a plurality of first electrodes spaced apart from each other; A bridge chip, comprising a first transfer electrode disposed on a lower surface and a second transfer electrode disposed on an upper surface, wherein the first transfer electrode is electrically connected to at least one of the first electrodes; A second device layer includes a second chip having a second electrode on at least one lower surface, wherein the second electrode is electrically connected to the second transfer electrode; An encapsulation layer, covering at least the exposed side walls of the first device layer and the second device layer and the exposed surface of the Bridge chip; a conductive column, penetrating the packaging layer above the first device layer and having a bottom end electrically connected to the first electrode; a rewiring layer, located on the upper surface of the packaging layer and electrically connected to the top of the conductive pillar; The conductive bump is located on the upper surface of the rewiring layer and is electrically connected to the pad in the rewiring layer.
2. The Bridge chip hybrid bonding packaging structure according to claim 1, characterized in that: The first chip further includes a first chip body and a first dielectric layer covering an upper surface of the first chip body, and the first electrode penetrates the first dielectric layer.
3. The Bridge chip hybrid bonding packaging structure according to claim 1, characterized in that: The first chip includes a SOC chip.
4. The Bridge chip hybrid bonding packaging structure according to claim 1, characterized in that: The devices in the Bridge chip include active devices and passive devices.
5. The Bridge chip hybrid bonding packaging structure according to claim 1, characterized in that: A second dielectric layer is disposed on the lower surface of the Bridge chip, and the first transfer electrode penetrates the second dielectric layer.
6. The Bridge chip hybrid bonding packaging structure according to claim 1, characterized in that: The material at the hybrid bonding interface between the first device layer and the Bridge chip is the same.
7. The Bridge chip hybrid bonding packaging structure according to claim 1, characterized in that: The material of the first switching electrode is the same as that of the first electrode.
8. The Bridge chip hybrid bonding packaging structure according to claim 1, characterized in that: The material of the second electrode is the same as that of the second switching electrode.
9. The Bridge chip hybrid bonding packaging structure according to claim 1, characterized in that: The upper surfaces of the packaging layer, the conductive pillars and the second device layer are flush.
10. The Bridge chip hybrid bonding packaging structure according to claim 1, characterized in that: The rewiring layer includes at least one alternately stacked conductive interconnect layer and dielectric layer, the conductive bump is electrically connected to the conductive interconnect layer at the top layer of the rewiring layer, and the conductive column is electrically connected to the conductive interconnect layer at the bottom layer of the rewiring layer.