Equipment power failure alarm circuit

Abstract

The utility model provides an equipment power-down alarm circuit, which comprises a power-down detection unit, a main control unit, a farad capacitor unit, a boost unit and a first interface, and is characterized in that the power-down detection unit is used for detecting whether a power-down phenomenon exists in a first direct-current power supply, and if the power-down phenomenon exists, the power-down phenomenon is fed back to the main control unit; the farad capacitor unit discharges outwards when the equipment is powered down, supplies power to the first interface through the boosting unit and further continues to supply power to the main control unit, and the main control unit can send a power-down signal to the control terminal through the first interface. The equipment power failure alarm circuit structure is simple in design structure, low in cost and capable of feeding back a power failure signal to a control terminal in time.

Description

Technical Field

[0001] The utility model relates to the field of safety protection, in particular to a power-off alarm circuit for equipment. Background Art

[0002] "Power failure alarm" usually refers to a warning signal issued when the power supply is unexpectedly interrupted or the power is too low. This alarm can appear in different devices and systems, such as data centers, industrial control systems, medical equipment, communication systems, etc.

[0003] The existing power-off alarm circuit requires a large-capacity electrolytic capacitor to be reserved at the front end of the device power supply. When the device detects that the power supply is reduced, the large-capacity electrolytic capacitor is discharged to ensure that the voltage of each circuit of the device is within the normal working range. The discharge time lasts until the device sends a power-off signal.

[0004] The electrolytic capacitor selected for the above power-off alarm circuit is large in size, large in capacity, and high in price and cost. The safety factor of electrolytic capacitors with large capacity and volume is relatively low, the structural design occupies a large space, and needs to be installed independently; and the power-off alarm circuit cannot feed back the power-off signal to the control terminal in time. Utility Model Content

[0005] In order to achieve the above-mentioned purpose, a technical solution adopted by the utility model is to provide a device power-off alarm circuit, characterized in that it includes: a power-off detection unit, the power-off detection unit includes a first voltage-dividing resistor, a second voltage-dividing resistor and a voltage detection chip, the first end of the first voltage-dividing resistor is electrically connected to a first DC power supply, the second end is electrically connected to the second voltage-dividing resistor and then grounded, and the second end of the first voltage-dividing resistor is also electrically connected to a voltage signal input end of the voltage detection chip; a main control unit, the voltage signal detection end of the main control unit is electrically connected to the voltage signal output end of the voltage detection chip, and the power-off signal output end of the main control unit is used to send a power-off signal to the outside; a farad capacitor unit, the input end of the farad capacitor unit is electrically connected to the second DC power supply, and the output end of the farad capacitor unit outputs the second DC power supply; a boost unit, the input end of the boost unit is electrically connected to the output end of the farad capacitor unit, and the output end of the boost unit outputs the first DC power supply; a first interface, the first interface is electrically connected to the output end of the boost unit for communicating with the outside.

[0006] In an embodiment of the present application, the farad capacitor unit includes: a farad capacitor, the positive electrode of the farad capacitor is electrically connected to the first resistor and then connected to the second DC power supply, and the negative electrode of the farad capacitor is grounded; a first diode, the positive electrode of the first diode is electrically connected to the positive electrode of the farad capacitor, and the negative electrode of the first diode outputs the second DC power supply when the farad capacitor is in a discharge state.

[0007] In an embodiment of the present application, the boost unit includes: a boost chip, wherein the input end of the boost chip is electrically connected to the cathode of the first diode; a second diode, wherein the anode of the second diode is electrically connected to the output end of the boost chip, and the cathode of the second diode outputs a first DC power supply; a first feedback resistor, wherein the first end of the first feedback resistor is electrically connected to the cathode of the second diode, and the second end is electrically connected to the feedback end of the boost chip; and a second feedback resistor, wherein the first end of the second feedback resistor is electrically connected to the second end of the first feedback resistor, and the second end is grounded.

[0008] In an embodiment of the present application, an inductor is further provided between the output end and the input end of the boost chip.

[0009] In an embodiment of the present application, the device power-off alarm circuit also includes: a step-down unit, the step-down unit includes a step-down chip, the input end of the step-down chip is electrically connected to the second DC power supply, and the output end outputs the third DC power supply; a first magnetic bead, one end of the first magnetic bead is electrically connected to the third DC power supply; a second interface, the second interface is electrically connected to the other end of the first magnetic bead for communicating with the outside.

[0010] In an embodiment of the present application, the device power-off alarm circuit further includes a second magnetic bead, one end of which is electrically connected to a third DC power supply, and the other end of which is electrically connected to a power supply end of the main control unit.

[0011] In an embodiment of the present application, the watchdog input terminal of the voltage detection chip is electrically connected to the first pull-up resistor and then connected to the second DC power supply; the watchdog output terminal of the voltage detection chip is electrically connected to the second pull-up resistor and then connected to the second DC power supply.

[0012] The beneficial effects of the utility model are as follows: the utility model provides a device power-off alarm circuit, including a power-off detection unit, a main control unit, a farad capacitor unit, a boost unit and a first interface, wherein the power-off detection unit is used to detect whether there is a power-off phenomenon in the first DC power supply, and if there is a power-off phenomenon, it is fed back to the main control unit; the farad capacitor unit discharges outward when the device is powered off, and supplies power to the first interface through the boost unit, and also continues to supply power to the main control unit, and the main control unit can send a power-off signal to the control terminal through the first interface. The device power-off alarm circuit structure design in the utility model is simple in structure and low in cost, and can feed back the power-off signal to the control terminal in time. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 It is a schematic diagram of the composition of the power-off alarm circuit of the utility model device;

[0014] Figure 2 It is a schematic diagram of the composition of the power-off detection unit in the power-off alarm circuit of the utility model device;

[0015] Figure 3 It is a schematic diagram of the composition of the farad capacitor unit in the power-off alarm circuit of the utility model device;

[0016] Figure 4 It is a schematic diagram of the composition of the boost unit in the power-off alarm circuit of the utility model device;

[0017] Figure 5 The utility model is a schematic diagram of the composition of the voltage reduction unit in the power failure alarm circuit of the equipment. DETAILED DESCRIPTION

[0018] In order to facilitate the understanding of the present invention, the present invention is described in more detail below in conjunction with the accompanying drawings and specific embodiments. The accompanying drawings provide preferred embodiments of the present invention. However, the present invention can be implemented in many different forms and is not limited to the embodiments described in this specification. On the contrary, the purpose of providing these embodiments is to make the understanding of the disclosure of the present invention more thorough and comprehensive.

[0019] It should be noted that, unless otherwise defined, all technical and scientific terms used in this specification have the same meaning as those commonly understood by those skilled in the art in the technical field of the present invention. The terms used in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used in this specification includes any and all combinations of one or more related listed items.

[0020] The utility model provides a device power-off alarm circuit, which can be applied to devices such as digital controllers and gateways. When the device loses power due to certain moments or external factors, the device power-off alarm circuit can detect the power-off phenomenon and feed back to the control terminal.

[0021] like Figure 1 As shown in FIG. 1 , as a specific embodiment of a device power failure alarm circuit, the device power failure alarm circuit includes a power failure detection unit 101 , a main control unit 109 , a farad capacitor unit 102 , a boost unit 104 and a first interface 107 .

[0022] The power-off detection unit 101 is used to detect whether the first DC power supply VCCA has a power-off phenomenon, and if the power-off phenomenon exists, it is fed back to the main control unit 109; the input end of the farad capacitor unit 102 is electrically connected to the second DC power supply VCCB, the second DC power supply VCCB can charge the farad capacitor unit 102, and the output end of the farad capacitor unit 102 outputs another second DC power supply VCCB, that is, the farad capacitor unit 102 discharges to the outside when the device loses power; the input end of the boost unit 104 is electrically connected to the output end of the farad capacitor unit 102, the output end of the boost unit 104 outputs another first DC power supply VCCA, and the output end of the boost unit 104 is electrically connected to the first interface 107, and the first interface 107 is used to communicate with the outside.

[0023] In this embodiment, if the device has a power-off phenomenon, the power-off detection unit 101 will feed back the detection signal to the main control unit 109, the farad capacitor unit 102 will discharge outward, and continue to supply power after being boosted by the boost unit 104 to maintain the normal operation of some circuits. For example, the main control unit 109 can send a power-off signal to the control terminal through the first interface 107, and the control terminal will display that the device is in a power-off state to facilitate maintenance personnel to perform maintenance.

[0024] like Figure 2 As shown, in this embodiment, the power-off detection unit 101 includes a first voltage-dividing resistor R21, a second voltage-dividing resistor R22 and a voltage detection chip U1, the first end of the first voltage-dividing resistor R21 is electrically connected to the first DC power supply VCCA, the second end is electrically connected to the second voltage-dividing resistor R22 and then grounded, and the second end of the first voltage-dividing resistor R21 is also electrically connected to the voltage signal input terminal PFI of the voltage detection chip U1, the voltage signal output terminal PFO of the voltage detection chip U1 is electrically connected to the voltage signal detection terminal of the main control unit 109, and the power-off signal output terminal of the main control unit 109 is used to send a power-off signal to the outside (control terminal). In this embodiment, when the first DC power supply VCCA is in a normal power supply state, the first DC power supply VCCA is divided by the first voltage-dividing resistor R21 and the second voltage-dividing resistor R22, and the level of the voltage signal input terminal PFI is high; and when the first DC power supply VCCA is powered off, the level of the voltage signal input terminal PFI is low, and at this time, the voltage signal output terminal PFO of the voltage detection chip U1 transmits the power-off signal to the main control unit 109.

[0025] exist Figure 2In the embodiment, the watchdog input terminal WDI of the voltage detection chip U1 is electrically connected to the first pull-up resistor R25 and then connected to the second DC power supply VCCB; the watchdog output terminal WDO of the voltage detection chip U1 is electrically connected to the second pull-up resistor R24 ​​and then connected to the second DC power supply VCCB; the voltage signal output terminal PFO of the voltage detection chip U1 is electrically connected to the resistor R28 and then connected to the voltage signal detection terminal of the main control unit 109, and the voltage signal detection terminal of the main control unit 109 is also electrically connected to the third pull-up resistor R26 and then connected to the second DC power supply VCCB; the power supply terminal VCC of the voltage detection chip U1 is powered by the second DC power supply VCCB, and the power supply terminal VCC of the voltage detection chip U1 is also electrically connected to the filter capacitor C21 and the filter capacitor C22 and then grounded; the manual reset terminal MR of the voltage detection chip U1 is electrically connected to the watchdog output terminal WDO.

[0026] In this embodiment, the first DC power supply VCCA may be +12V, and the second DC power supply VCCB may be +5V.

[0027] In this embodiment, if Figure 3 As shown, the farad capacitor unit 102 includes a farad capacitor C31 and a first diode D31. The positive electrode of the farad capacitor C31 is electrically connected to the first resistor R31 and then connected to the second DC power supply VCCB, and the negative electrode of the farad capacitor C31 is grounded; the positive electrode of the first diode D31 is electrically connected to the positive electrode of the farad capacitor C31, and the negative electrode of the first diode D31 outputs another second DC power supply VCCB when the farad capacitor C31 is in a discharging state. The negative electrode of the first diode D31 is also electrically connected to the filter capacitor C32 and the filter capacitor C33 and then grounded.

[0028] In this embodiment, if Figure 4 As shown, the boost unit 104 includes a boost chip U2, a second diode D41, a first feedback resistor R41 and a second feedback resistor R42; the input terminal VDD of the boost chip U2 is electrically connected to Figure 3 The cathode of the first diode D31, the anode of the second diode D41 is electrically connected to the output terminal LX of the boost chip U2, the cathode of the second diode D41 outputs the first DC power supply VCCA, the first end of the first feedback resistor R41 is electrically connected to the cathode of the second diode D41, the second end is electrically connected to the feedback terminal FB of the boost chip U2, the first end of the second feedback resistor R42 is electrically connected to the second end of the first feedback resistor R41, and the second end of the second feedback resistor R42 is grounded. In this embodiment, the boost chip U2 can boost the second DC power supply VCCB output when the farad capacitor C31 is discharged to the first DC power supply VCCA, and supply power to the first interface 107.

[0029] In this embodiment, an inductor L1 is further provided between the output terminal LX and the input terminal VDD of the boost chip U2.

[0030] Further, such as Figure 1 As shown, the device power failure alarm circuit also includes a step-down unit 103, a first magnetic bead 105 and a second magnetic bead 106, and a second interface 108; Figure 5 The step-down unit includes a step-down chip U3, the input end IN of the step-down chip U3 is electrically connected to the second DC power supply VCCB, the output end OUT outputs the third DC power supply VCCC, one end of the first magnetic bead 105 is electrically connected to the third DC power supply VCCC, the other end of the first magnetic bead 105 is electrically connected to the second interface 108, and the second interface 106 is used to communicate with the outside (control terminal); one end of the second magnetic bead 106 is electrically connected to the third DC power supply VCCC, and the other end of the second magnetic bead 106 is electrically connected to the power supply end of the main control unit 109. In this embodiment, the step-down chip U3 can step down the second DC power supply VCCB output when the farad capacitor C31 is discharged to the third DC power supply VCCC, the size of the third DC power supply VCCC is 3.3V, and supply power to the second interface 108 and the main control unit 109.

[0031] exist Figure 5 In the embodiment, the input terminal IN of the buck chip U3 is also electrically connected to the filter capacitor C11 and the filter capacitor C12 and then grounded, and the output terminal OUT of the buck chip U3 is also electrically connected to the filter capacitor C13 and the filter capacitor C14 and then grounded.

[0032] In some embodiments, the main control unit 109 is a single chip microcomputer, the first interface 107 is a PLC interface, and the second interface 108 is a network port. When the device loses power, the main control unit 109 can send a power-off signal to the control terminal through the first interface 107 or the second interface 108.

[0033] The utility model provides a device power failure alarm circuit, including a power failure detection unit, a main control unit, a farad capacitor unit, a boost unit and a first interface, wherein the power failure detection unit is used to detect whether there is a power failure in the first DC power supply, and if there is a power failure, the farad capacitor unit discharges outward when the device is powered off, and supplies power to the first interface through the boost unit, and also continues to supply power to the main control unit, and the main control unit can send a power failure signal to the control terminal through the first interface. The device power failure alarm circuit structure design in the utility model has a simple structure and low cost, and can timely feed back the power failure signal to the control terminal.

[0034] The above description is only an embodiment of the present invention, and does not limit the patent scope of the present invention. Any equivalent structural transformation made using the contents of the specification and drawings of the present invention, or directly or indirectly applied in other related technical fields, is also included in the patent protection scope of the present invention.

Claims

1. A device power-off alarm circuit, characterized in that: include: A power-off detection unit, the power-off detection unit comprising a first voltage-dividing resistor, a second voltage-dividing resistor and a voltage detection chip, wherein a first end of the first voltage-dividing resistor is electrically connected to a first DC power supply, a second end of the first voltage-dividing resistor is electrically connected to the second voltage-dividing resistor and then grounded, and a second end of the first voltage-dividing resistor is also electrically connected to a voltage signal input end of the voltage detection chip; A main control unit, wherein a voltage signal detection terminal of the main control unit is electrically connected to a voltage signal output terminal of the voltage detection chip, and a power-off signal output terminal of the main control unit is used to send a power-off signal to the outside; A farad capacitor unit, wherein an input end of the farad capacitor unit is electrically connected to a second DC power source, and an output end of the farad capacitor unit outputs the second DC power source; A boost unit, wherein an input end of the boost unit is electrically connected to an output end of the farad capacitor unit, and an output end of the boost unit outputs a first DC power supply; A first interface, wherein the first interface is electrically connected to the output end of the boost unit and is used for communicating with the outside.

2. The device power-off alarm circuit according to claim 1, characterized in that: The farad capacitor unit comprises: A farad capacitor, wherein a positive electrode of the farad capacitor is electrically connected to the first resistor and then connected to the second DC power supply, and a negative electrode of the farad capacitor is grounded; A first diode, wherein the anode of the first diode is electrically connected to the anode of the farad capacitor, and the cathode of the first diode outputs a second DC power supply when the farad capacitor is in a discharging state.

3. The device power-off alarm circuit according to claim 2, characterized in that: The boost unit comprises: A boost chip, wherein an input end of the boost chip is electrically connected to a cathode of the first diode; a second diode, wherein the anode of the second diode is electrically connected to the output end of the boost chip, and the cathode of the second diode outputs the first DC power supply; a first feedback resistor, wherein a first end of the first feedback resistor is electrically connected to the cathode of the second diode, and a second end of the first feedback resistor is electrically connected to the feedback end of the boost chip; A second feedback resistor, wherein a first end of the second feedback resistor is electrically connected to the second end of the first feedback resistor, and a second end of the second feedback resistor is grounded.

4. The device power-off alarm circuit according to claim 3, characterized in that: An inductor is also arranged between the output end and the input end of the boost chip.

5. The device power-off alarm circuit according to claim 1, characterized in that: The device power-off alarm circuit also includes: A step-down unit, the step-down unit comprising a step-down chip, the input end of the step-down chip is electrically connected to the second DC power supply, and the output end of the step-down chip outputs the third DC power supply; a first magnetic bead, one end of which is electrically connected to a third DC power supply; A second interface, the second interface is electrically connected to the other end of the first magnetic bead and is used for communicating with the outside.

6. The device power-off alarm circuit according to claim 5, characterized in that: The device power-off alarm circuit also includes a second magnetic bead, one end of which is electrically connected to a third DC power supply, and the other end of which is electrically connected to a power supply end of the main control unit.

7. The device power-off alarm circuit according to claim 1, characterized in that: The watchdog input terminal of the voltage detection chip is electrically connected to the first pull-up resistor and then connected to the second DC power supply; the watchdog output terminal of the voltage detection chip is electrically connected to the second pull-up resistor and then connected to the second DC power supply.

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