Display interaction device combining LED and LCD

Abstract

The utility model discloses an LED and LCD combined display interaction device, and belongs to the technical field of display screens. The touch screen comprises a touch cover plate, a display module, a fixed bracket and a PCB (Printed Circuit Board) control circuit board, the PCB control circuit board is fixedly installed at the lower end of the fixing support. The display module is fixedly mounted at the upper end of the fixed bracket; the touch cover plate is glued at the upper end of the display module; the display module comprises an LED display diaphragm and an LCD display screen. The distance between the LED display diaphragm and the LCD display screen is less than 4mm; the PCB control circuit board comprises a microprocessor, a DCDC power supply circuit, a Flash storage circuit, a TP sensor touch screen input circuit, a debugging circuit, a TFT display screen drive circuit and an LED display drive circuit. By means of the scheme, the large-size and low-cost display device can be achieved, the combination of the LED and the LCD is high in integrity, the touch function of the whole display area is achieved, and compared with a traditional display control interface, the function use and the visual effect are greatly improved.

Description

Technical Field

[0001] The utility model relates to the technical field of display screens, in particular to a display interaction device combining LEDs and LCDs. Background Art

[0002] LED, short for light-emitting diode, is a commonly used light-emitting device that emits light through the recombination of electrons and holes. LEDs efficiently convert electrical energy into light and have a wide range of applications in modern society, including lighting, flat-panel displays, and medical devices. LCD, short for liquid crystal display, is a type of flat-panel display used for television and computer screens. Its advantages include low power consumption, compact size, and low radiation. LCDs use a liquid crystal solution between two polarized materials. When an electric current passes through the liquid, the crystals rearrange to create an image.

[0003] A single LED display uses LED lights to transmit the display pattern printed on the film to display content. The display content is single and fixed, and it is impossible to switch between multiple interfaces. A single LCD screen display is expensive and not competitive in the market. An ED plus LCD screen display has a large distance between the display areas, generally more than 10mm, which results in poor integrity and poor visual effects.

[0004] Therefore, the present invention discloses a display interaction device combining LED and LCD to solve the above problems. Utility Model Content

[0005] The purpose of the present invention is to provide a display interaction device combining LED and LCD to solve the problems raised in the above background technology.

[0006] In order to solve the above technical problems, the present invention provides the following technical solutions: a display interaction device combining LED and LCD, characterized in that: the display interaction device includes a touch cover, a display module, a fixed bracket and a PCB control circuit board; the PCB control circuit board is fixedly installed at the lower end of the fixed bracket; the display module is fixedly installed at the upper end of the fixed bracket; the touch cover is glued to the upper end of the display module.

[0007] The display module includes an LED display film and an LCD display screen; the distance between the LED display film and the LCD display screen is less than 4 mm.

[0008] The PCB control circuit board includes a microprocessor, a DCDC power supply circuit, a Flash storage circuit, a TP sensor touch screen input circuit, a debugging circuit, a TFT display screen drive circuit, and an LED display drive circuit; the DCDC power supply circuit, the Flash storage circuit, the TP sensor touch screen input circuit, the debugging circuit, the TFT display screen drive circuit, and the LED display drive circuit are all connected to the microprocessor.

[0009] According to the above scheme, the microprocessor model is Lianyang IT9866; the microprocessor U1 includes pins 1 to 128; pin 1 is connected to one end of the resistor R3, and the other end of the resistor R3 is grounded; pins 2, 118, 119, 123, 124 and 128 are empty pins; pin 3 is connected to the RTC_X2 interface; pin 4 is connected to the RTC_X1 interface; pin 5 is connected to the power supply VDD_RTC; pins 6, 23, 32, 41, 58, 69, 87 and 103 are connected to the power supply VDD_IO; pin 7 is connected to the XIN interface; pin 8 is connected to the XOUT interface; pin 9 is connected to the power supply VDD_PULL; pins 10, 51, 52 Pin 11, 73, 97, 102, 115, 116, and 117 are connected to the power supply VDD_CORE; Pin 11 is connected to the RSTN interface; Pin 12 is grounded; Pins 13 to 22 are connected to the GPIO0 interface to the GPIO9 interface respectively; Pin 24 is connected to the GPIO10 interface; Pin 25 is connected to the GPIO11 interface; Pins 26 to 31 are connected to the GPIO13 interface to the GPIO18 interface respectively; Pins 33 to 40 are connected to the GPIO19 interface to the GPIO26 interface respectively; Pin 42 is connected to one end of the resistor R4, and the other end of the resistor R4 is grounded; Pin 43 is connected to one end of the resistor R2, and the other end of the resistor R2 is connected to the power supply VDD_MEM; Pins 44 to 49 Pin 50 is connected to the power supply VDD_MEM; Pin 50 is connected to the power supply VDD_MEMPLL; Pins 53 to 57 are respectively connected to the GPIO27 interface to the GPIO31 interface; Pins 59 to 64 are respectively connected to the GPIO32 interface to the GPIO37 interface; Pin 65 is connected to one end of the parallel diode D1 and resistor R10, and the other end of the diode D1 and resistor R10 is grounded; Pin 66 is grounded; Pin 67 is connected to the USB_DM interface; Pin 68 is connected to the USB_DP interface; Pin 70 is connected to the GPIO38 interface; Pin 71 is connected to the GPIO40 interface; Pin 72 is connected to the GPIO41 interface; Pins 74 to 86 are respectively connected to the GPIO42 interface to the GPIO54 interface; Pin 88 is connected to the USB_DM interface; Pin 89 is connected to the USB_DP interface; Pin 90 is connected to the GPIO38 interface; Pin 91 is connected to the GPIO40 interface; Pin 92 is connected to the GPIO41 interface; Pins 94 to 100 are respectively connected to the GPIO42 interface to the GPIO54 interface; Pin 93 is connected to the GPIO40 interface; Pin 94 is connected to the GPIO41 interface; Pin 95 is connected to the GPIO42 interface to the GPIO54 interface; Pin 96 is connected to the GPIO42 interface to the GPIO54 interface; Pin 97 is connected to the GPIO40 interface Pins 95 to 96 connect the GPIO55 interface to the GPIO62 interface respectively; pin 96 connects the GPIO63 interface; pins 98 to 101 connect the GPIO64 interface to the GPIO67 interface respectively; interface 104 is connected to one end of capacitor C3, and the other end of C3 is grounded; pin 105 connects to the MIPIDP3 interface; pin 106 connects to the MIPIDN3 interface; pin 107 connects to the MIPIDP2 interface; pin 108 connects to the MIPIDN2 interface; pin 109 connects to the MIPICKP interface; pin 110 connects to the MIPICKN interface; pin 111 connects to the MIPIDP1 interface; pin 112 connects to the MIPIDN1 interface; pin 113 connects to the MIPIDP0 interface;Pin 114 is connected to the MIPIDN0 interface; pin 120 is connected to the LMICIP interface; pin 121 is connected to the LMICIN interface; pin 122 is connected to the MICBIAS interface; pin 125 is grounded; pin 126 is connected to the RHPOUT interface; and pin 127 is connected to the LHPOUT interface.

[0010] According to the above scheme, the DCDC power supply circuit includes a step-down conversion circuit, a crystal oscillator reset circuit and a filter voltage stabilization circuit;

[0011] The buck conversion circuit includes a buck conversion chip U5, which includes pins 1 to 5, wherein pin 4 is connected to a power supply VDD5V, a capacitor C53, and one end of a resistor R72, the other end of the capacitor C53 is grounded, the other end of the resistor R72 is connected to pin 1 and one end of a capacitor C58, the other end of the capacitor C58 is grounded; pin 2 is grounded; pin 3 is connected to one end of an inductor L3, the other end of the inductor L3 is connected to a capacitor C54 and one end of a resistor R73 arranged in parallel, one end of capacitors C55 to C57, and a power supply VDD3V3 and VDD3V3_SOC arranged on a capacitor C56, the other ends of capacitors C55 to C57 are grounded respectively, the other ends of the capacitor C54 and the resistor R73 arranged in parallel are connected to one end of the resistor R74 and pin 5, and the other end of the resistor R74 is grounded;

[0012] The buck conversion circuit includes a buck conversion chip U6, which includes 1 to 5 pins, wherein pin 4 is connected to a power supply VDD5V, a capacitor C59, and one end of a resistor R79, the other end of the capacitor C53 is grounded, and the other end of the resistor R79 is connected to pin 1; pin 2 is grounded; pin 3 is connected to one end of an inductor L4, the other end of the inductor L4 is connected to one end of a capacitor C60 and a resistor R80 arranged in parallel, a power supply VDD11, one end of capacitors C61 and C62, and a power supply VDD1V1 arranged on the capacitor C52, the other ends of the capacitors C61 and C62 are respectively grounded, the other ends of the capacitor C60 and the resistor R80 arranged in parallel are connected to one end of the resistor R81 and pin 5, and the other end of the resistor R81 is grounded;

[0013] The buck conversion circuit includes a buck conversion chip U7, which includes 1 to 5 pins, wherein pin 4 is connected to a power supply VDD5V, a capacitor C66, and one end of a resistor R82, the other end of the capacitor C66 is grounded, and the other end of the resistor R82 is connected to pin 1; pin 2 is grounded; pin 3 is connected to one end of an inductor L5, the other end of the inductor L5 is connected to one end of a capacitor C67 and a resistor R85 arranged in parallel, one end of capacitors C68 to C70, and a power supply VDD18 arranged on the capacitor C68, and a power supply VDD1V8 arranged on the capacitor C69, the other ends of the capacitors C68 to C70 are respectively grounded, the other ends of the capacitor C67 and the resistor R85 arranged in parallel are connected to one end of the resistor R86 and pin 5, and the other end of the resistor R86 is grounded;

[0014] The aforementioned step-down converter circuit chip utilizes advanced switching power supply technology, effectively converting input power to the desired output voltage. Compared to linear power supplies, this higher conversion efficiency allows for better utilization of electrical energy, minimizing energy loss and heat generation, and thus reducing energy consumption to a certain extent.

[0015] Through a precise feedback control mechanism, the output voltage can be kept stable. It has strong anti-interference capabilities and can cope with input voltage fluctuations and load changes, ensuring that the output voltage is always stable within the set range. The use of reliable components and circuit protection measures improves its reliability and stability.

[0016] The integrated design features a compact size and lightweight structure. This allows it to adapt to various space constraints and facilitate installation in equipment. The compact design also helps reduce line connection impedance and electromagnetic interference, improving overall circuit performance.

[0017] The crystal oscillator reset circuit includes a power supply VDD_RTC, the power supply VDD_RTC is connected to one end of a capacitor C4, and the other end of the capacitor C4 is grounded;

[0018] The crystal oscillator reset circuit also includes a crystal oscillator Y1, one end of the crystal oscillator Y1 is connected to the RTC_X1 interface and one end of the capacitor C1, the RTC_X2 interface is connected to the other end of the crystal oscillator Y1 and one end of the capacitor C5, and the other ends of the capacitors C1 and C5 are grounded;

[0019] The crystal oscillator reset circuit further includes a resistor R1, one end of the resistor R1 is connected to the XIN interface, the crystal oscillator Y2 and one end of the capacitor C2, the other end of the resistor R1 is connected to the XOUT interface, the other end of the crystal oscillator Y2 and one end of the capacitor C6, and the other ends of the capacitors C2 and C6 are grounded;

[0020] The crystal oscillator reset circuit also includes a reset chip U2, which includes pins 1 to 5; pin 1 is connected to pin 2 of transistor Q1, pin 2 of transistor Q1 is connected to one end of resistor R11, the other end of resistor R11 is connected to one end of resistor R12 and the USB_ID interface, the other end of resistor R12 is connected to power supply VDD_IO, pin 3 of transistor Q1 is connected to one end of resistor R5, RSTN interface and one end of capacitor C7, the other end of resistor R5 is connected to power supply VDD_IO, and the other end of capacitor C7 is grounded; pin 2 is grounded; pin 3 is an empty pin; pin 4 is connected to one end of resistor R9, the other end of resistor R9 is connected to GPIO19 interface; pin 5 is connected to power supply VDD_IO and one end of capacitor C8, and the other end of capacitor C8 is grounded;

[0021] The crystal oscillator reset circuit also includes a patch J5, which includes pins 1 to 9, wherein pin 1 is connected to one end of a diode D10, one end of capacitors C63 to C65, and a power supply VDD5V, and the other end of the diode D10 is connected to the other end of the capacitors C63 to C65 and grounded; pin 2 is connected to a resistor R83 and one end of a diode D11, the other end of the resistor R83 is connected to the USB_DM interface, and the other end of the diode D11 is grounded; pin 3 is connected to a resistor R84 and one end of a diode D12, the other end of the resistor R84 is connected to the USB_DP interface, and the other end of the diode D12 is grounded; pin 4 is connected to one end of a diode D13 and the USB_ID interface, and the other end of the diode D14 is grounded; pins 5 to 9 are grounded;

[0022] Crystal oscillator reset circuits play a vital role in electronic devices. Crystal oscillators generate a stable frequency through oscillation, providing the accurate clock signal required by the device, ensuring proper operation and accurate data processing. Reset chips ensure the device is in the correct state upon startup, clearing any errors and improving device reliability.

[0023] The filtering and voltage stabilizing circuit includes capacitors C9 to C21 arranged in parallel, the power supply VDD1V1 and the power supply VDD_CORE are connected to one end of the capacitor C9, the power supply VDD_MEMPLL is connected to one end of the capacitor C19, the power supply VDD_PLL is connected to one end of the capacitor C21, and the other ends of the capacitors C9 to C21 arranged in parallel are grounded;

[0024] The filtering and voltage stabilizing circuit further includes capacitors C22 to C26 arranged in parallel, the power supply VDD1V8 and the power supply VDD_MEM are connected to one end of the capacitors C22 to C26, and the other ends of the capacitors C22 and C26 are grounded respectively;

[0025] The filtering and voltage-stabilizing circuit also includes capacitors C28 to C39 arranged in parallel, the power supply VDD3V3_SOC and the power supply VDD_IO are connected to one end of the capacitor C28, the power supply VDD_XTL is connected to one end of the capacitor C33, the power supply VDD_USB is connected to one end of the capacitor C34, and the power supply VDD_RTC is connected to one end of the capacitor C39. The other ends of the capacitors C28, C34, C36 and C38 arranged in parallel are grounded respectively.

[0026] The above-mentioned power supply VDD1V1, power supply VDD_CORE, power supply VDD_MEMPLL, power supply VDD_PLL, power supply VDD1V8, power supply VDD_MEM, power supply VDD3V3_SOC, power supply VDD_IO, power supply VDD_XTL, power supply VDD_USB and power supply VDD_RTC can remove ripples in the power supply output through the filtering and voltage stabilization circuit, so that the output voltage is smoother and more stable, thereby ensuring the normal operation of the circuit; preventing the ripples in the power supply output from damaging the circuit components, thereby extending the service life of the circuit components; and at the same time reducing the ripples in the power supply output, reducing the power consumption of the components in the circuit, improving the efficiency of the circuit, and saving energy.

[0027] According to the above scheme, the Flash storage circuit includes a chip U3, and the chip U3 includes pins 1 to 9, wherein pin 1 is connected to one end of the resistor R31, and the other end of the resistor R31 is connected to the AXISPI_CS0 interface; pin 2 is connected to one end of the resistor R25, and the other end of the resistor R25 is connected to the AXISPI_D1 interface; pin 3 is connected to one end of the resistor R27, and the other end of the resistor R27 is connected to the AXISPI_D2 interface; pin 5 is connected to one end of the resistor R24, and the other end of the resistor R24 ​​is connected to the AXISPI_D0 interface; pin 6 is connected to one end of the resistor R23, and the other end of the resistor R23 is connected to the AXISPI_CLK interface; pin 7 is connected to one end of the resistor R29, and the other end of the resistor R29 is connected to the AXISPI_D3 interface; pin 8 is connected to the power supply VDD_IO and one end of the capacitor C40, and the other end of the capacitor C40 is connected to pins 4 and 9 and grounded;

[0028] The power supply VDD_IO is connected to one end of resistors R26, R28, and R30. The other end of resistor R26 is connected to the AXISPI_CS0 interface. The other end of resistor R28 is connected to the AXISPI_D2 interface. The other end of resistor R30 is connected to the AXISPI_D3 interface.

[0029] The AXISPI_CS0 interface is electrically connected to the GPIO5 interface; the AXISPI_D0 interface is electrically connected to the GPIO6 interface; the AXISPI_D1 interface is electrically connected to the GPIO7 interface; the AXISPI_D2 interface is electrically connected to the GPIO8 interface; the AXISPI_D3 interface is electrically connected to the GPIO9 interface; and the AXISPI_CLK interface is electrically connected to the GPIO10 interface.

[0030] Flash memory is physically divided into several independent blocks; this structure makes memory operations more flexible and efficient. Flash memory is also inherently non-volatile, similar to magnetic storage, and does not require a backup power supply to retain data. Therefore, it has the advantage of not requiring electrical energy to retain data. It has fast read and write speeds, which can meet the high-speed storage needs of many applications. The memory has high storage capacity and density, which can meet the needs of large-capacity data storage. Flash memory also has relatively low power consumption, which is beneficial for energy conservation and emission reduction and extending the service life of equipment.

[0031] According to the above scheme, the TP sensor touch screen input circuit includes a patch J3, which includes pins 1 to 8, wherein pin 1 is connected to one end of the diode D2 and the TP_RSTn interface, and the other end of the diode D2 is grounded; pin 2 is connected to the power supply VDD3V3_LCD_1; pin 3 is grounded; pin 4 is connected to the resistor R50 and one end of the diode D3, the other end of the resistor R50 is connected to the TP_INTn interface, and the other end of the diode D3 is grounded; pin 5 is connected to the resistor R55 and one end of the diode D4, the other end of the resistor R55 is connected to the TP_SDA interface, and the other end of the diode D4 is grounded; pin 6 is connected to the resistor R57 and one end of the diode D5, the other end of the resistor R57 is connected to the TP_SCL interface, and the other end of the diode D5 is grounded; pins 7 and 8 are empty pins;

[0032] The TP sensor touch screen input circuit also includes a resistor R63. One end of the resistor R63 is connected to the power supply VDD3V3_LCD_1. The other end of the resistor R63 is connected to the TP_RSTn interface and one end of the capacitor C46. The other end of the capacitor C46 is grounded.

[0033] The power supply VDD3V3_LCD_1 is connected to one end of the capacitors C41 and C42; the other ends of the capacitors C41 and C42 are grounded respectively;

[0034] The power supply VDD3V3_SOC is connected to one end of resistors R6, R7 and R8, the other end of resistor R6 is connected to the GPIO44 interface, and the GPIO44 interface is electrically connected to the TP_INTn interface; the other end of resistor R7 is connected to the GPIO46 interface, and the GPIO46 interface is electrically connected to the TP_SDA interface; the other end of resistor R8 is connected to the GPIO47 interface, and the GPIO47 interface is electrically connected to the TP_SCL interface; the GPIO45 interface is electrically connected to the TP_RSTn interface.

[0035] The entire display area realizes the overall touch function, and the entire LED and LCD display area is covered by a touch cover. Any position of both can be touched to improve the user experience.

[0036] According to the above scheme, the debugging circuit includes a patch J1, and the patch J1 includes pins 1 to 8, wherein pin 1 is connected to the SSPI_CLK interface; pin 2 is connected to SSPI_CSN and one end of the resistor R17, and the other end of the resistor R17 is connected to the power supply VDD_IO; pin 3 is connected to the SSPI_MOSI interface; pin 4 is connected to the SSPI_MISO interface; pins 5 and 8 are grounded; pin 6 is connected to the DBG_TX interface, and pin 7 is connected to one end of the capacitor C27 and the power supply VDD_IO, and the other end of the capacitor C27 is grounded;

[0037] The debugging circuit also includes a patch J4, which includes pins 1 to 6, wherein pin 1 of the patch J4 is connected to one end of the diode D7, one end of the diode D8, one end of the diode D9, pin 1 of the inductor L2, and one end of the magnetic bead FB1; the other end of the diode D7 is connected to the RXD interface and pin 3 of the patch J4; the other end of the diode D8 is connected to the TXD interface and pin 4 of the patch J4; the other end of the diode D9 is connected to pin 2 of the patch J4, pin 2 of the inductor L2, and one end of the magnetic bead FB2; the other end of the magnetic bead FB1 is connected to pin 4 of the inductor L2, one end of the capacitors C50 and C51, and grounded; the other end of the magnetic bead FB2 is connected to pin 3 of the inductor L2, the other ends of the capacitors C50 and C51, and the power supply VDD5V;

[0038] The RXD interface is connected to one end of resistor R71, the other end of resistor R71 is connected to one end of resistor R69 and pin 3 of transistor Q2, the other end of resistor R69 is connected to power supply VDD5V, pin 1 of transistor Q2 is connected to one end of resistor R68, the other end of resistor 68 is connected to power supply VDD3V3_SOC, one end of resistor R70 of pin 2 of transistor Q2 is connected to the UART_RX interface, and the other end of resistor R70 is connected to power supply VDD3V3_SOC;

[0039] The TXD interface is connected to one end of resistor R78, the other end of resistor R78 is connected to one end of resistor R76 and pin 3 of transistor Q3, the other end of resistor R76 is connected to power supply VDD5V, pin 1 of transistor Q3 is connected to one end of resistor R75, the other end of resistor 75 is connected to power supply VDD3V3_SOC, one end of resistor R77 of pin 2 of transistor Q3 is connected to UART_TX interface, and the other end of resistor R77 is connected to power supply VDD3V3_SOC;

[0040] The SSPI_CLK interface is electrically connected to the GPIO0 interface; the SSPI_CSN interface is electrically connected to the GPIO1 interface; the SSPI_MOSI interface is electrically connected to the GPIO2 interface; the SSPI_MISO interface is electrically connected to the GPIO3 interface; the DBG_TX interface is electrically connected to the GPIO4 interface; the UART_RX interface is electrically connected to the GPIO20 interface; and the UART_TX interface is electrically connected to the GPIO21 interface.

[0041] According to the above scheme, the TFT display driving circuit includes a patch J2, which includes pins 1 to 42; pin 1 is connected to the LED_Negative interface, pin 2 is connected to the LED_Positive interface; pin 3 is grounded; pin 4 is connected to the power supply VDD3V3_LCD_2; pin 5 is connected to one end of the resistor R38, and the other end of the resistor R38 is connected to the LD0 interface; pin 6 is connected to one end of the resistor R39, and the other end of the resistor R38 is connected to the LD1 interface; pin 7 is connected to one end of the resistor R32, and the other end of the resistor R32 is connected to the LD2 interface; pin 8 is connected to one end of the resistor R33, and the other end of the resistor R33 is connected to the LD3 interface; pin 9 is connected to one end of the resistor R34, and the other end of the resistor R35 is connected to the LD6 interface. The other end of pin 34 is connected to the LD4 interface; pin 10 is connected to one end of resistor R35, and the other end of resistor R35 is connected to the LD5 interface; pin 11 is connected to one end of resistor R36, and the other end of resistor R36 is connected to the LD6 interface; pin 12 is connected to one end of resistor R37, and the other end of resistor R37 is connected to the LD7 interface; pin 13 is connected to one end of resistor R40, and the other end of resistor R40 is connected to the LD8 interface; pin 14 is connected to one end of resistor R41, and the other end of resistor R41 is connected to the LD9 interface; pin 15 is connected to one end of resistor R42, and the other end of resistor R42 is connected to the LD10 interface; pin 16 is connected to one end of resistor R43, and the other end of resistor R43 is connected to the LD11 interface; pin 17 is connected to resistor One end of resistor R44 and the other end of resistor R44 are connected to LD12 interface; pin 18 is connected to one end of resistor R45 and the other end of resistor R45 is connected to LD13 interface; pin 19 is connected to one end of resistor R46 and the other end of resistor R46 is connected to LD14 interface; pin 20 is connected to one end of resistor R47 and the other end of resistor R47 is connected to LD15 interface; pin 21 is connected to one end of resistor R48 and the other end of resistor R48 is connected to LD16 interface; pin 22 is connected to one end of resistor R49 and the other end of resistor R49 is connected to LD17 interface; pin 23 is connected to one end of resistor R51 and the other end of resistor R51 is connected to LD18 interface; pin 24 is connected to one end of resistor R52 and the other end of resistor R52 is connected to LD19 interface. Connect to the LD19 interface; pin 25 is connected to one end of resistor R51, and the other end of resistor R53 is connected to the LD20 interface; pin 26 is connected to one end of resistor R54, and the other end of resistor R54 is connected to the LD21 interface; pin 27 is connected to one end of resistor R56, and the other end of resistor R56 is connected to the LD22 interface; pin 28 is connected to one end of resistor R55, and the other end of resistor R55 is connected to the LD23 interface; pin 28 is grounded; pin 30 is connected to resistor R59 and one end of capacitor C45, the other end of capacitor C45 is grounded, and the other end of resistor R59 is connected to the LDCLK interface; pin 31 is connected to the LCD_ON interface; pin 32 is connected to one end of resistor R60, and the other end of resistor R60 is connected to the HSYNC interface;Pin 33 is connected to one end of resistor R61, and the other end of resistor R61 is connected to the VSYNC interface; pin 34 is connected to one end of resistor R62, and the other end of resistor R62 is connected to the LDEN interface; pin 36 is grounded; pins 35 and 37 to 42 are unconnected.

[0042] The power supply VDD3V3_LCD_2 is connected to one end of the capacitors C43 and C44, and the other ends of the capacitors C43 and C44 are grounded respectively;

[0043] The LCD_ON interface is connected to one end of resistors R64 and R65, the other end of resistor R64 is connected to the LCD_EN interface, and the other end of resistor R65 is grounded;

[0044] The TFT display driver circuit also includes a chip U4. Chip U4 includes pins 1 to 7. Pin 1 is connected to one end of resistor R67 and the LED_Negative interface, and the other end of resistor R67 is grounded. Pin 2 is a blank pin. Pins 3 and 7 are grounded. Pin 4 of chip U4 is connected to pin 2 of inductor L1 and the positive electrode of diode D6. The negative electrode of the diode is connected to one end of capacitors C52 and C49 and the LED_Positive interface. Pin 1 of the inductor is connected to pin 6 of chip U4, one end of capacitors C47 and C48 arranged in parallel, and power supply VDD5V. The other end of the capacitors C47 and C48 arranged in parallel is grounded. Pin 5 is connected to one end of resistor R66. The other end of resistor R66 is connected to the BL_EN_PWM interface.

[0045] The LD0 to LD16 interfaces are electrically connected to the GPIO51 to GPIO67 interfaces respectively; the LD17 interface is electrically connected to the MIPIDP3 interface; the LD18 interface is electrically connected to the MIPIDN3 interface; the LD19 interface is electrically connected to the MIPIDP2 interface; the LD20 interface is electrically connected to the MIPIDN2 interface; the LD21 interface is electrically connected to the MIPIDKP interface; the LD22 interface is electrically connected to the MIPIDKN interface; the LD23 interface is electrically connected to the MIPIDP1 interface; the LDCLK interface is electrically connected to the GPIO50 interface; the HSYNC interface is electrically connected to the MIPIDN1 interface; the VSYNC interface is electrically connected to the MIPIDP0 interface; the LDEN interface is electrically connected to the MIPIDN0 interface; the LCD_EN interface is electrically connected to the GPIO25 interface; and the BL_EN_PWM interface is electrically connected to the GPIO49 interface.

[0046] According to the above scheme, the LED display drive circuit includes a chip U9, and the chip U9 includes pins 1 to 24, wherein pins 1 to 4 are respectively connected to the DRV1_SEG7 to DRV1_SEG10 interfaces; pin 5 is connected to one end of resistors R95 and R97, the other end of resistor R95 is connected to the power supply VDD5V, and the other end of resistor R97 is connected to the DRV1_SDA_1 interface; pin 6 is connected to one end of resistors R94 and R96, the other end of resistor R94 is connected to the power supply VDD5V, and the other end of resistor R96 is connected to the DRV1_SDA_1 interface. Connect to the DRV1_SCL_1 interface; pin 7 is connected to one end of resistor R98, and the other end of resistor R89 ​​is connected to the power supply VDD5V; pins 8 to 15 are connected to the DRV1_GRID1 to DRV1_GRID8 interfaces respectively; pin 16 is grounded; pin 17 is connected to pin 24, and is connected to the power supply VDD5V and one end of the parallel capacitors C74 and C75, and the other end of the parallel capacitors C74 and C75 is grounded; pins 18 to 23 are connected to the DRV1_SEG1 to DRV1_SEG6 interfaces;

[0047] The DRV1_SEG1 interface connects to pin 1 of diodes D84, D74, D64, D54, D44, D34, D24, and D14; the DRV1_SEG2 interface connects to pin 1 of diodes D85, D75, D65, D55, D45, D35, D25, and D15; the DRV1_SEG3 interface connects to pin 1 of diodes D86, D76, D66, D56, D46, D36, D26, and D16; the DRV1_SEG4 interface connects to pin 1 of diodes D87, D77, D67, D57, D47, D37, D27, and D17; the DRV1_SEG5 interface connects to pin 1 of diodes D88, D78, D68, D 58, D48, D38, D28 and D18 pin 1; DRV1_SEG6 interface connects to diodes D89, D79, D69, D59, D49, D39, D29 and D19 pin 1; DRV1_SEG7 interface connects to diodes D90, D80, D70, D60, D50, D40, D30 and D20 pin 1; DRV1_SEG8 interface connects to diodes D91, D81, D71, D61, D51, D41, D31 and D21 pin 1; DRV1_SEG9 interface connects to diodes D92, D82, D72, D62, D52, D42, D32 and D22 pin 1; DRV1_S The EG10 interface connects to pin 1 of diodes D93, D83, D73, D63, D53, D43, D33, and D23; the DRV1_GRID1 interface connects to pin 2 of diodes D14, D15, D16, D17, D18, D19, D20, D21, D22, and D23; the DRV1_GRID2 interface connects to pin 2 of diodes D24, D25, D26, D27, D28, D29, D30, D31, D32, and D33; the DRV1_GRID3 interface connects to pin 2 of diodes D34, D35, D36, D37, D38, D39, D40, D41, D42, and D43; The ID4 interface is connected to pin 2 of diodes D44, D45, D46, D47, D48, D49, D50, D51, D52, and D53; the DRV1_GRID5 interface is connected to pin 2 of diodes D54, D55, D56, D57, D58, D59, D60, D61, D62, and D63; the DRV1_GRID6 interface is connected to pin 2 of diodes D64, D65, D66, D67, D68, D69, D70, D71, D72, and D73; the DRV1_GRID7 interface is connected to pin 2 of diodes D74, D75, D76, D77, D78, D79, D80, D81, D82, and D83;The DRV1_GRID8 interface connects to pin 2 of diodes D84, D85, D86, D87, D88, D89, D90, D91, D92, and D93;

[0048] The LED display driver circuit includes a chip U10, which includes pins 1 to 24, wherein pins 1 to 4 are respectively connected to interfaces DRV2_SEG7 to DRV2_SEG10; pin 5 is connected to one end of resistors R100 and R102, the other end of resistor R100 is connected to power supply VDD5V, and the other end of resistor R102 is connected to interface DRV2_SDA_2; pin 6 is connected to one end of resistors R99 and R101, the other end of resistor R99 is connected to power supply VDD5V, and the other end of resistor R101 is connected to interface DRV2_SCL_2; pins 7 and 16 are grounded; pins 8 to 15 are respectively connected to interfaces DRV2_GRID1 to DRV2_GRID8; pin 17 is connected to pin 24, and is also connected to power supply VDD5V and one end of capacitors C76 and C77 arranged in parallel, and the other ends of capacitors C74 and C75 arranged in parallel are grounded; pins 18 to 23 are connected to interfaces DRV2_SEG1 to DRV2_SEG6;

[0049] The DRV2_SEG1 interface is connected to pin 1 of diodes D164, D154, D144, D134, D124, D114, D104, and D94. The DRV2_SEG2 interface is connected to pin 1 of diodes D165, D155, D145, D135, D125, D115, D105, and D95. The DRV2_SEG3 interface is connected to pin 1 of diodes D166, D156, D146, D136, D126, D116, D106, and D96. The DRV2_SEG4 interface is connected to pin 1 of diodes D167, D157, D147, D137, D127, D117, D107, and D97. The DRV2_SEG5 interface is connected to pin 1 of diodes D168, D158, D148, D138, D128, D118, D108, and D98. The DRV2_SEG6 interface is connected to pin 1 of diodes D169, D159, D149, D139, D129, D119, D109, and D99. The DRV2_SEG7 interface is connected to pin 1 of diodes D170, D160, D150, D140, D130, D120, D110, and D100. The DRV2_SEG8 interface is connected to pin 1 of diodes D171, D161, D151, D141, D131, D121, D111, and D101. pin; DRV2_SEG9 interface connects to pin 1 of diodes D172, D162, D152, D142, D132, D122, D112 and D102; DRV2_SEG10 interface connects to pin 1 of diodes D173, D163, D153, D143, D133, D123, D113 and D103; DRV2_GRID1 interface connects to pin 2 of diodes D94, D95, D96, D97, D98, D99, D100, D101, D102 and D103; DRV2_GRID2 interface connects to diodes D104, D105, D106, D107, D108, D109, D The DRV2_GRID3 interface connects to pins 2 of diodes D114, D115, D116, D117, D118, D119, D120, D121, D122, and D123; the DRV2_GRID4 interface connects to pins 2 of diodes D124, D125, D126, D127, D128, D129, D130, D131, D132, and D133; the DRV2_GRID5 interface connects to pins 2 of diodes D134, D135, D136, D137, D138, D139, D140, D141, D142, and D143;The DRV2_GRID6 interface connects to pin 2 of diodes D144, D145, D146, D147, D148, D149, D150, D151, D152, and D153. The DRV2_GRID7 interface connects to pin 2 of diodes D154, D155, D156, D157, D158, D159, D160, D161, D162, and D163. The DRV2_GRID8 interface connects to pin 2 of diodes D164, D165, D166, D167, D168, D169, D170, D171, D172, and D173.

[0050] The DRV1_SCL_1 interface is electrically connected to the GPIO23 interface; the DRV1_SDA_1 interface is electrically connected to the GPIO24 interface;

[0051] The DRV2_SCL_2 interface is electrically connected to the GPIO27 interface; the DRV2_SDA_2 interface is electrically connected to the GPIO28 interface.

[0052] Compared with the existing technology, the beneficial effects achieved by the present invention are as follows: the step-down conversion circuit chip adopts advanced switching power supply technology, with high conversion efficiency, thereby reducing energy consumption to a certain extent; through a precise feedback control mechanism, the stability of the output voltage can be maintained; at the same time, an integrated design is adopted, with a compact size and lightweight structure; a large-size and low-cost display solution is achieved, the distance between the LED and LCD is less than 4mm, and the combination of the two has a strong integrity, realizing the touch function of the entire display area, which has greatly improved the functional use and visual effect compared with the traditional display control interface. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation of the present invention. In the accompanying drawings:

[0054] Figure 1 This is a structural diagram of a display interaction device combining LED and LCD in the utility model;

[0055] Figure 2 This is a schematic diagram of the touch cover and display module structure of a display interactive device combining LED and LCD in the present invention;

[0056] Figure 3 This is a schematic diagram of the PCB control circuit board structure of a display interactive device combining LED and LCD in the utility model;

[0057] Figure 4This is a schematic diagram of the connection between the microprocessor pins and part of the circuit of a display interactive device combining LED and LCD in the utility model;

[0058] Figure 5 This is a schematic diagram of the connection of a step-down conversion circuit for a display interactive device combining LED and LCD in the utility model;

[0059] Figure 6 This is a schematic diagram of the connection of a crystal oscillator reset circuit for a display interactive device combining LED and LCD in the utility model;

[0060] Figure 7 This is a schematic diagram of the connection of a filter and voltage stabilizing circuit for a display interactive device combining LED and LCD in the utility model;

[0061] Figure 8 This is a schematic diagram of the Flash storage circuit connection of a display interactive device combining LED and LCD in the utility model;

[0062] Figure 9 This is a schematic diagram of the TP sensor touch screen input circuit connection of a display interactive device combining LED and LCD in this utility model;

[0063] Figure 10 This is a schematic diagram of the debugging circuit connection of a display interactive device combining LED and LCD in the utility model;

[0064] Figure 11 This is a schematic diagram of a TFT display screen driving circuit of a display interactive device combining LED and LCD in the utility model;

[0065] Figure 12 This is a schematic diagram of the connection of the left LED display drive circuit of a display interactive device combining LED and LCD in the utility model;

[0066] Figure 13 This is a schematic diagram of the connection of the right LED display drive circuit of a display interactive device combining LED and LCD in the present invention;

[0067] In the figure: 1. touch cover; 2. display module; 201. LED display membrane; 202. LCD display; 3. fixing bracket; 4. PCB control circuit board. DETAILED DESCRIPTION

[0068] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0069] See also Figure 1 The utility model provides a technical solution: a display interaction device combining LED and LCD, characterized in that: the display interaction device includes a touch cover 1, a display module 2, a fixed bracket 3 and a PCB control circuit board 4; the PCB control circuit board 4 is fixedly installed at the lower end of the fixed bracket 3; the display module 2 is fixedly installed at the upper end of the fixed bracket 3; the touch cover 1 is glued to the upper end of the display module 2.

[0070] See also Figure 2 The display module 2 includes an LED display film 201 and an LCD display screen 202; the distance between the LED display film 201 and the LCD display screen 202 is less than 4 mm.

[0071] See also Figure 3 The PCB control circuit board 4 includes a microprocessor, a DCDC power supply circuit, a Flash storage circuit, a TP sensor touch screen input circuit, a debugging circuit, a TFT display screen drive circuit, and an LED display drive circuit; the DCDC power supply circuit, the Flash storage circuit, the TP sensor touch screen input circuit, the debugging circuit, the TFT display screen drive circuit, and the LED display drive circuit are all connected to the microprocessor.

[0072] See also Figure 4 In this embodiment, the microprocessor model U1 is Lianyang IT9866; the models of resistors R2 and R4 are 240R_1%; the model of resistor R3 is 10K_5%; the model of resistor 10 is 12K_1%; the model of capacitor C3 is 2.2uF_±10%_16V; and the model of diode D1 is NC / ESDA0402-05.

[0073] See also Figure 5In this embodiment, the chip U5 to U7 in the buck converter circuit are all LP3201AB5F; the inductors L3, L4, and L5 are all 2.2uH, 1A, 3*3*1.5mm; the resistors R72, R79, R81, R82, and R86 are all 100K_1%, the resistor R73 is 280K_1%, the resistor R74 is 62K_1%, and the resistor R80 is 93.1K_1%; the model of resistor R85 is 200K_1%; the model of capacitors C53, C57, C59, C61, C66 and C69 is 10uF_±10%_25V; the model of capacitors C55, C56, C58, C62, C69 and C70 is 100nF_±10%_50V; the model of capacitors C54, C60 and C67 is NC / 22pF_±10%_50V.

[0074] See also Figure 6 In this embodiment, the model of the crystal oscillator Y1 in the crystal oscillator reset circuit is 32.768k_12.5pF; the model of the crystal oscillator Y2 is 12MHz_20pF; the models of the capacitors C1, C2, C5 and C6 are 18pF_±10%_50V; the models of the capacitors C4, C7, C8, C64 and C65 are 100nF_±10%_50V; the model of the capacitor C63 is 330nF_±10%_50V The resistor R1 is 1M_5%; the resistors R5, R9, R11, and R12 are 10K_5%; the resistors R83 and R84 are 0R_5%; the transistor Q1 is MMBT3904; the diodes D10 to D13 are all ESDA0402-05; the chip U2 is TPV6823R-TR; the patch J5 is MICRO-B-XNJ-073;

[0075] See also Figure 7 In this embodiment, the capacitors C9 to C17, C22 to C24, C28 to C31, C33, C34, C36, and C38 in the filtering and voltage stabilization circuit are 100nF_±10%_25V; the capacitors C18 to C21, C25, C26, C32, C35, C37, and C39 are 4.7uF_±10%_25V;

[0076] See also Figure 8 In this embodiment, the resistors R23 to R25, R27, R29, and R31 in the Flash storage circuit are of type 470R_5%; the resistors R26, R28, and R30 are of type 10K_5%; the capacitor C40 is of type 100nF_±10%_50V; and the chip U3 is of type XT26G01CWSIGA.

[0077] See also Figure 9 In this embodiment, the resistors R6 to R8 in the TP sensor touch screen input circuit are 2.2K_5%; the resistors R50, R55, and R57 are 33R_5%; the resistor R63 is 10K_5%; the capacitor C41 is 4.7uF_±10%_25V; the capacitors C42 and C46 are 100nF_±10%_50V; and the diodes D2 to D5 are ESDA0402-05.

[0078] See also Figure 10 In this embodiment, the model of the patch J1 in the debugging circuit is TU1252WNV-08; the model of the patch J4 is 2.0-4P; the model of the diodes D7 and D8 is ESDA0402-05; the model of the diode D9 is SMF6.0CA; the model of the ferrite beads FB1 and FB2 is 220R_100MHz_2A; the model of the inductor L2 is NC / ISL0405-01; the model of the capacitor C50 is 10uF_±10%_25V; the model of the capacitor C51 is 100uF / 10V; the model of the capacitor C51 is 100nF_±10%_50V; the model of the resistors R71 and R78 is 100R_5%; the model of the resistors R68, R69, R70, R75, R76 and R77 is 10K_1%; the model of the transistors Q2 and Q32N7002;

[0079] See also Figure 11 In this embodiment, the model of the TFT display driver circuit patch J2 is FPC-0.5-6P; the model of the chip U4 is LP3321QVF; the model of the resistors R32 to R56, R58 to R62, and R66 is 470R_5%; the model of the resistor R67 is 2.4R_5%; the model of the resistor R64 is 1K_5%; the model of the resistor R65 is 10K_5%; the model of the capacitor C45 is NC / 100pF_±10%_50V; the model of the capacitor C47 is 3 30nF_±10%_50V; capacitor C48 is 10uF_±10%_10V; capacitor C52 is 100nF_±10%_50V; capacitor C49 is 1uF_±10%_50V; capacitor C43 is 4.7uF_±10%_25V; capacitor C44 is 100nF_±10%_50V; inductor L1 is 10uH, 770mA, 3*3*1.5mm; diode D6 is SS24L;

[0080] See also Figure 12 and 13In this embodiment, the capacitors C74 and C75 in the LED display driver circuit are of 1uF_±10%_25V; the resistors R94, R95, and R98 are of 10K_1%; the resistors R96 and R97 are of 100R_5%; the diodes D14 to D93 are all of WHITE; the capacitors C76 and C77 are of 1uF_±10%_25V; the resistors R9 and R100 are of 10K_1%; the resistors R101 and R102 are of 100R_5%; the diodes D94 to D173 are all of WHITE;

[0081] The working principle of the utility model is as follows: the microprocessor is based on the Lianyang IT9866 platform, and the peripheral circuit includes a DCDC power supply circuit, a Flash storage circuit, a TP sensor touch screen input circuit, and a TFT display screen drive circuit, both of which have the same principle; the system is connected to the power supply, and the DCDC power supply circuit stably steps down the original power supply to the voltage value required by the circuit. The microprocessor initializes and executes the display program, reads the Flash memory, obtains picture or video data, writes it to the TFT display screen through the RGB interface, and lights up the TFT display screen. This completes the display of the LCD area in the middle of the display module, sends I2C protocol data through the I2C interface, controls the LED driver, and drives the 10-row and 8-column LED display array to light up the LED membrane display areas on both sides. At this point, the display module is completed. When a touch signal is input, the TP sensor touch screen wakes up the microprocessor through the INT interrupt signal. The microprocessor reads the TP sensor touch screen controller through the I2C protocol, obtains touch position information, and completes the predetermined operation.

[0082] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus.

[0083] Finally, it should be noted that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art will be able to modify the technical solutions described in the aforementioned embodiments or replace some of the technical features therein with equivalents. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included within the scope of protection of the present invention.

Claims

1. A display interactive device combining LED and LCD, characterized in that: The display interaction device comprises a touch cover plate (1), a display module (2), a fixed bracket (3) and a PCB control circuit board (4); the PCB control circuit board (4) is fixedly mounted on the lower end of the fixed bracket (3); the display module (2) is fixedly mounted on the upper end of the fixed bracket (3); and the touch cover plate (1) is glued to the upper end of the display module (2).

2. The display interactive device combining LED and LCD according to claim 1, characterized in that: The display module (2) comprises an LED display film (201) and an LCD display screen (202); the distance between the LED display film (201) and the LCD display screen (202) is less than 4 mm.

3. The display interactive device combining LED and LCD according to claim 1, characterized in that: The PCB control circuit board (4) comprises a microprocessor, a DCDC power supply circuit, a Flash storage circuit, a TP sensor touch screen input circuit, a debugging circuit, a TFT display screen drive circuit and an LED display drive circuit; the DCDC power supply circuit, the Flash storage circuit, the TP sensor touch screen input circuit, the debugging circuit, the TFT display screen drive circuit and the LED display drive circuit are all connected to the microprocessor.

4. The display interactive device combining LED and LCD according to claim 3, characterized in that: The microprocessor model is Lianyang IT9866; the microprocessor U1 includes pins 1 to 128; wherein pin 1 is connected to one end of the resistor R3, and the other end of the resistor R3 is grounded; pins 2, 118, 119, 123, 124 and 128 are empty pins; pin 3 is connected to the RTC_X2 interface; pin 4 is connected to the RTC_X1 interface; pin 5 is connected to the power supply VDD_RTC; pins 6, 23, 32, 41, 58, 69, 87 and 103 are connected to the power supply VDD_IO; pin 7 is connected to the XIN interface; pin 8 is connected to the XOUT interface; pin 9 is connected to the power supply VDD_PULL; pins 10, 51, 52, 73 Pin 11, pin 97, pin 102, pin 115, pin 116 and pin 117 are connected to the power supply VDD_CORE; pin 11 is connected to the RSTN interface; pin 12 is grounded; pins 13 to 22 are connected to the GPIO0 interface to the GPIO9 interface respectively; pin 24 is connected to the GPIO10 interface; pin 25 is connected to the GPIO11 interface; pins 26 to 31 are connected to the GPIO13 interface to the GPIO18 interface respectively; pins 33 to 40 are connected to the GPIO19 interface to the GPIO26 interface respectively; pin 42 is connected to one end of resistor R4, and the other end of resistor R4 is grounded; pin 43 is connected to one end of resistor R2, and the other end of resistor R2 is connected to the power supply VDD_MEM; pins 44 to 49 are connected Power supply VDD_MEM; Pin 50 is connected to power supply VDD_MEMPLL; Pins 53 to 57 are connected to GPIO27 interface to GPIO31 interface respectively; Pins 59 to 64 are connected to GPIO32 interface to GPIO37 interface respectively; Pin 65 is connected to one end of the diode D1 and resistor R10 set in parallel, and the other end of the diode D1 and resistor R10 is grounded; Pin 66 is grounded; Pin 67 is connected to USB_DM interface; Pin 68 is connected to USB_DP interface; Pin 70 is connected to GPIO38 interface; Pin 71 is connected to GPIO40 interface; Pin 72 is connected to GPIO41 interface; Pins 74 to 86 are connected to GPIO42 interface to GPIO54 interface respectively; Pins 88 to 9 Pin 5 connects GPIO55 interface to GPIO62 interface respectively; pin 96 connects GPIO63 interface; pins 98 to 101 connect GPIO64 interface to GPIO67 interface respectively; interface 104 connects one end of capacitor C3, and the other end of C3 is grounded; pin 105 connects MIPIDP3 interface; pin 106 connects MIPIDN3 interface; pin 107 connects MIPIDP2 interface; pin 108 connects MIPIDN2 interface; pin 109 connects MIPICKP interface; pin 110 connects MIPICKN interface; pin 111 connects MIPIDP1 interface; pin 112 connects MIPIDN1 interface; pin 113 connects MIPIDP0 interface;Pin 114 is connected to the MIPIDN0 interface; pin 120 is connected to the LMICIP interface; pin 121 is connected to the LMICIN interface; pin 122 is connected to the MICBIAS interface; pin 125 is grounded; pin 126 is connected to the RHPOUT interface; pin 127 is connected to the LHPOUT interface. ; 5. The display interactive device combining LED and LCD according to claim 3, characterized in that: The DCDC power supply circuit includes a step-down conversion circuit, a crystal oscillator reset circuit and a filter voltage stabilization circuit; The buck conversion circuit includes a buck conversion chip U5, which includes 1 to 5 pins, wherein pin 4 is connected to a power supply VDD5V, a capacitor C53 and one end of a resistor R72, the other end of the capacitor C53 is grounded, the other end of the resistor R72 is connected to pin 1 and one end of a capacitor C58, the other end of the capacitor C58 is grounded; pin 2 is grounded; pin 3 is connected to one end of an inductor L3, the other end of the inductor L3 is connected to one end of a capacitor C54 and a resistor R73 arranged in parallel, one end of capacitors C55 to C57, and a power supply VDD3V3 and VDD3V3_SOC arranged on a capacitor C56, the other ends of capacitors C55 to C57 are grounded respectively, the other ends of the capacitor C54 and the resistor R73 arranged in parallel are connected to one end of the resistor R74 and pin 5, and the other end of the resistor R74 is grounded; The buck conversion circuit includes a buck conversion chip U6, which includes 1 to 5 pins, wherein pin 4 is connected to a power supply VDD5V, a capacitor C59 and one end of a resistor R79, the other end of the capacitor C53 is grounded, and the other end of the resistor R79 is connected to pin 1; pin 2 is grounded; pin 3 is connected to one end of an inductor L4, the other end of the inductor L4 is connected to one end of a capacitor C60 and a resistor R80 arranged in parallel, a power supply VDD11, one end of capacitors C61 and C62, and a power supply VDD1V1 arranged on the capacitor C52, the other ends of the capacitors C61 and C62 are grounded respectively, the other ends of the capacitors C60 and the resistor R80 arranged in parallel are connected to one end of the resistor R81 and pin 5, and the other end of the resistor R81 is grounded; The buck conversion circuit includes a buck conversion chip U7, which includes 1 to 5 pins, wherein pin 4 is connected to a power supply VDD5V, a capacitor C66 and one end of a resistor R82, the other end of the capacitor C66 is grounded, and the other end of the resistor R82 is connected to pin 1; pin 2 is grounded; pin 3 is connected to one end of an inductor L5, the other end of the inductor L5 is connected to one end of a capacitor C67 and a resistor R85 arranged in parallel, one end of capacitors C68 to C70, and a power supply VDD18 arranged on the capacitor C68, and a power supply VDD1V8 arranged on the capacitor C69, the other ends of the capacitors C68 to C70 are grounded respectively, the other ends of the capacitor C67 and the resistor R85 arranged in parallel are connected to one end of the resistor R86 and pin 5, and the other end of the resistor R86 is grounded; The crystal oscillator reset circuit includes a power supply VDD_RTC, the power supply VDD_RTC is connected to one end of a capacitor C4, and the other end of the capacitor C4 is grounded; The crystal oscillator reset circuit also includes a crystal oscillator Y1, one end of the crystal oscillator Y1 is connected to the RTC_X1 interface and one end of the capacitor C1, the RTC_X2 interface is connected to the other end of the crystal oscillator Y1 and one end of the capacitor C5, and the other ends of the capacitors C1 and C5 are grounded; The crystal oscillator reset circuit also includes a resistor R1, one end of the resistor R1 is connected to the XIN interface, the crystal oscillator Y2 and one end of the capacitor C2, the other end of the resistor R1 is connected to the XOUT interface, the other end of the crystal oscillator Y2 and one end of the capacitor C6, and the other ends of the capacitors C2 and C6 are grounded; The crystal oscillator reset circuit also includes a reset chip U2, which includes pins 1 to 5; wherein pin 1 is connected to pin 2 of transistor Q1, pin 2 of transistor Q1 is connected to one end of resistor R11, the other end of resistor R11 is connected to one end of resistor R12 and USB_ID interface, the other end of resistor R12 is connected to power supply VDD_IO, pin 3 of transistor Q1 is connected to one end of resistor R5, RSTN interface and one end of capacitor C7, the other end of resistor R5 is connected to power supply VDD_IO, and the other end of capacitor C7 is grounded; pin 2 is grounded; pin 3 is an empty pin; pin 4 is connected to one end of resistor R9, the other end of resistor R9 is connected to GPIO19 interface; pin 5 is connected to power supply VDD_IO and one end of capacitor C8, and the other end of capacitor C8 is grounded; The crystal oscillator reset circuit also includes a patch J5, which includes pins 1 to 9, wherein pin 1 is connected to one end of a diode D10, one end of capacitors C63 to C65 and a power supply VDD5V, and the other end of the diode D10 is connected to the other end of the capacitors C63 to C65 and grounded; pin 2 is connected to a resistor R83 and one end of a diode D11, the other end of the resistor R83 is connected to a USB_DM interface, and the other end of the diode D11 is grounded; pin 3 is connected to a resistor R84 and one end of a diode D12, the other end of the resistor R84 is connected to a USB_DP interface, and the other end of the diode D12 is grounded; pin 4 is connected to one end of a diode D13 and a USB_ID interface, and the other end of a diode D14 is grounded; pins 5 to 9 are grounded; The filtering and voltage stabilizing circuit includes capacitors C9 to C21 arranged in parallel, power supplies VDD1V1 and VDD_CORE are connected to one end of capacitor C9, power supply VDD_MEMPLL is connected to one end of capacitor C19, power supply VDD_PLL is connected to one end of capacitor C21, and the other ends of the capacitors C9 to C21 arranged in parallel are grounded; The filtering and voltage stabilizing circuit further includes capacitors C22 to C26 arranged in parallel, the power supply VDD1V8 and the power supply VDD_MEM are connected to one end of the capacitors C22 to C26, and the other ends of the capacitors C22 and C26 are grounded respectively; The filtering and voltage stabilizing circuit also includes capacitors C28 to C39 arranged in parallel, the power supplies VDD3V3_SOC and the power supply VDD_IO are connected to one end of the capacitor C28, the power supply VDD_XTL is connected to one end of the capacitor C33, the power supply VDD_USB is connected to one end of the capacitor C34, the power supply VDD_RTC is connected to one end of the capacitor C39, and the other ends of the capacitors C28, C34, C36 and C38 arranged in parallel are grounded respectively.

6. The display interactive device combining LED and LCD according to claim 3, characterized in that: The Flash storage circuit includes a chip U3, and the chip U3 includes pins 1 to 9, wherein pin 1 is connected to one end of a resistor R31, and the other end of the resistor R31 is connected to the AXISPI_CS0 interface; pin 2 is connected to one end of a resistor R25, and the other end of the resistor R25 is connected to the AXISPI_D1 interface; pin 3 is connected to one end of a resistor R27, and the other end of the resistor R27 is connected to the AXISPI_D2 interface; pin 5 is connected to one end of a resistor R24, and the other end of the resistor R24 ​​is connected to the AXISPI_D0 interface; pin 6 is connected to one end of a resistor R23, and the other end of the resistor R23 is connected to the AXISPI_CLK interface; pin 7 is connected to one end of a resistor R29, and the other end of the resistor R29 is connected to the AXISPI_D3 interface; pin 8 is connected to a power supply VDD_IO and one end of a capacitor C40, and the other end of the capacitor C40 is connected to pins 4 and 9 and grounded; The power supply VDD_IO is connected to one end of resistors R26, R28 and R30, the other end of resistor R26 is connected to the AXISPI_CS0 interface, the other end of resistor R28 is connected to the AXISPI_D2 interface, and the other end of resistor R30 is connected to the AXISPI_D3 interface; The AXISPI_CS0 interface is electrically connected to the GPIO5 interface; the AXISPI_D0 interface is electrically connected to the GPIO6 interface; The AXISPI_D1 interface is electrically connected to the GPIO7 interface; the AXISPI_D2 interface is electrically connected to the GPIO8 interface; the AXISPI_D3 interface is electrically connected to the GPIO9 interface; and the AXISPI_CLK interface is electrically connected to the GPIO10 interface.

7. The display interactive device combining LED and LCD according to claim 3, characterized in that: The TPsensor touch screen input circuit includes a patch J3, which includes pins 1 to 8, wherein pin 1 is connected to one end of a diode D2 and a TP_RSTn interface, and the other end of the diode D2 is grounded; pin 2 is connected to a power supply VDD3V3_LCD_1; pin 3 is grounded; pin 4 is connected to a resistor R50 and one end of a diode D3, the other end of the resistor R50 is connected to a TP_INTn interface, and the other end of the diode D3 is grounded; pin 5 is connected to a resistor R55 and one end of a diode D4, the other end of the resistor R55 is connected to a TP_SDA interface, and the other end of the diode D4 is grounded; pin 6 is connected to a resistor R57 and one end of a diode D5, the other end of the resistor R57 is connected to a TP_SCL interface, and the other end of the diode D5 is grounded; pins 7 and 8 are empty pins; The TP sensor touch screen input circuit also includes a resistor R63, one end of the resistor R63 is connected to the power supply VDD3V3_LCD_1, the other end of the resistor R63 is connected to the TP_RSTn interface and one end of the capacitor C46, ​​and the other end of the capacitor C46 is grounded; The power supply VDD3V3_LCD_1 is connected to one end of the capacitors C41 and C42; the other ends of the capacitors C41 and C42 are grounded respectively; The power supply VDD3V3_SOC is connected to one end of resistors R6, R7 and R8, the other end of resistor R6 is connected to the GPIO44 interface, and the GPIO44 interface is electrically connected to the TP_INTn interface; the other end of resistor R7 is connected to the GPIO46 interface, and the GPIO46 interface is electrically connected to the TP_SDA interface; the other end of resistor R8 is connected to the GPIO47 interface, and the GPIO47 interface is electrically connected to the TP_SCL interface; the GPIO45 interface is electrically connected to the TP_RSTn interface.

8. The display interactive device combining LED and LCD according to claim 3, characterized in that: The debugging circuit includes a patch J1, and the patch J1 includes pins 1 to 8, wherein pin 1 is connected to the SSPI_CLK interface; Pin 2 is connected to SSPI_CSN and one end of resistor R17, and the other end of resistor R17 is connected to power supply VDD_IO; Pin 3 is connected to SSPI_MOSI interface; Pin 4 is connected to SSPI_MISO interface; Pins 5 and 8 are grounded; Pin 6 is connected to DBG_TX interface, Pin 7 is connected to one end of capacitor C27 and power supply VDD_IO, and the other end of capacitor C27 is grounded; The debugging circuit also includes a patch J4, which includes pins 1 to 6, wherein pin 1 of the patch J4 is connected to one end of the diode D7, one end of the diode D8, one end of the diode D9, pin 1 of the inductor L2, and one end of the magnetic bead FB1, the other end of the diode D7 is connected to the RXD interface and pin 3 of the patch J4, the other end of the diode D8 is connected to the TXD interface and pin 4 of the patch J4, the other end of the diode D9 is connected to pin 2 of the patch J4, pin 2 of the inductor L2, and one end of the magnetic bead FB2, the other end of the magnetic bead FB1 is connected to pin 4 of the inductor L2, one end of the capacitors C50 and C51, and is grounded, and the other end of the magnetic bead FB2 is connected to pin 3 of the inductor L2, the other ends of the capacitors C50 and C51, and the power supply VDD5V; The RXD interface is connected to one end of the resistor R71, the other end of the resistor R71 is connected to one end of the resistor R69 and the 3-pin of the transistor Q2, the other end of the resistor R69 is connected to the power supply VDD5V, the 1-pin of the transistor Q2 is connected to one end of the resistor R68, the other end of the resistor 68 is connected to the power supply VDD3V3_SOC, one end of the resistor R70 of the 2-pin of the transistor Q2 and the UART_RX interface, the other end of the resistor R70 is connected to the power supply VDD3V3_SOC; The TXD interface is connected to one end of the resistor R78, the other end of the resistor R78 is connected to one end of the resistor R76 and the 3-pin of the transistor Q3, the other end of the resistor R76 is connected to the power supply VDD5V, the 1-pin of the transistor Q3 is connected to one end of the resistor R75, the other end of the resistor 75 is connected to the power supply VDD3V3_SOC, one end of the resistor R77 of the 2-pin of the transistor Q3 and the UART_TX interface, the other end of the resistor R77 is connected to the power supply VDD3V3_SOC; The SSPI_CLK interface is electrically connected to the GPIO0 interface; the SSPI_CSN interface is electrically connected to the GPIO1 interface; the SSPI_MOSI interface is electrically connected to the GPIO2 interface; the SSPI_MISO interface is electrically connected to the GPIO3 interface; the DBG_TX interface is electrically connected to the GPIO4 interface; the UART_RX interface is electrically connected to the GPIO20 interface; and the UART_TX interface is electrically connected to the GPIO21 interface.

9. The display interactive device combining LED and LCD according to claim 3, characterized in that: The TFT display screen driving circuit includes a patch J2, and the patch J2 includes pins 1 to 42; wherein pin 1 is connected to the LED_Negative interface, pin 2 is connected to the LED_Positive interface; pin 3 is grounded; pin 4 is connected to the power supply VDD3V3_LCD_2; pin 5 is connected to one end of the resistor R38, and the other end of the resistor R38 is connected to the LD0 interface; pin 6 is connected to one end of the resistor R39, and the other end of the resistor R38 is connected to the LD1 interface; pin 7 is connected to one end of the resistor R32, and the other end of the resistor R32 is connected to the LD2 interface; pin 8 is connected to one end of the resistor R33, The other end of resistor R33 is connected to the LD3 interface; pin 9 is connected to one end of resistor R34, and the other end of resistor R34 is connected to the LD4 interface; pin 10 is connected to one end of resistor R35, and the other end of resistor R35 is connected to the LD5 interface; pin 11 is connected to one end of resistor R36, and the other end of resistor R36 is connected to the LD6 interface; pin 12 is connected to one end of resistor R37, and the other end of resistor R37 is connected to the LD7 interface; pin 13 is connected to one end of resistor R40, and the other end of resistor R40 is connected to the LD8 interface; pin 14 is connected to one end of resistor R41, and the other end of resistor R41 is connected to the LD9 interface; Pin 15 is connected to one end of resistor R42, and the other end of resistor R42 is connected to LD10 interface; pin 16 is connected to one end of resistor R43, and the other end of resistor R43 is connected to LD11 interface; pin 17 is connected to one end of resistor R44, and the other end of resistor R44 is connected to LD12 interface; pin 18 is connected to one end of resistor R45, and the other end of resistor R45 is connected to LD13 interface; pin 19 is connected to one end of resistor R46, and the other end of resistor R46 is connected to LD14 interface; pin 20 is connected to one end of resistor R47, and the other end of resistor R47 is connected to LD15 interface; pin 21 is connected to one end of resistor R48, and the other end of resistor R48 is connected to LD16 interface; pin 22 is connected to one end of resistor R49, and the other end of resistor R49 is connected to LD17 interface; pin 23 is connected to one end of resistor R51, and the other end of resistor R51 is connected to LD18 interface; pin 24 is connected to one end of resistor R52, and the other end of resistor R52 is connected to LD19 interface ; Pin 25 is connected to one end of resistor R51, and the other end of resistor R53 is connected to LD20 interface; Pin 26 is connected to one end of resistor R54, and the other end of resistor R54 is connected to LD21 interface; Pin 27 is connected to one end of resistor R56, and the other end of resistor R56 is connected to LD22 interface; Pin 28 is connected to one end of resistor R55, and the other end of resistor R55 is connected to LD23 interface; Pin 28 is grounded; Pin 30 is connected to one end of resistor R59 and capacitor C45, the other end of capacitor C45 is grounded, and the other end of resistor R59 is connected to LDCLK interface; Pin 31 is connected to LCD_ON interface; Pin 32 is connected to one end of resistor R60, and the other end of resistor R60 is connected to HSYNC interface; Pin 33 is connected to one end of resistor R61, and the other end of resistor R61 is connected to VSYNC interface; Pin 34 is connected to one end of resistor R62, and the other end of resistor R62 is connected to LDEN interface; Pin 36 is grounded; Pins 35 and 37 to 42 are empty pins; The power supply VDD3V3_LCD_2 is connected to one end of the capacitors C43 and C44, and the other ends of the capacitors C43 and C44 are grounded respectively; The LCD_ON interface is connected to one end of resistors R64 and R65, the other end of resistor R64 is connected to the LCD_EN interface, and the other end of resistor R65 is grounded; The TFT display screen driving circuit also includes a chip U4, which includes pins 1 to 7, wherein pin 1 is connected to one end of a resistor R67 and an LED_Negative interface, and the other end of the resistor R67 is grounded; pin 2 is an empty pin; pins 3 and 7 are grounded; pin 4 of the chip U4 is connected to pin 2 of the inductor L1 and the positive electrode of the diode D6, and the negative electrode of the diode is connected to one end of capacitors C52 and C49 and the LED_Positive interface; pin 1 of the inductor is connected to pin 6 of the chip U4, one end of capacitors C47 and C48 arranged in parallel, and a power supply VDD5V, and the other end of the capacitors C47 and C48 arranged in parallel is grounded; pin 5 is connected to one end of a resistor R66, and the other end of the resistor R66 is connected to the BL_EN_PWM interface; The LD0 to LD16 interfaces are electrically connected to the GPIO51 to GPIO67 interfaces respectively; the LD17 interface is electrically connected to the MIPIDP3 interface; the LD18 interface is electrically connected to the MIPIDN3 interface; the LD19 interface is electrically connected to the MIPIDP2 interface; the LD20 interface is electrically connected to the MIPIDN2 interface; the LD21 interface is electrically connected to the MIPIDKP interface; the LD22 interface is electrically connected to the MIPIDKN interface; the LD23 interface is electrically connected to the MIPIDP1 interface; the LDCLK interface is electrically connected to the GPIO50 interface; the HSYNC interface is electrically connected to the MIPIDN1 interface; the VSYNC interface is electrically connected to the MIPIDP0 interface; the LDEN interface is electrically connected to the MIPIDN0 interface; the LCD_EN interface is electrically connected to the GPIO25 interface; and the BL_EN_PWM interface is electrically connected to the GPIO49 interface.

10. The display interactive device combining LED and LCD according to claim 3, characterized in that: The LED display drive circuit includes a chip U9, which includes pins 1 to 24, wherein pins 1 to 4 are respectively connected to interfaces DRV1_SEG7 to DRV1_SEG10; pin 5 is connected to one end of resistors R95 and R97, the other end of resistor R95 is connected to power supply VDD5V, and the other end of resistor R97 is connected to DRV1_SDA_1 interface; pin 6 is connected to one end of resistors R94 and R96, the other end of resistor R94 is connected to power supply VDD5V, and the other end of resistor R96 is connected to DRV 1_SCL_1 interface; pin 7 is connected to one end of resistor R98, and the other end of resistor R89 ​​is connected to power supply VDD5V; pins 8 to 15 are respectively connected to DRV1_GRID1 to DRV1_GRID8 interfaces; pin 16 is grounded; pin 17 is connected to pin 24, and is connected to power supply VDD5V and one end of capacitors C74 and C75 arranged in parallel, and the other end of capacitors C74 and C75 arranged in parallel is grounded; pins 18 to 23 are connected to DRV1_SEG1 to DRV1_SEG6 interfaces; The DRV1_SEG1 interface connects to pin 1 of diodes D84, D74, D64, D54, D44, D34, D24, and D14; the DRV1_SEG2 interface connects to pin 1 of diodes D85, D75, D65, D55, D45, D35, D25, and D15; the DRV1_SEG3 interface connects to pin 1 of diodes D86, D76, D66, D56, D46, D36, D26, and D16; the DRV1_SEG4 interface connects to pin 1 of diodes D87, D77, D67, D57, D47, D37, D27, and D17; the DRV1_SEG5 interface connects to diodes D88, D78, D68, D 58, D48, D38, D28 and 1 pin of D18; DRV1_SEG6 interface connects 1 pin of diodes D89, D79, D69, D59, D49, D39, D29 and D19; DRV1_SEG7 interface connects 1 pin of diodes D90, D80, D70, D60, D50, D40, D30 and D20; DRV1_SEG8 interface connects 1 pin of diodes D91, D81, D71, D61, D51, D41, D31 and D21; DRV1_SEG9 interface connects 1 pin of diodes D92, D82, D72, D62, D52, D42, D32 and D22; DRV1_S The EG10 interface connects to pin 1 of diodes D93, D83, D73, D63, D53, D43, D33, and D23; the DRV1_GRID1 interface connects to pin 2 of diodes D14, D15, D16, D17, D18, D19, D20, D21, D22, and D23; the DRV1_GRID2 interface connects to pin 2 of diodes D24, D25, D26, D27, D28, D29, D30, D31, D32, and D33; the DRV1_GRID3 interface connects to pin 2 of diodes D34, D35, D36, D37, D38, D39, D40, D41, D42, and D43; The ID4 interface is connected to the 2 pins of diodes D44, D45, D46, D47, D48, D49, D50, D51, D52 and D53; the DRV1_GRID5 interface is connected to the 2 pins of diodes D54, D55, D56, D57, D58, D59, D60, D61, D62 and D63; the DRV1_GRID6 interface is connected to the 2 pins of diodes D64, D65, D66, D67, D68, D69, D70, D71, D72 and D73; the DRV1_GRID7 interface is connected to the 2 pins of diodes D74, D75, D76, D77, D78, D79, D80, D81, D82 and D83;The DRV1_GRID8 interface connects to pin 2 of diodes D84, D85, D86, D87, D88, D89, D90, D91, D92, and D93; The LED display driving circuit includes a chip U10, and the chip U10 includes pins 1 to 24, wherein pins 1 to 4 are respectively connected to interfaces DRV2_SEG7 to DRV2_SEG10; pin 5 is connected to one end of resistors R100 and R102, the other end of resistor R100 is connected to power supply VDD5V, and the other end of resistor R102 is connected to DRV2_SDA_2 interface; pin 6 is connected to one end of resistors R99 and R101, the other end of resistor R99 is connected to power supply VDD5V, and the other end of resistor R101 is connected to DRV2_SCL_2 interface; pins 7 and 16 are grounded; pins 8 to 15 are respectively connected to interfaces DRV2_GRID1 to DRV2_GRID8; pin 17 is connected to pin 24, and is connected to power supply VDD5V and one end of capacitors C76 and C77 arranged in parallel, and the other end of capacitors C74 and C75 arranged in parallel is grounded; pins 18 to 23 are connected to interfaces DRV2_SEG1 to DRV2_SEG6; The DRV2_SEG1 interface is connected to pin 1 of diodes D164, D154, D144, D134, D124, D114, D104 and D94; the DRV2_SEG2 interface is connected to pin 1 of diodes D165, D155, D145, D135, D125, D115, D105 and D95; the DRV2_SEG3 interface is connected to pin 1 of diodes D166, D156, D146, D136, D126, D116, D106 and D96; the DRV2_SEG4 interface is connected to pin 1 of diodes D167, D157, D147, D137, D127, D117, D107 and D97; The DRV2_SEG5 interface is connected to the 1st pin of diodes D168, D158, D148, D138, D128, D118, D108 and D98; the DRV2_SEG6 interface is connected to the 1st pin of diodes D169, D159, D149, D139, D129, D119, D109 and D99; the DRV2_SEG7 interface is connected to the 1st pin of diodes D170, D160, D150, D140, D130, D120, D110 and D100; the DRV2_SEG8 interface is connected to the 1st pin of diodes D171, D161, D151, D141, D131, D121, D111 and D101. pin; DRV2_SEG9 interface connects to pin 1 of diodes D172, D162, D152, D142, D132, D122, D112 and D102; DRV2_SEG10 interface connects to pin 1 of diodes D173, D163, D153, D143, D133, D123, D113 and D103; DRV2_GRID1 interface connects to pin 2 of diodes D94, D95, D96, D97, D98, D99, D100, D101, D102 and D103; DRV2_GRID2 interface connects to diodes D104, D105, D106, D107, D108, D109, D The DRV2_GRID3 interface is connected to pin 2 of diodes D114, D115, D116, D117, D118, D119, D120, D121, D122, and D123; the DRV2_GRID4 interface is connected to pin 2 of diodes D124, D125, D126, D127, D128, D129, D130, D131, D132, and D133; the DRV2_GRID5 interface is connected to pin 2 of diodes D134, D135, D136, D137, D138, D139, D140, D141, D142, and D143;The DRV2_GRID6 interface is connected to pin 2 of diodes D144, D145, D146, D147, D148, D149, D150, D151, D152, and D153; the DRV2_GRID7 interface is connected to pin 2 of diodes D154, D155, D156, D157, D158, D159, D160, D161, D162, and D163; the DRV2_GRID8 interface is connected to pin 2 of diodes D164, D165, D166, D167, D168, D169, D170, D171, D172, and D173; The DRV1_SCL_1 interface is electrically connected to the GPIO23 interface; the DRV1_SDA_1 interface is electrically connected to the GPIO24 interface; The DRV2_SCL_2 interface is electrically connected to the GPIO27 interface; the DRV2_SDA_2 interface is electrically connected to the GPIO28 interface.

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