Automatic driving domain controller test system

Abstract

The utility model discloses an automatic driving domain controller test system. The automatic driving domain controller test system comprises an upper computer and a wire harness, wherein the upper computer is electrically connected with a PCBA (Printed Circuit Board Assembly) of an automatic driving domain controller to be tested through the wire harness; external interfaces of the PCBA comprise a first type of external interfaces and a second type of external interfaces, the first type of external interfaces are used for in-board circuit connection according to test items, and the second type of external interfaces are used for out-board circuit connection; and when line connection of the first type of external interface and the second type of external interface is completed, board card testing is carried out on the PCBA through the upper computer, and a board card testing result corresponding to each testing item is displayed. According to the technical scheme, the upper computer is used for carrying out board card testing on the PCBA, testing personnel only need to carry out simple wire harness connection, the PCBA testing can be rapidly completed, the PCBA testing efficiency can be improved, and the testing result has high reliability and accuracy.

Description

Technical Field

[0001] The present application relates to an autonomous driving domain controller testing system. Background Art

[0002] During the deployment of autonomous vehicles, it is necessary to test the quality of components of autonomous vehicles. For example, after the PCBA (Printed Circuit Board Assembly) of the autonomous driving domain controller is completed, the production quality of the PCBA needs to be tested to rule out hardware problems caused by patch production or functional abnormalities after the board is offline due to defects in the electronic materials themselves.

[0003] At present, the offline inspection of the PCBA of the autonomous driving domain controller is mainly carried out manually by testers. This inspection solution has the problems of low efficiency and unreliable test results. Utility Model Content

[0004] The purpose of the embodiments of the present application is to solve at least one of the above-mentioned technical defects. In particular, an autonomous driving domain controller testing system is proposed to perform semi-automatic testing of PCBAs produced on-site in batches, thereby improving the detection efficiency and the reliability of the detection results.

[0005] The present application embodiment adopts the following technical solutions:

[0006] An embodiment of the present application provides an autonomous driving domain controller test system, the autonomous driving domain controller test system comprising a host computer and a wiring harness, wherein the host computer and a PCBA of an autonomous driving domain controller to be tested are electrically connected through the wiring harness;

[0007] The external interface of the PCBA includes a first type of external interface and a second type of external interface, wherein the first type of external interface is used for connecting the circuits within the board according to the test items, and the second type of external interface is used for connecting the circuits outside the board;

[0008] When the line connection between the first type external interface and the second external interface is completed, the PCBA is tested by the host computer, and the board test result corresponding to each test item is displayed.

[0009] Optionally, the PCBA includes a main SOC chip, a slave SOC chip, an MCU chip, a first Switch chip, and a second Switch chip. The main SOC chip and the slave SOC chip are used to realize the computing power of the autonomous driving domain controller, the MCU chip is used to communicate with the chassis of the autonomous driving vehicle, and the first Switch chip and the second Switch chip are used to realize network interaction of the autonomous driving domain controller.

[0010] Optionally, the second type of external interface includes an RGMII external interface of the first Switch chip or an RGMII external interface of the second Switch chip, and the PCBA is electrically connected to the host computer through the RGMII external interface of the first Switch chip or the second Switch chip.

[0011] Optionally, the second type of external interface also includes all SGMII external interfaces of the first Switch chip and the second Switch chip and other RGMII external interfaces except for the one used for electrical connection with the host computer;

[0012] Each SGMII external interface and each RGMII external interface are connected to a network device, and the network device is configured with an IP address of the same network segment.

[0013] Optionally, the first type of external interface includes a multi-channel CAN external interface of the PCBA, and the multi-channel CAN external interface is connected in parallel according to a star topology to form a bus structure.

[0014] Optionally, the multiple CAN external interfaces include one CAN external interface of the master SOC chip, one CAN external interface of the slave SOC chip, and multiple CAN external interfaces of the MCU chip.

[0015] Optionally, the first type of external interface further includes multiple groups of UART external interfaces, at least one group of RS422 external interfaces and multiple IO external interfaces of the MCU chip, wherein every two IO external interfaces belong to a port cluster of the same heat dissipation element;

[0016] Each group of UART external interfaces of the MCU chip performs an internal loopback connection;

[0017] The RS422 external interface of the MCU chip is looped back;

[0018] The IO external interface for transmitting the control signal and the IO external interface for transmitting the feedback signal in every two IO external interfaces are loop-connected.

[0019] Optionally, the first type of external interface further includes multiple groups of UART external interfaces of the main SOC chip, at least one group of CSI external interfaces, at least one group of HDMI external interfaces and at least one group of USB external interfaces;

[0020] Each group of UART external interfaces of the main SOC chip performs an internal loopback connection;

[0021] The CSI external interface of the main SOC chip is connected to a CSI camera;

[0022] The HDMI external interface of the main SOC chip is connected to a display;

[0023] The USB external interface of the main SOC chip is connected to a U disk for mounting.

[0024] Optionally, the first type of external interface further includes multiple groups of UART external interfaces of the slave SOC chip, at least one group of CSI external interfaces, at least one group of HDMI external interfaces, and at least one group of USB external interfaces;

[0025] Each group of UART external interfaces of the slave SOC chip is connected to the group by a loopback connection;

[0026] The CSI external interface of the slave SOC chip is connected to a CSI camera;

[0027] The HDMI external interface of the slave SOC chip is connected to a display;

[0028] The USB external interface of the SOC chip is connected to a U disk for mounting.

[0029] Optionally, the first type of external interface also includes a UPHY external interface of the master SOC chip and a UPHY external interface of the slave SOC chip;

[0030] The UPHY external interface of the master SOC chip is connected to the UPHY external interface of the slave SOC chip.

[0031] At least one of the above technical solutions adopted in the embodiments of the present application can achieve the following beneficial effects:

[0032] When the PCBA patching of the autonomous driving domain controller is completed, the tester only needs to connect the wiring harness of the PCBA to be tested. After completing the electrical connection between the PCBA to be tested and the host computer through the wiring harness of the test system, the host computer can perform simple test operations on the host computer to execute the board test of the PCBA. The tester can intuitively understand the board test results corresponding to each test item through the visual display results of the host computer. In this way, the tester can promptly discover production problems at the patch site, reduce the impact of delayed delivery caused by production problems such as welding, and achieve the purpose of improving detection efficiency and improving the reliability of detection results. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0034] Figure 1A schematic diagram of the connection relationship between a host computer and a PCBA to be tested shown in an embodiment of the present application;

[0035] Figure 2 This is a schematic diagram of the composition structure of a PCBA of an autonomous driving domain controller shown in an embodiment of the present application. DETAILED DESCRIPTION

[0036] In order to make the purpose, technical solution and advantages of the present application clearer, the technical solution of the present application will be clearly and completely described below in combination with the specific embodiments of the present application and the corresponding drawings. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present application.

[0037] The following describes the embodiments of the present application in detail, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and should not be construed as limiting the present application. On the contrary, the embodiments of the present application include all changes, modifications and equivalents that fall within the spirit and connotation of the appended claims.

[0038] The technical solutions provided by various embodiments of the present application are described in detail below in conjunction with the accompanying drawings.

[0039] The present application embodiment provides an autonomous driving domain controller testing system, such as Figure 1 As shown, the autonomous driving domain controller test system of the embodiment of the present application includes a host computer and a wiring harness, and the host computer and the PCBA of the autonomous driving domain controller to be tested are electrically connected through the wiring harness, for example, the electrical connection relationship between the host computer and the PCBA is realized through an HDMI (High Definition Multimedia Interface) wiring harness or a LAN (Local Area Network) wiring harness;

[0040] The external interface of the PCBA includes a first type of external interface and a second type of external interface, wherein the first type of external interface is used for connecting the circuits within the board according to the test items, and the second type of external interface is used for connecting the circuits outside the board;

[0041] When the line connection between the first type external interface and the second external interface is completed, the PCBA is tested by the host computer, and the board test result corresponding to each test item is displayed.

[0042] The test items in this embodiment are related to factors such as the circuit composition of the PCBA and the function of the PCBA. Figure 2 As shown, when the PCBA includes a main SOC1 (System on Chip, also known as a system on chip, meaning that it is a product, an integrated circuit with a dedicated target, containing a complete system and all the contents of embedded software) chip, a slave SOC2 chip, an MCU (Microcontroller Unit, microprocessor) chip, a first Switch1 chip, and a second Switch2 chip, the test items may include SOC function test, MCU function test, and communication test.

[0043] Before conducting board testing, the test strategy corresponding to the test item can be written into an executable computer program. In this way, when the host computer runs the computer program, for example, by pressing the start button of the computer program, the corresponding test module can be started to execute the corresponding test item, thereby realizing automated board testing.

[0044] It should be noted that the present application is to form an executable computer program in a computer language by using a test strategy manually executed by a tester. Those skilled in the art can select a suitable computer language to write a computer program in combination with the prior art, and the present application does not impose any specific restrictions on this.

[0045] In this way, after the PCBA patching of the autonomous driving domain controller is completed, the solution of the present application allows the tester to only perform simple wiring harness connections without the need for the tester to perform specific test items. The tester can intuitively understand the board test results corresponding to each test item through the visual display results, and can promptly discover production problems at the patch site, reduce the impact of delayed delivery caused by production problems such as welding, and achieve the purpose of improving detection efficiency and improving the reliability of detection results.

[0046] In some embodiments of the present application, the PCBA includes a master SOC chip, a slave SOC chip, an MCU chip, a first Switch1 chip, and a second Switch2 chip;

[0047] Two NVIDIA Orin chips can be used as the main SOC chip and the slave SOC chip to provide computing power support; the MCU chip communicates with the chassis of the autonomous driving vehicle to achieve control of the autonomous driving vehicle; and two Switch chips are used to realize the network interaction function of the autonomous driving domain controller.

[0048] In some embodiments of the present application, the second type of external interface can be subdivided into two categories according to the different connection objects, one of which is used for electrical connection with a host computer, and the other is used for electrical connection with a network device.

[0049] Specifically, the second type of external interface includes an RGMII (Reduced Gigabit Media Independent Interface) external interface of the first Switch chip or an RGMII external interface of the second Switch chip, and the PCBA is electrically connected to the host computer through the RGMII external interface of the first Switch chip or the second Switch chip.

[0050] The second type of external interface also includes all SGMII external interfaces (Serial Gigabit Media Independent Interface) of the first Switch chip and the second Switch chip and other RGMII external interfaces except for the electrical connection with the host computer;

[0051] Each SGMII external interface and each RGMII external interface are connected to a network device, and the network device is configured with an IP address of the same network segment to perform a network communication test on the SGMII external interface and the RGMII external interface of the first Switch chip and the second Switch chip.

[0052] Combination Figure 2 As shown, the first Switch1 chip includes one RGMII external interface (P8) and six SGMII (P1-P6) external interfaces, wherein the P8 external interface serves as an Ethernet TX network port, and the six SGMII (P1-P6) external interfaces serve as an Ethernet T1 network port. In actual applications, the Ethernet T1 network port can be connected to a laser radar and / or a millimeter-wave radar, etc., but in the test scenario of this embodiment, the Ethernet T1 network port is used to connect a network device.

[0053] Similarly, the second Switch1 chip includes two RGMII external interfaces (P7 and P8) and six SGMII (P1-P6) external interfaces, wherein P7 and P8 external interfaces serve as Ethernet TX network ports, and six SGMII (P1-P6) external interfaces serve as Ethernet T1 network ports.

[0054] Assuming that the P8 external interface in the first Switch1 chip is electrically connected to the host of the upper computer, then the six SGMII (P1~P6) external interfaces in the first Switch1 chip, the two RGMII external interfaces (P7 and P8) in the second Switch1 chip and its six SGMII (P1~P6) external interfaces are all connected to network devices, and the network communication status is detected through the upper computer ping test.

[0055] It can be seen that in the test scenario of this embodiment, all external interfaces in the two Switch1 chips are connected by lines to test the network communication conditions of each RGMII external interface and each SGMII external interface. After the test passes, the corresponding RGMII and SGMII external interfaces can be reasonably used according to the autonomous driving requirements and test results.

[0056] It should be noted that when network devices are connected through the SGMII external interface and the RGMII external interface, these Ethernet ports can be connected to the same or different network devices. For example, a network device can be assigned to each Ethernet port so that each Ethernet port is connected to a different network device. Of course, several types of network devices can be prepared in advance according to the types of network devices connected to the autonomous driving domain controller, and the above-mentioned Ethernet ports can be connected to these types of network devices.

[0057] The wiring harness connection of the second type of external interface can be completed through the above embodiment, and the wiring harness connection solution of the first type of external interface will be described next.

[0058] In some embodiments of the present application, the first type of external interface includes a multi-channel CAN external interface of the PCBA, and the multi-channel CAN external interface is connected in parallel according to a star topology to form a bus structure, so as to perform a bus communication test on the PCBA through the bus structure.

[0059] The multi-channel CAN external interface of this embodiment includes one CAN external interface of the master SOC chip, one CAN external interface of the slave SOC chip, and multiple CAN external interfaces of the MCU chip, so that bus communication test can be performed on the master and slave SOC chips and the MCU chip through the bus structure.

[0060] exist Figure 2 In the scenario shown, the seven CANFD ports in the MCU chip, the CAN1 port in the master SOC1 chip, and the CAN1 port in the slave SOC2 chip form a bus structure, that is, the CAN_H in the nine CAN ports are short-circuited together, and the CAN_L in the nine CAN ports are short-circuited together, and the corresponding test module in the host computer is run to detect whether the communication of each node on the CAN bus is successful.

[0061] In some embodiments of the present application, the first type of external interface also includes multiple groups of UART external interfaces, at least one group of RS422 external interfaces and multiple IO external interfaces of the MCU chip, wherein every two IO external interfaces belong to a port cluster of the same heat dissipation element;

[0062] Each group of UART external interfaces of the MCU chip is looped back within the group to perform a communication test on the UART external interfaces of the MCU chip;

[0063] The RS422 external interface of the MCU chip is looped back to perform a communication test on the RS422 external interface of the MCU chip;

[0064] The IO external interface for transmitting the control signal and the IO external interface for transmitting the feedback signal in every two IO external interfaces are loop-back connected to perform a communication test on the IO external interface of the MCU chip.

[0065] The UART (Universal Asynchronous Receiver / Transmitter) port is a bidirectional serial port, generally including a transmission line TX, a reception line RX and a ground line GND. In the embodiment of the present application, the TX and RX in each group of UART serial ports are short-circuited, and by running the corresponding test module in the host computer, TX sends data and RX receives data, and the communication status of each group of UART serial ports is detected according to the data reception result of RX.

[0066] A typical RS422 interface includes five signal lines. In the embodiment of the present application, the TX and RX in the RS422 interface are short-circuited, and by running the corresponding test module in the host computer, the TX in the RS422 interface sends data and the RX in the RS422 interface receives data. The communication status of the RS422 interface is detected according to the data reception result of the RX in the RS422 interface.

[0067] Continue with Figure 2 Taking the scenario shown as an example, at this time, the four groups of UART external interfaces, one group of RS422 external interfaces and four IO external interfaces of the MCU chip are first-class external interfaces. The UART communication test of the MCU chip can be performed through the intra-group loopback connection of each group of UART external interfaces, and the RS422 communication test of the MCU chip can be performed through the loopback connection of the RS422 external interface.

[0068] As for the IO communication test of the MCU chip, taking the water cooling method of the autonomous driving domain controller as an example, the cooling elements include fans and water pumps. The fans and water pumps are controlled by the MCU chip to adjust the internal temperature of the autonomous driving domain controller through the fans and water pumps to make it work within the appropriate temperature range. For example, the CPU of the autonomous driving domain controller does not reduce the frequency within the temperature range of -25℃-80℃.

[0069] Assume that the fan is connected to the first IO port cluster of the MCU chip, and the water pump is connected to the second IO port cluster of the MCU chip. The first IO port cluster includes a PWM control line for transmitting a PWM (Pulse Width Modulation) control signal and an FG feedback line for transmitting an FG feedback signal. In this way, the PWM control line and the FG feedback line in the first IO port cluster can be short-circuited. By running the corresponding test module in the host computer, the PWM control line outputs a PWM control signal, and the IO port communication status in the first IO port cluster is detected according to the reception status of the PWM control signal by the FG feedback line.

[0070] Similarly, the second IO port cluster also includes a PWM control line for transmitting a PWM control signal and an FG feedback line for transmitting an FG feedback signal. The PWM control line and the FG feedback line in the second IO port cluster are short-circuited, and the PWM control line outputs a PWM control signal by running the corresponding test module in the host computer. The communication status of the IO ports in the second IO port cluster is detected according to the reception status of the PWM control signal by the FG feedback line.

[0071] In this way, the IO communication test of the MCU chip in this embodiment can realize the fan control feedback test and the water cooling control feedback test.

[0072] In some embodiments of the present application, the first type of external interface also includes multiple groups of UART external interfaces of the main SOC1 chip, at least one group of CSI (Camera Serial Interface) external interfaces, at least one group of HDMI external interfaces and at least one group of USB (Universal Serial Bus) external interfaces;

[0073] Each group of UART external interfaces of the main SOC chip is looped back within the group to perform a communication test on the UART external interfaces of the main SOC chip;

[0074] The CSI external interface of the main SOC chip is connected to a CSI camera to perform a communication test on the CSI external interface of the main SOC chip;

[0075] The HDMI external interface of the main SOC chip is connected to a display to perform a communication test on the HDMI external interface of the main SOC chip;

[0076] The USB external interface of the main SOC chip is connected to a U disk mount to perform a communication test on the USB external interface of the main SOC chip.

[0077] Similarly, the first type of external interface also includes multiple groups of UART external interfaces from the SOC2 chip, at least one group of CSI external interfaces, at least one group of HDMI external interfaces, and at least one group of USB external interfaces;

[0078] Each group of UART external interfaces of the slave SOC chip is looped back within the group to perform a communication test on the UART external interfaces of the slave SOC chip;

[0079] The CSI external interface of the slave SOC chip is connected to a CSI camera to perform a communication test on the CSI external interface of the slave SOC chip;

[0080] The HDMI external interface of the slave SOC chip is connected to a display to perform a communication test on the HDMI external interface of the slave SOC chip;

[0081] The USB external interface of the slave SOC chip is connected to a U disk for mounting, so as to perform a communication test on the USB external interface of the slave SOC chip.

[0082] In practical applications, the camera can be connected via the GMSL coaxial cable. Figure 2 As shown, with the help of the GMSL coaxial cable and eight-way trigger corresponding to the SOC1 chip, and the GMSL coaxial cable and eight-way trigger corresponding to the SOC2 chip, sixteen-way GMSL camera triggering can be achieved. In the embodiment of the present application, when the CSI external interface is connected to the CSI camera via a coaxial cable, the communication status of the CSI external interface can be detected by running the corresponding test module in the host computer, for example, whether the image is successfully output through the CSI external interface.

[0083] In some application scenarios, when the computer program for executing the board test of PCBA in the host computer runs in the main SOC1 chip, the HDMI external interface of the main SOC1 chip can be connected to the display of the host computer, and the HDMI external interface of the slave SOC2 chip can be connected to other displays, so that the HDMI interface communication can be detected through the display interface of the display. In addition, this embodiment can perform an identification test based on the U disk mounting to obtain the communication status detection result of the USB external interface.

[0084] In some embodiments of the present application, the first type of external interface also includes a UPHY external interface of the master SOC chip and a UPHY external interface of the slave SOC chip;

[0085] The UPHY external interface of the master SOC chip is connected to the UPHY external interface of the slave SOC chip to perform an inter-chip communication test on the master SOC chip and the slave SOC chip.

[0086] UPHY (Universal PHY Interface, where PHY stands for Physical Layer) is a standardized interface protocol used for data transmission between different hardware platforms and physical layers. UPHY interface can be used in various communication fields, such as computer networks and mobile communication systems. By using UPHY interface, interconnection and interoperability between different devices can be achieved.

[0087] by Figure 2 Taking the figure as an example, it is assumed that the UPHY7 port in the master SOC1 chip is used for information reception, the UPHY9 port is used for information transmission, the UPHY7 port in the slave SOC2 chip is used for information reception, and the UPHY9 port is used for information transmission; in this case, the UPHY7 port in the master SOC1 chip can be connected to the UPHY9 port in the slave SOC2 chip through an Ethernet harness, and the UPHY9 port in the master SOC1 chip can be connected to the UPHY7 port in the slave SOC2 chip. After completing the above connection, the host computer can automatically test whether the communication between the master and slave SOC chips is successful.

[0088] Thus, the functional test of the MCU chip and the SOC chip can be realized through the line connection of the above embodiment of the present application, and the communication test of the SOC chip and the MCU chip can be realized. For example, the CAN bus test, the fan control feedback test, the water cooling control feedback test, the serial communication test (including the MCU chip, the UART external interface in the master-slave SOC chip, the 422 external interface in the MCU chip), the CSI test, the HDMI test, the USB test, the Ethernet test and other test items can be realized.

[0089] When each test item is executed, the test result is displayed by the host computer. For example, when the test fails, it is highlighted by a red abnormal display. Of course, the test items that failed the test can also be sent by SMS, email, etc.

[0090] It should be noted that this application Figure 2 The number of external interfaces included in each chip of the PCBA is merely exemplified. In practical applications, those skilled in the art may reasonably set external interfaces with relevant functions, and this embodiment does not impose any particular limitation on this.

[0091] It can be seen from the above embodiments of the present application that when using the autonomous driving domain controller test tooling to perform board testing on PCBA, the tester needs to connect fewer wires and does not need to perform redundant and complex wiring harness operations. The test can be started by controlling the mouse, screen touch, etc., and the operation is simple. The present application automatically determines the board test results of each test item through a computer program in the host computer. The test results are not subject to human intervention, which can not only quickly complete the board test, but also ensure the reliability of the test results.

[0092] It should be noted that, in the description of this application, the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance. In addition, in the description of this application, unless otherwise specified, the meaning of "plurality" is two or more.

[0093] In this application, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or communication with each other; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0094] In the present application, unless otherwise clearly specified and limited, a first feature being “above” or “below” a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being “above”, “above”, and “above” a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being “below”, “below”, and “below” a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0095] In the description of the present application, the terms "left", "right", "front", "rear", etc. indicate directions or positional relationships based on the directions or positional relationships shown in the accompanying drawings. They are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction. Therefore, they should not be understood as limitations on the present application.

[0096] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, segment or portion of code that includes one or more executable instructions for implementing the steps of a specific logical function or process, and the scope of the preferred embodiments of the present application includes alternative implementations in which functions may not be performed in the order shown or discussed, including performing functions in a substantially simultaneous manner or in the reverse order depending on the functions involved, which should be understood by technicians in the technical field to which the embodiments of the present application belong.

[0097] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0098] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application.

Claims

1. An autonomous driving domain controller test system, characterized in that: The autonomous driving domain controller test system includes a host computer and a wiring harness, wherein the host computer and the PCBA of the autonomous driving domain controller to be tested are electrically connected through the wiring harness; The external interface of the PCBA includes a first type of external interface and a second type of external interface, wherein the first type of external interface is used for connecting the circuits within the board according to the test items, and the second type of external interface is used for connecting the circuits outside the board; When the line connection between the first type external interface and the second external interface is completed, the board test result corresponding to each test item of the PCBA is displayed through the host computer.

2. The autonomous driving domain controller test system according to claim 1, characterized in that: The PCBA includes a main SOC chip, a slave SOC chip, an MCU chip, a first Switch chip, and a second Switch chip; The master SOC chip and the slave SOC chip are used to realize the computing power of the autonomous driving domain controller, the MCU chip is used to communicate with the autonomous driving vehicle chassis, and the first Switch chip and the second Switch chip are used to realize the network interaction of the autonomous driving domain controller.

3. The autonomous driving domain controller test system according to claim 2, characterized in that: The second type of external interface includes an RGMII external interface of the first Switch chip or an RGMII external interface of the second Switch chip, and the PCBA is electrically connected to the host computer through the RGMII external interface of the first Switch chip or the second Switch chip.

4. The autonomous driving domain controller test system according to claim 2, characterized in that: The second type of external interface also includes all SGMII external interfaces of the first Switch chip and the second Switch chip and other RGMII external interfaces except for the electrical connection with the host computer; Each SGMII external interface and each RGMII external interface are connected to a network device, and the network device is configured with an IP address of the same network segment.

5. The autonomous driving domain controller test system according to claim 2, characterized in that: The first type of external interface includes a multi-channel CAN external interface of the PCBA, and the multi-channel CAN external interface is connected in parallel according to a star topology to form a bus structure.

6. The autonomous driving domain controller test system according to claim 5, characterized in that: The multiple CAN external interfaces include one CAN external interface of the master SOC chip, one CAN external interface of the slave SOC chip and multiple CAN external interfaces of the MCU chip.

7. The autonomous driving domain controller test system according to claim 2, characterized in that: The first type of external interface also includes multiple groups of UART external interfaces, at least one group of RS422 external interfaces and multiple IO external interfaces of the MCU chip, wherein every two IO external interfaces belong to a port cluster of the same heat dissipation component; Each group of UART external interfaces of the MCU chip performs an internal loopback connection; The RS422 external interface of the MCU chip is looped back; The IO external interface for transmitting the control signal and the IO external interface for transmitting the feedback signal in every two IO external interfaces are loop-connected.

8. The autonomous driving domain controller test system according to claim 2, characterized in that: The first type of external interface also includes multiple groups of UART external interfaces of the main SOC chip, at least one group of CSI external interfaces, at least one group of HDMI external interfaces and at least one group of USB external interfaces; Each group of UART external interfaces of the main SOC chip performs an internal loopback connection; The CSI external interface of the main SOC chip is connected to a CSI camera; The HDMI external interface of the main SOC chip is connected to a display; The USB external interface of the main SOC chip is connected to a U disk for mounting.

9. The autonomous driving domain controller test system according to claim 2, characterized in that: The first type of external interface also includes multiple groups of UART external interfaces, at least one group of CSI external interfaces, at least one group of HDMI external interfaces, and at least one group of USB external interfaces of the slave SOC chip; Each group of UART external interfaces of the slave SOC chip is connected to the group by a loopback connection; The CSI external interface of the slave SOC chip is connected to a CSI camera; The HDMI external interface of the slave SOC chip is connected to a display; The USB external interface of the SOC chip is connected to a U disk for mounting.

10. The autonomous driving domain controller test system according to claim 2, characterized in that: The first type of external interface also includes a UPHY external interface of the master SOC chip and a UPHY external interface of the slave SOC chip; The UPHY external interface of the master SOC chip is connected to the UPHY external interface of the slave SOC chip.

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