Power-on circuit, chip and system

Abstract

The utility model relates to the technical field of integrated circuits, and discloses a power-on circuit, a chip and a system, a certain equivalent inductive reactance is generated by using an active inductance module, the equivalent inductive reactance can be improved along with the improvement of the communication rate, communication signals on a transmission bus are prevented from being absorbed by a capacitor of a power supply part, and direct current on a transmission line is obtained. The effects of taking power from the transmission bus and outputting stable voltage to the slave side circuit are achieved. The rectifier bridge and the active inductor unit are integrated together, so that the active inductor unit can be in non-polar connection with the first bus and the second bus, the rectifier bridge on the slave side is omitted, the circuit is more suitable for application scenarios with long communication line bus transmission distance, and power consumption is reduced.

Description

Technical Field

[0001] The utility model relates to the technical field of integrated circuits, in particular to a power-generating circuit, a chip and a system. Background Art

[0002] With the development of computer technology, communication technology, and network technology, various systems are becoming more and more intelligent, whether in the industrial field or in multiple fields such as smart home and security monitoring. The communication effect between devices is becoming more and more important. In order to realize the basic communication functions between various hardware devices, it can be divided into wireless communication and wired communication from the perspective of whether there is a transmission line. Among them, wireless communication is susceptible to external electromagnetic interference. In applications with weak security, complex environment, and high stability requirements, wired communication solutions are still used. Traditional communication solutions usually require power cords and communication cables. The power cord is responsible for powering each device in the communication network, and the communication line is the way to transmit communication signals between devices. However, this type of wired communication solution often faces obvious defects such as high cost, difficult construction, and long time consumption when there are many communication nodes, long communication distances, harsh environments, and complex wiring.

[0003] In the field of air conditioners that use DC power line carrier communication solutions, twisted pair cables are generally used as transmission lines for signal and power transmission. The signals on the two transmission lines are differential signals (i.e., signals are transmitted on both lines, and the amplitudes of the two signals are the same and the phases are opposite; the signal receiving end compares the difference between the two voltages to determine the logical state sent by the sending end). Since the communication signal and power are both transmitted on a pair of transmission lines, in order to obtain the communication signal and power from the transmission lines respectively, the former can simply isolate the DC power through the "AC-passing and DC-isolating" characteristics of the capacitor to obtain the communication signal on the transmission line, while the latter needs to isolate the communication signal on the transmission line through the differential mode inductance generated by the differential mode inductor to the high-frequency changing signal to obtain the DC power on the transmission line. However, the differential mode inductor is large in size and noisy, and as the communication distance becomes longer, the number of communication nodes increases, and the node structure becomes more complex, the differential mode inductor in the DC power line carrier communication solution often causes some troubles to the solution developers or users from the design stage to the actual application stage. Utility Model Content

[0004] The utility model aims to overcome the problem of poor application effect of differential mode inductance in the existing DC power line carrier communication scheme, and provides a power circuit, chip and system.

[0005] In order to achieve the above object, the utility model provides a power circuit, comprising: an active inductor unit and a rectifier bridge; the active inductor unit is connected to an external first bus and a second bus through the rectifier bridge;

[0006] The active inductor unit is used to isolate the AC differential signal input from the first bus and the second bus, and output a DC power signal;

[0007] The rectifier bridge is used to achieve non-polarity connection between the active inductor unit and the first bus and the second bus.

[0008] As an implementable embodiment, the active inductor module further includes an overcurrent protection unit;

[0009] The overcurrent protection unit is used to control the active inductor unit to implement overcurrent protection.

[0010] As an implementable embodiment, the active inductor module further includes an over-temperature protection unit;

[0011] The over-temperature protection unit is used to control the active inductor unit to achieve over-temperature protection.

[0012] As an implementable embodiment, the active inductor module further includes a power supply unit;

[0013] The power supply unit is used to output a constant voltage after stepping down the DC power supply signal.

[0014] As an implementable embodiment, the active inductor module further includes: a dynamic matching module; the dynamic matching module is used in conjunction with an external encoding module, the encoding module is used to receive an input signal through an encoding input terminal, encode the input signal and output a differential signal through two encoding output terminals, and the two encoding output terminals of the encoding module are respectively connected to the first bus and the second bus;

[0015] The dynamic matching module is used to connect a waveform optimization unit between the two encoding output terminals of the encoding module when the input signal switches from a first level to a second level, so that the voltage difference between the two encoding output terminals is quickly switched from a preset voltage difference to 0V, thereby preventing the voltage waveform output by the two encoding output terminals from being not steep enough and causing subsequent miscoding.

[0016] As an implementable embodiment, the dynamic matching module includes: a first delay unit, a switch unit and a waveform optimization unit;

[0017] The first delay unit is used for, when the input signal switches from the first level to the second level, starting delay based on the second level and turning on the power supply to the switch unit so as to turn on the switch unit, and ending the delay and stopping the power supply to the switch unit when the first predetermined time interval is reached so as to turn off the switch unit;

[0018] The switch unit is used to connect the waveform optimization unit between the two encoding output terminals after being turned on, and disconnect the connection between the waveform optimization unit and the two encoding output terminals after being turned off;

[0019] The waveform optimization unit is used to quickly switch the voltage difference between the two encoding output ends from a preset voltage difference to 0V.

[0020] As an implementable embodiment, the switch unit is a MOS tube.

[0021] As an implementable embodiment, the dynamic matching module further includes a first charging unit and a first discharging unit;

[0022] The first charging unit is used to charge the parasitic capacitor Cgs of the MOS tube to form a charging loop when the input signal is at the second level and the power supply to the MOS tube is turned on, so as to quickly turn on the MOS tube;

[0023] The first discharge unit is used to form a discharge loop for discharging the parasitic capacitance Cgs of the MOS tube when the input signal is at the second level and the delay ends and the power supply to the MOS tube stops when the first predetermined time interval is reached, so as to quickly shut down the MOS tube.

[0024] As an implementable embodiment, the dynamic matching module further includes a second discharge unit;

[0025] The second discharge unit is used to start delaying based on the second level when the input signal switches from the first level to the second level, and discharge the MOS tube when a second predetermined time interval is reached, so as to quickly turn off the MOS tube, wherein the second predetermined time interval is greater than the first predetermined time interval.

[0026] As an implementable embodiment, the second discharge unit includes a second delay unit, a first discharge sub-unit and a second discharge sub-unit;

[0027] The second delay unit is used to turn on the first discharge sub-unit when the input signal switches from the first level to the second level and delays to a second predetermined time interval; wherein the second predetermined time interval is greater than the first predetermined time interval;

[0028] The first discharge sub-unit is used to discharge the switch unit after being turned on, so as to quickly turn off the switch unit;

[0029] The second discharge sub-unit is used for discharging the second delay unit based on the first level and disconnecting the first discharge sub-unit when the input signal switches from the second level to the first level according to a normal switching cycle.

[0030] As an implementation method, the encoding module is used to receive an input signal through a signal input terminal, encode the input signal and output a differential signal through two encoding output terminals, and the two encoding output terminals of the encoding module are respectively connected to a first bus and a second bus.

[0031] Correspondingly, the utility model also provides a chip, including the power-generating circuit as described above.

[0032] Correspondingly, the utility model also provides a power supply system, including the aforementioned chip.

[0033] Beneficial effects of the utility model:

[0034] The active inductor module of the utility model generates a certain equivalent inductive reactance by using an active inductor unit, and can be increased with the increase of the communication rate, playing the same effect as using a differential mode inductor, preventing the communication signal on the transmission line from being absorbed by the capacitor of the power supply part and obtaining the direct current on the transmission line, and realizing the effect of taking power from the transmission bus and outputting a stable voltage to the slave side circuit. By integrating the rectifier bridge and the active inductor unit together, the active inductor unit can realize a non-polarity connection between the first bus and the second bus, eliminating the rectifier bridge on the slave side, and is more suitable for application scenarios with long communication line bus transmission distances, reducing power consumption. Moreover, due to the long transmission distance of the communication line bus, the rectifier bridge circuit of the utility model uses a MOS tube as a rectifier bridge. The MOS tube is a unidirectional conduction device with a small conduction impedance, and the forward voltage drop can be much lower than that of an ordinary diode, so the power consumption of the power supply is reduced, and the use in long-distance communication improves efficiency.

[0035] The utility model integrates the rectifier bridge, active inductor unit, power supply unit, overcurrent protection unit, and overtemperature protection unit into one chip, thus enriching the functions. Not only does the active inductor unit replace the differential mode inductor of each slave, but also the rectifier bridge and power supply chip on each slave side are omitted, and a fixed voltage value can be directly obtained from the output pin of the chip. If other voltage values ​​are to be obtained, the power supply can be further converted at the DC power signal output terminal VDD of the chip. The utility model can also integrate the dynamic impedance matching module and the encoding module into one chip with the active inductor module to further reduce power consumption.

[0036] The utility model can better guarantee the signal quality in complex situations through the dynamic impedance matching module. The utility model is simple to apply, greatly saves costs, has good communication effects, high integration, good stability, helps to improve the overall performance of the solution, has stronger market competitiveness and higher profit margins.

[0037] The dynamic impedance matching module of the utility model can pull the voltage difference between the two encoding output ends to 0V by connecting the waveform optimization unit between the two encoding output ends of the encoding module, thereby improving the signal quality. By connecting the waveform optimization unit between the two encoding output ends of the encoding module by turning on the MOS tube, the voltage difference between the two encoding output ends can be pulled to 0V more quickly, further improving the communication quality and achieving better results. The MOS tube can be quickly turned on and off by the first charging unit and the first discharging unit; abnormal discharge can be prevented by the second discharging unit. The anti-backflow unit can prevent the signal on the bus from backflowing into the dynamic matching module when the two encoding output ends of the encoding module do not output differential signals, thereby reducing power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 A schematic diagram of an active inductor module provided in some embodiments of the utility model;

[0039] Figure 2 A schematic diagram of a chip that can integrate an active inductor module provided in some embodiments of the utility model;

[0040] Figure 3 A schematic diagram of a power-generating circuit provided in some embodiments of the utility model;

[0041] Figure 4 A schematic diagram of a dynamic matching module provided in some embodiments of the utility model;

[0042] Figure 5 A schematic diagram of changes in the signal waveform diagrams provided in some embodiments of the utility model under an ideal state;

[0043] Figure 6 A schematic diagram of the change of the signal waveform diagram provided in some embodiments of the utility model when OUT (A) - OUT (B) produces an oscillation state in actual application;

[0044] Figure 7 A schematic diagram of the change of OUT (A)-OUT (B) of the signal waveform diagram provided in some embodiments of the present invention after the waveform optimization unit is introduced;

[0045] Figure 8 A schematic diagram of a chip with an integrated dynamic matching module provided in some embodiments of the present invention. DETAILED DESCRIPTION

[0046] The following will be combined with the drawings in the embodiments of the utility model to clearly and completely describe the technical solutions in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments in the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.

[0047] The technical terms or scientific terms used in this application should be understood by those skilled in the art in general. The terms "first", "second", "third", "fourth" and similar words used in the specification and claims of this application do not indicate any order, quantity or importance, but are only used to distinguish different components. Therefore, the features defined as "first", "second", "third" and "fourth" may explicitly or implicitly include one or more of the features. "One end" and "the other end" and "the proximal end" and "the distal end" generally refer to two corresponding parts, which include not only the endpoints, and the terms "installation", "connection" and "connection" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral body; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, it can be the internal connection of two components or the interaction relationship between two components. Unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to the specific circumstances.

[0048] See also Figure 1 Some embodiments of the utility model provide a power circuit, including an active inductor module 10, wherein the active inductor module 10 includes: a rectifier bridge 200 and an active inductor unit 100; the active inductor unit 100 is connected to an external first bus and a second bus through the rectifier bridge 200; the first input end of the rectifier bridge 200 and the second input end of the rectifier bridge 200 can be connected to a first signal input end DA and a second signal input end DB respectively, the first signal input end DA and the second signal input end DB are respectively used to connect the first bus and the second bus, the first output end of the rectifier bridge 200 and the second output end of the rectifier bridge 200 are respectively connected to the first input end of the active inductor unit 100 and the second input end of the active inductor unit 100, the first output end of the active inductor unit 100 is connected to a DC power signal output end VDD, and the DC power signal output end VDD is used to output a DC power signal; the second output end of the active inductor unit 100 is connected to a ground end GND. The active inductor unit 100 is used to isolate the AC differential signal input from the first bus and the second bus, and output a DC power signal; the rectifier bridge 200 is used to achieve a non-polarity connection between the active inductor unit 100 and the first bus and the second bus.

[0049] In some embodiments, see Figure 2 When the rectifier bridge 200 and the active inductor unit 100 are integrated into a chip and then packaged onto a PCB board, the first signal input terminal DA, the second signal input terminal DB, the DC power signal output terminal VDD and the ground terminal GND can be four pins of the chip. In some embodiments, when the active inductor module 10 including the rectifier bridge 200 and the active inductor unit 100 is integrated into the chip, and then the chip is packaged on the PCB board, the DC power signal on the transmission bus can be obtained through the rectifier bridge 200 and the active inductor unit 100 inside the chip, and the DC power is output from the DC power signal output terminal VDD. The output voltage value at the DC power signal output terminal VDD = the DC power supply voltage on the transmission bus - the voltage drop lost on the transmission bus - the voltage drop inside the chip. Generally, a variety of DC voltages (such as 5.0V, 3.3V, 1.5V, etc.) may be required on the PCB board to make the chip or circuit work normally. Therefore, power can be taken from the transmission bus through the DC power signal output terminal VDD. Other suitable power modules 20 are externally connected to the DC power signal output terminal VDD to perform power conversion so as to output other required DC voltage values. The power module 20 can be a DC-DC power chip.

[0050] In some embodiments, the active inductor unit 100 includes a first active inductor and a second active inductor; one end of the first active inductor is connected to the first signal input terminal DA through the rectifier bridge 200, and the other end of the first active inductor is connected to the DC power supply signal output terminal VDD; one end of the second active inductor is connected to the second signal input terminal DB through the rectifier bridge 200, and the other end of the second active inductor is connected to the ground terminal GND.

[0051] The power circuit provided by the utility model, the active inductor module 10 generates a certain equivalent inductive reactance by using the active inductor unit 100, and can be increased with the increase of the communication rate, and has the same effect as using the differential mode inductor, preventing the communication signal on the transmission line from being absorbed by the capacitor of the power supply part and obtaining the direct current on the transmission line, and realizing the effect of taking power from the transmission bus and outputting a stable voltage to the slave side circuit. By integrating the rectifier bridge 200 and the active inductor unit 100 together, the active inductor unit 100 can achieve a non-polarity connection between the first bus and the second bus, which is more suitable for long-distance communication and consumes less power. Moreover, since the communication line bus has a long transmission distance, the rectifier bridge circuit of the utility model uses a MOS tube as the rectifier bridge 200, which has a small on-resistance and a forward voltage drop that can be much lower than that of an ordinary diode, so the power consumption of the power supply is reduced, and it is used in long-distance communication to reduce power consumption.

[0052] In some embodiments, the active inductor module 10 also includes an overcurrent protection unit 400; the first control end of the overcurrent protection unit 400 is connected to the active inductor unit 100, and the overcurrent protection unit 200 is used to control the active inductor unit 100 to implement overcurrent protection, so that when the output end is short-circuited, the voltage on the transmission bus can be lowered to avoid affecting the communication of other devices.

[0053] In some embodiments, the active inductor module 10 further includes an over-temperature protection unit 500; a first control end of the over-temperature protection unit 500 is connected to the active inductor unit 100, and the over-temperature protection unit 500 is used to control the active inductor unit 100 to implement over-temperature protection, so that when the temperature is abnormal, the active inductor unit 100 is turned off.

[0054] The active inductor module 10 of this embodiment integrates protection functions such as over-current protection and over-temperature protection, so that when integrated into a chip, the chip is shut down when the chip temperature is abnormal or the output is short-circuited without affecting the communication of other nodes on the transmission line.

[0055] In some embodiments, the active inductor module 10 further includes a power supply unit 300; the first input end of the power supply unit 300 is connected to the DC power signal output end VDD, and the first output end of the power supply unit 300 is connected to the constant voltage output end VO; the constant voltage output end VO is used to output a constant voltage. The second input end of the power supply unit 300 is connected to the enable end EN, and the power on / off function of the power supply unit 300 can be realized through the enable end EN. The power supply unit 300 is used to step down the DC power signal output by the active inductor unit 100 and output a constant voltage, which can ensure that the differential signal of the transmission bus is not absorbed by the power supply part capacitor and obtain the DC power on the transmission bus. For example, the power supply unit 300 can directly control the output voltage of 5V, which is simple to apply and easy to apply to more scenarios of slave devices. In some embodiments, the power supply unit 300 can be implemented by LDO or charge pump principle. By using LDO, the circuit is simple, there is no electromagnetic interference, and the cost is low; by using a charge pump, the conversion efficiency is better and the performance is better. This slave device takes the wire controller product in the air-conditioning field as an example. A single wire controller usually only needs to draw a current of less than 200mA, and the power is relatively small, so the power supply unit can be designed using either LDO or charge pump.

[0056] The power-generating circuit provided in this embodiment can be used in more scenarios by directly obtaining a fixed voltage value of a low voltage. If other voltage values ​​are to be obtained, the power conversion can be further performed on an external power supply module at the DC power signal output terminal VDD of the chip.

[0057] In some embodiments, see Figure 3 , the power circuit also includes: an encoding module 40, the encoding module 40 is used to receive the input signal TXD through the signal input terminal DATA IN, encode the input signal and output the differential signal through two encoding output terminals, namely OUT (A) and OUT (B), and the two encoding output terminals of the encoding module 40 are respectively connected to the first bus A and the second bus B. The active inductor module 10 draws power from the external first bus A and the second bus B. In some embodiments, the encoding module 40 can be integrated into one chip with the active inductor module 10, and in other embodiments, the encoding module 40 can also be a separate communication chip. Specifically, the encoding input terminal DATA IN of the encoding module 40 receives the input signal TXD sent from the MCU and encodes it into a differential signal, which is sent to the first bus A and the second bus B from the two encoding output terminals, namely OUT (A) and OUT (B), respectively, and the first signal input terminal DA and the second signal input terminal DB are respectively connected to the first bus A and the second bus B. Finally, the encoding module 40 decodes 0 or 1 by judging the difference range of the differential signal on the transmission bus, so as to achieve the effect of signal restoration and successful communication between devices. Furthermore, the active inductor unit 100 obtains the differential signals outputted from the two encoding output terminals, OUT (A) and OUT (B), isolates the AC differential signals, and obtains the DC power on the bus.

[0058] See also Figure 5 The signal waveform diagram of each input and output terminal of the coding module 40 under ideal conditions when normally sending and receiving signals, such as: when RESET is set to low, the coding module 40 can normally send and receive signals, DATA IN (TXD) is a schematic diagram of the level change corresponding to the input signal TXD, which is directly given to the coding module 40 by the MCU, and after being encoded as a differential signal inside the coding module 40, the differential signal is output from the two encoding output terminals OUT (A) and OUT (B) and sent to the first bus and the second bus. Finally, the coding module 40 obtains the differential signal through the two acquisition terminals IN1 and IN2, judges the difference range of the differential signal on the transmission bus, decodes 0 or 1 (that is, judges the waveform range shown as OUTA-OUTB in the figure) to obtain the decoded signal RXD, and outputs the decoded signal RXD through the output terminal DATA OUT, so as to achieve the effect of signal restoration and successful communication between devices. However, in actual applications, due to many factors such as long communication distance, many nodes, and complex node structure, the parasitic parameters on the transmission bus have a greater adverse effect on communication, such as Figure 6 This is the "communication chip signal timing diagram under complex working conditions". The waveform of the OUT (A)-OUT (B) signal on the transmission line is not "steep" enough and even oscillates when it changes from "low level to middle level" or "high level to middle level" ( Figure 6OUT(A)-OUT(B) in the decoded signal DATA OUT), which will cause the "1" pulse width of the decoded signal DATA OUT to be insufficient or cause miscoding ( Figure 6 The DATA OUT in the transmission line causes abnormal communication; while the two stages of the OUT (A) and OUT (B) signals on the transmission line from "intermediate level to high level" or "intermediate level to low level" are realized by the internal transistor of the encoding module 40 quickly pulling up to the preset voltage or quickly pulling down to 0V, which is basically not affected by the parasitic parameters on the transmission line.

[0059] Therefore, in order to further improve the communication quality, solve the problem that the waveform of the OUT (A) - OUT (B) signal on the transmission line is not "steep" enough or even oscillates when it changes from "low level to middle level" or "high level to middle level", which will cause the "1" pulse width of the decoding signal DATA OUT to be insufficient or misinterpretation, resulting in abnormal communication; and in order to be more conducive to the active inductor unit 100, the AC differential signal input from the first bus and the second bus can be isolated. Figure 3 The power circuit further includes: a dynamic matching module 30; the dynamic matching module 30 is used in conjunction with an external encoding module 40, and the dynamic matching module 30 is used to connect a waveform optimization unit between two encoding output terminals of the encoding module 40, namely, OUT (A) and OUT (B), when the input signal TXD switches from the first level to the second level, see Figure 7 , within the first predetermined time interval t1 after the input signal TXD switches from the first level to the second level, a high level voltage brought by the waveform optimization unit can be introduced between the two encoding output terminals, OUT (A) and OUT (B), so that the voltage difference between the two encoding output terminals, OUT (A) and OUT (B), is quickly switched from a preset voltage, such as 5V, to 0V, thereby preventing miscoding caused by insufficiently steep waveforms. Figure 7 It can be seen that by introducing the waveform optimization unit, the encoding module 40 outputs the decoding signal RXD through the output terminal DATA OUT to achieve the effect of signal restoration and improve the communication quality.

[0060] In some embodiments, the first level is one of a high level and a low level, and the second level is the other of the high level and the low level. In the following text, the first level is understood as a low level and the second level is a high level. In some embodiments, the preset voltage difference between the two encoding output terminals, OUT (A) and OUT (B), is a high level voltage value of OUT (A) - OUT (B), and the high level voltage value can be set according to actual needs, for example, it can be set to 5V.

[0061] In some embodiments, the "dynamic matching module" can achieve such an effect that when the device sends a signal, the dynamic matching module is connected between the buses so that when the input signal TXD switches from a low level to a high level, OUT (A) - OUT (B) can be quickly switched from a high / low level to an intermediate level to improve signal quality and communication effects. In addition, since in some DC power line carrier communication schemes, only one device is sending a signal at the same time, there will be no situation where multiple dynamic matching modules are simultaneously incorporated into the bus to reduce the impedance between the buses.

[0062] In some embodiments, see Figure 4 , the dynamic matching module 30 includes: a first delay unit, a switch unit and a waveform optimization unit;

[0063] The signal input terminal V1 of the dynamic matching module 30 is connected to the encoding input terminal DATA IN, and is used to receive the input signal TXD. The first delay unit is used to start delaying based on the second level and turn on the power supply to the switch unit when the input signal switches from the first level to the second level, so as to turn on the switch unit. When the first predetermined time interval is reached, the delay ends and the power supply to the switch unit is stopped to turn off the switch unit. The switch unit is used to connect the waveform optimization unit between the two encoding output terminals after being turned on, and disconnect the connection between the waveform optimization unit and the two encoding output terminals after being turned off. The waveform optimization unit is used to quickly switch the voltage difference between the two encoding output terminals from the preset voltage difference to 0V. Specifically, when the input signal TXD switches from the first level to the second level, the first delay unit starts the delay and opens the switch unit, and the waveform optimization unit is connected to the two encoding output terminals, namely OUT (A) and OUT (B) through the switch unit; then the delay ends when the first delay unit delays the first predetermined time interval t1, so that OUT (A)-OUT (B) is quickly switched from a high / low level to an intermediate level, and then the switch unit is turned off, so as to disconnect the connection between the waveform optimization unit and the two encoding output terminals.

[0064] In some embodiments, the first delay unit includes a delay capacitor. Specifically, the first delay unit includes a first capacitor C1 and a first resistor R1, and the delay time of the first delay unit is determined according to the capacity of the first capacitor C1 and the resistance value of the first resistor R1, that is, the first predetermined time interval t1 can be set by setting the capacity of the first capacitor C1 and the resistance value of the first resistor R1. When charging the first capacitor C1 based on the second level, the right end of the first capacitor C1 is a high level, thereby turning on the second transistor Q2 and the first transistor Q1 in turn to achieve the expected goal. When the first predetermined time interval t1 passes during the second level, the voltage on the right side of the first capacitor C1 is finally reduced to a low level, and the second transistor Q2 and the first transistor Q1 are turned off to achieve the expected effect. Figure 7 The waveform t1 in the figure shows the time point when the dynamic impedance matching circuit takes effect and the duration of its maintenance. When the TXD signal changes from 0 to 1, the dynamic impedance matching circuit takes effect and maintains the t1 time. Figure 4 Actually, it is equivalent to connecting the waveform optimization unit between the buses during this time period.

[0065] The purpose of setting up the dynamic matching module in the utility model is to quickly pull the two encoding output terminals to the same voltage. Theoretically, it is best if there is no voltage drop. However, the voltage drop of the triode is much larger than that of the MOS, which will cause the bus signal OUTA-OUTB to still have a voltage difference when it should be 0V, thereby affecting the judgment of the two signal acquisition terminals IN1 and IN2 of the communication chip and causing miscoding. Therefore, in the utility model, the switch unit is a MOS tube, the conduction voltage drop of the MOS tube is much smaller than that of the triode, and the current capacity of the MOS is also greater than that of the triode, which can more quickly pull the voltage difference of the two encoding output terminals OUT (A) and OUT (B) to 0V, further improving the communication quality and achieving better results.

[0066] In some embodiments, the waveform optimization unit is composed of matching resistors, and matching resistors can be connected to the two encoding output terminals, so that the voltage difference between the two encoding output terminals OUT (A) and OUT (B) can be pulled to 0V more quickly to improve the signal quality. When the OUT (A) and OUT (B) signals are quickly pulled to the intermediate level through the matching resistors, there is no voltage difference in the transmission line, and no current will flow through the matching resistors to generate additional power consumption. In the scheme based on the HBS communication protocol, only one device sends a signal at the same time, and there will be no situation where multiple matching resistors are incorporated into the bus to reduce the impedance between the buses. In some embodiments, when a MOS tube is selected to form a switch unit, the switch unit includes a first switch unit and a second switch unit, the first switch unit is a first MOS tube Q4, and the second switch unit is a second MOS tube Q5; correspondingly, the waveform optimization unit includes a first waveform optimization unit and a second waveform optimization unit, corresponding to the tenth resistor R10 and the eleventh resistor R11, respectively.

[0067] In some embodiments, the MOS transistor includes a first MOS transistor Q4 and a second MOS transistor Q5, the waveform optimization unit includes a first waveform optimization unit and a second waveform optimization unit, the source S of the first MOS transistor Q4 is connected to the first coding output terminal through the first waveform optimization unit, the drain D of the second MOS transistor Q5 is connected to the first coding output terminal, the gate G of the first MOS transistor Q4 and the gate G of the second MOS transistor Q5 are connected to the first delay unit, the drain D of the first MOS transistor Q4 is connected to the second coding output terminal, and the source S of the second MOS transistor Q5 is connected to the second coding output terminal through the second waveform optimization unit. In some embodiments, the first coding output terminal may be the coding output terminal OUT (A) or the coding output terminal OUT (B), and the second coding output terminal may be the corresponding coding output terminal OUT (B) or the coding output terminal OUT (A). Exemplarily, the first end of the first delay unit is connected to the signal input end V1, the second end of the first delay unit is connected to the gate G of the first MOS tube Q4 and the source S of the first MOS tube Q4, the source S of the first MOS tube Q4 is connected to the first end of the first waveform optimization element R10, the second end of the first waveform optimization unit is connected to the first waveform optimization signal output end V3, the first waveform optimization signal output end V3 is connected to the encoding output end OUT (A) of the encoding module, the drain D of the first MOS tube Q4 is connected to the second waveform optimization signal output end V2, the second waveform optimization signal output end V2 is connected to the encoding output end OUT (B), the second end of the first delay unit is also connected to the gate G of the second MOS tube Q5 and the source S of the second MOS tube Q5, the drain D of the second MOS tube Q5 is connected to the first waveform optimization signal output end V3, the first waveform optimization signal output end V3 is connected to the encoding output end OUT (A) of the encoding module, the source S of the second MOS tube Q5 is connected to the first end of the second waveform optimization unit, the second end of the second waveform optimization unit is connected to the second waveform optimization signal output end V2, and the second waveform optimization signal output end V2 is connected to the encoding output end OUT (B).

[0068] In some embodiments, the dynamic matching module 30 further includes an anti-backflow unit located between the switch unit and the waveform optimization unit, which is used to prevent the high-level signal on the bus from backflowing into the dynamic matching module to cause power consumption when the two encoding output terminals stop outputting signals. Figure 4 If there is no backflow prevention unit, when the input signal of the second waveform optimization signal output terminal V2 is high level, the high level signal will pass through the second waveform optimization unit and the second MOS tube Q5 to reach the first waveform optimization signal output terminal V3, thereby generating power consumption. In this embodiment, the circuit is disconnected by the backflow prevention unit, thereby reducing power consumption.

[0069] In some embodiments, the anti-backflow unit is an anti-backflow diode, and when the switch unit is a MOS tube, the positive electrode of the anti-backflow diode is connected to the source electrode of the MOS tube, and the negative electrode of the anti-backflow diode is connected to one end of the waveform optimization unit. Specifically, the anti-backflow unit includes a first anti-backflow unit corresponding to the first MOS tube Q4 and a second anti-backflow unit corresponding to the second MOS tube Q5, the first anti-backflow unit is a fourth diode D4, and the second anti-backflow unit is a fifth diode D5. Specifically, the drain electrode D of the first MOS tube Q4 is connected to the second waveform optimization signal output terminal V2, and the source electrode S of the first MOS tube Q4 is connected in sequence through the fourth diode D4, the first waveform optimization unit and the first waveform optimization signal output terminal V3. Specifically, the source electrode S of the first MOS tube Q4 is connected to the positive electrode of the fourth diode D4, the negative electrode of the fourth diode D4 is connected to one end of the first waveform optimization unit, and the other end of the first waveform optimization unit is connected to the first waveform optimization signal output terminal V3. The drain D of the second MOS tube is connected to the first waveform optimization signal output terminal V3, and the source S of the second MOS tube is connected in sequence through the fifth diode D5, the second waveform optimization unit and the second waveform optimization signal output terminal V2. Specifically, the source S of the second MOS tube Q5 is connected to the anode of the fifth diode D5, the cathode of the fifth diode D5 is connected to one end of the second waveform optimization unit, and the other end of the second waveform optimization unit is connected to the second waveform optimization signal output terminal V2.

[0070] In some embodiments, due to the presence of parasitic capacitance between the gate and source of the MOS tube, the dynamic matching module further includes a first charging unit and a first discharging unit; the first charging unit is used to form a charging loop for charging the parasitic capacitance Cgs of the MOS tube when the input signal is at the second level and the power supply to the MOS tube is turned on, so as to quickly turn on the MOS tube; the first discharging unit is used to form a discharging loop for discharging the parasitic capacitance Cgs of the MOS tube when the input signal is at the second level and the delay ends and the power supply to the MOS tube is stopped when the first predetermined time interval t1 is reached, so as to quickly turn off the MOS tube.

[0071] In some embodiments, the first charging unit includes a first charging subunit and a second charging subunit; the first charging subunit is used for, when the input signal is at the second level and the power supply to the first MOS tube Q4 is turned on, to form a first charging loop for charging the parasitic capacitor Cgs of the first MOS tube Q4, so as to quickly turn on the first MOS tube Q4; the second charging subunit is used for, when the input signal is at the second level and the power supply to the second MOS tube Q5 is turned on, to form a second charging loop for charging the parasitic capacitor Cgs of the second MOS tube Q5, so as to quickly turn on the second MOS tube Q5.

[0072] Specifically, the first charging subunit includes a second diode D2, the anode of the second diode D2 is connected to the source of the first MOS transistor Q4 and the gate of the first MOS transistor Q4, and the cathode of the second diode D2 is connected to the ground terminal; the anode of the second diode D2 is connected to the gate of the first MOS transistor Q4, specifically, the anode of the second diode D2 is connected to the gate of the first MOS transistor Q4 through the eighth resistor R8. The second charging subunit includes a third diode D3, the anode of the third diode D3 is connected to the source of the second MOS transistor Q5 and the gate of the second MOS transistor Q5, and the cathode of the third diode D3 is connected to the ground terminal. The anode of the third diode D3 is connected to the gate of the second MOS transistor Q5, specifically, the anode of the third diode D3 is connected to the gate of the second MOS transistor Q5 through the ninth resistor R9.

[0073] In some embodiments, the first discharge unit includes a third discharge sub-unit and a fourth discharge sub-unit; the third discharge sub-unit is used to form a first discharge loop for discharging the parasitic capacitance Cgs of the first MOS tube Q4 when the input signal is at the second level and the delay ends when the first predetermined time interval t1 is reached and the power supply to the first MOS tube Q4 is stopped, so as to realize rapid shutdown of the first MOS tube Q4; the fourth discharge sub-unit is used to form a second discharge loop for discharging the parasitic capacitance Cgs of the second MOS tube Q5 when the input signal is at the second level and the delay ends when the first predetermined time interval t1 is reached and the power supply to the second MOS tube Q5 is stopped, so as to realize rapid shutdown of the second MOS tube Q5.

[0074] Specifically, the third discharge sub-unit includes an eighth resistor R8, one end of the eighth resistor R8 is connected to the source of the first MOS tube Q4, and the other end of the eighth resistor R8 is connected to the gate of the first MOS tube Q4. The fourth discharge sub-unit includes a ninth resistor R9, one end of the ninth resistor R9 is connected to the source of the second MOS tube Q5, and the other end of the ninth resistor R9 is connected to the gate of the second MOS tube Q5.

[0075] In some embodiments, generally speaking, since the conduction time of the first MOS tube Q4 and the second MOS tube Q5 is much less than 104us (for example, in the communication scheme of the HBS protocol with a DC 9600bps communication rate, the minimum high-level pulse width of the signal is 104uS), there is no problem that the first MOS tube Q4 and the second MOS tube Q5 are turned off slowly, because Q4 and Q5 start to turn off after being turned on for tens of uS, that is, they will be turned off during the period when the input signal TXD is at the second level. Under normal circumstances, they will not mislead when the indoor unit does not send a signal or receives a signal. However, in order to prevent abnormal situations, the present embodiment further provides a second discharge unit, which is used to start delaying based on the second level when the input signal switches from the first level to the second level, and discharge the parasitic capacitance Cgs of the MOS tube when the second predetermined time interval t2 is reached, so as to quickly turn off the MOS tube; wherein the second predetermined time interval t2 is greater than the first predetermined time interval t1.

[0076] In some embodiments, the second discharge unit includes a second delay unit, a first discharge sub-unit, and a second discharge sub-unit; the second delay unit is used to start delaying based on the second level when the input signal switches from the first level to the second level, and the delay ends and the first discharge sub-unit is turned on when the second predetermined time interval is reached; wherein the second predetermined time interval t2 is greater than the first predetermined time interval t1; the first discharge sub-unit is used to discharge the parasitic capacitance Cgs of the MOS tube after being turned on, so as to quickly turn off the MOS tube; the second discharge sub-unit is used to discharge the second delay unit when the input signal switches from the second level to the first level according to the normal switching cycle, so as to turn off the first discharge sub-unit. In one embodiment, the second delay unit can be discharged faster by the second discharge sub-unit. In some embodiments, the first discharge sub-unit includes a third triode Q3 and a stabilization unit, the collector of the third triode is connected to the base of the third triode Q3, the collector of the third triode Q3 is connected to the gate of the MOS tube, the collector of the third triode Q3 is also connected to the input signal terminal through the stabilization unit, and the input signal terminal is connected to the base of the third triode Q3. The third triode Q3 is used to discharge the MOS tube; the stabilization unit is used to isolate the third triode Q3 and the input signal terminal V1 during the process of the third triode Q3 discharging the MOS tube, so as to prevent the discharge sub-unit from interfering with the input signal. Specifically, when the stabilization unit does not exist, the collector of the third transistor Q3 is connected to the gate of the MOS tube, the emitter of the third transistor Q3 is connected to the ground terminal, the base of the third transistor Q3 is connected to the collector of the third transistor, the base of the third transistor Q3 is also connected to the input signal terminal and one end of the second delay unit, and the other end of the second delay unit is connected to the ground terminal. The input signal TXD of the input signal terminal will be pulled low when the third transistor Q3 is turned on. When the stabilization unit is set, the connection between the collector of the third transistor and the input signal terminal V1 is disconnected by the stabilization unit, thereby avoiding interference with the input signal TXD of the input signal terminal.

[0077] Specifically: when the input signal switches from the first level to the second level, the second delay unit starts the delay, and the delay ends when the second predetermined time interval t2 is delayed and the first discharge sub-unit is turned on, the first discharge sub-unit discharges the switch unit, so that the switch unit is quickly turned off, and the stabilization unit is used to prevent the discharge sub-unit from pulling down the input signal TXD in the process of discharging the switch unit, thereby affecting the normal switching of the input signal TXD; when the input signal switches from the second level to the first level, the second discharge sub-unit discharges the second delay unit and disconnects the first discharge sub-unit; wherein, in order to ensure that no logical abnormality occurs, the first predetermined time interval t1 is less than the second predetermined time interval t2, and after the high level of the first predetermined time interval t1 is introduced to the two encoding output ends of the encoding module, the switch unit can be discharged by the first discharge sub-unit, so that the switch unit is quickly disconnected to prevent abnormalities.

[0078] In some embodiments, the second delay unit includes a delay capacitor. Specifically, the second delay unit includes a second capacitor C2 and a sixth resistor R6, and the delay time of the second delay unit is determined according to the capacity of the delay capacitor and the resistance value of the sixth resistor R6, that is, the second predetermined time interval t2 can be set by setting the capacity of the second capacitor C2 and the resistance value of the second resistor R6. In some embodiments, the first discharge sub-unit includes a third transistor Q3, the second discharge sub-unit includes a first diode D1, and the stabilization unit includes a first transistor Q1 and a second transistor Q2. The second delay unit includes a second capacitor C2, the first discharge sub-unit includes a third transistor Q3, the second discharge sub-unit includes a first diode D1, the stabilization unit includes a first transistor Q1 and a second transistor Q2, one end of the second capacitor C2 is connected to the base of the third transistor Q3 through a seventh resistor R7, and is connected to the input signal terminal V1 through a sixth resistor R6, the input signal terminal V1 is used to receive an input signal, the other end of the second capacitor C2 is connected to the ground terminal, the collector of the third transistor Q3 is connected to the gate of the MOS tube and the collector of the first transistor Q1, the emitter of the third transistor Q3 is connected to the ground terminal, and the emitter of the first transistor Q1 is connected to the input signal terminal V1. Terminal V1, the base of the first triode Q1 is connected to the input signal terminal V1 through the second resistor R2, the base of the first triode Q1 is connected to the collector of the second triode Q2 through the fourth resistor R4, the base of the second triode Q2 is connected to the first delay unit, specifically connected to the other end of the first capacitor C1 through the first resistor R1, the base of the second triode Q2 is connected to the emitter of the second triode Q2 through the third resistor R3, the emitter of the second triode Q2 is connected to the ground terminal, the cathode of the first diode D1 is connected to the input signal terminal V1, the anode of the first diode is connected to one end of the second capacitor C2 and the seventh resistor R7, and is connected to the ground terminal through the fifth resistor R5.

[0079] Specifically, the operation process of the entire circuit is as follows: when the input signal TXD is at the second level, the first capacitor C1 and the second capacitor C2 are charged, the first capacitor turns on the second transistor Q2, the second transistor Q2 turns on the first transistor Q1, the first transistor Q1 turns on the switch unit, the switch unit introduces the waveform optimization unit between the two encoding output terminals of the encoding module, namely OUT (A) and OUT (B), at a first predetermined time interval t1 after the first capacitor C1 starts to charge, the first capacitor C1 is fully charged, that is, the delay ends, the second transistor Q2 and the first transistor Q1 are turned off, thereby stopping the power supply to the switch unit; at a second predetermined time interval t2 after the second capacitor C2 starts to charge, the second capacitor C2 is fully charged, that is, the delay ends, the The second capacitor C2 turns on the third transistor Q3, and the third transistor Q3 quickly discharges the switch unit, thereby quickly turning off the switch unit. In this process, since the base of the third transistor Q3 is connected to the input signal terminal V1 through the seventh resistor R7 and the sixth resistor R6, and the collector of the third transistor Q3 is connected to the base of the third transistor Q3 through the sixth resistor R6 and the seventh resistor R7, and the input signal TXD input by the signal input terminal V1 is still high level, in order to prevent the third transistor Q3 from pulling down the input signal TXD input by the signal input terminal V1, this embodiment introduces the first transistor Q1 and the second transistor Q2 to block the circuit of the third transistor Q3 and the signal input terminal V1, thereby avoiding abnormal switching of the input signal TXD. Afterwards, when the input signal TXD switches to a low level according to the normal switching cycle, the first diode D1 starts discharging the second capacitor C2 and turns off the third transistor Q3, and the voltage at the left end of the first capacitor C1 is pulled to 0V, and the right end becomes negative. It should be noted that in this embodiment, a first diode D1 is additionally provided to accelerate the discharge of the second capacitor C2. The second discharge unit enables the entire circuit to operate normally when the input signal TXD is then switched to a high level according to a normal switching cycle, thereby ensuring that the dynamic matching module can also normally cooperate with the transceiver signal of the encoding module 40 during the entire waveform cycle of the input signal TXD.

[0080] In some embodiments, the collector of the third triode Q3 is connected to the switch unit, specifically connected to the gate of the MOS tube, specifically connected to the gate of the first MOS tube Q4 and the gate of the second MOS tube Q5; the emitter of the third triode Q3 is connected to the ground end, the base of the third triode Q3 is connected to one end of the seventh resistor R7, one end of the second capacitor C2 is connected to the other end of the seventh resistor R7 and one end of the sixth resistor R6, the other end of the sixth resistor R6 is connected to the signal input end V1, the other end of the second capacitor C2 is connected to the ground end and one end of the fifth resistor R5, the other end of the fifth resistor R5 is connected to the positive electrode of the first diode D1, and the negative electrode of the first diode D1 is connected to the other end of the sixth resistor R6. The collector of the first transistor Q1 is connected to the collector of the third transistor Q3, the emitter of the first transistor Q1 is connected to one end of the second resistor R2 and the signal input terminal V1, the base of the first transistor Q1 is connected to the fourth resistor R4 and the other end of the second resistor R2, the other end of the fourth resistor R4 is connected to the collector of the second transistor Q2, the base of the second transistor Q2 is connected to one end of the first resistor R1 and one end of the third resistor R3, the emitter of the second transistor Q2 is connected to the other end of the third resistor R3 and the ground terminal, and the other end of the first resistor R1 is connected to the other end of the first capacitor C1.

[0081] Correspondingly, the utility model also provides a chip on which the power-generating circuit introduced above is integrated, thereby greatly saving the solution cost, making the solution design simpler, the overall integration is higher than that of traditional solutions, and the communication effect is more stable.

[0082] See also Figure 2 The chip can mainly integrate the rectifier bridge with active inductor module, active inductor unit, and power supply unit, and integrate over-current protection unit and over-temperature protection unit. Figure 8 The chip can integrate a rectifier bridge, an active inductor unit, an overcurrent protection unit, an overtemperature protection unit and a power supply unit, and integrate a dynamic matching module, making it Figure 2 The multi-integrated dynamic matching module connects the DIN pin of the dynamic matching module to the input end of the encoding module, and the OUTA and OUTB pins of the dynamic matching module are connected to the OUT (A) and OUT (B) of the transmission line after the encoding module encodes the signal internally. The capacitor is isolated from the transmission bus by DC current, and the time when the dynamic matching module is connected to the bus can be changed by different resistance values ​​indirectly through TM and GND. When TM is suspended, the time when the dynamic matching module is connected to the bus is equal to the high-level pulse width of the input signal of the encoding module. In some embodiments, the encoding module 40 can also be integrated into the chip to further improve the integration, reliability and reduce costs.

[0083] Correspondingly, the utility model also proposes a power supply system, including the chip mentioned above.

[0084] Although the utility model has been disclosed as above in the form of a preferred embodiment, it is not intended to limit the utility model. Any technical personnel in this field can make possible changes and modifications to the technical solution of the utility model by using the methods and technical contents disclosed above without departing from the spirit and scope of the utility model. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the utility model without departing from the content of the technical solution of the utility model are within the protection scope of the technical solution of the utility model.

Claims

1. A power circuit, characterized in that: An active inductor module is included, and the active inductor module includes: an active inductor unit and a rectifier bridge; the active inductor unit is connected to an external first bus and a second bus through the rectifier bridge; The active inductor unit is used to isolate the AC differential signal input from the first bus and the second bus, and output a DC power signal; The rectifier bridge is used to achieve non-polarity connection between the active inductor unit and the first bus and the second bus.

2. The power circuit according to claim 1, characterized in that: The active inductor module also includes an overcurrent protection unit; The overcurrent protection unit is used to control the active inductor unit to implement overcurrent protection.

3. The power circuit according to claim 1, characterized in that: The active inductor module also includes an over-temperature protection unit; The over-temperature protection unit is used to control the active inductor unit to achieve over-temperature protection.

4. The power circuit according to claim 1, characterized in that: The active inductor module also includes a power supply unit; The power supply unit is used to step down the DC power supply signal and then output a constant voltage.

5. The power circuit according to claim 1, characterized in that: It also includes a coding module, which is used to receive an input signal through a signal input terminal, encode the input signal and output a differential signal through two coding output terminals, and the two coding output terminals of the coding module are respectively connected to the first bus and the second bus.

6. The power circuit according to claim 5, characterized in that: Also includes: Dynamic matching module; When the input signal switches from a first level to a second level, a waveform optimization unit is connected between the two encoding output terminals of the encoding module, so that the voltage difference between the two encoding output terminals is quickly switched from a preset voltage difference to 0V, thereby preventing the voltage waveform output by the two encoding output terminals from being not steep enough to cause subsequent miscoding.

7. The power circuit according to claim 6, characterized in that: The dynamic matching module includes: a first delay unit, a switch unit and a waveform optimization unit; The first delay unit is used for, when the input signal switches from the first level to the second level, starting delay based on the second level and turning on the power supply to the switch unit so as to turn on the switch unit, and ending the delay and stopping the power supply to the switch unit when the first predetermined time interval is reached so as to turn off the switch unit; The switch unit is used to connect the waveform optimization unit between the two encoding output terminals after being turned on, and to disconnect the connection between the waveform optimization unit and the two encoding output terminals after being turned off; The waveform optimization unit is used to quickly switch the voltage difference between the two encoding output ends from a preset voltage difference to 0V.

8. The power circuit according to claim 7, characterized in that: The switch unit is a MOS tube.

9. The power circuit according to claim 8, characterized in that: The dynamic matching module also includes a first charging unit and a first discharging unit; The first charging unit is used to charge the parasitic capacitor Cgs of the MOS tube to form a charging loop when the input signal is at the second level and the power supply to the MOS tube is turned on, so as to quickly turn on the MOS tube; The first discharge unit is used to form a discharge loop for discharging the parasitic capacitance Cgs of the MOS tube when the input signal is at the second level and the delay ends and the power supply to the MOS tube stops when the first predetermined time interval is reached, so as to quickly shut down the MOS tube.

10. The power circuit according to claim 8, characterized in that: The dynamic matching module also includes a second discharge unit; The second discharge unit is used to start delaying based on the second level when the input signal switches from the first level to the second level, and discharge the MOS tube when a second predetermined time interval is reached, so as to quickly turn off the MOS tube, wherein the second predetermined time interval is greater than the first predetermined time interval.

11. The power circuit according to claim 10, characterized in that: The second discharge unit includes a second delay unit, a first discharge sub-unit and a second discharge sub-unit; The second delay unit is used for starting delay based on the second level when the input signal switches from the first level to the second level, and ending the delay when the second predetermined time interval is reached and turning on the first discharge sub-unit; wherein the second predetermined time interval is greater than the first predetermined time interval; The first discharge sub-unit is used to discharge the parasitic capacitance Cgs of the MOS tube after being turned on, so as to quickly turn off the MOS tube; The second discharge sub-unit is used for discharging the second delay unit based on the first level to disconnect the first discharge sub-unit when the input signal switches from the second level to the first level according to a normal switching cycle.

12. A chip, characterized in that: Comprising a power-generating circuit as described in any one of claims 1-11.

13. A power supply system, characterized in that: Comprising the chip as claimed in claim 12.

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