Side-mounted chip packaging structure
By adopting a side-mounted chip package structure in the semiconductor package structure, the chip is accommodated by trenches and electrically connected by conductive bumps, the substrate complexity and warping problems are solved, and the packaging structure is thin, short and high reliability is achieved.
Patent Information
- Application Number
- CN202421159951.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-05-24
- Publication Date
- 2025-01-07
- Estimated Expiration
- 2034-05-24
AI Technical Summary
While the existing semiconductor packaging structure is pursuing lightweight and short, the substrate design is complex and easy to cause warping due to differences in the thermal expansion coefficient of the material, affecting the packaging reliability.
Adopt a side-mounted chip packaging structure. By setting trenches on the substrate and installing the chip side in the groove, using part of the substrate space to accommodate the chip, reducing the complexity of the substrate design, and electrically connecting it to the conductive area through conductive bumps to avoid increasing Additional material between layers to prevent warping caused by differences in thermal expansion coefficients.
The volume reduction of the packaging structure is achieved, which meets the requirements of lightness and lightness, reduces the complexity of the substrate design, improves the reliability of the packaging structure, avoids warping problems, and enhances the electrical connection performance.
Smart Images
Figure CN222320252U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of semiconductor packaging, in particular to a side-mounted chip packaging structure. Background Art
[0002] As packaging technology continues to evolve, higher requirements are also placed on semiconductor packaging. In response to the requirements of semiconductor packaging being light, thin and short, current packaging structures are working in two directions: 1. Reducing the package size; 2. Functional integration. As for reducing the package size, there is limited room for improvement, so the packaging industry focuses on improving functional integration, that is, integrating some functional components or other electronic devices into the substrate in an embedded manner to expand the functional integration of the entire package. However, due to the complexity of the substrate design circuit, the manufacturing process of the embedded substrate is more complicated and the process requirements are relatively high. In addition, since the interlayer materials of the substrate after the components are embedded are more complex and diverse, and the thermal expansion coefficients of different materials vary greatly, the warping problem of the entire substrate is serious, the stratification is aggravated, and even the problem of bursting the board is caused. Summary of the invention
[0003] The utility model provides a side-mounted chip packaging structure, which can meet the requirements of semiconductor packaging being light, thin and short, and can reduce the complexity of substrate design, and does not require the addition of additional interlayer materials, thereby preventing warping problems caused by large differences in thermal expansion coefficients of different materials.
[0004] In one embodiment, the side-mounted chip packaging structure includes: a substrate, the top surface of the substrate having a groove, one side wall of the groove being an electrical connection side wall, the electrical connection side wall being step-shaped, and a first conductive area being arranged on at least one step surface of the electrical connection side wall; a side-mounted chip, side-mounted in the groove, the front surface of the side-mounted chip facing the electrical connection side wall, and a conductive bump being arranged on the front surface of the side-mounted chip, the conductive bump being placed on the step surface and electrically connected to the first conductive area.
[0005] In one embodiment, a side wall connected to the step surface on one side above the step surface constitutes a step wall, a second conductive region is provided on the step wall corresponding to the step surface provided with the first conductive region, a contact surface between the conductive bump and the step surface is electrically connected to the first conductive region, and a contact surface between the conductive bump and the step wall is electrically connected to the second conductive region.
[0006] In one embodiment, the side wall of the groove opposite to the electrical connection side wall is a supporting side wall, and the back side of the side-mounted chip is fixed on the supporting side wall.
[0007] In one embodiment, the supporting side wall is a flat plate structure, and the back surface of the side-mounted chip is in contact with the surface of the supporting side wall.
[0008] In one embodiment, the back surface of the side-mounted chip has a supporting bump, and the supporting bump is arranged on the top surface of the substrate.
[0009] In one embodiment, the supporting side wall is in a step shape, and the back side of the side-mounted chip has a supporting bump, and the supporting bump is arranged on the step surface of the supporting side wall.
[0010] In one embodiment, in the second direction, the step surface of the supporting side wall and the step surface of the electrical connection side wall are at the same height, or the step surface of the supporting side wall is higher or lower than the step surface of the electrical connection side wall, and the second direction is a direction perpendicular to the top surface of the substrate.
[0011] In one embodiment, in a first direction, the first conductive area is disposed discontinuously or continuously, the side-mounted chip includes a plurality of conductive bumps arranged at intervals, the conductive bumps are connected to different areas of the first conductive area, and the first direction is parallel to the top surface of the substrate.
[0012] In one embodiment, in a second direction, the groove penetrates the substrate, and the second direction is a direction perpendicular to the top surface of the substrate.
[0013] In one embodiment, the side-mounted chip packaging structure also includes a fixed structure arranged in the groove, the fixed structure includes a supporting base plate and a fixed side plate connected to one end of the supporting base plate, the supporting base plate is arranged on the side of the side-mounted chip for supporting the side-mounted chip, and the fixed side plate is arranged between the side-mounted chip and the side wall of the groove and fixed on the side wall of the groove.
[0014] In one embodiment, the fixed structure also includes a limiting top plate extending along a third direction, the limiting top plate is connected to an end of the fixed side plate away from the supporting bottom plate and is fixed on the substrate, and the third direction is a direction parallel to the top surface of the substrate.
[0015] In one embodiment, the side-mounted chip packaging structure further includes at least one functional chip, and the functional chip is mounted face-up or flip-down on the top surface of the substrate.
[0016] In one embodiment, a surface of the side-mounted chip is lower than a surface of the functional chip.
[0017] In the side-mounted chip packaging structure provided by the embodiment of the utility model, a groove is provided on the substrate, and the side-mounted chip is side-mounted in the groove. Part of the space of the substrate is used to accommodate the side-mounted chip. On the one hand, the volume of the packaging structure is reduced to meet the requirements of light, thin and short semiconductor packaging; on the other hand, there is no need to integrate the chip inside the substrate in an embedded manner, which reduces the complexity of the substrate design and does not require the addition of additional interlayer materials, thereby preventing warping problems caused by large differences in thermal expansion coefficients of different materials, thereby greatly improving the reliability of the packaging structure. BRIEF DESCRIPTION OF THE DRAWINGS
[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0019] Figure 1 is a schematic diagram of a side-mounted chip packaging structure provided by the first embodiment of the utility model;
[0020] Figure 2A It is a schematic diagram of a substrate in a side-mounted chip packaging structure provided by the first embodiment of the utility model;
[0021] Figure 2B yes Figure 2A A top view of the area A after the side-mounted chip is set;
[0022] Figure 3 is a schematic diagram of a side-mounted chip packaging structure provided by a second embodiment of the present utility model;
[0023] Figure 4 is a top view schematic diagram of the position relationship between the step surface and the side-mounted chip in the side-mounted chip packaging structure provided by the third embodiment of the utility model;
[0024] Figure 5 is a schematic diagram of a side-mounted chip packaging structure provided by a fourth embodiment of the present utility model;
[0025] Figure 6 is a schematic diagram of a side-mounted chip packaging structure provided by a fifth embodiment of the present utility model;
[0026] Figure 7 is a schematic diagram of a side-mounted chip packaging structure provided by a sixth embodiment of the present utility model;
[0027] Figure 8 It is a schematic diagram of a side-mounted chip packaging structure provided by the seventh embodiment of the present utility model. DETAILED DESCRIPTION
[0028] The specific implementation of the side-mounted chip packaging structure provided by the utility model is described in detail below with reference to the accompanying drawings.
[0029] Figure 1 is a schematic diagram of a side-mounted chip packaging structure provided by the first embodiment of the utility model, Figure 2A It is a schematic diagram of a substrate in a side-mounted chip packaging structure provided by the first embodiment of the utility model; Figure 2B yes Figure 2A The top view of the side-mounted chip in the middle A area is shown in the figure below. Figure 1 , Figure 2A as well as Figure 2B The side-mounted chip packaging structure includes: a substrate 100, the top surface of the substrate 100 has a groove 110, one side wall of the groove 110 is an electrical connection side wall 111, the electrical connection side wall 111 is stepped, and a first conductive area 113 is arranged on at least one step surface 114 of the electrical connection side wall 111; a side-mounted chip 120, which is side-mounted in the groove 110, the front side of the side-mounted chip 120 faces the electrical connection side wall 111, and a conductive bump 121 is arranged on the front side of the side-mounted chip 120, and the conductive bump 121 is placed on the step surface 114 and is electrically connected to the first conductive area 113.
[0030] In the side-mounted chip packaging structure, a groove 110 is provided on the substrate 100, and the side-mounted chip 120 is side-mounted in the groove 110. Part of the space of the substrate 100 is used to accommodate the side-mounted chip 120. On the one hand, the volume of the packaging structure is reduced, meeting the requirements of light, thin and short semiconductor packaging; on the other hand, there is no need to integrate the chip inside the substrate 100 in an embedded manner, reducing the complexity of the design of the substrate 100, and there is no need to add additional interlayer materials, thereby preventing warping problems caused by large differences in thermal expansion coefficients of different materials, thereby greatly improving the reliability of the packaging structure.
[0031] The substrate 100 includes a top surface and a bottom surface arranged relative to each other in a second direction D2, wherein the second direction D2 is a direction perpendicular to the top surface of the substrate 100, and solder pads (not shown in the drawings) are arranged on the top and bottom surfaces of the substrate 100, and the conductive circuits in the substrate 100 are electrically connected to the solder pads.
[0032] In some embodiments, the side-mounted chip packaging structure further includes at least one functional chip 130, which is mounted face-up or flip-down on the top surface of the substrate 100, and the functional chip 130 is interconnected or electrically connected to the side-mounted chip 120 and external devices through the pads on the top surface of the substrate 100, the conductive circuit inside the substrate 100, the pads on the bottom surface of the substrate 100, etc. In some embodiments, the side-mounted chip packaging structure further includes at least one passive device 140, which is arranged on at least one of the top and bottom surfaces of the substrate 100, and the passive device 140 is interconnected or electrically connected to the functional chip 130, the side-mounted chip 120, and external devices through the pads on the top surface of the substrate 100, the conductive circuit inside the substrate 100, the pads on the bottom surface of the substrate 100, etc. The plastic package 150 covers the substrate 100, the side-mounted chip 120, the functional chip 130, and the passive device 140.
[0033] In the second direction D2, the groove 110 extends from the top surface of the substrate 100 toward the inside of the substrate 100. The groove 110 may penetrate the substrate 100, or the groove 110 only extends to a set depth inside the substrate 100 and does not penetrate the substrate 100. For example, in this embodiment, in the second direction D2, the groove 110 penetrates the substrate 100, and the lower side of the side-mounted chip 120 disposed in the groove 110 is exposed to the bottom surface of the substrate 100. For another example, in another embodiment, Figure 3 As shown, Figure 3 It is a schematic diagram of the side-mounted chip packaging structure provided by the second embodiment of the present utility model, wherein the groove 110 extends to a set depth inside the substrate 100, the groove 110 does not penetrate the substrate 100, the lower side surface of the side-mounted chip 120 is in contact with the substrate 100 at the bottom of the groove 110, and the substrate 100 at the bottom of the groove 110 can support the side-mounted chip 120.
[0034] Please continue reading Figure 1 , Figure 2A and Figure 2B, one side wall of the groove 110 is an electrical connection side wall 111, the electrical connection side wall 111 is stepped, a first conductive area 113 is provided on at least one step surface 114 of the electrical connection side wall 111, and a conductive bump 121 of the side-mounted chip 120 is provided on the step surface 114 having the first conductive area 113, and is electrically connected to the first conductive area 113. The first conductive area 113 is connected to the internal circuit of the substrate 100, and is used to realize the electrical connection between the side-mounted chip 120 and the substrate 100. In some embodiments, the first conductive area 113 may be a conductive pad embedded in the substrate 100, and in other embodiments, the first conductive area 113 may also be a conductive pad protruding from the substrate 100.
[0035] The step surface 114 of the step electrically connected to the side wall 111 extends along the first direction D1. Figure 2B As shown, the step surface 114 extends along a first direction D1 , and the first direction D1 is a direction parallel to the top surface of the substrate 100 .
[0036] In some embodiments, the electrical connection sidewall 111 has one or more steps, so that it has one or more step surfaces. Figure 1 and Figure 2A As shown, in this embodiment, the electrical connection side wall 111 has a step, which has a step surface 114, on which the first conductive area 113 is arranged, and the conductive bump 121 of the side-mounted chip 120 is arranged on the step surface 114 and electrically connected to the first conductive area 113. For another example, in some other embodiments, the electrical connection side wall 111 has multiple step surfaces, and the multiple step surfaces are arranged along a third direction D3, and the third direction D3 is a direction parallel to the top surface of the substrate 100, and the third direction D3 is perpendicular to the first direction D1. The first conductive area 113 is arranged on the bottom step surface, and the conductive bump 121 of the side-mounted chip 120 is arranged on the bottom step surface and electrically connected to the first conductive area 113. It can be understood that when the electrical connection side wall 111 has multiple step surfaces, the first conductive area 113 can also be set on the middle step surface or the topmost step surface, or the first conductive area 113 can be set on multiple step surfaces, and each step surface corresponds to a conductive bump 121, so that multi-point electrical connection can be achieved.
[0037] In some embodiments, in the first direction D1, the first conductive area 113 is disposed discontinuously or continuously, and the side-mounted chip 120 includes a plurality of conductive bumps 121 arranged at intervals, and the conductive bumps 121 are connected to different areas of the first conductive area 113. Figure 2BAs shown, in this embodiment, on the step surface 114, in the first direction D1, the first conductive area 113 is intermittently arranged, the side-mounted chip 120 includes a plurality of conductive bumps 121 arranged at intervals along the first direction D1, the conductive bumps 121 are connected to different areas of the first conductive area 113, and the different areas of the first conductive area 113 are separated from each other. For another example, Figure 4 As shown, Figure 4 It is a top view schematic diagram of the positional relationship between the step surface and the side-mounted chip 120 in the side-mounted chip packaging structure provided in the third embodiment of the present utility model. In this embodiment, on the step surface 114, in the first direction D1, the first conductive area 113 is continuously arranged, and the side-mounted chip 120 includes a plurality of conductive bumps 121 arranged at intervals along the first direction D1, and the conductive bumps 121 are connected to different areas of the first conductive area 113.
[0038] In some embodiments, Figure 1 and Figure 2A As shown, the side wall connected to the step surface 114 on one side above the step surface 114 constitutes a step wall 115, and the step wall 115 corresponding to the step surface 114 provided with the first conductive area 113 is provided with a second conductive area 116, and the contact surface of the conductive bump 121 with the step surface 114 is electrically connected to the first conductive area 113, and the contact surface of the conductive bump 121 with the step wall 115 is electrically connected to the second conductive area 116. The second conductive area 116 is connected to the internal circuit of the substrate 100, and is used to realize the electrical connection between the side-mounted chip 120 and the substrate 100. In some embodiments, the second conductive area 116 can be a conductive pad embedded in the substrate 100, and in other embodiments, the second conductive area 116 can also be a conductive pad protruding from the substrate 100. The conductive area is provided on the step surface 114 and the step wall 115 of the step, which can expand the contact area between the conductive bump 121 and the conductive area, reduce the contact resistance, and thus improve the electrical connection performance of the packaging structure. In some embodiments, the first conductive region 113 is connected to the second conductive region 116 to further expand the contact area between the conductive bump 121 and the conductive region.
[0039] The front side of the side-mounted chip 120 is a functional surface of the side-mounted chip 120, which faces the electrical connection side wall 111. The conductive bump 121 is disposed on the front side and connected to the circuit in the side-mounted chip 120. The back side of the side-mounted chip 120 is disposed opposite to the front side of the side-mounted chip 120, and the back side is used as a fixing surface of the side-mounted chip 120.
[0040] In some embodiments, see Figure 1 , Figure 2A , Figure 2BThe side wall of the groove 110 opposite to the electrical connection side wall 111 is a support side wall 112, and the back side of the side-mounted chip 120 is fixed on the support side wall 112. For example, the back side of the side-mounted chip 120 is fixedly adhered to the support side wall 112 through an adhesive layer 122 to achieve the fixation of the side-mounted chip 120.
[0041] In the first embodiment, if Figure 1 As shown, the supporting side wall 112 is a flat plate structure, and the back of the side-mounted chip 120 is bonded to the surface of the supporting side wall 112 to fix the side-mounted chip 120. Furthermore, the back of the side-mounted chip 120 is bonded to the surface of the supporting side wall 112 through an adhesive layer 122 to fix the side-mounted chip 120.
[0042] In some embodiments, the back surface of the side-mounted chip 120 has a supporting bump, and the supporting bump is disposed on the top surface of the substrate 100. Figure 5 , Figure 5 1 is a schematic diagram of a side-mounted chip packaging structure provided by the fourth embodiment of the utility model. In the fourth embodiment, the upper side of the side-mounted chip 120 protrudes from the top surface of the substrate 100, and the back of the side-mounted chip 120 has a supporting bump 500, which is arranged on the top surface of the substrate 100. The top surface of the substrate 100 supports the supporting bump 500, and then the side-mounted chip 120 is supported and fixed by the supporting bump 500. In some embodiments, the supporting bump 500 can be fixed on the top surface of the substrate 100 through an adhesive layer. In some embodiments, the back of the side-mounted chip 120 has a plurality of supporting bumps 500 arranged at intervals in the first direction D1, and the supporting bumps 500 are all arranged on the top surface of the substrate 100. In other embodiments, the back of the side-mounted chip 120 has a supporting bump 500 with a longer length, which extends parallel to the first direction D1 and is arranged on the top surface of the substrate 100.
[0043] In another embodiment, the supporting side wall 112 is stepped, and the back of the side-mounted chip 120 has a supporting bump 500, and the supporting bump 500 is arranged on the stepped surface of the supporting side wall 112. Figure 6 , Figure 6 It is a schematic diagram of the side-mounted chip packaging structure provided by the fifth embodiment of the utility model. In the fifth embodiment, the supporting side wall 112 is not a flat side wall, but is stepped. The supporting side wall 112 has one or more steps, and the step surface 600 of the step extends along the first direction D1. The multiple steps are arranged along the third direction D3.
[0044] In this embodiment, the supporting sidewall 112 has a step having a step surface 600. The back of the side-mounted chip 120 has a supporting bump 500, and the supporting bump 500 is disposed on the step surface 600 of the supporting sidewall 112. The step surface 600 is used to support the supporting bump 500, and then the supporting bump 500 is used to support and fix the side-mounted chip 120. In some embodiments, the supporting bump 500 can be fixed on the step surface 600 by an adhesive layer.
[0045] In some embodiments, the back side of the side-mounted chip 120 has a plurality of support bumps 500 arranged at intervals along the first direction D1, and the support bumps 500 are all disposed on the step surface 600 of the support side wall 112. In other embodiments, the back side of the side-mounted chip 120 has a larger support bump 500, and the support bump 500 extends along the first direction D1 and is disposed on the step surface 600 of the support side wall 112.
[0046] The height of the step surface 600 of the supporting side wall 112 may be set according to the height of the supporting bump 500 of the side-mounted chip 120. Figure 6 As shown, in the fifth embodiment, the height of the supporting bump 500 is higher than the height of the conductive bump 121, and the step surface 600 of the supporting side wall 112 is higher than the step surface 114 of the electrical connection side wall 111. In other embodiments, the height of the supporting bump 500 is flush with the height of the conductive bump 121, or the height of the supporting bump 500 is lower than the height of the conductive bump 121, and the step surface 600 of the supporting side wall 112 is at the same height as the step surface 114 of the electrical connection side wall 111, or the step surface 600 of the supporting side wall 112 is lower than the step surface 114 of the electrical connection side wall 111.
[0047] In some other embodiments, the side-mounted chip 120 is fixed in the groove 110 by a fixing structure. Figure 7 , Figure 7: is a schematic diagram of a side-mounted chip packaging structure provided by the sixth embodiment of the utility model. In the sixth embodiment, the side-mounted chip packaging structure also includes a fixed structure 700 disposed in the groove 110. The fixed structure 700 includes a supporting base plate 701 and a fixed side plate 702 connected to one end of the supporting base plate 701. The supporting base plate 701 is disposed on the side of the side-mounted chip 120 for supporting the side-mounted chip 120. The fixed side plate 702 is disposed between the side-mounted chip 120 and the side wall of the groove 110 and fixed on the side wall of the groove 110. In some embodiments, the supporting base plate 701 directly contacts the lower side of the side-mounted chip 120. In other embodiments, the supporting base plate 701 may also contact the lower side of the side-mounted chip 120 through an adhesive layer to further increase the fixation of the side-mounted chip 120. In some embodiments, the outer surface of the fixed side plate 702 is fixed to the supporting side wall 112 (indicated at) of the groove 110 through an adhesive layer. Figure 2A In the sixth embodiment, the supporting side wall 112 is a flat plate structure. In other embodiments, the supporting side wall 112 is stepped, and the outer surface of the fixed side plate 702 is fixed to the step wall of the step by the adhesive layer.
[0048] In order to further strengthen the support and fixation of the side-mounted chip 120, the fixing structure 700 also includes a limiting top plate 800. Figure 8 , Figure 8 is a schematic diagram of the side-mounted chip packaging structure provided by the seventh embodiment of the utility model. In the seventh embodiment, the fixed structure 700 further includes a limit top plate 800 extending along the third direction D3. The limit top plate 800 is connected to an end of the fixed side plate 702 away from the supporting bottom plate 701 and fixed to the substrate 100, thereby strengthening the support and fixation of the side-mounted chip 120. In the seventh embodiment, the supporting side wall 112 (indicated at Figure 6 The limiting top plate 800 is located on the step surface 600 (marked at Figure 6 In some other embodiments, the supporting side wall 112 is a flat plate structure, the limiting top plate 800 is located above the substrate 100, and the lower surface of the limiting top plate 800 is fixed to the top surface of the substrate 100 through an adhesive layer.
[0049] In some embodiments, the surface of the side-mounted chip 120 is lower than the surface of the functional chip 130. Specifically, in the first direction D1, Figure 1 As shown, the upper side of the side-mounted chip 120 is lower than the surface of the functional chip 130 , so that the overall height of the packaging structure is not limited by the side-mounted chip 120 , which is conducive to further reducing the overall height of the packaging structure.
[0050] The side-mounted chip packaging structure provided by the embodiment of the utility model utilizes part of the space of the substrate to accommodate the side-mounted chip, which on the one hand reduces the volume of the packaging structure and meets the requirements of light, thin and short semiconductor packaging; on the other hand, it reduces the complexity of the substrate design and does not require the addition of additional interlayer materials, thereby preventing warping problems caused by large differences in thermal expansion coefficients of different materials, thereby greatly improving the reliability of the packaging structure.
[0051] It should be noted that the terms "including" and "having" and their variations involved in the documents of the present utility model are intended to cover non-exclusive inclusions. The terms "first", "second", etc. are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence, unless the context clearly indicates, and it should be understood that the data used in this way can be interchanged under appropriate circumstances. The term "one or more" depends at least in part on the context, and can be used to describe features, structures or characteristics in a singular sense, or can be used to describe a combination of features, structures or features in a plural sense. The term "based on" can be understood as not necessarily intended to express a set of exclusive factors, but can alternatively, also at least in part depending on the context, allow the presence of other factors that are not necessarily explicitly described. In addition, in the absence of conflict, the embodiments of the present utility model and the features in the embodiments can be combined with each other. In addition, in the above description, the description of known components and technologies is omitted to avoid unnecessary confusion of the concept of the present utility model. In the above embodiments, each embodiment focuses on the differences from other embodiments, and the same / similar parts between the embodiments can be referred to each other.
[0052] The above is only a preferred embodiment of the present invention. It should be pointed out that ordinary technicians in this technical field can make several improvements and modifications without departing from the principle of the present invention. These improvements and modifications should also be regarded as the protection scope of the present invention.
Claims
1. A side-mounted chip packaging structure, characterized in that: include: A substrate, wherein a top surface of the substrate has a groove, a side wall of the groove is an electrical connection side wall, the electrical connection side wall is stepped, and a first conductive area is arranged on at least one step surface of the electrical connection side wall; A side-mounted chip is side-mounted in the groove, the front side of the side-mounted chip faces the electrical connection side wall, and a conductive bump is provided on the front side of the side-mounted chip. The conductive bump is placed on the step surface and is electrically connected to the first conductive area.
2. The side-mounted chip packaging structure according to claim 1, characterized in that: The side wall connected to the step surface on one side above the step surface constitutes a step wall, the step wall corresponding to the step surface provided with the first conductive area is provided with a second conductive area, the contact surface between the conductive bump and the step surface is electrically connected to the first conductive area, and the contact surface between the conductive bump and the step wall is electrically connected to the second conductive area.
3. The side-mounted chip packaging structure according to claim 1, characterized in that: The side wall of the groove opposite to the electrical connection side wall is a supporting side wall, and the back side of the side-mounted chip is fixed on the supporting side wall.
4. The side-mounted chip packaging structure according to claim 3, characterized in that: The supporting side wall is a flat plate structure, and the back surface of the side-mounted chip is in contact with the surface of the supporting side wall.
5. The side-mounted chip packaging structure according to claim 4, characterized in that: The back surface of the side-mounted chip is provided with a supporting bump, and the supporting bump is arranged on the top surface of the substrate.
6. The side-mounted chip packaging structure according to claim 3, characterized in that: The supporting side wall is in a step shape, and the back side of the side-mounted chip is provided with a supporting protrusion, and the supporting protrusion is arranged on the step surface of the supporting side wall.
7. The side-mounted chip packaging structure according to claim 6, characterized in that: In the second direction, the step surface of the support side wall and the step surface of the electrical connection side wall are at the same height, or the step surface of the support side wall is higher or lower than the step surface of the electrical connection side wall, and the second direction is a direction perpendicular to the top surface of the substrate.
8. The side-mounted chip packaging structure according to claim 1, characterized in that: In a first direction, the first conductive area is disposed discontinuously or continuously, the side-mounted chip comprises a plurality of conductive bumps arranged at intervals, the conductive bumps are connected to different areas of the first conductive area, and the first direction is parallel to the top surface of the substrate.
9. The side-mounted chip packaging structure according to claim 1, characterized in that: In a second direction, the groove penetrates the substrate, and the second direction is a direction perpendicular to the top surface of the substrate.
10. The side-mounted chip packaging structure according to claim 9, characterized in that: The side-mounted chip packaging structure also includes a fixed structure arranged in the groove, and the fixed structure includes a supporting base plate and a fixed side plate connected to one end of the supporting base plate. The supporting base plate is arranged on the side of the side-mounted chip to support the side-mounted chip, and the fixed side plate is arranged between the side-mounted chip and the side wall of the groove and fixed on the side wall of the groove.
11. The side-mounted chip packaging structure according to claim 10, characterized in that: The fixing structure also includes a limiting top plate extending along a third direction, the limiting top plate is connected to an end of the fixing side plate away from the supporting bottom plate and is fixed on the base plate, and the third direction is a direction parallel to the top surface of the base plate.
12. The side-mounted chip packaging structure according to any one of claims 1 to 11, characterized in that: The side-mounted chip packaging structure further includes at least one functional chip, and the functional chip is mounted face-up or flip-down on the top surface of the substrate.
13. The side-mounted chip packaging structure according to claim 12, characterized in that: The surface of the side-mounted chip is lower than the surface of the functional chip.