Digital configuration type resonant switching power supply

Abstract

The utility model discloses a digital configuration type resonant switching power supply, which comprises a digital configuration type PFC (Power Factor Correction), an LLC (Logical Link Control) resonant control circuit, a half-bridge resonant conversion circuit, an output rectification filter circuit and an output voltage regulation circuit, and perfects the self-configurable protection functions, including power supply undervoltage protection, overpower protection and internal and external overheat protection. The capacitor mode is adjusted, accurate overvoltage protection, overcurrent protection, surge current protection, power-on / power-off protection and the like are realized, and the normal working state and reliability of the power supply are ensured; optimization of stable adjustment of PFC and LLC resonance control circuits is realized, and miniaturization, high efficiency and standardization of an industrial power supply are realized.

Description

Technical Field

[0001] The utility model belongs to the technical field of switch power supplies, and in particular relates to a digital configuration type resonant switch power supply. Background Art

[0002] LLC resonant converters are widely used in small and medium power DC / DC converters due to their high efficiency and high power density. LLC resonant converters have high system efficiency when using variable frequency control, but due to the steep low-frequency gain curve of the variable frequency control converter, it is easy to cause output voltage overshoot and system instability. Utility Model Content

[0003] The utility model aims at solving the problems existing in the prior art and proposes the following technical solutions:

[0004] A digitally configured resonant switching power supply, including a digitally configured PFC, LLC resonant control circuit, a half-bridge resonant conversion circuit, an output rectifier filter circuit and an output voltage adjustment circuit;

[0005] In the digital configuration PFC, LLC resonant control circuit, the TEA2017AAT digital control chip with position number U300 has a total of 16 external pins. The first pin SNSMAINS of the TEA2017AAT digital control chip is connected to the resistor R303 in series with the resistor R302, the resistor R301, and the resistor R300 to the positive electrode of the input capacitor VH+. The first pin SNSMAINS is connected to the positive electrode of the diode D300. The cathode of the diode D300 is connected to the parallel connection of the resistor R304 and the resistor R305 and then to one end of the thermistor RT300. The other end of the thermistor RT300 is grounded. The second pin SNSBOOT is connected to the series connection of the resistor R313, the resistor R312, the resistor R311, Resistor R310 is connected to the positive electrode of input capacitor VH+. The parallel connection of resistors R313, R312, R311, R310, R315 and R314 forms a voltage divider function. Capacitor C310 is connected at both ends of resistors R314 and R315. The second pin SNSBOOST of TEA2017AAT digital control chip is connected to the collector of field effect tube Q3. Capacitor C734 is connected between the collector and emitter of field effect tube Q3. The emitter of field effect tube Q3 is grounded. After resistor R735 is connected in parallel with capacitor C733, one end of resistor R735 is connected to the base of field effect tube Q3, and the other end of resistor R735 is connected to the emitter of field effect tube Q3. The base of field effect tube Q3 is connected to The three pins of the optocoupler QC730 and the four pins of the optocoupler QC730 are connected in series with resistor R738 and then connected to the 13th pin of the TEA2017AAT digital control chip, the SUPIC chip power supply end. The three and four pins of the optocoupler QC730 are connected in parallel with resistor RV730. The third pin SNSCURPFC of the TEA2017AAT digital control chip is connected to one end of the capacitor C320, and the other end of the capacitor C320 is grounded. The fourth pin GND of the TEA2017AAT digital control chip is the grounding end. The fifth pin of the TEA2017AAT digital control chip is the driving end of the PFCMOSFET, and the series resistor R203 is connected to the PFC switch tube. The sixth pin GATELS of the TEA2017AAT digital control chip is the LCC. The power supply for the low-side MOSFET driver and bootstrap capacitor, the seventh pin HVS of the TEA2017AAT digital control chip is the high-low voltage separation pin, which is not connected to the circuit, the eighth pin DRAINPFC of the TEA2017AAT digital control chip is connected to the drain of the field effect tube Q200, the ninth pin GATEHS of the TEA2017AAT digital control chip, the high-side MOSFET driver of the LCC, the tenth pin SUPHS of the TEA2017AAT digital control chip is the power supply for the high-side driver, which is connected to one end of the capacitor C500 bootstrap capacitor, the sixth pin GATELS of the TEA2017AAT digital control chip connects the diode D500 to the tenth pin SUPHS of the TEA2017AAT digital control chip,Charge the bootstrap capacitor C500. The 11th pin HB of the TEA2017AAT digital control chip is the reference for the high-side drive and the input of the half-bridge detection. The 11th pin HB of the TEA2017AAT digital control chip is connected to the other end of the bootstrap capacitor C500 and is also connected to the position of the transformer T1 at the midpoint of the high-side and low-side MOSFETs of the LCC. The 12th pin HVS of the TEA2017AAT digital control chip is the high-low voltage separation pin and is not connected to the circuit. The 13th pin of the TEA2017AAT digital control chip is the SUPIC chip. At the power supply end, capacitor C341 is connected in parallel between the SUPIC chip power supply end and the ground at the 13th pin of the TEA2017AAT digital control chip. At the SNSCAPLLC capacitor detection end at the 14th pin of the TEA2017AAT digital control chip, one end of the resonant capacitor C241 is connected in series with resistor R30 and resistor R29 and then divides the voltage with resistor R520, and transmits the divided voltage signal to the 14th pin of the TEA2017AAT digital control chip SNSCAPLLC. Capacitor C522, capacitor C521 and resistor R520 are connected in parallel, and capacitor C52 0 is connected in parallel to the two ends of the resistor R30 and the resistor R29 in series. The fifteenth pin SNSCURLLC of the TEA2017AAT digital control chip is the LCC current detection terminal. The fifteenth pin SNSCURLLC of the TEA2017AAT digital control chip is connected to one end of the capacitor C514. The other end of the capacitor C514 is connected to one end of the resistor R510. The resistors R511 and R510 are connected in parallel. The other end of the resistor R510 is grounded. The capacitors C512 and C513 are connected in parallel to the two ends of the resistor R510. One end of the resistor R511 is connected to the One end of capacitor C510 and capacitor C511 connected in parallel, the other end of capacitor C510 and capacitor C511 connected in parallel is connected to one end of resonant capacitor C241, the sixteenth pin SNSFB of TEA2017AAT digital control chip is the feedback end, the sixteenth pin SNSFB of TEA2017AAT digital control chip is connected to one end of resistor R501, the other end of resistor R501 is connected to the four pins of optocoupler QC700, the three pins of QC700 are grounded, and resistor RV700 and resistor R712 are connected in parallel between the three and four pins of optocoupler QC700.

[0006] As a preferred embodiment of the above technical solution, in the half-bridge resonant conversion circuit, the AC L is connected to one end of the fuse FS1, the other end of the fuse FS1 is connected to the front end of the inductor L100, the AC N is connected to the other front end of the inductor L100, the varistor RV100, the resistor R104, and the capacitor CX100 are connected in parallel between the front two ends of the inductor L100, the rear two ends of the inductor L100 are respectively connected to the two ends of AC of the bridge stack BD1, the two ends of AC are respectively connected to the capacitor CY103, the capacitor CY103 is connected to the earth PE, the V- end of the bridge stack BD1 is connected to one end of the resistor R250, It is also connected to the SNSCURPFC terminal of the TEA2017AAT digital control chip U300. The other end of the resistor R250 is connected to GND. The V+ end of the bridge BD1 is connected to one end of the thermistor RT1. The capacitor C100 is connected in parallel between the V+ and V- terminals. The other end of the thermistor RT1 is connected to one end of the inductor L200. The other end of the inductor L200 is connected to the positive electrode of the diode D220. The positive electrode of the diode D220 also needs to be connected to the DRAINPFC terminal of the TEA2017AAT digital control chip U300. The diode D230 is connected across To between one end of the inductor L200 and the cathode of the diode D220, the anode of the capacitor C230 is connected to the cathode of the diode D220, the cathode of the capacitor C230 is connected to GND, the anode of the diode D220 is connected to the drain of the field effect transistor Q210, the source of the field effect transistor Q210 is connected to GND, the capacitor C210 is connected between the drain and source of the field effect transistor Q210, the gate of the field effect transistor Q210 is connected to the anode of the diode D210, the cathode of the diode D210 is connected to the GATEPFC terminal of the TEA2017AAT digital control chip U300, and the resistor R211 is connected to The two ends of the diode D210, the resistor R210 is connected between the gate and source of the field effect transistor Q210, the drain of the field effect transistor Q410 is connected to the positive electrode of the capacitor C230, the capacitor C410 is connected between the drain and source of the field effect transistor Q410, the resistor R410 is connected between the gate and source of the field effect transistor Q410, the source of the field effect transistor Q410 and the drain of the field effect transistor Q420 are connected and then connected to one end of the first winding of the transformer T1, the other end of the first winding of the transformer T1 is connected to the capacitor C421 to GND, the drain of the field effect transistor Q420 is connected to GND,Resistor R420 is connected between the gate and source of field effect transistor Q420, capacitor C420 is connected between the drain and source of field effect transistor Q420, one end of the first winding of transformer T1 also needs to be connected to the HB end of TEA2017AAT digital control chip U300, the gate of field effect transistor Q420 is connected to the GATEHS end of TEA2017AAT digital control chip U300 through resistor R411, the gate of field effect transistor Q410 is connected to the GATELS end of TEA2017AAT digital control chip U300 through resistor R421, the other end of the first winding of transformer T1 is connected to the circuit for detecting LLC overcurrent, the second winding of transformer T1 One end is connected to the positive electrode of diode D752, the negative electrode of diode D752 is connected to the positive electrode of capacitor C753, the other end of the second winding of transformer T1 is connected to GND, the negative electrode of capacitor C753 is connected to GND, the positive electrode of capacitor C753 is connected to the collector of transistor Q750, resistor R750 is connected between the base and collector of transistor Q750, the negative electrode of voltage regulator ZD750 is connected to the base of transistor Q750, the positive electrode of voltage regulator ZD750 is connected to GND, the positive electrode of capacitor C340 is connected to the emitter of transistor Q750, the negative electrode of capacitor C340 is connected to GND, and the positive electrode of capacitor C340 needs to be connected to the SUPIC end of TEA2017AAT digital control chip U300. ,

[0007] As a preferred embodiment of the above technical solution, in the output rectifier and filter circuit, one end of the third winding of the transformer T1 is connected to the cathode of the diode D333, the resistor R440 and the capacitor C440 are connected in series and then connected across the two ends of the diode D333, the other end of the third winding of the transformer T1 is connected to the OUT+ end, the anode of the diode D333 is connected to the anode of the diode D336 and then connected to the SGND end, one end of the fourth winding of the transformer T1 is connected to the other end of the third winding of the transformer T1, the other end of the fourth winding of the transformer T1 is connected to the cathode of the diode D336, the resistor R430 and the capacitor C430 are connected in series and then connected across the two ends of the diode D336, the capacitor C453, the capacitor C454, the capacitor C455 and the resistor R451 are connected in parallel between the OUT+ end and the SGND end, the OUT+ end is connected to the 4th and 5th pins of TB2, and the SGND is connected to the 1st, 2nd and 3rd pins of TB2.

[0008] As a preferred embodiment of the above technical solution, in the output voltage adjustment circuit, pin 1 of the optocoupler QC700 is connected to the resistor R706 to the OUT+ terminal, the resistor R707 is connected in parallel between the pins 1 and 2 of the optocoupler QC700, the pin 2 of the optocoupler QC700 is connected to the pin 3 of the modulator U700, the pin 2 of the modulator U700 is connected to the SGND terminal, the capacitor C701 and the resistor R705 are connected in series and then bridged between the pins 1 and 3 of the modulator U700, and the pin 1 of the modulator U700 is connected to the resistor R706. 00 to OUT+ terminal, pin 1 of modulator U700 is connected to one end of resistor R704, the other end of resistor R704 is connected to potentiometer VR1 to SGND terminal, pin 1 of optocoupler QC730 is connected to one end of resistor R733, the other end of resistor R733 is connected to the positive electrode of Zener diode Z700, the negative electrode of Zener diode ZD700 is connected to OUT+ terminal, resistor R734 is between pins 1 and 2 of optocoupler QC730, and pin 2 of optocoupler QC730 is connected to SGND terminal.

[0009] The beneficial effects of the utility model are:

[0010] The utility model configures PFC and LLC resonant control circuits through the TEA2017AAT digital controller, and improves the self-configurable protection functions, including power undervoltage protection, overpower protection, internal and external overheating protection, capacitor mode adjustment, with precise overvoltage protection, overcurrent protection, surge current protection, power-on / power-off protection, etc., to ensure the normal working state and reliability of the power supply; to achieve the optimization of the stable adjustment of the PFC and LLC resonant control circuits, and to realize the miniaturization, high efficiency and standardization of industrial power supplies. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 It is a topological structure diagram of a digitally configured resonant switching power supply;

[0012] Figure 2 This is the basic block diagram of TEA2017AAT;

[0013] Figure 3 This is the basic pin diagram of TEA2017AAT;

[0014] Figure 4 This is the pin description of TEA2017AAT;

[0015] Figure 5 Connection diagram between the burning tool and TEA2017AAT;

[0016] Figure 6 It is a schematic diagram of the topology of the digital configuration PFC, LLC resonant control circuit;

[0017] Figure 7 It is a schematic diagram of the topological structure of a half-bridge resonant converter circuit;

[0018] Figure 8 It is a schematic diagram of the topological structure of the output rectifier and filter circuit;

[0019] Fig. 9 Schematic diagram of the topology of the output voltage adjustment circuit. DETAILED DESCRIPTION

[0020] In order to make the purpose, technical solution and advantages of the embodiments of the present utility model clearer, the technical solution of the present utility model will be clearly and completely described below in conjunction with the embodiments.

[0021] Figure 1 The topological structure diagram of the digital configuration resonant switching power supply is shown. The switching power supply includes a digital configuration PFC, an LLC resonant control circuit, a half-bridge resonant conversion circuit, an output rectifier filter circuit and an output voltage adjustment circuit.

[0022] The technical solution adopted by the utility model is: digital configuration type PFC, LLC resonance control circuit.

[0023] LLC resonant converter can achieve ZVS of the primary switch tube and ZCS of the secondary rectifier tube, greatly improving the efficiency of the converter. The switch of LLC resonant converter can operate in high-frequency mode, which reduces the size of the converter and improves the power density of the converter. It is a new topology.

[0024] The LLC resonant converter is difficult to control due to its nonlinear gain. If the LLC resonant converter uses a fixed parameter regulator, the LLC resonant converter does not have good anti-disturbance capability and cannot cope with a wider input voltage adjustment range. How to quickly adapt to the changing parameters and propose a digital regulator parameter adaptive control method to improve the dynamic response performance and anti-disturbance capability of the converter. By changing the parameters of the regulator according to the adjustment error of the output voltage until the converter has better dynamic response performance. This requires that the LLC resonant control circuit must be a digital solution.

[0025] TEA2017AAT is a digitally configured multi-mode PFC+LLC integrated controller with a built-in MCU digital power control IC. For PFC, it is a phase-shifted sine wave shaping average current mode control. The available selective control mode (DCM, CRM, CCM) can make the input current track the input voltage well through phase shift control, which greatly improves the PF value and THD. For LLC, it has multi-mode working states, BM, LP and HP modes. The BM and LP working modes can improve the light load efficiency of the whole machine. Since the voltage on the resonant capacitor in the resonant cavity loop is proportional to the output power, the LLC drive is controlled by sampling the resonant capacitor voltage, and the output power is controlled by the cycle by cycle digital control method. Therefore, this digital control method has a better output dynamic response, and the drive is controlled by sampling the LLC resonant cavity midpoint voltage slope to avoid entering the capacitive area. Improved the self-configurable protection functions, including power undervoltage protection, overpower protection, internal and external overheat protection, capacitor mode adjustment, precise overvoltage protection, overcurrent protection, inrush current protection, power-on / power-off protection, etc., to ensure the normal working state and reliability of the power supply, see Figure 3 and Figure 4 , Figure 3 The following is the basic pin diagram of TEA2017AAT. Figure 4 Shown is the pin description of TEA2017AAT.

[0026] The LLC system regulates the output voltage VOUT digitally. The TEA2017AAT regulates the output power by regulating the voltage across the primary capacitor. The advantage over the standard frequency analog control loop is that the digital control loop has a constant gain characteristic and the IC has real-time information about the output power. Therefore, the operating mode transition point is determined by the output power. Although the TEA2017AAT uses the primary capacitor voltage as the regulation parameter, all application values, such as the resonant impedance, resonant capacitor and primary MOSFET, remain unchanged compared to the frequency-controlled LLC converter. The secondary TL431 circuit and the optocoupler connected to the primary SNSFB pin continuously regulate the output voltage. When the divided resonant capacitor voltage (VSNSCAP) exceeds the capacitor voltage high level (Vhs(SNSCAP)), the high-side MOSFET is turned off and after a short delay, the low-side MOSFET is turned on. Due to the resonant current, the resonant capacitor voltage keeps increasing further, but then gradually decreases. When the divided resonant capacitor voltage (VSNSCAP) drops below the capacitor voltage low level (Vls(SNSCAP)), the low-side MOSFET is turned off. After a short delay, the high-side MOSFET is turned on. The switching frequency is the result of this switching behavior. In frequency-controlled systems, frequency is a control parameter and output power is the result. But the TEA2017AAT regulates power and frequency is the result. The difference between the high and low capacitor voltage levels is an indicator of the output power provided. The value of the primary optocoupler current is determined by the secondary TL431 circuit, which determines the difference between the high and low capacitor voltages. If the output load increases, the current drawn from the SNSFB pin will decrease. The result is that the TEA2017AAT increases the high-level capacitor voltage and decreases the low-level capacitor voltage. As the output power increases, the output voltage gradually increases to the regulation level. In order to minimize the no-load input power of the system, the primary current into the optocoupler is continuously regulated to Ireg(SNSFB). The output voltage is sampled by the TL431 and connected to the SNSFB pin of the TEA2017AAT via the optocoupler feedback. When the load power is minimum, the current flowing through the optocoupler is maximum. Therefore, this current parameter is a critical parameter for no-load. To achieve maximum efficiency at no-load, the TEA2017AAT continuously adjusts the optocoupler current to a very small value until it is independent of the load power. To achieve low no-load input power, the current through the optocoupler must be set to a low current. However, depending on the selected optocoupler, a higher optocoupler current may be required. Therefore, the optocoupler current can be set to different values ​​in the range of 80μA to 1.2mA.

[0027] The PFC system regulates the output voltage (VBOOST) digitally. The PFC operates in QR or DCM (valley switching) mode. The next turn-on condition of the PFC switch is when the secondary side is turned on and the current on the PFC MOSFET reaches the minimum value. In order to detect the demagnetization of the transformer and the minimum voltage on the MOSFET, the control chip continuously monitors the voltage on the PFC MOSFET and the current flowing through the PFC circuit. In order to prevent the transformer from generating noise during the startup process, the IC integrates the PFC system soft start function, and the duty cycle slowly increases and the PFC startup conditions are met. When the PFC starts switching, the maximum duty cycle increases from zero cycle by cycle until ton is adjusted to the maximum duty cycle limit of the MOSFET. The turn-on time of the PFC MOSFET is determined by the internal digital loop, including the compensation loop. For the mains compensation, the current flowing into the SNSMAINS pin is used to reflect the size of the mains voltage. The error amplifier (SNSBOOST pin) adjusts the output voltage (VBOOST) changes. The VBOOST bus voltage is divided by a high-value resistor and connected to the SNSBOOST pin. The internal digital control loop compares a precisely adjustable reference voltage Vreg(SNSBOOST) with the SNSBOOST voltage and adjusts the output voltage (VBOOST) by adjusting the on-time. In order to ensure that the TEA2017AAT operates in DCM or QR mode, the PFC switch tube operates after the transformer is demagnetized. In order to reduce switching losses and EMI, the next turn-on time is when the PFC switch tube drain voltage is at its minimum (bottom turn-on). Demagnetization and valley detection are implemented through the SNSCURPFC and DRAINPFC pins. In order to reduce transformer losses and switching losses, the switching frequency is limited to fsw(PFC)max. If the quasi-resonant operating frequency If this limit is exceeded, the system will enter DCM. When the system is in DCM, the PFC switch tube operates at the bottom of the valley. In order to ensure that the PFC MOSFET can be correctly controlled under various operating conditions, the minimum off time of the switch tube is limited to toff(PFC)min. The transfer function of the power factor corrector includes the square term of the input voltage. In typical applications, when the input voltage is low, this is a low-bandwidth loop. At high input voltages, the grid resonance suppression MHR requirements are difficult to meet. In order to compensate for the influence of the input voltage, the TEA2017AAT includes a correction circuit. The input voltage is measured through the SNSMAINS pin, and this signal is fed forward to the internal mains compensation circuit. Through this digital compensation, the bandwidth of the regulation loop can be guaranteed to be constant over the entire input voltage range. In this way, when the load step changes, the input voltage is independent, thereby meeting the Class D current harmonic requirements.

[0028] TEA2017AAT is equipped with an internal MTP, on which different settings can be programmed. Use the MTP's RingoGUI software to change the MTP parameter settings. After the connection is successful, reading and writing are very convenient. (Press the read and write button on the lower left), and the program settings are automatically verified to form a unique identification verification code to ensure that the program settings are correct. See Figure 2 , Figure 2 Shown is the basic block diagram of TEA2017AAT.

[0029] PFC programming settings:

[0030] 1. For the start-up time of PFC, the following RC time periods can be selected: 13ms, 25ms, 51ms or 102ms.

[0031] 2. Active X-capacitor discharge When the TEA2017AAT detects that the mains is disconnected, the X-capacitor discharge is activated after a delay of td(dch). The following delay times can be selected: 100ms, 200ms and 400ms. This function can also be disabled.

[0032] 3. Mains measurement impedance To achieve low no-load input power levels, the external resistor connected to the SNSMAINS pin for measuring the mains input voltage is typically 20MΩ. However, some applications require a maximum resistance of 10MΩ. With this bit, 10MΩ or 20MΩ can be selected for the external resistor without affecting the levels related to the mains voltage, such as brownin and brownout.

[0033] 4. PFC operating mode After enabling multi-mode, PFC can operate in DCM, QR or CCM mode. However, the frequency varies between the minimum and maximum frequencies. It is also possible to disable CCM mode or select fixed frequency mode. For evaluation purposes, the option of disabling PFC is also provided.

[0034] 5. PFC minimum and maximum frequency The minimum switching frequency of PFC can be set in the range of 25kHz to 80kHz. When the CCM operation mode is disabled, PFC always waits until the PFC coil is demagnetized before starting the next cycle. Therefore, the switching frequency may drop below the minimum frequency. The maximum frequency can be set in the range of 75kHz to 250kHz. When the PFC operation mode is set to fixed frequency, the frequency can be set between 55kHz and 200kHz.

[0035] 6. Burst mode: output voltage ripple. When the PFC enters burst mode, if the SNSBOOST voltage reflecting the PFC output voltage reaches its regulation level and the LLC stops switching, switching will stop. When the voltage on the SNSBOOST pin drops to the programmed level, the PFC will be enabled again. For the difference between these two levels, the following values ​​can be selected: 70mV, 105mV, 140mV, 175mV, 210mV, 245mV and 280mV. These values ​​usually correspond to ripples on the PFC output voltage of 10V, 16V, 22V, 28V, 34V, 40V and 46V. The PFC burst mode can also be synchronized to the LLC burst mode. At this time, it will follow the on and off cycles of the LLC. But it can ensure that SNSBOOST reaches its regulation level.

[0036] 7. Burst Mode: Soft Start / Soft Stop Time To minimize the audible noise of the PFC, the burst mode soft start and soft stop can be selected independently. The selectable values ​​are: Normal, Short and Long. It is also possible to disable the additional soft start and soft stop.

[0037] LLC programming settings:

[0038] 1. Startup Maximum (Startup) Frequency The maximum switching frequency of the LLC is limited to the value defined using the parameter. This value also defines the maximum switching frequency during startup. The maximum frequency can be set to different values ​​between 150kHz and 800kHz. LLC Soft-Start Time The LLC soft-start time defines the rate at which the converter reduces its switching frequency. The rate can be selected between 2 and 20, which results in a startup time between about 1ms and 10ms. However, this depends on the LLC design. A higher rate shortens the startup time. However, it results in high charging current and output voltage overshoot.

[0039] 2. Maximum primary current during startup At startup, LLC starts switching at maximum frequency and gradually reduces the frequency until ΔVSNSCAP reaches the required level. If during this startup time, the primary current reflecting the output current reaches a predefined level, the frequency is temporarily not further reduced until the primary current drops below this level again. This level is measured via the SNSCURLLC pin. The following values ​​can be selected: 0.5V, 0.75V, 1.0V or 1.25V.

[0040] 3. LLC switch ΔVSNSCAP dump level When the system is in low power mode, the switching cycle is followed by a waiting period. The system ensures that the phase in which it continues to operate is the same as the phase in which it stopped. In order to achieve maximum efficiency, the end of the last switching cycle can be fine-tuned. For the ΔVSNSCAP dump level, the selectable value is 2.525V to 2.7V, with a step size of 25mV.

[0041] 4. Minimum non-overlap time To ensure that GATEHS is properly turned off before GATELS is turned on (and vice versa), the minimum non-overlap time needs to be set. For the minimum non-overlap time, the following values ​​can be selected: 100ns, 230ns, 350ns, 500ns. Maximum non-overlap time After turning off GATEHS, when the system does not detect a valley at the HB node, the system will turn on GATELS after the maximum non-overlap time. The same is true if no peak is detected at the HB node after turning off GATELS and turning on GATEHS. For the maximum non-overlap time, the following values ​​can be selected: 0.5μs, 0.7μs, 0.9μs, or 1.1μs Maximum on-time When the on-time of GATELS or GATEHS exceeds the maximum on-time, the switch will turn off and the LLC converter will start the next cycle. For the maximum on-time, the following values ​​can be selected: 10μs, 20μs, 30μs, or 38μs.

[0042] 5. Capacitive mode regulation When the voltage on the SNSCURLLC pin, which reflects the resonant current, drops below a predefined value, the LLC converter starts the next switching cycle. In this way, the TEA2017AAT can avoid the converter operating in the capacitive region. For capacitive mode regulation, the following values ​​can be selected: 20mV to 160mV in steps of 20mV. 5: When the LLC operates in LP mode, it counts the number of ringings. If no ringing is detected, a peak is assumed after a timeout. This timeout can be set to 3μs, 5μs, 7.5μs, or 10μs. The appropriate value depends on the application. The selected value must be just greater than the maximum ringing period.

[0043] 6. Feedback To achieve low no-load input power, the current through the optocoupler must be set to a low current. However, depending on the selected optocoupler, a higher optocoupler current may be required. Therefore, the optocoupler current can be set to different values ​​in the range of 80μA to 1.2mA, see Figure 5 , Figure 5 Shown is the connection diagram between the programming tool and TEA2017AAT.

[0044] The above are the basic settings for the PFC and LLC parameter programming of TEA2017AAT.

[0045] The above embodiments are only used to illustrate the technical solution of the present invention, but not to limit it.

Claims

1. A digitally configured resonant switching power supply, characterized in that: Including digital configuration PFC, LLC resonant control circuit, half-bridge resonant conversion circuit, output rectification and filtering circuit and output voltage adjustment circuit; In the digital configuration PFC, LLC resonant control circuit, the TEA2017AAT digital control chip with position number U300 has a total of 16 external pins. The first pin SNSMAINS of the TEA2017AAT digital control chip is connected to the resistor R303 in series with the resistor R302, the resistor R301, and the resistor R300 to the positive electrode of the input capacitor VH+. The first pin SNSMAINS is connected to the positive electrode of the diode D300. The cathode of the diode D300 is connected to the parallel connection of the resistor R304 and the resistor R305 and then to one end of the thermistor RT300. The other end of the thermistor RT300 is grounded. The second pin SNSBOOT is connected to the series connection of the resistor R313, the resistor R312, the resistor R311, Resistor R310 is connected to the positive electrode of input capacitor VH+. The parallel connection of resistors R313, R312, R311, R310, R315 and R314 forms a voltage divider function. Capacitor C310 is connected at both ends of resistors R314 and R315. The second pin SNSBOOST of TEA2017AAT digital control chip is connected to the collector of field effect tube Q3. Capacitor C734 is connected between the collector and emitter of field effect tube Q3. The emitter of field effect tube Q3 is grounded. After resistor R735 is connected in parallel with capacitor C733, one end of resistor R735 is connected to the base of field effect tube Q3, and the other end of resistor R735 is connected to the emitter of field effect tube Q3. The base of field effect tube Q3 is connected to The three pins of the optocoupler QC730 and the four pins of the optocoupler QC730 are connected in series with resistor R738 and then connected to the 13th pin of the TEA2017AAT digital control chip, the SUPIC chip power supply end. The three and four pins of the optocoupler QC730 are connected in parallel with resistor RV730. The third pin SNSCURPFC of the TEA2017AAT digital control chip is connected to one end of the capacitor C320, and the other end of the capacitor C320 is grounded. The fourth pin GND of the TEA2017AAT digital control chip is the grounding end. The fifth pin of the TEA2017AAT digital control chip is the driving end of the PFCMOSFET, and the series resistor R203 is connected to the PFC switch tube. The sixth pin GATELS of the TEA2017AAT digital control chip is the LCC. The power supply for the low-side MOSFET driver and bootstrap capacitor, the seventh pin HVS of the TEA2017AAT digital control chip is the high-low voltage separation pin, which is not connected to the circuit, the eighth pin DRAINPFC of the TEA2017AAT digital control chip is connected to the drain of the field effect tube Q200, the ninth pin GATEHS of the TEA2017AAT digital control chip, the high-side MOSFET driver of the LCC, the tenth pin SUPHS of the TEA2017AAT digital control chip is the power supply for the high-side driver, which is connected to one end of the capacitor C500 bootstrap capacitor, the sixth pin GATELS of the TEA2017AAT digital control chip connects the diode D500 to the tenth pin SUPHS of the TEA2017AAT digital control chip,Charge the bootstrap capacitor C500. The 11th pin HB of the TEA2017AAT digital control chip is the reference for the high-side drive and the input of the half-bridge detection. The 11th pin HB of the TEA2017AAT digital control chip is connected to the other end of the bootstrap capacitor C500 and is also connected to the position of the transformer T1 at the midpoint of the high-side and low-side MOSFETs of the LCC. The 12th pin HVS of the TEA2017AAT digital control chip is the high-low voltage separation pin and is not connected to the circuit. The 13th pin of the TEA2017AAT digital control chip is the SUPIC chip. At the power supply end, capacitor C341 is connected in parallel between the SUPIC chip power supply end and the ground at the 13th pin of the TEA2017AAT digital control chip. At the SNSCAPLLC capacitor detection end at the 14th pin of the TEA2017AAT digital control chip, one end of the resonant capacitor C241 is connected in series with resistor R30 and resistor R29 and then divides the voltage with resistor R520, and transmits the divided voltage signal to the 14th pin of the TEA2017AAT digital control chip SNSCAPLLC. Capacitor C522, capacitor C521 and resistor R520 are connected in parallel, and capacitor C52 0 is connected in parallel to the two ends of the resistor R30 and the resistor R29 in series. The fifteenth pin SNSCURLLC of the TEA2017AAT digital control chip is the LCC current detection terminal. The fifteenth pin SNSCURLLC of the TEA2017AAT digital control chip is connected to one end of the capacitor C514. The other end of the capacitor C514 is connected to one end of the resistor R510. The resistors R511 and R510 are connected in parallel. The other end of the resistor R510 is grounded. The capacitors C512 and C513 are connected in parallel to the two ends of the resistor R510. One end of the resistor R511 is connected to the One end of capacitor C510 and capacitor C511 connected in parallel, the other end of capacitor C510 and capacitor C511 connected in parallel is connected to one end of resonant capacitor C241, the sixteenth pin SNSFB of TEA2017AAT digital control chip is the feedback end, the sixteenth pin SNSFB of TEA2017AAT digital control chip is connected to one end of resistor R501, the other end of resistor R501 is connected to the four pins of optocoupler QC700, the three pins of QC700 are grounded, and resistor RV700 and resistor R712 are connected in parallel between the three and four pins of optocoupler QC700.

2. The digitally configured resonant switching power supply according to claim 1, characterized in that: In the half-bridge resonant conversion circuit, the AC L is connected to one end of the fuse FS1, the other end of the fuse FS1 is connected to the front end of the inductor L100, the AC N is connected to the other front end of the inductor L100, the varistor RV100, the resistor R104, and the capacitor CX100 are connected in parallel between the front ends of the inductor L100, the rear ends of the inductor L100 are respectively connected to the two ends of the AC of the bridge BD1, the two ends of the AC are respectively connected to the capacitor CY103, the capacitor CY103 is connected to the earth PE, the V- end of the bridge BD1 is connected to one end of the resistor R250, and is also connected to TEA2 017AAT digital control chip U300's SNSCURPFC terminal, the other end of resistor R250 is connected to GND, the V+ end of bridge BD1 is connected to one end of thermistor RT1, capacitor C100 is connected in parallel between V+ and V- terminals, the other end of thermistor RT1 is connected to one end of inductor L200, the other end of inductor L200 is connected to the positive electrode of diode D220, the positive electrode of diode D220 also needs to be connected to the DRAINPFC terminal of TEA2017AAT digital control chip U300, and diode D230 is connected across inductor L20 0 and the cathode of diode D220, the anode of capacitor C230 is connected to the cathode of diode D220, the cathode of capacitor C230 is connected to GND, the anode of diode D220 is connected to the drain of field effect transistor Q210, the source of field effect transistor Q210 is connected to GND, capacitor C210 is connected between the drain and source of field effect transistor Q210, the gate of field effect transistor Q210 is connected to the anode of diode D210, the cathode of diode D210 is connected to the GATEPFC terminal of TEA2017AAT digital control chip U300, resistor R211 is connected to diode The two ends of D210, the resistor R210 is connected between the gate and source of the field effect tube Q210, the drain of the field effect tube Q410 is connected to the positive electrode of the capacitor C230, the capacitor C410 is connected between the drain and source of the field effect tube Q410, the resistor R410 is connected between the gate and source of the field effect tube Q410, the source of the field effect tube Q410 and the drain of the field effect tube Q420 are connected and then connected to one end of the first winding of the transformer T1, the other end of the first winding of the transformer T1 is connected to the capacitor C421 to GND, the drain of the field effect tube Q420 is connected to GND,Resistor R420 is connected between the gate and source of field effect transistor Q420, capacitor C420 is connected between the drain and source of field effect transistor Q420, one end of the first winding of transformer T1 also needs to be connected to the HB end of TEA2017AAT digital control chip U300, the gate of field effect transistor Q420 is connected to the GATEHS end of TEA2017AAT digital control chip U300 through resistor R411, the gate of field effect transistor Q410 is connected to the GATELS end of TEA2017AAT digital control chip U300 through resistor R421, the other end of the first winding of transformer T1 is connected to the circuit for detecting LLC overcurrent, the second winding of transformer T1 One end is connected to the positive electrode of diode D752, the negative electrode of diode D752 is connected to the positive electrode of capacitor C753, the other end of the second winding of transformer T1 is connected to GND, the negative electrode of capacitor C753 is connected to GND, the positive electrode of capacitor C753 is connected to the collector of transistor Q750, resistor R750 is connected between the base and collector of transistor Q750, the negative electrode of voltage regulator ZD750 is connected to the base of transistor Q750, the positive electrode of voltage regulator ZD750 is connected to GND, the positive electrode of capacitor C340 is connected to the emitter of transistor Q750, the negative electrode of capacitor C340 is connected to GND, and the positive electrode of capacitor C340 needs to be connected to the SUPIC end of TEA2017AAT digital control chip U300. , 3. The digitally configured resonant switching power supply according to claim 2, characterized in that: In the output rectifier and filter circuit, one end of the third winding of the transformer T1 is connected to the cathode of the diode D333, a resistor R440 and a capacitor C440 are connected in series and then connected across the two ends of the diode D333, the other end of the third winding of the transformer T1 is connected to the OUT+ end, the anode of the diode D333 is connected to the anode of the diode D336 and then connected to the SGND end, one end of the fourth winding of the transformer T1 is connected to the other end of the third winding of the transformer T1, the other end of the fourth winding of the transformer T1 is connected to the cathode of the diode D336, a resistor R430 and a capacitor C430 are connected in series and then connected across the two ends of the diode D336, a capacitor C453, a capacitor C454, a capacitor C455 and a resistor R451 are connected in parallel between the OUT+ end and the SGND end, the OUT+ end is connected to the 4th and 5th pins of TB2, and the SGND is connected to the 1st, 2nd and 3rd pins of TB2.

4. The digitally configured resonant switching power supply according to claim 3, characterized in that: In the output voltage adjustment circuit, the pin 1 of the optocoupler QC700 is connected to the resistor R706 to the OUT+ terminal, the resistor R707 is connected in parallel between the pins 1 and 2 of the optocoupler QC700, the pin 2 of the optocoupler QC700 is connected to the pin 3 of the modulator U700, the pin 2 of the modulator U700 is connected to the SGND terminal, the capacitor C701 and the resistor R705 are connected in series and then bridged between the pins 1 and 3 of the modulator U700, and the pin 1 of the modulator U700 is connected to the resistor R700 to the OUT + terminal, pin 1 of modulator U700 is connected to one end of resistor R704, the other end of resistor R704 is connected to potentiometer VR1 to SGND terminal, pin 1 of optocoupler QC730 is connected to one end of resistor R733, the other end of resistor R733 is connected to the positive electrode of Zener diode Z700, the negative electrode of Zener diode ZD700 is connected to OUT+ terminal, resistor R734 is between pins 1 and 2 of optocoupler QC730, and pin 2 of optocoupler QC730 is connected to SGND terminal.

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