Small-size high-capacity embedded memory structure

Abstract

The utility model discloses a small-size large-capacity embedded memory structure, which relates to the technical field of semiconductor packaging and comprises a substrate, a passive component, a memory controller chip and a flash memory chip stack, and the passive component is connected and fixed on the top surface of the substrate; the storage controller chip is attached to the substrate through a DAF film and is electrically connected with the substrate through a first gold wire. The flash memory chip stacking body is located above the storage controller chip, the flash memory chip stacking body is fixedly connected with the substrate through the DAF film, and according to the scheme, the storage controller chip and the routing thereof are buried in the DAF film between the flash memory chip stacking body and the substrate, so that the storage controller chip and the high-stacking flash memory chip are simultaneously packaged in a limited space; the product has a smaller packaging volume and a higher storage capacity; due to the fact that the distance between the storage controller chip and the flash memory chip is shortened, the higher transmission speed can be achieved, and the overall storage performance is improved.

Description

Technical Field

[0001] The utility model relates to a small-size and large-capacity embedded memory structure, belonging to the technical field of semiconductor packaging. Background Art

[0002] As the market demand for large-capacity storage increases, flash memory chips with larger storage capacity are needed, and the number of stacked layers of flash memory chips also needs to be increased. However, the chip size of large-capacity flash memory is also relatively large. In the traditional solution, the storage controller is arranged adjacent to the flash memory chip. If the size of the flash memory chip becomes larger, it is difficult to place the storage controller and the flash memory chip at the same time without changing the size of the packaged product. At the same time, because the storage controller is arranged adjacent to the flash memory chip and is relatively far away from the flash memory chip, its transmission speed is also affected. However, with the update and iteration of smart devices, we need to develop the finished embedded memory in the direction of smaller size, larger capacity and faster transmission speed. Utility Model Content

[0003] The utility model aims to provide a small-size and large-capacity embedded memory structure in order to overcome the deficiencies of the prior art.

[0004] To achieve the above-mentioned purpose, the technical solution adopted by the utility model is: a small-size, large-capacity embedded memory structure, comprising a substrate, passive components, a storage controller chip and a flash memory chip stack, wherein the passive components are connected and fixed on the top surface of the substrate; the storage controller chip is adhered to the substrate by a DAF film, and is electrically connected to the substrate through a first gold wire; the flash memory chip stack is located above the storage controller chip, and the flash memory chip stack is connected and fixed to the substrate through the DAF film, so that the storage controller chip and the first gold wire are buried in the DAF film between the flash memory chip stack and the substrate, and the flash memory chip stack is electrically connected to the substrate; epoxy resin is arranged above the substrate, and the epoxy resin is used to plasticize the passive components, the storage controller chip and the flash memory chip stack.

[0005] Preferably, the flash memory chip stack comprises a plurality of flash memory chips, the plurality of flash memory chips are stacked in sequence in a stepped shape, and adjacent flash memory chips are connected and fixed by a DAF film.

[0006] Preferably, adjacent flash memory chips are electrically connected via a second gold wire, and each flash memory chip is electrically connected to the substrate via a third gold wire.

[0007] Preferably, lead-free solder paste is provided between the passive component and the substrate, the passive component is connected to the substrate via the lead-free solder paste, and is fixed via reflow soldering.

[0008] Preferably, a plurality of solder balls are arranged on the bottom surface of the substrate.

[0009] Due to the application of the above technical solution, the utility model has the following advantages compared with the prior art:

[0010] (1) By burying the storage controller chip and its bonding wires in the DAF film between the flash memory chip stack and the substrate, the storage controller chip and the high-stacked flash memory chip can be packaged simultaneously in a limited space, making the product have a smaller packaging volume and higher storage capacity.

[0011] (2) Since the distance from the storage controller chip to the flash memory chip is shortened, faster transmission speed can be achieved, improving the overall storage performance.

[0012] (3) The mass production of embedded memory can make terminal smart devices more lightweight and efficient. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The technical solution of the utility model is further described below in conjunction with the accompanying drawings:

[0014] Attached Figure 1 This is a structural schematic diagram of a small-size and large-capacity embedded memory structure described in the utility model;

[0015] Attached Figure 2 This is a structural schematic diagram of step 2 in the processing of the utility model;

[0016] Attached Figure 3 This is a structural schematic diagram of step three in the processing of the utility model;

[0017] Attached Figure 4 This is a structural schematic diagram of step 4 in the processing of the utility model;

[0018] Attached Figure 5 This is a structural schematic diagram of step five in the processing of the utility model;

[0019] Attached Figure 6 This is a structural schematic diagram of step six in the processing of the utility model;

[0020] Attached Figure 7 This is a structural diagram of step seven in the processing of the utility model;

[0021] Attached Figure 8 It is a structural schematic diagram of step eight in the processing process of the utility model;

[0022] Attached Fig. 9 It is a structural schematic diagram of step nine in the processing of the utility model.

[0023] In the figure: 1. substrate; 2. passive components; 3. storage controller chip; 4. DAF film; 5. first gold wire; 6. epoxy resin; 7. flash memory chip; 8. second gold wire; 9. third gold wire; 10. lead-free solder paste; 11. solder ball. DETAILED DESCRIPTION

[0024] The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0025] As attached Figure 1 As shown, a small-size and large-capacity embedded memory structure described in the utility model includes a substrate 1, passive components 2, a storage controller chip 3 and a flash memory chip stack.

[0026] The passive component 2 is connected and fixed on the top surface of the substrate 1, wherein a lead-free solder paste 10 is provided between the passive component 2 and the substrate 1, and the passive component 2 is connected to the substrate 1 through the lead-free solder paste 10 and fixed by reflow soldering.

[0027] The storage controller chip 3 is attached to the substrate 1 by using a DAF film 4, and is electrically connected to the substrate 1 by a first gold wire 5. In this embodiment, the first gold wire 5 is a gold wire with a purity of 99.99%; the flash memory chip stack is located above the storage controller chip 3, and the flash memory chip stack is connected and fixed to the substrate 1 by the DAF film 4, so that the storage controller chip 3 and the first gold wire 5 are buried in the DAF film 4 between the flash memory chip stack and the substrate 1, thereby shortening the transmission distance from the storage controller chip 3 to the flash memory chip stack, achieving a faster transmission speed, and improving the overall storage performance; and the flash memory chip stack is electrically connected to the substrate 1; in this embodiment, the thickness of the DAF film 4 between the flash memory chip stack and the substrate 1 is 120um, and the storage controller chip 3 and the first gold wire 5 are completely buried in the DAF film 4 by using the DAF film buried chip and gold wire buried technology, and the wire arc of the storage controller chip 3 is ensured to be complete, without swinging and collapsing, and the bubbles in the DAF film are driven out by 2.5Kg pressure baking to make it react and solidify thoroughly.

[0028] Epoxy resin 6 is disposed above the substrate 1 , and the epoxy resin 6 is used to encapsulate the passive components 2 , the storage controller chip 3 and the flash memory chip stack.

[0029] The flash memory chip stack includes multiple flash memory chips 7. In this embodiment, the flash memory chip stack has 4 flash memory chips 7. The multiple flash memory chips 7 are stacked in sequence and in a stepped shape. Adjacent flash memory chips 7 are connected and fixed by DAF films 4. Adjacent flash memory chips 7 are electrically connected by second gold wires 8. Each flash memory chip 7 is electrically connected to the substrate 1 by a third gold wire 9. In this embodiment, the first gold wire 5 and the second gold wire 8 are both gold wires with a purity of 99.99%.

[0030] By adopting multi-chip stacking picking and bonding technology, limited by the thickness of the chip as thin as 41um, a special thin chip picking fixture is used to peel the chip from the carrier film through the protrusions of the multi-step platform. Due to the stacking of multiple chips, the chip bonding position and the distance control between chips are particularly important. The introduction of high-precision bonding machines makes it possible to step-like one-time bonding of 4 layers of chips, which can ensure the accuracy of ±15um, effectively reducing the loss of yield and realizing mass production of multi-chip stacking.

[0031] A plurality of solder balls 11 are arranged on the bottom surface of the substrate 1 .

[0032] In this solution, the thickness of the storage controller chip 3 and the flash memory chip 7 are both below 41um. An invisible laser is used to first separate the middle of the chip, then thin it, and finally break the wafer. Since there is no influence of blade cutting, the side edge breaking is better controlled, and at the same time, the internal stress of the chip is smaller, and the chip thickness can be further reduced.

[0033] like Figure 2-9 As shown, the processing process of the memory structure of this scheme is as follows:

[0034] Step 1: Use DAG technology to grind the storage controller chip to 50um, and use sDBG technology to grind the flash memory chip to 41um.

[0035] Step 2: Passive components bonding;

[0036] Passive components are reflowed on the substrate using lead-free solder paste.

[0037] Step 3: Memory controller chip bonding;

[0038] Use ordinary DAF film to bond the storage controller chip to the substrate.

[0039] Step 4: Gold wire bonding of storage controller chip;

[0040] The memory controller chip is interconnected with the substrate using a first gold wire of 99.99% purity.

[0041] Step 5: Attach the first layer of flash memory chips;

[0042] A 120um thick DAF film is used to bond the first layer of flash memory chips, and the storage controller chip and its bonding wires are buried in the DAF film.

[0043] Step 6: Attach the 2nd to 4th layer of flash memory chips;

[0044] Use DAF film to bond the 2nd to 4th layer flash memory chips.

[0045] Step 7: Gold wire bonding of the 1st to 4th layer flash memory chips;

[0046] A second gold wire with a purity of 99.99% is used to interconnect the flash memory chips of the 1st to 4th layers, and a third gold wire with a purity of 99.99% is used to interconnect the flash memory chips of the 1st to 4th layers with the substrate.

[0047] Step 8: Epoxy resin material injection molding;

[0048] The product is encapsulated with epoxy resin material.

[0049] Step 9: Plant the bulb and cut into pieces;

[0050] The solder balls are soldered to the ball planting pads on the back of the substrate; at the same time, the strip level packaged products are cut into unit level particles.

[0051] The small-size, large-capacity embedded memory structure described in this solution is not limited to the embedded memory product category, nor is it limited to the BGA packaging type. The chip grinding thickness and position are not limited, and the type of packaged chip is not limited, thereby improving adaptability.

[0052] The above are only specific application examples of the utility model and do not constitute any limitation to the protection scope of the utility model; any technical solutions formed by equivalent transformation or equivalent replacement shall fall within the protection scope of the utility model.

Claims

1. A small-size, large-capacity embedded memory structure, characterized in that: The invention comprises a substrate (1), a passive component (2), a memory controller chip (3) and a flash memory chip stack, wherein the passive component (2) is connected and fixed on the top surface of the substrate (1); the memory controller chip (3) is attached to the substrate (1) by a DAF film (4) and is electrically connected to the substrate (1) via a first gold wire (5); the flash memory chip stack is located above the memory controller chip (3), the flash memory chip stack is connected and fixed to the substrate (1) via the DAF film (4), the memory controller chip (3) and the first gold wire (5) are buried in the DAF film (4) between the flash memory chip stack and the substrate (1), and the flash memory chip stack is electrically connected to the substrate (1); an epoxy resin (6) is arranged above the substrate (1), and the epoxy resin (6) is used to encapsulate the passive component (2), the memory controller chip (3) and the flash memory chip stack.

2. The small-size, large-capacity embedded memory structure according to claim 1, characterized in that: The flash memory chip stack comprises a plurality of flash memory chips (7), wherein the plurality of flash memory chips (7) are stacked in sequence and in a stepped shape, and adjacent flash memory chips (7) are connected and fixed via a DAF film (4).

3. The small-size and large-capacity embedded memory structure according to claim 2, characterized in that: Adjacent flash memory chips (7) are electrically connected via a second gold wire (8), and each flash memory chip (7) is electrically connected to the substrate (1) via a third gold wire (9).

4. The small-size and large-capacity embedded memory structure according to claim 1, characterized in that: A lead-free solder paste (10) is provided between the passive component (2) and the substrate (1); the passive component (2) is connected to the substrate (1) via the lead-free solder paste (10) and is fixed via reflow soldering.

5. The small-size and large-capacity embedded memory structure according to claim 1, characterized in that: A plurality of solder balls (11) are arranged on the bottom surface of the substrate (1).

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