High-reliability single-CPU control protection device

Abstract

The utility model discloses a high-reliability single-CPU control protection device. An existing single-CPU control protection device cannot timely and effectively discover abnormity or faults of the working state of a CPU. The device comprises a CPU (7) and a power supply (8), the positive electrode end of the power supply is respectively connected to a coil (4) of a power-on time-delay closing relay and a coil (6) of a power-off time-delay closing relay, and the coil of the power-on time-delay closing relay and the coil of the power-off time-delay closing relay are connected in parallel and then connected to the DQ end of the CPU; the input connecting wire (1) is respectively connected to a power-on time-delay closing node (3) of the power-on time-delay closing relay and a power-off time-delay closing node (5) of the power-off time-delay closing relay, and the output ends of the power-on time-delay closing node of the power-on time-delay closing relay and the power-off time-delay closing node of the power-off time-delay closing relay are connected in parallel and then connected to the output connecting wire (2). The single-CPU control protection circuit is used for single-CPU control protection.

Description

Technical Field

[0001] The utility model relates to a high-reliability single-CPU control protection device. Background Art

[0002] The existing single-CPU control protection device is widely used and has high reliability. However, compared with the dual-CPU control protection system, it lacks monitoring of the status of the main working CPU and cannot effectively detect abnormalities or failures in the CPU working status in a timely manner, resulting in serious consequences such as failure of the control protection system due to CPU failure and no alarm. Utility Model Content

[0003] The purpose of the utility model is to make up for the deficiencies of the prior art and provide a high-reliability single CPU control protection device.

[0004] The above purpose is achieved through the following technical solutions:

[0005] A high-reliability single CPU control protection device, comprising: a CPU and a power supply, wherein the positive terminal of the power supply is respectively connected to the coil of a power-on delay closing relay and the coil of a power-off delay closing relay, and the output ends of the power-on delay closing relay and the coil of the power-off delay closing relay are connected in parallel to the DQ terminal of a PLC;

[0006] The input wiring is respectively connected to the power-on delay closing node of the power-on delay closing relay and the power-off delay closing node of the power-off delay closing relay, and the output ends of the power-on delay closing node of the power-on delay closing relay and the power-off delay closing node of the power-off delay closing relay are connected in parallel to the output wiring.

[0007] The high-reliability single-CPU control protection device, the input wiring is connected to the user power supply terminal.

[0008] The high-reliability single-CPU control protection device, the output wiring is connected to the user signal or control loop. Beneficial Effects

[0009] 1. The utility model uses a single CPU control protection device to achieve all control and protection functions, effectively reducing equipment manufacturing and procurement costs, and can promptly issue an alarm when a serious fault such as hardware or software failure or power failure, CPU crash, etc. occurs in the CPU.

[0010] 2. The utility model uses two external low-cost delay relays to effectively solve the problem that a single CPU cannot self-check whether it is working normally.

[0011] 3. This protection device monitors the CPU working status through external hard-wired logic, can resist equipment anomalies caused by high-tech intrusions such as computer viruses, and has high reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Attached Figure 1 It is a circuit diagram of the utility model;

[0013] In the figure: 1. Input wiring; 2. Output wiring; 3. Power-on delay closing node of the power-on delay closing relay; 4. Coil of the power-on delay closing relay; 5. Power-off delay closing node of the power-off delay closing relay; 6. Coil of the power-off delay closing relay; 7. CPU; 8. Power supply. DETAILED DESCRIPTION

[0014] Reference Figure 1 , a high reliability single CPU control protection device, comprising: a CPU, part number: 7 and a power supply 8, wherein the positive terminal of the power supply is respectively connected to the coil 4 of the power-on delay closing relay and the coil 6 of the power-off delay closing relay, and the output ends of the coil of the power-on delay closing relay and the coil of the power-off delay closing relay are connected in parallel to the DQ terminal of the CPU;

[0015] The input wiring 1 is respectively connected to the power-on delay closing node 3 of the power-on delay closing relay and the power-off delay closing node 5 of the power-off delay closing relay, and the power-on delay closing node of the power-on delay closing relay and the power-off delay closing node of the power-off delay closing relay are connected in parallel to the output wiring 2.

[0016] The high-reliability single-CPU control protection device, the input wiring is connected to the user power supply terminal.

[0017] The high-reliability single-CPU control protection device, the output wiring is connected to the user signal or control loop.

[0018] This device is suitable for single CPU control protection device or equipment control system design with CPU reliability requirements not higher than Class I load.

[0019] The working principle of the high-reliability single-CPU protection device is: use a single CPU to realize all the functions of control protection. In this control protection function, a non-redundant detection channel design or a redundant protection signal detection channel design can be used according to the actual use. The specific working principle of the protection device is written according to the original logic principle to realize the control protection function program, but two independent control programs should be added at the end of the control protection program. The task of one of the programs is to output a pulse signal with a duty cycle of 1 and a period adjustable from 1 to 4S from the output port specified by the CPU. This output signal is connected to a delay relay with two coils in parallel. The contacts of these two delay relays are pressed according to Figure 1 The schematic wiring diagram is shown and output to the outside; the task of another program is to periodically detect the hardware and software fault signals inside the CPU, and turn off the pulse signal of the specified output port when a fault signal that affects the normal operation of the CPU appears. The output signals of the two delay relays are connected in parallel through hard wiring or output OUT after logic, and an alarm is given to the outside or an emergency processing procedure is started to remind the staff to deal with the protection device failure in time to prevent the control protection system from malfunctioning and no alarm prompt after CPU failure or power failure.

[0020] The single CPU control protection device has all control protection functions; the CPU power supply has no clear requirements, and can be AC ​​or DC according to the specific CPU requirements; the CPU has two independent control protection programs in addition to the normal control protection program. The task of one control program is that during normal operation, the CPU outputs a pulse signal with a duty cycle of 1 and a period adjustable within 1 to 4S to the designated output port. This output signal is connected to a delay relay with two coils in parallel, one of which is a power-on delay type delay relay, and the other is a power-off delay type relay. The power-off delay relay also serves as the CPU power monitoring alarm relay. The contacts of these two delay relays are connected in parallel and then output to the outside; the task of another program is to periodically detect the hardware and software fault signals inside the CPU control protection device, and when there is a fault signal that affects the normal operation of the CPU, the pulse signal of the designated output port is closed, and the external power-off delay relay is activated to output the alarm signal.

[0021] The shortest delay time of these two delay relays is greater than or equal to twice the maximum scanning cycle of the CPU; the maximum delay time is limited to the shortest allowable alarm time designed by the control protection device. The delay of 1 to 4 seconds is an engineering experience value.

Claims

1. A high reliability single CPU control protection device, comprising: The CPU and power supply are characterized in that: the positive terminal of the power supply is respectively connected to the coil of the power-on delay closing relay and the coil of the power-off delay closing relay, and the output ends of the power-on delay closing relay and the coil of the power-off delay closing relay are connected in parallel to the DQ terminal of the PLC; The input wiring is respectively connected to the power-on delay closing node of the power-on delay closing relay and the power-off delay closing node of the power-off delay closing relay, and the output ends of the power-on delay closing node of the power-on delay closing relay and the power-off delay closing node of the power-off delay closing relay are connected in parallel to the output wiring.

2. The high reliability single CPU control protection device according to claim 1 is characterized in that: The input wiring is connected to the user power supply terminal.

3. The high reliability single CPU control protection device according to claim 2 is characterized in that: The output wiring is connected to the user signal or control loop.

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