Back contact battery and photovoltaic module

By forming a tower base on the surface of the silicon wafer and combining the tunneling oxide layer and doped polysilicon layer, the concave and convex structure on the surface of the silicon wafer is optimized, which solves the problem of low conversion efficiency of the back contact battery and achieves a more efficient tunneling oxide layer Growth and battery performance improvements.

CN222339924UActive Publication Date: 2025-01-10嘉兴阿特斯阳光能源科技有限公司
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Patent Information

Application Number
CN202323663880.4
Authority / Receiving Office
CN · China
Patent Type
Utility models(China)
Current Assignee / Owner
Filing Date
2023-12-29
Publication Date
2025-01-10
Estimated Expiration
2033-12-29

AI Technical Summary

Technical Problem

In the prior art, there are few researches on the polishing surface of the first electrode region of the back contact battery, which affects the passivation effect of the tunneled oxide layer and leads to a low conversion efficiency.

Method used

By forming a tower base on the surface of the silicon wafer, defining its Zeta size is between 20μm and 50μm, combining the design of the tunneling oxide layer and the doped polysilicon layer, the concave and convex structure on the surface of the silicon wafer is optimized, and the passivation effect of the tunneling oxide layer is improved. and current and voltage performance.

Benefits of technology

It achieves better tunneling oxide layer growth effect and battery efficiency, and improves the conversion efficiency and performance of back contact batteries.

✦ Generated by Eureka AI based on patent content.

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Abstract

The utility model discloses a back contact cell and a photovoltaic assembly, the back contact cell comprises a silicon wafer, the silicon wafer comprises a silicon wafer body and a tower footing formed on the surface of the silicon wafer body, the Zeta size of the tower footing is d1, and the d1 satisfies the following conditions: 20 [mu] m < = d1 < = 50 [mu] m; the tunneling oxide layer is arranged on the surface of one side of the silicon wafer in the thickness direction; and the tunneling doped polycrystalline silicon layer is arranged on one side, far away from the silicon wafer, of the tunneling oxide layer in the thickness direction. According to the back contact cell provided by the utility model, through limiting the Zeta size of the tower footing on the surface of the silicon wafer body, contribution of trap auxiliary tunneling to transmission of microscopic particles such as electrons is facilitated, growth of a tunneling oxide layer is facilitated to obtain a better passivation effect, and tunneling is also facilitated.
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Description

Technical Field

[0001] The utility model relates to the technical field of photovoltaic cells, in particular to a back contact cell and a photovoltaic component. Background Art

[0002] In the prior art, the polished surface of the first electrode region of the back contact (XBC, XBC also includes TBC, HBC, or HTBC) battery is the substrate for growing the tunneling oxide layer, and the quality of the substrate plays a crucial role in the subsequent passivation effect and tunneling contact. However, there are relatively few studies on the polished surface, and the existing research is basically a conventional polishing process. Utility Model Content

[0003] The utility model aims to solve at least one of the technical problems existing in the prior art. To this end, one purpose of the utility model is to provide a back contact battery with high conversion efficiency.

[0004] Another object of the present invention is to provide a photovoltaic module.

[0005] According to an embodiment of the first aspect of the utility model, the utility model provides a back-contact battery, comprising: a silicon wafer, the silicon wafer comprising a silicon wafer body and a tower base formed on the surface of the silicon wafer body, the Zeta size of the tower base is d1, wherein the d1 satisfies: 20μm≤d1≤50μm; a tunneling oxide layer, the tunneling oxide layer is arranged on one side surface of the silicon wafer in the thickness direction; a tunneling doped polysilicon layer, the tunneling doped polysilicon layer is arranged on the side of the tunneling oxide layer in the thickness direction away from the silicon wafer.

[0006] According to the back contact battery of the utility model, by limiting the Zeta size of the tower base on the surface of the silicon wafer body, the surface of the silicon wafer body has certain bumps and depressions. In this way, the contact interface between the silicon wafer and the tunneling oxide layer has a suitable defect state density, which is conducive to the contribution of trap-assisted tunneling to the transmission of microscopic particles such as electrons. The defect state density surface is more convenient for the passivation of the poly-Si layer to the substrate with a relatively regular and orderly surface. It is not only conducive to the growth of the tunneling oxide layer to obtain a better passivation effect, but also has a certain defect structure, which is more conducive to tunneling. In addition, it is found through experiments that when the Zeta size of the tower base is between 20μm and 50μm, the back contact battery of the specific embodiment of the utility model will show a better current and voltage relationship (IV) performance.

[0007] According to some embodiments of the present invention, the d1 further satisfies: 25 μm≤d1≤35 μm.

[0008] According to some embodiments of the present invention, the silicon wafer is an N-type silicon wafer.

[0009] According to some embodiments of the present invention, the resistivity of the silicon wafer is 0.5Ω / cm 2 ~3Ω / cm 2 .

[0010] According to some embodiments of the present invention, the thickness of the silicon wafer is d2, wherein d2 satisfies: 100 μm≤d2≤150 μm.

[0011] According to some embodiments of the present invention, the tower base is formed by etching the silicon wafer body.

[0012] According to some embodiments of the utility model, the tower base is formed by etching the silicon wafer with an etching solution.

[0013] According to some embodiments of the present invention, the etching solution is an alcohol solution of KOH, an alcohol solution of NaOH, or an alcohol solution of tetramethylammonium hydroxide.

[0014] According to some embodiments of the present invention, the EFF of the back contact battery is ≥25.95%.

[0015] According to an embodiment of the second aspect of the utility model, the utility model provides a photovoltaic component, including: a back contact cell according to the embodiment of the first aspect of the utility model.

[0016] Additional aspects and advantages of the present invention will be given in part in the following description, and in part will become apparent from the following description, or will be learned through the practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0018] Figure 1 is a SEM image of a silicon wafer of a back contact battery according to an embodiment of the utility model;

[0019] Figure 2 According to the utility model Figure 1 Statistical diagram of the tower base in section A of the silicon wafer of the back contact battery.

[0020] Reference numerals:

[0021] 1: Silicon wafer;

[0022] 11: Silicon wafer body; 12: Tower base. DETAILED DESCRIPTION

[0023] The embodiments of the present invention are described in detail below. The embodiments described with reference to the accompanying drawings are exemplary. Figure 1-Figure 2A back contact battery according to a specific embodiment of the present invention is described.

[0024] The back contact cell of the specific embodiment of the utility model comprises: a silicon wafer 1, a tunneling oxide layer (not shown) and a tunneling doped polysilicon layer (not shown). The tunneling oxide layer is arranged on one side surface of the silicon wafer 1 in the thickness direction, and the tunneling doped polysilicon layer is arranged on the side of the tunneling oxide layer in the thickness direction away from the silicon wafer 1.

[0025] In addition, if Figure 1 As shown, the silicon wafer 1 includes a silicon wafer body 11 and a tower base 12 formed on the surface of the silicon wafer body 11, Figure 2 , the Zeta size of the tower base 12 is d1, where d1 satisfies: 20μm≤d1≤50μm. In this way, if d1 is less than 20μm, the Zeta size of the tower base 12 is small, the surface of the silicon wafer body 11 is relatively flat, and it is easy to grow epitaxially to obtain a crystallized layer, thereby affecting the passivation effect of the tunneling oxide layer and the doped polysilicon layer; if d1 is greater than 50μm, the Zeta size of the tower base 12 is large, and the surface of the silicon wafer body 11 is uneven, which may cause the battery efficiency to decrease. By setting so that d1 satisfies 20μm≤d1≤50μm, the Zeta size of the tower base 12 is appropriate, and the surface of the silicon wafer body 11 is appropriate, which is conducive to improving the tunneling effect and passivation effect of the tunneling oxide layer and the tunneling doped polysilicon layer, thereby improving the efficiency of the battery.

[0026] The Zeta size of the surface of the silicon wafer body 11 is measured by the following method:

[0027] 1. Use a 3D laser microscope (SEM) to photograph the surface of the silicon wafer 1 after texturing, and the magnification is required to be 500K. Figure 1 As shown;

[0028] 2. Use ImageJ software to process the SEM image obtained in the first step to obtain the shape parameters of a single pyramid base 12 (including two diagonals); select the longest value to define it as the pyramid Zeta size; Figure 2 As shown;

[0029] 3. Fit the size data obtained in the second step through the Gaussian equation to obtain the pyramid size and its half-height width.

[0030] According to the back contact battery of the specific embodiment of the utility model, by limiting the Zeta size of the tower base 12 on the surface of the silicon wafer body 11, the surface of the silicon wafer body 11 has certain bumps and depressions. In this way, the contact interface between the silicon wafer 1 and the tunneling oxide layer has a suitable defect state density, which is conducive to the contribution of trap-assisted tunneling to the transmission of microscopic particles such as electrons, and the relatively regular and orderly surface, the defect state density surface is more convenient for the passivation of the poly-Si layer to the substrate, which is not only conducive to the growth of the tunneling oxide layer to obtain a better passivation effect, but also has a certain defect structure, which is also more conducive to tunneling. In addition, it is found through experiments that when the Zeta size of the tower base 12 is between 20μm and 50μm, the back contact battery of the specific embodiment of the utility model will show a better current and voltage relationship (IV) performance.

[0031] According to some embodiments of the present invention, d1 further satisfies: 25 μm ≤ d1 ≤ 35 μm. With this arrangement, the Zeta size of the tower base 12 is more appropriate, and the surface concavoconvexity of the silicon wafer body 11 is more appropriate, which is conducive to improving the tunneling effect and passivation effect of the tunneling oxide layer and the tunneling doped polysilicon layer, thereby improving the efficiency of the battery.

[0032] According to some embodiments of the present invention, the silicon wafer 1 is an N-type silicon wafer. In this way, the performance of the N-type silicon wafer is more suitable for etching and forming the tower base 12 on the surface.

[0033] According to some embodiments of the present invention, the resistivity of the silicon wafer 1 is 0.5Ω / cm 2 ~3Ω / cm 2 By setting the resistivity of the silicon wafer 1 appropriately, the lifetime of minority carriers (microscopic particles such as electrons) is longer, the photoelectric conversion efficiency is higher, and the cost is relatively low.

[0034] According to some embodiments of the utility model, the thickness of the silicon wafer 1 is d2, wherein d2 satisfies: 100μm≤d2≤150μm. In this way, if d2 is less than 100μm, the thickness of the silicon wafer 1 is small. After the tower base 12 is formed on the surface of the silicon wafer body 11, the thickness of the silicon wafer body 11 is small, which may make the silicon wafer 1 easy to break, and the safety of the back contact battery is low; if d2 is greater than 150μm, the thickness of the silicon wafer 1 is large, resulting in a waste of resources. By setting, d2 satisfies 100μm≤d2≤150μm, the thickness of the silicon wafer 1 is appropriate, the safety of the back contact battery is good, and the production cost is low.

[0035] According to some embodiments of the present invention, the tower base 12 is formed by etching the silicon wafer 1. Such a configuration facilitates the use of anisotropic etching of the single crystal silicon in the silicon wafer 1 to etch the tower base 12 on the surface of the silicon wafer body 11.

[0036] According to some embodiments of the present invention, the tower base 12 is formed by etching the silicon wafer 1 with an etching solution. In this way, the silicon wafer 1 is etched with an etching solution to form the tower base 12 on the surface of the silicon wafer body 11, which is convenient for operation.

[0037] According to some embodiments of the utility model, the etching solution is an alcohol solution of KOH or an alcohol solution of NaOH or an alcohol solution of tetramethylammonium hydroxide. In this way, the method of adding KOH or NaOH or tetramethylammonium hydroxide (TMAH) to alcohol has good etching effect and is easy to operate.

[0038] Specifically, the preparation process of the back contact battery of the specific embodiment of the utility model includes the following steps:

[0039] 1. Silicon wafer 1: Use N-type silicon wafer with a resistivity of 0.5-3Ω.cm, a thickness of 100-150μm, and a size of 182*91mm;

[0040] 2. Cleaning and texturing: First, use a 5% diluted HF solution to remove the surface oxide layer, and use KOH or NaOH or tetramethylammonium hydroxide (TMAH) plus alcohol to etch the tower base 12 on the surface of the silicon wafer body 11 by anisotropic etching of single crystal silicon. Optionally, the etching temperature is 80°C ± 20°C, but is not limited thereto.

[0041] That is, the process of polishing the silicon wafer 1 (battery) (forming the tower base 12) generally includes the steps of pre-cleaning, removing the damaged layer, polishing, post-cleaning, and drying.

[0042] Texturing method: The specific embodiment of the utility model includes: a damage layer removal step (SDE), the silicon wafer 1 is etched to a thickness of 2μm to 5μm, preferably 3μm to 4μm, the concentration of the alcohol solution of KOH in the solution of the specific embodiment of the utility model is 4% to 10%, and the SDE time in the specific embodiment of the utility model is 100 to 140s. The conventional SDE time is 160 to 200s. After SDE, a smooth pyramid base 12 plane is formed. The structural features of the back contact battery of the specific embodiment of the utility model include: after the overall texturing step is completed, the base 12 Zeta size is obtained to be 20-50μm, preferably 25-35μm.

[0043] In this way, the velvet size of the back contact battery prepared according to the specific embodiment of the utility model is reduced, the reflectivity is further reduced, the passivation is slightly increased, and the battery efficiency is high.

[0044] According to some embodiments of the present invention, the EFF of the back contact battery is ≥ 25.95%. Thus, the efficiency of the back contact battery of the specific embodiment of the present invention is high.

[0045] The following is a specific example to illustrate the effect of the size of the tower base 12 Zeta (other parameters are assumed to be the same) on the performance of the back contact battery of the specific embodiment of the utility model, including: battery efficiency (EFF), short circuit current (Isc (A)), fill factor (FF), open circuit voltage (VOC).

[0046] Table 1. Tower base 12 Zeta dimensions and battery performance for Examples 1 to 3

[0047]

[0048]

[0049] It can be seen from Table 1 that when Zeta is within the optimal range, the back contact battery of the specific embodiment of the utility model has the highest conversion efficiency. When the Zeta size is too low, the back contact battery has the optimal FF, but the Voc is low. When the Zeta size is too high, the back contact battery has the optimal Voc, but the FF is low.

[0050] According to an embodiment of the second aspect of the utility model, the utility model provides a photovoltaic component, including a back contact cell according to an embodiment of the first aspect of the utility model.

[0051] The photovoltaic module according to the specific embodiment of the utility model has high photoelectric conversion efficiency.

[0052] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the utility model. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example.

[0053] Although the embodiments of the present invention have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the claims and their equivalents.

Claims

1. A back contact battery, characterized in that: include: A silicon wafer, comprising a silicon wafer body and a tower base formed on a surface of the silicon wafer body, wherein a Zeta size of the tower base is d1, wherein d1 satisfies: 20 μm≤d1≤50 μm; A tunneling oxide layer, the tunneling oxide layer being disposed on one side surface of the silicon wafer in a thickness direction; A tunneling doped polysilicon layer is provided on a side of the tunneling oxide layer away from the silicon wafer in a thickness direction of the tunneling oxide layer.

2. The back contact cell according to claim 1, characterized in that: The d1 further satisfies: 25 μm≤d1≤35 μm.

3. The back contact battery according to claim 1, characterized in that: The silicon wafer is an N-type silicon wafer.

4. The back contact cell according to claim 1, characterized in that: The resistivity of the silicon wafer is 0.5Ω / cm 2 ~3Ω / cm 2 .

5. The back contact cell according to claim 1, characterized in that: The thickness of the silicon wafer is d2, wherein d2 satisfies: 100 μm≤d2≤150 μm.

6. The back contact cell according to claim 1, characterized in that: The tower base is formed by etching the silicon wafer body.

7. The back contact cell according to claim 1, characterized in that: The tower base is formed by etching the silicon wafer with an etching solution.

8. The back contact battery according to claim 7, characterized in that: The etching solution is an alcohol solution of KOH, an alcohol solution of NaOH, or an alcohol solution of tetramethylammonium hydroxide.

9. The back contact cell according to any one of claims 1 to 8, characterized in that The EFF of the back contact cell is ≥ 25.95%.

10. A photovoltaic module, characterized in that: Comprising a back contact cell according to any one of claims 1-9.