Control circuit, battery management system, distribution box, battery pack and electric energy equipment

Abstract

The utility model discloses a control circuit, a battery management system, a distribution box, a battery pack and electric energy equipment. The control circuit comprises a latch circuit, a first signal unit, a delay circuit and a second signal unit. The first signal unit is electrically connected with the latch circuit and is used for determining a working signal and a reset signal; the time delay circuit is electrically connected with the latch circuit; the second signal unit is electrically connected with the time delay circuit and is used for outputting a first enable signal for switching on the control switch and a second enable signal for switching off the control switch; when the first signal unit determines the working signal, the latch circuit inputs a first preset signal to the time delay circuit, so that the time delay circuit controls the second signal unit to output a first enable signal; and when the first signal unit determines the reset signal, the latch circuit inputs a second preset signal to the time delay circuit, so that the time delay circuit controls the second signal unit to output a second enable signal after a preset duration.

Description

Technical Field

[0001] The present application relates to the field of electricity, and more specifically to a control circuit, a battery management system, a distribution box, a battery pack and an electric energy device. Background Art

[0002] During the use of electric vehicles, energy is stored by charging the battery, and the battery car is driven by discharging the battery. When the main control chip of the battery is stuck, it can be restarted by inputting a hard-wire reset signal. In the related art, when the control switch of the battery is turned on and working, if the main control chip is stuck and reset, the control switch of the battery cannot be disconnected, which reduces the safety of the battery. Utility Model Content

[0003] The utility model is proposed to solve at least one of the above problems. According to the first aspect of the present application, a control circuit for controlling a control switch of a battery is provided, the control circuit comprising: a latch circuit, a first signal unit, a delay circuit and a second signal unit; wherein the first signal unit is electrically connected to the latch circuit, and the first signal unit is used to input a working signal and a reset signal; the delay circuit is electrically connected to the latch circuit; the second signal unit is electrically connected to the delay circuit, and the second signal unit is used to output a first enable signal for turning on the control switch and a second enable signal for turning off the control switch; wherein, when the first signal unit determines the working signal, the latch circuit inputs a first preset signal to the delay circuit, so that the delay circuit controls the second signal unit to output the first enable signal; when the first signal unit determines the reset signal, the latch circuit inputs a second preset signal to the delay circuit, so that the delay circuit controls the second signal unit to output the second enable signal after a preset time.

[0004] In one embodiment of the present application, the control circuit further includes: an unlocking circuit and a third signal unit; wherein the unlocking circuit is electrically connected to the latching circuit; the third signal unit is electrically connected to the unlocking circuit, and the third signal unit is used to determine a latching signal and an unlocking signal; wherein, when the first signal unit determines the working signal and the third signal unit determines the unlocking signal, the latching circuit inputs the first preset signal to the delay circuit; when the first signal unit determines the reset signal and the third signal unit determines the latching signal, the latching circuit inputs the second preset signal to the delay circuit.

[0005] In one embodiment of the present application, the working signal is a high-level signal, and the reset signal is a PWM wave signal alternating between high and low levels; when the first signal unit inputs a low level in the reset signal and the third signal unit determines the latch signal, the latch circuit inputs the second preset signal to the delay circuit; when the first signal unit inputs a high level in the reset signal and the third signal unit determines the latch signal, the latch circuit maintains inputting the second preset signal to the delay circuit.

[0006] In one embodiment of the present application, the unlock signal is a high-level signal, and the latch signal is a high-impedance signal.

[0007] In one embodiment of the present application, the first preset signal is a high level signal, and the second preset signal is a low level signal.

[0008] In one embodiment of the present application, the latch circuit includes: a first output terminal, a first switch and a second switch; wherein the first output terminal is electrically connected to the delay circuit, and the first output terminal is also electrically connected to the reference voltage terminal; the first end of the second switch is electrically connected to the control end of the first switch and the first output terminal, and the second end of the second switch is electrically connected to the ground terminal; the control end of the second switch is electrically connected to the second end of the first switch; wherein the control end of the second switch is also electrically connected to the first signal unit and the unlocking circuit; when the first signal unit determines the working signal and the third signal unit determines the unlocking signal, the second switch is disconnected, the first switch is disconnected, and the first output terminal outputs the first preset signal; when the first signal unit determines the reset signal and the third signal unit determines the latch signal, the second switch is turned on, the first switch is turned on, and the first output terminal outputs the second preset signal.

[0009] In one embodiment of the present application, the first switch is a PMOS switch tube or an NPN transistor, and the second switch is an NMOS switch tube or a PNP transistor.

[0010] In one embodiment of the present application, the latch circuit also includes: a first resistor, a second resistor and a third resistor; wherein the first end of the first resistor is electrically connected to the reference voltage end, and the second end of the first resistor is electrically connected to the first output end; the control end of the first switch is also electrically connected to the second end of the first resistor; the first end of the second switch is also electrically connected to the first end of the first resistor; the second resistor and the third resistor are connected in series, and the control end of the second switch is electrically connected to the connection node between the second resistor and the third resistor; the first end of the second resistor is electrically connected to the second end of the first switch, and the second end of the second resistor is electrically connected to the connection node; the first end of the third resistor is electrically connected to the connection node, and the second end of the third resistor is electrically connected to the ground end; the connection node is electrically connected to the first signal unit and the unlocking circuit.

[0011] In one embodiment of the present application, the latch circuit further includes: a first input terminal, a third switch and a diode; wherein the first input terminal is electrically connected to the first signal unit; the first terminal of the third switch is electrically connected to the reference voltage terminal, the second terminal of the third switch is electrically connected to the ground terminal, and the control terminal of the third switch is electrically connected to the first input terminal; the anode of the diode is electrically connected to the reference voltage terminal and the first terminal of the third switch, and the cathode of the diode is electrically connected to the connection node; wherein, when the first signal unit inputs a low level in the reset signal and the third signal unit determines the latch signal, the third switch is disconnected to turn on the second switch and turn on the first switch; when the first signal unit inputs a high level in the reset signal and the third signal unit determines the latch signal, the diode maintains the second switch and the first switch turned on.

[0012] In one embodiment of the present application, the latch circuit also includes: a fourth resistor, a fifth resistor and a sixth resistor; wherein the first end of the fourth resistor is electrically connected to the reference voltage end, and the second end of the fourth resistor is electrically connected to the first end of the third switch and the positive electrode of the diode; the first end of the fifth resistor is electrically connected to the first input end, the second end of the fifth resistor is electrically connected to the control end of the third switch and the first end of the sixth resistor, and the second end of the sixth resistor is electrically connected to the ground end.

[0013] In one embodiment of the present application, the third switch is an NMOS switch tube or a PNP transistor.

[0014] In one embodiment of the present application, the unlocking circuit includes: a second input terminal, a second output terminal, and a fourth switch; wherein the second input terminal is electrically connected to the third signal unit; the second output terminal is electrically connected to the cathode of the diode and the connection node; the first terminal of the fourth switch is electrically connected to the second output terminal, the second terminal of the fourth switch is electrically connected to the ground terminal, and the control terminal of the fourth switch is electrically connected to the second input terminal; wherein, when the first signal unit determines the working signal and the third signal unit determines the unlocking signal, the third switch is disconnected and the fourth switch is turned on, so that the second switch is disconnected and the first switch is disconnected; when the first signal unit inputs a low level in the reset signal and the third signal unit determines the latch signal, the third switch is disconnected and the fourth switch is disconnected, so that the second switch is turned on and the first switch is turned on; when the first signal unit inputs a high level in the reset signal and the third signal unit determines the latch signal, the fourth switch is disconnected and the diode maintains the second switch and the first switch turned on.

[0015] In one embodiment of the present application, the fourth switch is an NMOS switch tube or a PNP transistor.

[0016] In one embodiment of the present application, the unlocking circuit includes: a seventh resistor and an eighth resistor, the first end of the seventh resistor is electrically connected to the second input end, the second end of the seventh resistor is electrically connected to the control end of the fourth switch and the first end of the eighth resistor, and the second end of the eighth resistor is electrically connected to the ground end.

[0017] In one embodiment of the present application, at least one of the first signal unit, the second signal unit and the third signal unit is a pin.

[0018] According to a second aspect of the present application, a battery management system is further provided, the battery management system comprising: any one of the control circuits described above for controlling a control switch of a battery.

[0019] According to a third aspect of the present application, a distribution box is also provided, and the distribution box includes: any one of the battery management systems described above.

[0020] According to the fourth aspect of the present application, a battery pack is also provided, which includes: a battery, a control switch, a main control chip, a driving chip and any one of the above-mentioned distribution boxes; wherein the control switch is used to control the battery; the main control chip has a fourth signal unit; wherein the fourth signal unit is electrically connected to the first signal unit to input the working signal and the reset signal to the first signal unit; the driving chip is electrically connected to the control switch and the second signal unit, and the driving chip is used to: control the control switch to be turned on according to the first enable signal output by the second signal unit, and control the control switch to be turned off according to the second enable signal output by the second signal unit.

[0021] In one embodiment of the present application, the main control chip further has a fifth signal unit, and the fifth signal unit is used to electrically connect to the third signal unit in the control circuit to input a latch signal and an unlock signal to the third signal unit.

[0022] According to the fifth aspect of the present application, an electric energy device is also provided, and the vehicle includes: a control circuit for controlling a control switch of a battery as described in any one of the above, a battery management system as described in any one of the above, a distribution box as described in any one of the above, or a battery pack as described in any one of the above.

[0023] According to the control circuit, battery management system, distribution box, battery pack and electric energy equipment provided by the present application, a latch circuit is set between the delay circuit and the first signal unit; when the first signal unit determines the working signal, the latch circuit inputs the first preset signal to the delay circuit, so that the delay circuit controls the third signal unit to output the first enable signal, thereby turning on the control switch and the battery works; when the first signal unit determines the reset signal, the latch circuit inputs the second preset signal to the delay circuit, so that the delay circuit controls the second signal unit to output the second enable signal after a preset time, thereby turning off the control switch and stopping the battery from working. Compared with the related art, in the process of the first signal unit determining the reset signal, the present application can keep the latch state of the second preset signal input to the delay circuit unchanged through the latch circuit, so as to control the second signal unit to delay the output of the second enable signal through the delay circuit, so as to turn off the control switch, thereby preventing the situation where the control switch cannot be turned off due to the reset signal input by the first signal unit, thereby improving the safety of the battery. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present utility model. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0025] Figure 1 A schematic block diagram of a battery control circuit according to an embodiment of the present utility model;

[0026] Figure 2 A schematic block diagram of a battery control circuit according to another embodiment of the present utility model;

[0027] Figure 3 The present invention is a schematic diagram of a control circuit of a battery according to an embodiment of the present invention. DETAILED DESCRIPTION

[0028] In order to make the purpose, technical solution and advantages of the utility model more obvious, the exemplary embodiments according to the utility model will be described in detail with reference to the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the utility model, rather than all the embodiments of the utility model, and it should be understood that the utility model is not limited to the exemplary embodiments described here. Based on the embodiments of the utility model described in the utility model, all other embodiments obtained by those skilled in the art without creative work should fall within the protection scope of the utility model.

[0029] In the following description, a large number of specific details are given to provide a more thorough understanding of the utility model. However, it is obvious to those skilled in the art that the utility model can be implemented without one or more of these details. In other examples, in order to avoid confusion with the utility model, some technical features known in the art are not described.

[0030] It should be understood that the utility model can be implemented in different forms and should not be interpreted as being limited to the embodiments proposed herein. On the contrary, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the utility model to those skilled in the art.

[0031] In order to thoroughly understand the present invention, a detailed structure will be presented in the following description to illustrate the technical solution proposed by the present invention. The optional embodiments of the present invention are described in detail below, but in addition to these detailed descriptions, the present invention may also have other implementations.

[0032] In conjunction with the accompanying drawings, some embodiments of the present invention are described in detail below. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0033] Regardless of whether the power battery is in the charging or discharging process, when the main control MCU (Microcontroller Unit, microcontroller, the main control chip in the BMS, monitors and processes the information of each functional module of the BMS, and plays a role of central control) of the BMS (Battery Management System, a management system for lithium batteries of electric vehicles, which monitors and manages the status of the vehicle battery and ensures the safety of the vehicle) is in a continuous stuck state, the main control chip will reset by outputting a PWM wave signal with alternating high and low levels. In the related art, when the control switch of the battery is turned on and working, if the main control chip is stuck and reset, when the main control chip outputs a low level in the PWM wave signal with alternating high and low levels, the enable signal that enables the control switch to be disconnected will be outputted through a delay circuit; and when the main control chip outputs a high level in the PWM wave signal with alternating high and low levels, the enable signal that enables the control switch to be turned on will be immediately outputted through the delay circuit. Since the reset signal is a PWM wave signal with alternating high and low levels, if the duration of the low level signal is less than the delay output duration of the delay circuit, the battery control switch cannot be disconnected, reducing the safety of the battery. The above technical problems existing in the related art can be solved by the technical solutions shown in some embodiments of the present application.

[0034] The present application embodiment provides a battery control circuit, referring to Figure 1 The control circuit includes: a latch circuit, a first signal unit, a delay circuit and a second signal unit; wherein the first signal unit is electrically connected to the latch circuit, and the first signal unit is used to determine the working signal and the reset signal; the delay circuit is electrically connected to the latch circuit; the second signal unit is electrically connected to the delay circuit, and the second signal unit is used to output a first enable signal for turning on the control switch and a second enable signal for turning off the control switch; wherein, when the first signal unit determines the working signal, the latch circuit inputs a first preset signal to the delay circuit so that the delay circuit controls the second signal unit to output the first enable signal; when the first signal unit determines the reset signal, the latch circuit inputs a second preset signal to the delay circuit so that the delay circuit controls the second signal unit to output the second enable signal after a preset time.

[0035] In the above scheme, a latch circuit is added between the delay circuit and the first signal unit; when the first signal unit determines the working signal, the latch circuit inputs a first preset signal to the delay circuit, so that the delay circuit controls the second signal unit to output a first enable signal, thereby turning on the control switch and the battery works; when the first signal unit determines the reset signal, the latch circuit inputs a second preset signal to the delay circuit, so that the delay circuit controls the second signal unit to output a second enable signal after a preset time, thereby turning off the control switch and stopping the battery from working. Compared with the related art, in the process of the first signal unit determining the reset signal, the present application can keep the latch state of the second preset signal input to the delay circuit unchanged through the latch circuit, so as to control the second signal unit to delay the output of the second enable signal through the delay circuit, so as to turn off the control switch, thereby preventing the situation where the control switch cannot be turned off due to the reset signal input by the first signal unit, thereby improving the safety of the battery. The above structures are described in detail below in conjunction with the accompanying drawings.

[0036] For the settings of the first signal unit, refer to Figure 1 , Figure 2 and Figure 3 , the first signal unit is used to determine the working signal and the reset signal. Among them, the working signal can be a control signal that controls the conduction of the control switch of the battery, so that the battery and the external load or charging device are turned on, so that the battery can be charged or discharged. Among them, the reset signal is a reset signal output by the control chip of the battery during the reset process. Exemplarily, the reset signal can be based on the wake-up signal in the process of waking up the main control chip in the BMS. Exemplarily, the first signal unit can be a pin. Of course, in other embodiments, the first signal unit can also be a signal transmission unit such as but not limited to a wireless or contactless signal, that is, as long as the working signal and the reset signal can be determined, they are within the protection scope of the present utility model.

[0037] It should be explained that the first signal unit may determine the working signal and the reset signal in a manner such as but not limited to receiving a signal input from other modules or a signal directly generated by the signal unit.

[0038] Exemplary, reference Figure 1 , Figure 2 and Figure 3The first signal unit can be connected to the main control chip in the BMS, and can even be connected to the SBC (System Basis Chip, which is an independent chip that includes power supply, communication, monitoring diagnosis, safety monitoring and other features as well as GPIO) chip in the BMS. Exemplarily, the first signal unit can be a PORST pin. Among them, PORST is a hard-line reset signal of the main control chip, which is reset and output by the SBC chip. When working normally, it outputs a working signal to the first signal unit, and when resetting, it outputs a reset signal to the first signal unit.

[0039] For the setting of the second signal unit, refer to Figure 1 , Figure 2 and Figure 3 , the second signal unit is used to output a first enable signal to turn on the control switch. The battery is electrically connected to an external load and a charging device through the control switch. Exemplarily, the control switch can be a switching device such as but not limited to a contactor, a relay, etc. The control switch is connected in the charging circuit and the discharging circuit of the battery. Only after the control switch is closed can the battery be connected to the external charging device and the load to charge the battery, or the battery can be discharged to the outside. The second signal unit serves as an enable pin for outputting an enable signal, and the first enable signal outputted by the second signal unit can enable the control switch to be turned on. Exemplarily, the second signal unit is connected to the driver chip to send a first enable signal to the driver chip, so that the driver chip enables the control switch to be turned on according to the received first enable signal.

[0040] Exemplary, reference Figure 1 , Figure 2 and Figure 3 , the second signal unit is also used to output a second enable signal to disconnect the control switch, thereby disconnecting the battery from the external charging device and the load. Exemplarily, when the second signal unit is connected to the driver chip, after the driver chip receives the second enable signal, the control switch is enabled to disconnect. Exemplarily, one of the first enable signal and the second enable signal is a high-level signal, and the other enable signal is a low-level signal. For example, the first enable signal is a low-level signal, and the second enable signal is a high-level signal; or, the first enable signal is a high-level signal, and the second enable signal is a low-level signal.

[0041] Exemplarily, the second signal unit may be a pin. Of course, in other embodiments, the second signal unit may also be a signal transmission unit such as but not limited to a wireless or contactless signal transmission unit, that is, any method capable of outputting the first enable signal and the second enable signal is within the protection scope of the present utility model.

[0042] When setting up latch circuits and delay circuits, refer to Figure 1 , Figure 2and Figure 3 The latch circuit is electrically connected between the first signal unit and the delay circuit, and the delay circuit is electrically connected between the latch circuit and the second signal unit. The latch circuit has a latching function, and the delay circuit has a delayed output function.

[0043] Specifically, refer to Figure 1 , Figure 2 and Figure 3 When the first signal unit determines the working signal, the latch circuit inputs the first preset signal to the delay circuit, so that the delay circuit controls the second signal unit to output the first enable signal, thereby turning on the control switch and the battery works. Exemplarily, at this time, the delay circuit can control the second signal unit to immediately output the first enable signal according to the first preset signal output by the latch circuit, that is, at this time, in the process of turning on the control switch, the delay control function is not used, so that the battery can work quickly.

[0044] refer to Figure 1 , Figure 2 and Figure 3 , when the first signal unit determines the reset signal, the latch circuit inputs the second preset signal to the delay circuit, so that the delay circuit controls the second signal unit to output the second enable signal after the preset time, that is, the extension circuit at this time controls the second signal unit to delay the output of the second enable signal, so that the control switch is delayed to disconnect, and the battery stops working. It can be seen that the delay circuit at this time can control the second signal unit to delay the output of the first enable signal according to the second preset signal output by the latch circuit, that is, at this time, in the process of disconnecting the control switch, the delay control function is used, so that the battery can be disconnected with a delay, so that the vehicle will not suddenly lose power and lose control during operation to ensure driving safety.

[0045] Compared with the related art, the present application can determine the reset signal through the first signal unit to reset the main control chip when the main control chip is abnormal due to factors such as but not limited to being stuck. At this time, in the process of the first signal unit determining the reset signal, the latch state of the second preset signal input to the delay circuit can be kept unchanged through the latch circuit, so as to control the second signal unit to delay the output of the second enable signal through the delay circuit, so as to disconnect the control switch, thereby preventing the control switch from being unable to disconnect due to the reset signal input by the first signal unit, thereby improving the safety of the battery.

[0046] Exemplary, reference Figure 2 and Figure 3, the control circuit may further include: an unlocking circuit and a third signal unit. Among them, the unlocking circuit is electrically connected to the latching circuit, and the third signal unit is electrically connected to the unlocking circuit. That is, the unlocking circuit is electrically connected between the third signal unit and the latching circuit. The third signal unit is used to determine the latching signal and the unlocking signal. Specifically, when the first signal unit determines the working signal and the third signal unit determines the unlocking signal, the latching circuit inputs the first preset signal to the delay circuit; when the first signal unit determines the reset signal and the third signal unit determines the latching signal, the latching circuit inputs the second preset signal to the delay circuit. It can be seen that the third signal unit can control whether the latching circuit enters the latching state. Specifically, when the third signal unit determines the latching signal, it can prompt the latching circuit to enter the latching state, ensuring that the latching circuit continuously inputs the second preset signal to the delay circuit unchanged, so that during the reset process of the main control chip, the delay circuit continuously outputs the second enable signal to control the control switch to be disconnected, preventing the control switch from being unable to be disconnected due to the reset signal input by the first signal unit, thereby improving the safety of the battery. After the main control chip completes the reset and works normally, while the first signal unit determines the working signal, the third signal unit determines the unlocking signal, so that the latch circuit is no longer in a latched state. The latch circuit can input the first preset signal to the delay circuit according to the working signal determined by the first signal unit, so that the delay circuit continuously outputs the first enable signal to control the control switch to be turned on, so that the battery can work normally.

[0047] Exemplarily, the third signal unit may be a pin. Exemplarily, the third signal unit may be an UNLOCK pin. Of course, in other embodiments, the third signal unit may also be a signal transmission unit such as but not limited to a wireless or contactless signal transmission unit, that is, as long as the method of determining the latch signal and the unlock signal can be within the protection scope of the present utility model. It should be explained that the method of determining the latch signal and the unlock signal by the third signal unit may be such as but not limited to a signal received from other modules or a signal directly generated by the signal unit.

[0048] Exemplary, reference Figure 2 and Figure 3, the working signal can be a high-level signal, and the reset signal can be a PWM wave signal with alternating high and low levels. At this time, when the first signal unit determines the reset signal and the third signal unit determines the latch signal, the latch circuit inputs the second preset signal to the delay circuit, which can be specifically: when the first signal unit inputs the low level in the reset signal and the third signal unit determines the latch signal, the latch circuit inputs the second preset signal to the delay circuit; and when the first signal unit inputs the high level in the reset signal and the third signal unit determines the latch signal, the latch circuit maintains the input of the second preset signal to the delay circuit unchanged. That is, when the third signal unit determines the latch signal and triggers the latch circuit to have a latch function, the trigger signal of the latch function is a low-level signal. That is, during the reset process of the main control chip, the third signal unit continues to determine the latch signal. At this time, when the first signal unit first inputs the low level in the reset signal, the latch circuit enters the self-locking state and inputs the second preset signal to the delay circuit. Afterwards, when the first signal unit inputs the high level in the reset signal, the latch circuit still remains in the self-locking state, and the latch circuit maintains the input of the second preset signal to the delay circuit unchanged. Therefore, a sufficient time can be provided for the delayed output of the second enabling signal of the delay circuit to ensure that the control switch can be controlled to be disconnected during the resetting process of the main control chip, thereby improving the safety of the battery.

[0049] Exemplary, reference Figure 2 and Figure 3 , the unlock signal can be a high level signal, and the latch signal can be a high impedance signal. Of course, in other embodiments, the unlock signal and the latch signal can be adjusted according to the specific latch circuit.

[0050] Exemplary, reference Figure 2 and Figure 3 , the first preset signal can be a high level signal, and the second preset signal can be a low level signal. Of course, in other embodiments, the types of the first preset signal and the second preset signal can be adjusted according to the specific latch circuit and delay circuit.

[0051] When setting the latch circuit and the unlock circuit, multiple methods can be used. The following introduces several latch circuits and unlock circuits using the following limiting conditions as examples. The above limiting conditions specifically include: the working signal is a high-level signal, the reset signal is a PWM wave signal that alternates between high and low levels; the unlock signal is a high-level signal, and the latch signal is a high-impedance signal; the first preset signal is a high-level signal, and the second preset signal is a low-level signal.

[0052] Exemplary, reference Figure 3The latch circuit comprises: a first output terminal, a first switch (Q2) and a second switch (Q4); wherein the first output terminal is electrically connected to the delay circuit, and the first output terminal is also electrically connected to the reference voltage terminal; the first terminal of the second switch (Q4) is electrically connected to the control terminal of the first switch (Q2) and the first output terminal, and the second terminal of the second switch (Q4) is electrically connected to the ground terminal; the control terminal of the second switch (Q4) is electrically connected to the second terminal of the first switch (Q2); wherein the control terminal of the second switch (Q4) is also electrically connected to the first signal unit and the unlocking circuit.

[0053] In a specific application, when the first signal unit determines the working signal and the third signal unit determines the unlocking signal, the second switch (Q4) is disconnected, the first switch (Q2) is disconnected, and the first output terminal outputs the first preset signal. Specifically, since when the second switch (Q4) is disconnected and the first switch (Q2) is disconnected, the first output terminal can be connected to the reference voltage terminal, so that the first output terminal outputs a high-level signal as the first preset signal.

[0054] When the first signal unit determines the reset signal and the third signal unit determines the latch signal, the second switch (Q4) is turned on, the first switch (Q2) is turned on, and the first output terminal outputs the second preset signal. Specifically, when the second switch (Q4) is turned on and the first switch (Q2) is turned on, the first output terminal can be connected to the ground terminal through the second switch (Q4), so that the first output terminal outputs a low-level signal as the second preset signal.

[0055] Exemplary, reference Figure 3 , the latch circuit may also include: a first resistor (R2), a second resistor (R5) and a third resistor (R8); wherein the first end of the first resistor (R2) is electrically connected to the reference voltage end, and the second end of the first resistor (R2) is electrically connected to the first output end; the control end of the first switch (Q2) is also electrically connected to the second end of the first resistor (R2); the first end of the second switch (Q4) is also electrically connected to the first end of the first resistor (R2); the second resistor (R5) and the third resistor (R8) are connected in series, and the control end of the second switch (Q4) is electrically connected to a connection node between the second resistor (R5) and the third resistor (R8); the first end of the second resistor (R5) is electrically connected to the second end of the first switch (Q2), and the second end of the second resistor (R5) is electrically connected to the connection node; the first end of the third resistor (R8) is electrically connected to the connection node, and the second end of the third resistor (R8) is electrically connected to the ground end; the connection node is electrically connected to the first signal unit and the unlocking circuit.

[0056] For specific applications, refer to Figure 3When the first signal unit determines the working signal and the third signal unit determines the unlocking signal, the second switch (Q4) is turned off, the first switch (Q2) is turned off, and the first output terminal outputs the first preset signal, so that the first output terminal is connected to the reference voltage terminal through the first resistor (R2), so that the first output terminal outputs a high-level signal as the first preset signal. When the first signal unit determines the reset signal and the third signal unit determines the latching signal, the second switch (Q4) is turned on, the first switch (Q2) is turned on, and the first output terminal outputs the second preset signal, so that the first output terminal is connected to the ground terminal through the second switch (Q4), so that the first output terminal outputs a low-level signal as the second preset signal.

[0057] Exemplarily, the types of the first switch (Q2) and the second switch (Q4) may be of various types. Figure 3 , the first switch (Q2) can be a PMOS switch tube, and the second switch (Q4) can be an NMOS switch tube. It should be explained that the NMOS switch tube refers to an N-type metal oxide semiconductor, and its full English name is Negative Channel Metal Oxide Semiconductor. When the control end of the NMOS switch tube receives a high-level signal, the NMOS switch tube is turned on; when the control end of the NMOS switch tube receives a low-level signal, the NMOS switch tube is turned off. The switch tube corresponding to the NMOS switch tube is a PMOS switch tube, which refers to a P-type metal oxide semiconductor, and its full English name is Positive Channel Metal Oxide Semiconductor. When the control end of the PMOS switch tube receives a high-level signal, the PMOS switch tube is turned off; when the control end of the PMOS switch tube receives a low-level signal, the PMOS switch tube is turned on.

[0058] Of course, it should be noted that the first switch (Q2) is not limited to using a PMOS switch tube. In addition, other switch devices with high-level signals turned on and low-level signals turned off can also be used. For example, the first switch (Q2) can also be an NPN transistor. The second switch (Q4) is not limited to using an NMOS switch tube. In addition, other switch devices with high-level signals turned on and low-level signals turned off can also be used. For example, the second switch (Q4) can also be a PNP transistor.

[0059] Exemplary, reference Figure 2 and Figure 3, the latch circuit may further include: a first input terminal, a third switch (Q5) and a diode; wherein the first input terminal is electrically connected to the first signal unit; the first terminal of the third switch (Q5) is electrically connected to the reference voltage terminal, the second terminal of the third switch (Q5) is electrically connected to the ground terminal, and the control terminal of the third switch (Q5) is electrically connected to the first input terminal; the anode of the diode is electrically connected to the reference voltage terminal and the first terminal of the third switch (Q5), and the cathode of the diode (D1) is electrically connected to the connection node. wherein, when the first signal unit inputs a low level in the reset signal and the third signal unit inputs a latch signal, the third switch (Q5) is disconnected to turn on the second switch (Q4), and the first switch (Q2) is turned on, so that the first output terminal is connected to the ground terminal through the second switch (Q4), so that the first output terminal outputs a low level signal as the second preset signal. When the first signal unit inputs a high level in the reset signal and the third signal unit determines the latch signal, the diode prevents the high level of the gate of the second switch (Q4) from being connected to the ground terminal through the third switch (Q5), that is, the diode D1 prevents the G pole (gate) level of Q4 from being pulled down by Q5, and Q2 and Q4 form a self-locking part, which can latch the low level in the reset signal input by the first signal unit, so that the diode can maintain the second switch (Q4) and the first switch (Q2) to be connected unchanged, so that the first output terminal remains connected to the ground terminal through the second switch (Q4), so that the first output terminal maintains the output of the low level signal as the second preset signal unchanged.

[0060] Exemplary, reference Figure 2 and Figure 3 The latch circuit further comprises: a fourth resistor (R3), a fifth resistor (R7) and a sixth resistor (R9); wherein a first end of the fourth resistor is electrically connected to a reference voltage end, and a second end of the fourth resistor is electrically connected to a first end of a third switch (Q5) and an anode of a diode; a first end of the fifth resistor (R7) is electrically connected to the first input end, a second end of the fifth resistor (R7) is electrically connected to a control end of the third switch (Q5) and a first end of a sixth resistor (R9), and a second end of the sixth resistor (R9) is electrically connected to a ground end.

[0061] Exemplary, reference Figure 3 , the third switch (Q5) is an NMOS switch tube. Of course, it should be noted that the third switch (Q5) is not limited to using an NMOS switch tube. In addition, other switch devices with high-level signals turned on and low-level signals turned off can also be used. For example, the third switch (Q5) can also be a PNP transistor.

[0062] Exemplary, reference Figure 2 and Figure 3, the unlocking circuit may include: a second input terminal, a second output terminal, and a fourth switch (Q7); wherein the second input terminal is electrically connected to the third signal unit; the second output terminal is electrically connected to the cathode of the diode and the connection node; the first terminal of the fourth switch (Q7) is electrically connected to the second output terminal, the second terminal of the fourth switch (Q7) is electrically connected to the ground terminal, and the control terminal of the fourth switch (Q7) is electrically connected to the second input terminal.

[0063] When the first signal unit determines the working signal and the third signal unit determines the unlocking signal, the third switch (Q5) is turned off and the fourth switch (Q7) is turned on, so that the second switch (Q4) is turned off and the first switch (Q2) is turned off, so that the first output end is connected to the reference voltage end through the first resistor (R2), so that the first output end outputs a high-level signal as a first preset signal.

[0064] When the first signal unit inputs a low level in the reset signal and the third signal unit determines the latch signal, the third switch (Q5) is turned off and the fourth switch (Q7) is turned off to turn on the second switch (Q4) and the first switch (Q2), so that the first output terminal is connected to the ground terminal through the second switch (Q4), so that the first output terminal outputs a low level signal as a second preset signal.

[0065] When the first signal unit inputs a high level in the reset signal and the third signal unit determines the latch signal, the fourth switch (Q7) is disconnected, the diode prevents the high level of the gate of the second switch (Q4) from being connected to the ground terminal through the third switch (Q5), and the diode D1 prevents the G pole (gate) level of Q4 from being pulled down by Q5. Q2 and Q4 form a self-locking part, which can latch the low level in the reset signal input by the first signal unit, so that the diode can maintain the second switch (Q4) and the first switch (Q2) to be connected unchanged, so that the first output terminal remains connected to the ground terminal through the second switch (Q4), so that the first output terminal maintains the output of the low level signal as the second preset signal unchanged.

[0066] Exemplary, reference Figure 3 , the fourth switch (Q7) can be an NMOS switch tube. Of course, it should be noted that the fourth switch (Q7) is not limited to using an NMOS switch tube. In addition, other switch devices with high-level signals turned on and low-level signals turned off can also be used. For example, the fourth switch (Q7) can also be a PNP transistor.

[0067] Exemplary, reference Figure 2 and Figure 3The unlocking circuit may further include: a seventh resistor (R10) and an eighth resistor (R11), wherein a first end of the seventh resistor (R10) is electrically connected to the second input end, a second end of the seventh resistor (R10) is electrically connected to a control end of the fourth switch (Q7) and a first end of the eighth resistor (R11), and a second end of the eighth resistor (R11) is electrically connected to the ground end.

[0068] When setting the delay circuit, a variety of methods can be used. For example, refer to Figure 3 , the delay circuit may include: a third input terminal and a third output terminal. Among them, the third input terminal of the delay circuit is electrically connected to the first output terminal of the latch circuit. The third output terminal of the delay circuit is electrically connected to the second signal unit. When the first output terminal of the latch circuit outputs the first preset signal, the third output terminal outputs the first enable signal to the second signal unit to turn on the control switch of the battery and the battery works normally. When the first output terminal of the latch circuit outputs the second preset signal, the third output terminal delays the output of the second enable signal to the second signal unit to delay the disconnection of the control switch of the battery, so that the vehicle will not suddenly lose power or lose control during operation to ensure driving safety.

[0069] Exemplary, reference Figure 3 , the delay circuit can be composed of NMOS Q3, resistor R4, resistor R1, capacitor C2, resistor R6, NMOS Q6, and PMOS Q1, wherein NMOS Q3, Q1, and Q6 play a role in level conversion, resistors R4 and R6 limit current, and capacitor C1 stores energy. Resistor R4 and NMOS Q3 provide a charging circuit for capacitor C1, and the resistance value of resistor R4 needs to be set to be small, so that capacitor C1 charges quickly, so that the high-level signal as the first preset signal is not delayed output. Resistor R1 provides a discharge circuit for capacitor C1, and the resistance value of resistor R1 is configured to be large, and the discharge speed of capacitor C1 is slow, so that the low-level signal as the second preset signal can be delayed output. The parameters of resistor R1 and capacitor C1 can be configured to adjust the delay time, that is, the preset time length can be adjusted by configuring the parameters of resistor R1 and capacitor C1. The low-level signal as the second preset signal input by the delay circuit can delay the output of the second enable signal, and the high-level signal as the first preset signal input by the delay circuit can immediately output the first enable signal.

[0070] Exemplary, reference Figure 3, the latch circuit is composed of a fifth resistor R7, a sixth resistor R9, a third switch NMOS Q5, a fourth resistor R3, a diode D1, a second resistor R5, a third resistor R8, a first resistor R2, a second switch NMOS Q4, and a first switch PMOS Q2. Among them, resistors R7 and R9, R5 and R8 play a voltage-dividing role; resistors R2 and R3 play a current-limiting role. Q5 performs level conversion, and diode D1 prevents the G pole (gate) level of Q4 from being pulled down by Q5. Q2 and Q4 form a self-locking part, which can latch the low level in the reset signal input by the first signal unit. Exemplarily, the reset signal can be a hard-line reset signal of the MCU to prevent the hard-line reset signal from being restored, and the control switch is not disconnected when the MCU is continuously stuck.

[0071] Exemplary, reference Figure 3 , the unlocking circuit can be composed of a seventh resistor R10, an eighth resistor R11, and a fourth switch NMOS Q7, R10 and R11 play a voltage dividing role, and Q7 performs level conversion. The unlocking circuit can unlock the self-locking state of the latch circuit. Exemplarily, the third signal unit is an UNLOCK pin, and the UNLOCK pin is used to input a high-level signal as an unlocking signal, or a high-impedance signal as a latching signal. When a high-level signal is input to the UNLOCK pin, the self-locking state of the latch circuit can be unlocked.

[0072] Exemplary, reference Figure 3 , the PORST pin can be the first signal unit, which is the hard-line reset signal of the main control chip MCU, and is reset and output by the SBC. During normal operation, a high-level signal is input as a working signal, and a PWM wave signal with alternating high and low levels as a reset signal is input during reset. The unlocking signal of the UNLOCK pin as the third signal unit is output by the main control chip MCU. During normal operation, the UNLOCK pin as the third signal unit inputs a high-level signal as an unlocking signal, and the UNLOCK pin inputs a high-impedance state as a latching signal during reset. The EN pin is the second signal unit, which is connected to the enable pin of the driver chip. When the second signal unit outputs the first enable signal, the driver chip is enabled and the enable control switch is turned on; when the second signal unit outputs the second enable signal, the driver chip enable is invalid and the enable control switch is turned off.

[0073] It should be noted that each of the above-mentioned resistors does not refer to a single resistor device, but a resistor component with voltage division or current limiting function formed by connecting one or more resistor devices in series or in parallel.

[0074] The specific implementation process of the solution is as follows:

[0075] refer to Figure 3, during normal operation, the PORST pin as the first signal unit inputs a high-level signal as a working signal, and the UNLOCK pin as the third signal unit inputs a high-level signal as an unlocking signal, Q7 is turned on, and the unlocking circuit outputs a low level. The unlocking circuit outputs a low level, causing Q4 to be disconnected, Q2 to be disconnected, and the latch circuit outputs a high level as the first preset signal to the delay circuit. The latch circuit outputs a high level, causing Q3 to be turned on, Q1 to be turned on, Q6 to be disconnected, and the delay circuit outputs a high-level signal (first enable signal). The delay circuit outputs a high level, and the EN pin as the second signal unit outputs a high level (first enable signal), enabling the driver chip to control the control switch to be turned on, and the battery can work normally.

[0076] refer to Figure 3 When the main control chip MCU is in a continuous stuck state, the PORST pin as the first signal unit inputs the PWM wave signal as the reset signal, and the UNLOCK pin as the third signal unit inputs a high-impedance signal. The UNLOCK pin is in a high-impedance state, causing Q7 to be disconnected, and the unlocking circuit outputs a high-impedance signal. When the PWM wave signal as the reset signal is a low level in the PWM wave signal, Q5 is disconnected, and the unlocking circuit outputs a high-impedance signal, causing Q4 to be turned on, Q2 to be turned on, Q2 and Q4 to form a self-locking state, and the latch circuit outputs a low-level signal as the second preset signal. When the PWM wave signal as the reset signal is a high level in the PWM wave signal, due to the presence of diode D1, the self-locking state of Q2 and Q4 cannot be released, and the latch circuit maintains the output of the low-level signal as the second preset signal unchanged. The latch circuit outputs a low-level signal as the second preset signal to the delay circuit, causing Q3 to disconnect, capacitor C1 to slowly discharge through resistor R1, Q6 to be turned on with a delay, and Q1 to be turned off with a delay. The delay circuit delays the output of a low-level signal as the second enable signal, and the control switch can be turned off with a delay.

[0077] refer to Figure 3 After the main control chip MCU is restored, the PORST pin as the first signal unit inputs a high-level signal as a working signal, and the UNLOCK pin as the third signal unit inputs a high-level signal as an unlocking signal, Q7 is turned on, and the unlocking circuit outputs a low level. The unlocking circuit outputs a low level, causing Q4 to be disconnected, Q2 to be disconnected, and the latch circuit outputs a high level as the first preset signal to the delay circuit. The latch circuit outputs a high level, causing Q3 to be turned on, Q1 to be turned on, Q6 to be disconnected, and the delay circuit outputs a high-level signal (the first enable signal). The delay circuit outputs a high level, and the EN pin as the second signal unit outputs a high level (the first enable signal), enabling the driver chip to control the control switch to be turned on, and the battery can work normally.

[0078] In the various embodiments shown above, a latch circuit is added between the delay circuit and the first signal unit; when the first signal unit determines the working signal, the latch circuit inputs the first preset signal to the delay circuit, so that the delay circuit controls the second signal unit to output the first enable signal, thereby turning on the control switch and the battery works; when the first signal unit determines the reset signal, the latch circuit inputs the second preset signal to the delay circuit, so that the delay circuit controls the second signal unit to output the second enable signal after a preset time period, thereby turning off the control switch and the battery stops working.

[0079] In the related art, the control circuit for the control switch has no latching function, and the hard-wired reset signal of the main control chip MCU is not latched or unlocked. The main disadvantages are: when the vehicle is driving, if the main control chip MCU of the BMS is continuously in the reset state, the high-voltage contactor used as the control switch may not be disconnected, causing the vehicle to lose control. The reason for this disadvantage is that in the related art, the low level of the hard-wired reset signal of the main control chip MCU is not latched. If the main control MCU of the BMS is continuously stuck, the hard-wired reset signal is not a continuous low level but a PWM wave that outputs alternating high and low levels, which will cause the high-voltage contactor used as the control switch to be unable to disconnect.

[0080] Compared with the related art, the present application can maintain the latch state of the second preset signal input to the delay circuit unchanged through the latch circuit during the process of the first signal unit determining the reset signal, so as to control the second signal unit to delay the output of the second enable signal through the delay circuit to disconnect the control switch, thereby preventing the situation where the control switch cannot be disconnected due to the reset signal input by the first signal unit, thereby improving the safety of the battery.

[0081] Compared with the related art, some of the above embodiments of the present application latch the hard-wire reset signal of the main control chip MCU, and the main control chip MCU needs to send an unlock signal through the third signal unit to cancel the latch state of the latch circuit, which can prevent the MCU from being stuck and the control switch from being disconnected. When the main control chip MCU is abnormally reset, the hard-wire reset signal of the main control chip MCU is used to control the control switch to disconnect, which is associated with the hard-wire reset signal of the main control chip MCU, so as to avoid the situation where the control switch is disconnected by mistake.

[0082] In some embodiments, the present application controls the enable signal of the second signal unit so that when the vehicle is driving, if the main control chip MCU of the BMS is continuously stuck, the high-voltage contactor serving as the control switch will be disconnected with a delay, so that the vehicle will not suddenly lose power or control during operation, ensuring driving safety.

[0083] Furthermore, the present application embodiment also provides a battery management system, referring to Figure 1 to Figure 3The battery management system includes any one of the above control circuits for controlling a control switch of a battery. Exemplarily, the battery management system may be a BMS in a battery pack, which is used to control the batteries in the battery pack.

[0084] In addition, the present application also provides a distribution box, referring to Figure 1 to Figure 3 , the distribution box includes any of the above-mentioned battery management systems. Exemplarily, the distribution box can be a distribution box in a battery pack. The distribution box is provided with a battery management system and other devices to control the batteries in the battery pack and realize other power distribution functions.

[0085] In addition, the present application also provides a battery pack, referring to Figure 1 to Figure 3 The battery system includes: a battery, a control switch, a main control chip, a driving chip and a control circuit of any one of the above batteries; wherein the control switch is used to control the battery; the main control chip has a fourth signal unit; the fourth signal unit is electrically connected to the first signal unit to input a working signal and a reset signal to the first signal unit; the driving chip is electrically connected to the control switch and the second signal unit, and the driving chip is used to: control the control switch to be turned on according to the first enable signal output by the second signal unit, and control the control switch to be turned off according to the second enable signal output by the second signal unit.

[0086] As in some of the above embodiments, reference Figure 2 and Figure 3 The control circuit also has an unlocking circuit and a third signal unit. At this time, exemplarily, the main control chip also has a fifth signal unit, which is used to electrically connect the third signal unit in the control circuit to input a latch signal and an unlocking signal to the third signal unit.

[0087] Exemplarily, the control switch may be any type of switch device such as, but not limited to, a contactor, a relay, etc. Exemplarily, the control switch is connected to the charging circuit and the discharging circuit of the battery. Only after the control switch is closed can the battery be connected to an external charging device and a load to charge the battery or discharge the battery to the outside.

[0088] Exemplarily, the driver chip can be any type of chip, which is used to enable the control switch to be turned on or off according to the enable signal it receives. Exemplarily, after receiving the first enable signal, the driver chip enables the control switch to be turned on so that the battery is connected to the external charging device and the load; after receiving the second enable signal, the driver chip enables the control switch to be turned off so that the battery is disconnected from the external charging device and the load.

[0089] Furthermore, the present application also provides an electric energy device, referring to Figure 1 to Figure 3, the electric energy device includes: any one of the above-mentioned control circuits for controlling the control switch of the battery, any one of the above-mentioned battery management systems, any one of the above-mentioned distribution boxes, or any one of the above-mentioned battery packs. Exemplarily, the electric energy device can be a device with electric energy such as but not limited to vehicles, aircraft, ships, household appliances or energy storage cabinets. When the electric energy device is a vehicle, exemplarily, the vehicle can be any vehicle including a battery such as but not limited to an electric vehicle, a hybrid vehicle, etc. Exemplarily, the above-mentioned battery can be a power battery of the vehicle, and can also be a storage battery of the vehicle.

[0090] The utility model has been described through the above embodiments, but it should be understood that the above embodiments are only for the purpose of example and description, and are not intended to limit the utility model to the scope of the described embodiments. In addition, it can be understood by those skilled in the art that the utility model is not limited to the above embodiments, and more variations and modifications can be made according to the teachings of the utility model, and these variations and modifications all fall within the scope of protection claimed by the utility model. The protection scope of the utility model is defined by the attached claims and their equivalents.

Claims

1. A control circuit for controlling a control switch of a battery, characterized in that: include: Latch circuit; A first signal unit, electrically connected to the latch circuit, for determining a working signal and a reset signal; A delay circuit electrically connected to the latch circuit; a second signal unit, electrically connected to the delay circuit, and configured to output a first enable signal for turning on the control switch and a second enable signal for turning off the control switch; When the first signal unit determines the working signal, the latch circuit inputs a first preset signal to the delay circuit, so that the delay circuit controls the second signal unit to output the first enable signal; When the first signal unit determines the reset signal, the latch circuit inputs a second preset signal to the delay circuit, so that the delay circuit controls the second signal unit to output the second enable signal after a preset time period.

2. The control circuit according to claim 1, characterized in that: Also includes: an unlocking circuit, electrically connected to the latching circuit; a third signal unit, electrically connected to the unlocking circuit, and used to determine a latch signal and an unlocking signal; Wherein, when the first signal unit determines the working signal and the third signal unit determines the unlocking signal, the latch circuit inputs the first preset signal to the delay circuit; When the first signal unit determines the reset signal and the third signal unit determines the latch signal, the latch circuit inputs the second preset signal to the delay circuit.

3. The control circuit according to claim 2, characterized in that: The working signal is a high level signal, and the reset signal is a PWM wave signal with alternating high level and low level; When the first signal unit inputs a low level of the reset signal and the third signal unit determines the latch signal, the latch circuit inputs the second preset signal to the delay circuit; When the first signal unit inputs a high level of the reset signal and the third signal unit asserts the latch signal, the latch circuit maintains inputting the second preset signal to the delay circuit.

4. The control circuit according to claim 3, characterized in that: The unlock signal is a high level signal, and the latch signal is a high impedance signal.

5. The control circuit according to claim 4, characterized in that: The first preset signal is a high level signal, and the second preset signal is a low level signal.

6. The control circuit according to claim 5, characterized in that: The latch circuit comprises: A first output terminal, electrically connected to the delay circuit and electrically connected to a reference voltage terminal; a first switch, wherein a first end of the first switch is electrically connected to the reference voltage end; a second switch, wherein a first end of the second switch is electrically connected to a control end of the first switch and the first output end, a second end of the second switch is electrically connected to a ground end, and a control end of the second switch is electrically connected to a second end of the first switch; Wherein, the control end of the second switch is also electrically connected to the first signal unit and the unlocking circuit; When the first signal unit determines the working signal and the third signal unit determines the unlocking signal, the second switch is turned off, the first switch is turned off, and the first output terminal outputs the first preset signal; When the first signal unit determines the reset signal and the third signal unit determines the latch signal, the second switch is turned on, the first switch is turned on, and the first output terminal outputs the second preset signal.

7. The control circuit according to claim 6, characterized in that: The first switch is a PMOS switch tube or an NPN transistor, and the second switch is an NMOS switch tube or a PNP transistor.

8. The control circuit according to claim 6, characterized in that: The latch circuit further comprises: a first resistor, wherein a first end of the first resistor is electrically connected to the reference voltage end, and a second end of the first resistor is electrically connected to the first output end; a control end of the first switch is also electrically connected to the second end of the first resistor; and a first end of the second switch is also electrically connected to the first end of the first resistor; a second resistor and a third resistor connected in series, wherein the control end of the second switch is electrically connected to a connection node between the second resistor and the third resistor; a first end of the second resistor is electrically connected to a second end of the first switch, and a second end of the second resistor is electrically connected to the connection node; a first end of the third resistor is electrically connected to the connection node, and a second end of the third resistor is electrically connected to the ground terminal; Wherein, the connection node is electrically connected to the first signal unit and the unlocking circuit.

9. The control circuit according to claim 8, characterized in that: The latch circuit further comprises: A first input terminal, electrically connected to the first signal unit; a third switch, wherein a first end of the third switch is electrically connected to the reference voltage end, a second end of the third switch is electrically connected to the ground end, and a control end of the third switch is electrically connected to the first input end; a diode, wherein an anode of the diode is electrically connected to the reference voltage terminal and the first end of the third switch, and a cathode of the diode is electrically connected to the connection node; Wherein, when the first signal unit inputs the low level of the reset signal and the third signal unit determines the latch signal, the third switch is turned off to turn on the second switch and the first switch is turned on; When the first signal unit inputs a high level in the reset signal and the third signal unit asserts the latch signal, the diode maintains the second switch and the first switch turned on.

10. The control circuit according to claim 9, characterized in that: The latch circuit further comprises: a fourth resistor, wherein a first end of the fourth resistor is electrically connected to the reference voltage end, and a second end of the fourth resistor is electrically connected to the first end of the third switch and the anode of the diode; A fifth resistor and a sixth resistor, wherein a first end of the fifth resistor is electrically connected to the first input end, a second end of the fifth resistor is electrically connected to the control end of the third switch and a first end of the sixth resistor, and a second end of the sixth resistor is electrically connected to the ground end.

11. The control circuit according to claim 9, characterized in that: The third switch is an NMOS switch tube or a PNP transistor.

12. The control circuit according to claim 9, characterized in that: The unlocking circuit comprises: A second input terminal, electrically connected to the third signal unit; a second output terminal, electrically connected to the cathode of the diode and the connection node; a fourth switch, wherein a first end of the fourth switch is electrically connected to the second output end, a second end of the fourth switch is electrically connected to the ground end, and a control end of the fourth switch is electrically connected to the second input end; Wherein, when the first signal unit determines the working signal and the third signal unit determines the unlocking signal, the third switch is turned off and the fourth switch is turned on, so that the second switch is turned off and the first switch is turned off; When the first signal unit inputs a low level in the reset signal and the third signal unit determines the latch signal, the third switch is turned off and the fourth switch is turned off, so that the second switch is turned on and the first switch is turned on; When the first signal unit inputs a high level in the reset signal and the third signal unit asserts the latch signal, the fourth switch is turned off and the diode maintains the second switch and the first switch turned on.

13. The control circuit according to claim 12, characterized in that: The fourth switch is an NMOS switch tube or a PNP transistor.

14. The control circuit according to claim 12, characterized in that: The unlocking circuit comprises: A seventh resistor and an eighth resistor, wherein the first end of the seventh resistor is electrically connected to the second input end, the second end of the seventh resistor is electrically connected to the control end of the fourth switch and the first end of the eighth resistor, and the second end of the eighth resistor is electrically connected to the ground end.

15. The control circuit according to claim 2, characterized in that: At least one of the first signal unit, the second signal unit and the third signal unit is a pin.

16. A battery management system, characterized in that: include: A control circuit for controlling a control switch of a battery according to any one of claims 1 to 15.

17. A distribution box, characterized in that: include: The battery management system as claimed in claim 16.

18. A battery pack, characterized in that: include: Battery; A control switch, used for controlling the battery; The distribution box as claimed in claim 17; A main control chip having a fourth signal unit; wherein the fourth signal unit is electrically connected to the first signal unit to input the working signal and the reset signal to the first signal unit; A driving chip is electrically connected to the control switch and the second signal unit, and is used to: control the control switch to be turned on according to the first enable signal output by the second signal unit, and control the control switch to be turned off according to the second enable signal output by the second signal unit.

19. The battery pack according to claim 18, characterized in that: The main control chip also has a fifth signal unit, and the fifth signal unit is used to electrically connect to the third signal unit in the control circuit to input a latch signal and an unlock signal to the third signal unit.

20. An electric energy device, characterized in that: include: A control circuit for controlling a control switch of a battery as claimed in any one of claims 1 to 15, a battery management system as claimed in claim 16, a distribution box as claimed in claim 17, or a battery pack as claimed in any one of claims 18 to 19.

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