Gas sensor chip with lens

Abstract

The embodiment of the utility model provides a gas sensor chip with a lens. The gas sensor chip comprises a silicon lens array structure and a chip body, the silicon lens array structure comprises a silicon substrate and a plurality of optical filters; the silicon substrate is provided with a first surface and a second surface which are opposite to each other, and a lens array is formed on the first surface; the optical filter is arranged on the second surface of the silicon substrate; the position of the lens corresponds to that of the optical filter; the first surface of the silicon substrate is integrally connected with the upper surface of the chip body; wherein the lens corresponds to the central hot end of the chip body in position and is used for converging energy of an external infrared light source to the central hot end of the chip body. According to the chip, the optical filter is integrated on the chip body, and the lens array is formed on the silicon substrate of the optical filter carrier, so that the lens can gather the energy of an external infrared light source to the central hot end of the chip body, and the sensitivity of the chip is improved.

Description

Technical Field

[0001] The embodiments of the present disclosure belong to the technical field of gas sensors, and in particular relate to a gas chip with a lens. Background Art

[0002] Non-dispersive infrared (NDIR) gas sensor is a sensor that uses the principle of infrared absorption to detect gas composition by detecting the absorption of infrared radiation of a specific wavelength by specific gas molecules in the ambient air. NDIR gas sensors are mainly composed of light source, sample chamber, spectral filter, detector, etc. The sensor passes ambient air through the sample chamber. The gas molecules in the sample chamber that are irradiated by the infrared light source will absorb infrared radiation of a specific wavelength. The amount of infrared radiation absorbed is proportional to the gas concentration. Subsequently, the sensor uses a spectral filter to select the wavelength of interest so that it can only reach the detector. The detector can measure the intensity of the absorbed infrared radiation, which in turn reflects the gas concentration value.

[0003] NDIR infrared gas sensor is realized by using the characteristics that different gases have their own unique molecular structure and specific absorption spectrum for infrared light, that is, different gases have the ability to absorb infrared light of a certain band. And this specific band of infrared light is called the infrared absorption peak of the gas. The infrared absorption peaks of different gases are different. Even in a mixed gas environment, the infrared absorption between gases will not interfere with each other. This property will not change due to changes in external conditions. The amount of energy absorbed by a certain gas to be measured is related to the concentration of the gas in the infrared light region. The greater the concentration, the more energy is absorbed. When infrared light passes through the gas, energy attenuation will occur at the corresponding frequency, and the degree of energy attenuation is related to the gas concentration. By analyzing the attenuation degree of infrared light, the concentration of the gas to be measured can be calculated. The absorption of infrared light by the gas to be measured obeys the Lambert-Beer law. NDIR gas sensor uses this characteristic to perform qualitative and quantitative analysis on the concentration of a specific gas.

[0004] Compared with other sensors, NDIR gas sensors have the advantages of high detection accuracy, fast response speed, good stability, strong anti-interference, and can detect a variety of gas components. Therefore, NDIR gas sensors are widely used in air quality detection, industrial emission monitoring, medical diagnosis and other fields.

[0005] The chips in the NDIR gas sensor detectors in the industry generally need to be used with externally purchased filters of specific wavelengths to detect characteristic gases, but there are the following problems: 1. Low detection sensitivity; 2. The externally purchased filters need to be TO-packaged with the gas chips, resulting in a large sensor size, which is inconvenient for customers to install and use, and the consistency of the device is uncontrollable; 3. It is unable to detect the concentrations of different types of gases; 4. The anti-interference ability of gas concentration detection is poor.

[0006] Therefore, how to solve the above problems has become a technical problem that needs to be solved urgently by those skilled in the art. Utility Model Content

[0007] The embodiments of the present disclosure aim to solve at least one of the technical problems existing in the prior art and provide a gas chip with a lens.

[0008] According to a first aspect of an embodiment of the present disclosure, a gas chip having a lens is provided, comprising:

[0009] The chip comprises a silicon lens array structure and a chip body; the silicon lens array structure comprises a silicon substrate and a plurality of filters; the silicon substrate has a first surface and a second surface opposite to each other, the first surface is formed with a lens array; the second surface of the silicon substrate is provided with the filters; the lens is provided correspondingly to the position of the filters;

[0010] The first surface of the silicon substrate is integrally connected to the upper surface of the chip body; wherein the lens corresponds to the position of the central hot end of the chip body, and is used to gather the energy of the external infrared light source to the central hot end of the chip body.

[0011] Optionally, the lens array comprises a concave lens array.

[0012] Optionally, the filter includes a methane filter, a reference comparison filter and a carbon dioxide filter; the methane filter includes an AgF film or a MgF2 film; the reference comparison filter includes an Al(NO3)3 film; and the carbon dioxide filter includes an AlGaS film.

[0013] Furthermore, it also includes:

[0014] A resonant cavity array structure is arranged on the lower surface of the chip body; the resonant cavity array structure is formed with a pit array;

[0015] The substrate of the chip body is formed with a back cavity, and the back cavity corresponds to the central hot end position of the chip body;

[0016] Among them, a reflective layer is provided on the surface of the pit; the pit and the back cavity are arranged correspondingly, and the pit and the back cavity together constitute a resonant cavity.

[0017] Optionally, the back cavity is convex; the back cavity and the pit together constitute a concave-convex resonant cavity.

[0018] Optionally, the pit array includes pits of different depths.

[0019] Optionally, the pit depth value is 1 / 4λ to 3 / 4λ, wherein λ is the wavelength of the infrared band.

[0020] Optionally, the chip body includes a semiconductor structure layer and a CMOS device structure and a MEMS device structure integrated in the semiconductor structure layer.

[0021] Optionally, the semiconductor structure layer includes a substrate and a support layer, an oxide layer and a passivation layer stacked on the substrate;

[0022] The support layer includes a first support layer, a second support layer and a third support layer stacked sequentially on the substrate; wherein the first support layer is used as an oxide layer of the gate of the CMOS device structure; the third support layer is used as a field oxygen wet oxide layer for electrical isolation between the CMOS device structures.

[0023] Optionally, the material of the first supporting layer and the third supporting layer includes silicon oxide; and the material of the second supporting layer includes silicon nitride.

[0024] The beneficial effects of the embodiments of the present disclosure include:

[0025] In the present disclosure, by integrating a filter on the chip body and forming a lens array on the silicon substrate of the filter carrier, the lens can gather the energy of the external infrared light source to the central hot end of the chip body, thereby improving the chip sensitivity. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1-8 This is a flow chart of a process for preparing a gas chip with a lens according to an embodiment of the present disclosure;

[0027] Figure 9-15 A flowchart of a chip body preparation process according to an embodiment of the present disclosure;

[0028] Fig.16 A schematic diagram of a chip body array structure according to an embodiment of the present disclosure;

[0029] Figure 17-23 A flowchart of a process for preparing an array chip for multiple gas detection according to an embodiment of the present disclosure;

[0030] Fig.24 This is a schematic diagram of a gas chip structure with a lens according to an embodiment of the present disclosure;

[0031] Fig.25 This is a diagram showing the infrared light incident effect of a SOC integrated with a silicon micro-concave lens, a bottom reflection layer and an NDIR infrared gas sensor chip of an embodiment of the present invention. DETAILED DESCRIPTION

[0032] In order to enable those skilled in the art to better understand the technical solution of the present disclosure, the present disclosure is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0033] The following is a further detailed description of the implementation methods of the present application in conjunction with the accompanying drawings and examples. The detailed descriptions and drawings of the following examples are used to illustrate the principles of the present application, but cannot be used to limit the scope of the present application, that is, the present application is not limited to the described embodiments. In the description of the present application, it should be noted that, unless otherwise specified, the meaning of "multiple" is more than two; the orientation or position relationship indicated by the terms "upper", "lower", "left", "right", "inside", "outside", etc. is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance. "Vertical" is not vertical in the strict sense, but within the error tolerance range. "Parallel" is not parallel in the strict sense, but within the error tolerance range.

[0034] In the description of this application, it should also be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to the specific circumstances.

[0035] like Figure 7-8 As shown, a gas chip with a lens comprises:

[0036] The chip includes a silicon lens array structure 10 and a chip body 11. The silicon lens array structure 10 includes a silicon substrate 1 and a plurality of filters. The silicon substrate 1 has a first surface and a second surface opposite to each other, and a lens array is formed on the first surface. The second surface of the silicon substrate 1 is provided with a filter, and the position of the lens and the filter is correspondingly arranged.

[0037] The first surface of the silicon substrate 1 is integrally connected to the upper surface of the chip body 11 , wherein the lens corresponds to the position of the central hot end of the chip body 11 .

[0038] In the present disclosure, by integrating a filter on the chip body 11 and forming a lens array on the silicon substrate 1 of the filter carrier, the lens can gather the energy of the external infrared light source to the central hot end of the chip body 11, thereby improving the chip sensitivity.

[0039] In some embodiments, the filter is a narrow-band spectral thin film filter.

[0040] In some embodiments, the lens array comprises a concave lens array.

[0041] In the present disclosure, by integrating a filter on the chip body 11 and forming a concave lens array on the silicon lens array structure 10 of the filter carrier, the concave lens can effectively gather the energy of the external infrared light source to the central hot end of the chip body 11, thereby significantly improving the chip sensitivity.

[0042] In some embodiments, reference Figure 7 The filters include a methane filter 6, a reference comparison filter 7 and a carbon dioxide filter 8. The methane filter includes an AgF film or a MgF2 film, the reference comparison filter includes an Al(NO3)3 film, and the carbon dioxide filter includes an AlGaS film.

[0043] In the present disclosure, the reference comparison filter is used for reference comparison, which can eliminate external environmental interference. In addition, by selecting different filter film materials to realize the integration of the same chip, the concentration of multiple different types of gases can be detected, and the TO package of external discrete devices can be omitted. The use of chip-level integrated packaging can reduce the size and facilitate customer installation and use. At the same time, because it is an integrated wafer preparation process, the process is controllable, and thus the consistency of the integrated device is controllable.

[0044] refer to Figure 20-24 In some embodiments, the gas sensor chip further includes a resonant cavity array structure 20. The resonant cavity array structure 20 is disposed on the lower surface of the chip body, and the resonant cavity array structure 20 forms an array of pits of different depths. The substrate of the chip body forms a back cavity, and the back cavity corresponds to the central hot end position of the chip body, wherein a reflective layer is provided on the surface of the pit, the pit and the back cavity are disposed correspondingly, and the pit and the back cavity together constitute a resonant cavity.

[0045] In the present disclosure, different infrared bands and wavelengths are required for the detection of different gas concentrations, and thus different heights of the selected resonant cavities are selected. The present disclosure sets pits of different depths so that they form resonant cavities of different heights with the back cavity, which can realize the detection of multiple gases. Furthermore, the reflection effect of the reflective layer causes the light to propagate back and forth in the resonant cavity, so that the light energy of the narrow-band filter passing through is continuously enhanced, forming self-excited oscillation, thereby further increasing the reception and convergence of the weak light intensity emitted by the light source at the center of the chip, thereby enhancing the sensitivity of the chip to specific gas detection.

[0046] Furthermore, the filter is corresponding to the position of the pit, and different filters are arranged for pits of different depths. This arrangement can be used to detect a variety of gases.

[0047] In some embodiments, the dimples include dimple 117 , dimple 118 , and dimple 119 .

[0048] In a specific example, the pit 117 is arranged corresponding to the methane filter, the pit 118 is arranged corresponding to the reference comparison filter, and the pit 119 is arranged corresponding to the carbon dioxide filter.

[0049] In some embodiments, reference Fig.16 and Fig. 22 The back cavity 45 is convex, and the back cavity 45 and the pit together constitute a concave-convex resonant cavity 13.

[0050] In the present disclosure, the concave-convex resonant cavity formed by the convex surface of the back cavity 45 and the concave surface of the substrate bottom of the chip body 11 can significantly enable light to propagate back and forth in the resonant cavity, so that the energy of the transmitted narrowband light is continuously enhanced, forming self-excited oscillation, further increasing the reception and convergence of the weak light intensity emitted by the light source in the center of the chip, thereby enhancing the chip's sensitivity to specific gas detection.

[0051] In some embodiments, reference Fig. 20 , the pit array includes pits of different depths.

[0052] In some embodiments, the pit depth is 1 / 4λ to 3 / 4λ, where λ is the wavelength of the infrared band.

[0053] In the present disclosure, the pits of different depths correspond to different infrared bands and wavelengths required for the detection of various gas concentrations, and thus different heights of the resonant cavity. Furthermore, resonant cavities of different heights are selected to form self-excited oscillations, thereby increasing the reception and convergence of the weak light intensity emitted by the infrared light source at the center of the chip.

[0054] In some embodiments, reference Figure 12-16 and Figure 22-24 The chip body 11 includes a semiconductor structure layer and a CMOS device structure and a MEMS device structure integrated in the semiconductor structure layer.

[0055] The MEMS device structure includes a plurality of thermocouple pairs formed in the semiconductor structure layer. The thermocouple pairs include a cold-end thermocouple pair and a hot-end thermocouple pair. The hot-end thermocouple pair is arranged at the hot end in the center of the chip body.

[0056] Among them, a cold-end thermocouple pair is connected to the drain of the CMOS device structure as a positive electrode, and another cold-end thermocouple pair is connected to the P+ contact GND terminal as a negative electrode, and the gate is connected to the multiplexer (also called signal multiplexer) of the peripheral circuit. Among them, the multiplexer (signal multiplexer (MUX) 122) is used to realize chip channel selection for the gas chip array. Specifically, the CMOS device structure uses the signal multiplexer (MUX) 122 to select and control the MEMS thermopile gas chip by adjusting the gate 30 voltage of different monomers in the array, thereby selectively detecting different gas concentrations.

[0057] Specifically, the chip body 11 includes a semiconductor structure layer and a CMOS device structure and a MEMS device structure integrated in the semiconductor structure layer. The semiconductor structure layer includes a substrate and a support layer stacked on the substrate, an oxide layer 41 and a passivation layer 44 .

[0058] refer to Figure 11-14 The CMOS device structure includes a P-well structure 24 formed on a substrate, a source 29 , a gate 30 , a drain 31 and a P+ contact GND terminal 36 .

[0059] Specifically, the MEMS device structure includes a thermopile formed on a support layer, and the thermopile includes a plurality of thermocouple pairs.

[0060] Among them, one cold-end thermocouple is connected to the drain 31 as the positive electrode, the other cold-end thermocouple is connected to the P+ contact GND terminal 36 as the negative electrode, and the gate 30 is connected to the multiplexer of the peripheral circuit.

[0061] In the present disclosure, the thermopile gas chip is integrated with the CMOS-MEMS process, and the designed CMOS device is integrated with the thermopile process. The CMOS device can be innovatively used to select and control the MEMS thermopile gas chip, thereby realizing the detection of different types of gas concentrations by different monomers in the array.

[0062] In some embodiments, a CMOS device structure and a MEMS device structure array are integrated on the gas sensor.

[0063] In some embodiments, reference Fig.12 The support layer includes a first support layer 25, a second support layer 26 and a third support layer 27 stacked on the substrate in sequence. The first support layer 25 is used as an oxide layer of the gate 30, and the third support layer 27 is used as a field oxygen wet oxide layer for electrical isolation between CMOS device structures.

[0064] In some embodiments, the stress of the first supporting layer 25 and the third supporting layer 27 is opposite to that of the second supporting layer 26 .

[0065] Specifically, for the MEMS device structure, the three supporting layers are prepared to improve the stress of the supporting film layer by making the stress of the first supporting layer 25 and the third supporting layer 27 reverse to that of the second supporting layer 26. For the CMOS device structure, the first supporting layer 25 can be used as the gate 30 oxide layer, the third supporting layer 27 can be used as the field oxygen wet oxide layer for electrical isolation between CMOS device structures, and the second supporting layer 26 can be used as a blocking mask layer for the growth of the third supporting layer 27.

[0066] In some embodiments, the first supporting layer 25 is a silicon oxide supporting layer, the second supporting layer 26 is a silicon nitride supporting layer, and the third supporting layer 27 is a silicon oxide supporting layer.

[0067] refer to Figure 1-8 In one embodiment of the present disclosure, a method for preparing a gas chip having a lens is provided, comprising:

[0068] S101, preparing a silicon lens array structure 10;

[0069] S102, preparing a chip body 11;

[0070] S103 , integrating the silicon lens array structure 10 and the chip body 11 ; wherein the lens of the silicon lens array structure 10 corresponds to the position of the central hot end of the chip body 11 .

[0071] In some embodiments, the step S101 of preparing the silicon lens array structure 10 includes:

[0072] S1011, providing a silicon substrate 1, and performing cleaning and thinning processes.

[0073] In some embodiments, reference Figure 1 , the silicon substrate 1 is a P-type double-polished silicon wafer. Further, the P-type double-polished silicon wafer is placed in acetone, anhydrous ethanol and deionized water for ultrasonic treatment for 5 minutes respectively according to the standard, and after ultrasonic treatment, the silicon wafer is placed on a hot plate and heated at 100° C. for half an hour. The above cleaning treatment can remove pollutants and dust particles on the surface of the silicon wafer.

[0074] Furthermore, after cleaning, the silicon wafer is thinned to a thickness of 400-600 um, wherein a preset number of the thinned silicon wafers are prepared for use as required.

[0075] S1012. Etching the surface of the silicon substrate using a femtosecond laser processing technique to form a lens array on the silicon substrate.

[0076] In some embodiments, the cleaned and thinned silicon wafer (silicon substrate 1) is placed on a high-precision three-dimensional moving platform, and a laser with a wavelength of 800 nm, a laser pulse width of 100 to 300 fs, a repetition frequency of 1 to 3 kHz, a pulse number of 100 to 200, and a laser energy range of 50 to 100 nJ / cm 2 The linearly polarized femtosecond laser is focused onto the surface of the silicon wafer through an objective lens with a numerical aperture of 0.8 (magnification of 80 times).

[0077] Further, refer to Figure 2 , through the movement of the three-dimensional mobile platform, a microporous structure array with a certain arrangement is prepared on the surface of the silicon wafer. Specifically, after laser modification at a specific position, the sample is ultrasonically treated in deionized water for 5 minutes to remove the particles generated by surface laser ablation and scattered on the sample surface. After removing the surface particles, a preliminary solid pit array 2 is formed inside the silicon wafer.

[0078] Furthermore, after laser modification, the silicon wafer with the solid pit array 2 is placed in an etching chamber of an inductively coupled plasma etching system (ICP) and dry-etched in a plasma environment of SF6 gas. ICP is selected because of its controllability in lateral and longitudinal etching.

[0079] In some embodiments, the upper RF source power and the lower RF source power of the etching system are adjustable in the range of 400-500 W and 200-300 W, respectively, and the gas flow rate is 40-100 sccm.

[0080] In some embodiments, the etching process includes two stages, firstly, the rapid etching of the solid pit array 2 in the laser modified area in the initial stage, and then the process of the concave structure expanding as the etching time increases. The rapid etching of the solid pit array 2 in the laser modified area in the initial stage lasts for 3 to 5 minutes.

[0081] refer to Figure 3 During the process of laser ablation to form the solid pit array 2 in the laser modified area, oxygen in the air will react with silicon atoms to form silicon oxide, and the crystal type of the silicon lattice in the ablated area will also change from a single crystal state to a polycrystalline or amorphous state. Therefore, in the first 3 to 5 minutes of etching, the solid pit array 2 in the laser modified area is quickly etched away, and the etching depth will quickly reach a maximum value. In the initial stage of etching, the solid pit array 2 in the laser modified area is quickly etched away to form a hollow pit array 3, because the etching rate of the modified area is faster than that of the unmodified area, about 4 to 8 times.

[0082] Further, refer to Figure 4In the expansion stage, the size of the microporous structure increases with the increase of etching time, and gradually expands to form a concave lens 4. Specifically, the silicon substrate has a first surface and a second surface opposite to each other, wherein the concave lens array is formed on the first surface.

[0083] In some embodiments, the etching time of the etching expansion phase is 5 to 50 minutes.

[0084] When the etching time is between 5 and 20 minutes, the lateral size of the concave lens increases approximately linearly with the increase of etching time. Therefore, with the increase of etching time, the lateral etching rate is relatively stable. And as the etching time increases to 20 to 50 minutes, the surface of the concave structure becomes smoother and smoother.

[0085] In the above etching process, as the etching time increases, the etching depth will gradually decrease and gradually tend to be constant. This is caused by aspect ratio dependent etching (ARDE, or aperture effect). The aperture effect will cause insufficient local gas supply and untimely discharge of the reflected product, thereby causing the etching rate at the bottom of the concave lens 4 to decrease, while the external etching rate is not affected at all. As the etching time increases, the aspect ratio of the concave lens 4 will gradually decrease, so the aperture effect will also be weakened accordingly, so the etching depth will gradually tend to be constant.

[0086] S1013, integrating a filter on the surface of the silicon substrate 1 opposite to the lens array to prepare a silicon lens array structure 10. The filter corresponds to the position of the lens and is used to gather the energy of the external infrared light source to the central hot end of the chip body.

[0087] Specifically, refer to Figure 5 A layer of photoresist is coated on the bottom silicon plane of the silicon substrate 1 and a photolithography process is performed to form a photoresist 5 structure as a mask structure for subsequent filter integration. Specifically, the bottom surface is the second surface of the silicon substrate 1 .

[0088] refer to Figure 6 , a layer of AgF thin film structure 6 with a thickness of 400-700nm or a layer of MgF2 thin film structure with a thickness of 800-1400nm is deposited on the second surface of the silicon substrate 1. Both functional materials have high transmittance to the 3.43um infrared band. Since methane gas has a strong absorption characteristic for infrared light in the 3.43um band, the concentration of methane gas can be detected by feedback of the infrared light energy in the 3.43um band from the gas chip.

[0089] Therefore, integrating a filter with a high transmittance in a specific infrared band on the surface of the gas sensitive chip can greatly improve the detection sensitivity. At the same time, different gases absorb different infrared bands, so this method has high selectivity in detecting gas concentration. And here, integrating a specific 3.43um infrared band high transmittance filter film 6 can detect the methane gas concentration.

[0090] refer to Figure 7 , in the same way, Al(NO3)3 film 7 with a thickness of 400-800nm ​​and AlGaS film 8 with a thickness of 500-1000nm are deposited on the surface of the silicon substrate 1 to prepare a silicon lens array structure 10. These two functional materials have high transmittance in the infrared bands of 3.95um and 4.26um respectively. Most gases do not absorb infrared light in the 3.95um band, and only water vapor absorbs a large amount of infrared light in the 3.95um band. Therefore, the Al(NO3)3 film 7 functional material is used as a reference to eliminate external environmental interference. Carbon dioxide gas has a strong absorption characteristic for infrared light in the 4.26um band, because the concentration of carbon dioxide gas can be detected by feedback of the infrared light energy in the 4.26um band by the gas chip. Therefore, the functionality of the three functional materials on the surface of the silicon substrate 1 is a monomer for detecting the concentration of methane gas, a reference monomer, and a monomer for detecting the concentration of carbon dioxide gas.

[0091] In some embodiments, the invention further comprises: S1014, integrating the silicon lens array structure 10 with the integrated filter film with the chip body 11 through the optical adhesive 9 for SOC integration. The chip body 11 is an NDIR infrared gas sensor chip array. Figure 8 .

[0092] Specifically, the first step is to perform ultra-precision polishing on the bonding surface of the integrated device. The bonding surface of the silicon lens array structure 10 is the front side relative to the lens surface on both sides, and the bonding surface of the NDIR infrared gas sensor chip array is the heat-sensitive surface facing up. The second step is to perform constant temperature treatment on the silicon lens array structure 10 and the NDIR infrared gas sensor chip array that are about to be photo-bonded. Place the two photo-bonded parts in an environment of 50-100°C and keep the temperature constant for about 3 hours to make the device temperature uniform, which is conducive to the firmness of the photo-bonded parts. The third step is to clean the photo-bonded parts. Use soft materials in the same environment to clean the photo-bonded surface, and cover it with a dust-free glass cover after cleaning. The fourth step is to apply a certain amount of pressure on the two devices to achieve photo-bonding, and then apply a thin layer of photosensitive glue on the outside of the contact edge of the photo-bonded surface to enhance the photo-bonded effect.

[0093] In another embodiment of the present disclosure, a method for preparing an array chip for detecting multiple gases is provided, comprising:

[0094] S201, preparing a silicon lens array structure 10;

[0095] S202, preparing a chip body 11;

[0096] S203, preparing a resonant cavity array structure 20;

[0097] S204 , integrating the silicon lens array structure 10 , the resonant cavity array structure 20 and the chip body 11 .

[0098] In some embodiments, the step S202 of preparing the chip body 11 includes:

[0099] S2021. Provide a substrate 21.

[0100] In some embodiments, reference Fig. 9 The substrate 21 is a P-type double-polished silicon wafer, which is cleaned and thinned.

[0101] In some embodiments, the P-type double-polished silicon wafer is placed in acetone, anhydrous ethanol and deionized water for ultrasonic treatment for 5 minutes respectively according to the standard, and the silicon wafer is placed on a hot plate and heated at 100° C. for half an hour after ultrasonic treatment. The above cleaning treatment can remove pollutants and dust particles on the surface of the silicon wafer.

[0102] Furthermore, after cleaning, the silicon wafer is thinned to a thickness of 400-600 um, wherein a preset number of the thinned silicon wafers are prepared for use as required.

[0103] In some embodiments, reference Fig.10 , a barrier layer 22 is implanted on the upper surface of the substrate 21 by a thermal oxidation (dry oxygen) process, wherein the thermal oxidation current is 500 to 1000A.

[0104] In some embodiments, the structure layer consisting of the substrate 21 and the barrier layer 22 is subjected to photolithography.

[0105] Specifically, refer to Fig.11 A layer of photoresist 23 is coated on the surface of the barrier layer 22, wherein the photoresist 23 exposes the CMOS region of the substrate 21. Further, boron ions are implanted into the CMOS region to form a lightly doped P-well structure 24, and the photoresist 23 is removed.

[0106] S2022, sequentially forming an upper support layer, an oxide layer 41 and a passivation layer 44 on the substrate 21 to prepare a semiconductor structure layer.

[0107] Further, refer to Fig.12 The supporting layer includes a first supporting layer 25 , a second supporting layer 26 and a third supporting layer 27 .

[0108] In some embodiments, the first supporting layer 25 is a silicon oxide supporting layer, the second supporting layer 26 is a silicon nitride supporting layer, and the third supporting layer 27 is a silicon oxide supporting layer.

[0109] In some embodiments, forming a support layer on the substrate 21 includes: performing a thermal oxidation process again on the surface of the structural layer composed of the substrate 21 and the barrier layer to deposit a first support layer 25 with a thickness of 0.1 to 5 um, and using front low-pressure chemical vapor deposition on the surface of the first support layer 25 to deposit a second support layer 26 with a thickness of 0.01 to 0.5 um and a third support layer 27 with a thickness of 0.01 to 0.5 um.

[0110] In the present disclosure, for the MEMS device structure, three support layers are prepared by the stress reversal of silicon nitride and silicon oxide to improve the stress of the support film layer. For the CMOS device structure, the first support layer 25 can be used as the gate 30 oxide layer, the third support layer 27 can be used as a field oxygen wet oxide layer for electrical isolation between CMOS devices, and the second support layer 26 can be used as a blocking mask layer for the growth of the third support layer 27.

[0111] S2023. Fabricate a CMOS device structure and a MEMS device structure on the semiconductor structure layer.

[0112] Specifically, refer to Fig.13 A layer of polysilicon 28 with a thickness of 0.1 to 2 um is sputtered on the surface of the third supporting layer 27 by using a plasma enhanced chemical vapor deposition process, and phosphorus ions are doped by ion implantation and diffusion to form an N-type polysilicon semiconductor.

[0113] Further, a source 29, a gate 30 and a drain 31 of the CMOS device structure are formed on the structural layer composed of the substrate 21 and the support layer by a heavy doping process. A thermopile of the MEMS device structure is formed on the polysilicon 28 by a heavy doping process, wherein the gas chip thermopile of the MEMS device structure includes a cold end thermocouple 32 and a cold end thermocouple 35 of another thermocouple pair, and the gas chip thermopile also includes a hot end thermocouple 33 and a hot end thermocouple 34 of another thermocouple pair.

[0114] Furthermore, boron ions are doped into the polysilicon 28 by ion implantation and diffusion to form a P-type polysilicon semiconductor.

[0115] Further, refer to Fig.14, a P+ contact GND terminal 36 of the CMOS tube is formed on the structural layer composed of the substrate 21 and the support layer by a heavy doping process, which is used to provide a low-impedance connection point for the CMOS tube and suppress the reverse breakdown of the source-drain junction and the generation of leakage current. At the same time, a gas chip thermopile cold-end thermocouple 37 and a cold-end thermocouple 40 of another thermocouple pair, a gas chip thermopile hot-end thermocouple 38 and a hot-end thermocouple 39 of another thermocouple pair are formed on the polysilicon 28 by a heavy doping process. Among them, the hot-end thermocouple 38 (P-type polysilicon) and the hot-end thermocouple 33 (N-type polysilicon) form a pair of hot-end thermocouple pairs. The hot-end thermocouple 39 (P-type polysilicon) and the hot-end thermocouple 34 (N-type polysilicon) form a pair of hot-end thermocouple pairs. The cold-end thermocouple 37 (P-type polysilicon) and the cold-end thermocouple 32 (N-type polysilicon) form a pair of cold-end thermocouple pairs. The cold-end thermocouple 40 (P-type polysilicon) and the cold-end thermocouple 35 (N-type polysilicon) form a hot-end thermocouple pair.

[0116] In some embodiments, the thermocouples are connected in series via Al metal, and the potential is accumulated to form a highly sensitive thermopile, wherein the infrared gas chip formed by the thermopile can provide instant feedback on infrared light energy.

[0117] In some embodiments, reference Fig.15 A layer of silicon oxide with a thickness of 0.01 to 10 um is deposited on the polysilicon 28 by plasma enhanced chemical vapor deposition to form a top oxide layer 41 for electrical insulation.

[0118] In some embodiments, a layer of metal aluminum with a thickness of 100 to 500 nm is deposited by magnetron sputtering, and photolithography is performed to form a wire layer 42. The wire layer 42 is used to connect the thermocouple pairs of each MEMS part, and at the same time connect the cold end thermocouple 37 (positive electrode) of the MEMS gas chip to the drain 31 of the CMOS part.

[0119] Furthermore, a layer of silicon nitride with a thickness of 0.01-10 um is deposited on the surface of the oxide layer 41 by plasma enhanced chemical vapor deposition to form a passivation layer 44 .

[0120] In some embodiments, continue to refer to Fig.15 , a layer of tungsten gold with a thickness of 100 to 500 nm is deposited by secondary magnetron sputtering as the PAD layer 43 metal, and the PAD layer 43 metal is leaked out and connected to the peripheral board-level circuit. Further, refer to Fig.16 The silicon substrate 21 is etched on the bottom surface by deep silicon etching to form a back cavity 45, so as to release the central hot end position of the device, form a back release cavity, and complete the production of the MEMS gas chip, wherein the back cavity 45 is used to reduce the heat loss of the central hot end, thereby forming a temperature difference between the hot and cold ends.

[0121] In some embodiments, two layers of tungsten gold are used to connect the cold end thermocouple 35 (negative pole) of the MEMS gas chip to the P+ contact GND terminal 36 of the CMOS part in an array, forming a MEMS gas sensor chip integrating an electronic switch CMOS tube, wherein the thermopile monomers and the CMOS devices are connected one-to-one.

[0122] Furthermore, the array gate 30 is connected in parallel to the peripheral circuit multiplexer MUX, and the gate 30 voltages of different monomers in the array are adjusted to selectively detect different gas concentrations. When the gate 30 supply voltage is greater than the threshold voltage, these electrons form an N-type thin layer on the surface of the P substrate 21 near the gate 30, and are connected to the two N+ regions, forming an N-type conductive channel between the drain and source. At this time, the CMOS tube is in the on state, otherwise, it is in the off state.

[0123] In some embodiments, the step S203 of preparing the resonant cavity array structure 20 includes:

[0124] S2031, provide a P-type double-polished silicon wafer 110, and perform cleaning and thinning treatment. Fig.17 .

[0125] In some embodiments, the P-type double-polished silicon wafer 110 is placed in acetone, anhydrous ethanol and deionized water for ultrasonic treatment for 5 minutes respectively according to the standard, and then the silicon wafer is placed on a hot plate and heated at 100° C. for half an hour. The above cleaning treatment can remove pollutants and dust particles on the surface of the silicon wafer.

[0126] Furthermore, after cleaning, the silicon wafer is thinned to a thickness of 400-600 um, wherein a preset number of the thinned silicon wafers are prepared for use as required.

[0127] S2032. Etch the surface of the silicon wafer using a femtosecond laser processing technique to form a pit array on the silicon wafer.

[0128] Specifically, refer to Fig.18 The cleaned and thinned silicon wafer 110 is placed on a high-precision three-dimensional mobile platform, and a laser with a wavelength of 800nm, a pulse width of 100-300fs, a repetition frequency of 1-3KHz, a pulse number of 20-50, and a laser energy range of 20 to 50nJ / cm 2 The solid pit 111 is prepared by linearly polarized femtosecond laser. The pulse number is 100 to 200 and the laser energy ranges from 50 to 100 nJ / cm 2 The solid pit 112 is prepared by linearly polarized femtosecond laser. The pulse number is 300 to 500 and the laser energy ranges from 100 to 150 nJ / cm 2Solid pits 113 were prepared using linearly polarized femtosecond laser.

[0129] In some embodiments, reference Fig.19 The laser-modified silicon wafer 110 is placed in an etching chamber of an inductively coupled plasma etching system (ICP) and dry-etched in a plasma environment of SF6 gas to form hollow pits 114, 115, and 116. Fig. 20 The etching duration is 20 to 50 minutes to form pits 117, 118 and 119 of different depths.

[0130] S2033, forming a reflective layer on the surface of the pit.

[0131] Specifically, refer to Fig.21 A metal reflective layer 125 of aluminum-chromium alloy with a thickness of 300-500 nm is deposited on the silicon concave surface of the pit by LPCVD to complete the preparation of the resonant cavity array structure 20. The resonant cavity array structure 20 is a solid bottom silicon structure.

[0132] Aluminum-chromium alloy can reflect more than 90% of infrared light, increase the heat of the hot end of the gas chip, and thus improve the sensitivity of gas concentration detection. The pits of different depths are because the infrared bands and wavelengths required for the detection of different gas concentrations are different, and thus the height of the bottom selected as the resonant cavity is different.

[0133] In some embodiments, the height of the resonant cavity is generally 1 / 4λ to 3 / 4λ, where λ is the wavelength of the infrared band. The wavelengths selected in the present disclosure are 3.43um, 3.95um, and 4.26um, respectively, so resonant cavities of different heights are selected to form self-excited oscillations, thereby increasing the reception and convergence of the weak light intensity emitted by the infrared light source at the center of the chip.

[0134] In some embodiments, reference Fig. 22 The resonant cavity array structure 20 is SOC integrated with the chip body 11 through an optical adhesive 120, wherein the chip body 11 is an NDIR gas sensor chip.

[0135] In some embodiments, reference Fig.23 The gate 30 of the electronic switch CMOS of the gas chip array integrated with the resonant cavity array structure 20 is connected to the signal multiplexer (MUX) 122 through the gold wire 121, and the signal multiplexer (MUX) 122 is used to select the chip channel of the gas chip array.

[0136] Further, the entire chip array is fixed and packaged on the bottom PCB board 124 using a mounting glue 123, and the bottom is a resonant cavity array structure 20 base structure. In the present disclosure, compared with the back cavity structure, in actual use, the solid bottom silicon structure is more convenient for WLP packaging, which improves the overall reliability and practicality of the gas chip array. Further, refer to Fig.24 The silicon lens array structure 10, the chip body 11 and the resonant cavity array structure 20 are packaged to prepare a gas sensor chip with integrated silicon lens.

[0137] In some embodiments, reference Fig.25 , Fig.25 The SOC integrated infrared light incident effect diagram of the silicon micro-concave lens with integrated filter, the bottom reflective layer and the NDIR infrared gas sensor chip. In the figure, the design disclosed in the present invention can make the infrared light energy emitted by the infrared light source concentrated at the hot end as much as possible, and the micro-concave lens and the bottom concave-convex resonant cavity can focus the energy of the infrared light source on the sensitive area of ​​the infrared chip, improve the chip output, and then improve the gas concentration detection sensitivity.

[0138] It is to be understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of the present disclosure, but the present disclosure is not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and substance of the present disclosure, and these modifications and improvements are also considered to be within the scope of protection of the present disclosure.

Claims

1. A gas sensor chip having a lens, characterized in that: The chip comprises a silicon lens array structure and a chip body; the silicon lens array structure comprises a silicon substrate and a plurality of filters; the silicon substrate has a first surface and a second surface opposite to each other, the first surface is formed with a lens array; the second surface of the silicon substrate is provided with the filters; the lens is provided correspondingly to the position of the filters; The first surface of the silicon substrate is integrally connected to the upper surface of the chip body; wherein the lens corresponds to the position of the central hot end of the chip body, and is used to gather the energy of the external infrared light source to the central hot end of the chip body.

2. The chip according to claim 1, characterized in that: The lens array includes a concave lens array.

3. The chip according to claim 1, characterized in that: The optical filters include a methane filter, a reference comparison filter and a carbon dioxide filter; the methane filter includes an AgF film or a MgF2 film; the reference comparison filter includes an Al(NO3)3 film; and the carbon dioxide filter includes an AlGaS film.

4. The chip according to claim 1, characterized in that: Also includes: A resonant cavity array structure is arranged on the lower surface of the chip body; the resonant cavity array structure is formed with a pit array; The substrate of the chip body is formed with a back cavity, and the back cavity corresponds to the central hot end position of the chip body; Among them, a reflective layer is provided on the surface of the pit; the pit and the back cavity are arranged correspondingly, and the pit and the back cavity together constitute a resonant cavity.

5. The chip according to claim 4, characterized in that: The back cavity is convex; the back cavity and the pit together form a concave-convex resonant cavity.

6. The chip according to claim 4, characterized in that: The dimple array includes dimples of varying depths.

7. The chip according to claim 4, characterized in that: The pit depth value is 1 / 4λ to 3 / 4λ, wherein λ is the wavelength of the infrared band.

8. The chip according to claim 1, characterized in that: The chip body comprises a semiconductor structure layer and a CMOS device structure and a MEMS device structure integrated in the semiconductor structure layer.

9. The chip according to claim 8, characterized in that: The semiconductor structure layer includes a substrate and a support layer, an oxide layer and a passivation layer stacked on the substrate; The support layer includes a first support layer, a second support layer and a third support layer stacked sequentially on the substrate; wherein the first support layer is used as an oxide layer of the gate of the CMOS device structure; the third support layer is used as a field oxygen wet oxide layer for electrical isolation between the CMOS device structures.

10. The chip according to claim 9, characterized in that: The material of the first supporting layer and the third supporting layer includes silicon oxide; the material of the second supporting layer includes silicon nitride.

Images