Power management chip and electronic device

Abstract

The utility model relates to a power management chip and electronic equipment. The power management chip comprises: a functional circuit; the packaging layer is used for packaging the functional circuit; the plurality of interfaces are located on the packaging layer and are electrically connected with the functional circuit; wherein the plurality of interfaces are arranged in an array along the row direction and the column direction, and the plurality of interfaces comprise a first type of interfaces, a second type of interfaces and a third type of interfaces located between the first type of interfaces and the second type of interfaces; the first type of interface comprises a plurality of interface columns which are at least used for being connected with a power supply output signal and an external circuit with a power buffering function; the second type of interface comprises at least one interface column which is at least used for connecting data input and / or output signals; and the third type of interface comprises a plurality of interface columns arranged along the column direction and is at least used for connecting a power input signal.

Description

Technical Field

[0001] The present disclosure relates to the field of computer communications, and in particular to a power management chip and an electronic device. Background Art

[0002] As electronic devices become smaller, lighter and more intelligent, users have higher requirements for the battery life of these electronic devices while their functions meet their various needs. Electronic devices consume power faster and faster, and are limited by the battery capacity in electronic devices. Batteries cannot provide long-term battery life. Therefore, it is necessary to optimize power management chips to improve the power supply efficiency of batteries in electronic devices. Utility Model Content

[0003] In order to overcome the problems existing in the related art, the present disclosure provides a power management chip and an electronic device.

[0004] According to a first aspect of an embodiment of the present disclosure, a first power management chip is provided, comprising: a functional circuit; a packaging layer, encapsulating the functional circuit; and a plurality of interfaces, located on the packaging layer and electrically connected to the functional circuit; wherein the plurality of interfaces are arranged in an array along row and column directions, and the plurality of interfaces include a first type of interface, a second type of interface, and a third type of interface located between the first type of interface and the second type of interface; the first type of interface includes a plurality of interface columns, at least for connecting a power output signal and for connecting an external circuit with a power buffering function; the second type of interface includes at least one interface column, at least for connecting a data input and / or output signal; the third type of interface includes a plurality of interface columns arranged along the column direction, at least for connecting a power input signal.

[0005] In some embodiments, the first type of interface includes a plurality of interface columns including a first interface column and a second interface column; the first interface column is used to connect a power output signal; and the second interface column is used to connect a ground signal.

[0006] In some embodiments, the first type of interface also includes interfaces located on both sides of the first interface column and used to connect the power input-output ratio signal; the interface for connecting the power input-output ratio signal is also located in the center interface row; the power input-output ratio signal is used to characterize the ratio of the power input signal to the power output signal.

[0007] In some embodiments, the external circuit includes a flying capacitor; the flying capacitor includes a first flying capacitor and a second flying capacitor; the first type of interface includes a plurality of interface columns including a third interface column, a fourth interface column and a fifth interface column; the third interface column, the fourth interface column and the fifth interface column each include a plurality of parts symmetrical with respect to a central interface row; wherein the first part of the third interface column is used to connect a first electrode and a first phasor of the first flying capacitor, the second part is used to connect a second electrode and a second phasor of the first flying capacitor, the third part is used to connect a first electrode and a second phasor of the first flying capacitor, and the fourth part is used to connect a second electrode and a first phasor of the first flying capacitor; the first part of the fourth interface column is used to connect a first electrode and a first phasor of the second flying capacitor, and the second part is used to connect a first electrode and a second phasor of the second flying capacitor; the first part of the fifth interface column is used to connect a second electrode and a first phasor of the second flying capacitor, and the second part is used to connect a second electrode and a second phasor of the second flying capacitor.

[0008] In some embodiments, the first interface column, the second interface column, the third interface column, the fourth interface column and the fifth interface column are arranged adjacent to each other, and one of the first interface column, the second interface column, the third interface column, the fourth interface column and the fifth interface column is located at an edge position of multiple interfaces arranged in an array.

[0009] In some embodiments, the second type of interface includes a sixth interface column; the sixth interface column includes an interface for connecting an I2C communication signal, an interface for connecting a clock signal, and an interface for connecting a data input and / or output signal.

[0010] In some embodiments, the sixth interface column also includes at least one of the following multiple interfaces: an interface for connecting a voltage detection signal, including an interface for a negative input for battery voltage sensing and an interface for a positive input for battery voltage sensing; an interface for connecting a low power mode enable signal; an interface for connecting a state change alarm signal; and an interface for connecting a low voltage difference signal.

[0011] In some embodiments, an interface for connecting an I2C communication signal, an interface for connecting a voltage detection signal, an interface for connecting a low power mode enable signal, and an interface for connecting a state change alarm signal are all located at the edge of a plurality of interfaces arranged in an array.

[0012] In some embodiments, the third type of interface includes two parts; the two parts are symmetrical with respect to the center interface row; a plurality of interfaces arranged along the column direction include adjacent seventh interface columns and eighth interface columns; the external circuit includes a switching capacitor; wherein the seventh interface column is used to connect the input signal and ground signal of the switching capacitor power stage; the eighth interface column is used to connect the power supply input signal.

[0013] In some embodiments, the third type of interface also includes multiple analysis interfaces located in the center interface row and the eighth interface column; the multiple analysis interfaces are arranged in the middle position among the multiple interfaces, and are used to connect bootstrap capacitors for problem analysis; the seventh interface column also includes an auxiliary interface and an address allocation interface, both of which are arranged at the edge position among the multiple interfaces; the auxiliary interface includes an interface for connecting to the first power line and an interface for connecting to the second power line; the address allocation interface is used to allocate the address of the power management chip during power-on reset. In some embodiments, the sixth interface column also includes: an interface for connecting a wireless input sensing signal, adjacent to an interface for connecting an input signal of a switched capacitor power stage; an interface for connecting a USB input sensing signal, adjacent to an interface for connecting an input signal of a switched capacitor power stage; an interface for connecting a charge pump output signal of a USB input sensing signal, adjacent to an interface for connecting an input signal of a switched capacitor power stage, or adjacent to an interface for connecting an input signal of a wireless input sensing signal; an interface for connecting an analog ground signal, spaced from a ground signal of an input signal of a switched capacitor power stage; the seventh interface column also includes: an interface for connecting a charge pump output signal of a wireless input sensing signal, adjacent to an interface for connecting an input signal of a switched capacitor power stage, and arranged at an edge position among the multiple interfaces.

[0014] In some embodiments, the power management chip includes a charge pump charging chip.

[0015] According to a second aspect of an embodiment of the present disclosure, a second power management chip is provided, characterized in that it includes: a functional circuit; a packaging layer encapsulating the functional circuit; and a plurality of interfaces, which are located on the packaging layer and electrically connected to the functional circuit, including a first interface column to an eighth interface column arranged in an array along the row direction and the column direction; wherein the first interface column is used to connect a ground signal; a first part of the second interface column is used to connect a first electrode and a first phasor of a second flying capacitor of an external circuit, and a second part is used to connect the first electrode and the second phasor of the second flying capacitor, and a central interface row of the second interface column is used to connect a second power supply input-output ratio signal; wherein the first of the second interface column The first part of the fourth interface column and the second part of the second interface column are located on both sides of the center interface row; the third interface column is used to connect the power supply output signal; the first part of the fourth interface column is used to connect the second electrode and the first phasor of the second flying capacitor, and the second part is used to connect the second electrode and the second phasor of the second flying capacitor, and the center interface row of the fourth interface column is used to connect the first power supply input-output proportional signal; wherein the first part of the fourth interface column and the second part of the fourth interface column are located on both sides of the center interface row; the first part of the fifth interface column is used to connect the first electrode and the first phasor of the first flying capacitor of the external circuit, and the second part is used to connect the second electrode and the second phasor of the first flying capacitor The first part of the sixth interface column is used to connect the first electrode and the second phase of the first flying capacitor, the fourth part is used to connect the second electrode and the first phase of the first flying capacitor, and the central interface row of the fifth interface column is used to connect the bootstrap capacitor of the external circuit; wherein the second part of the fifth interface column and the fourth part of the fifth interface column are located on both sides of the central interface row, the first part of the fifth interface column is located outside the second part of the fifth interface column, and the third part of the fifth interface column is located outside the fourth part of the fifth interface column; the first part and the second part of the sixth interface column are used to connect the input signal of the switch capacitor power stage of the external circuit, and the third part and the fourth part of the sixth interface column are used to connect the input signal of the switch capacitor power stage of the external circuit. The ground signal of the external circuit is connected, and the central interface row of the sixth interface column is used to connect the bootstrap capacitor of the external circuit; wherein the first part of the sixth interface column and the second part of the sixth interface column are located on both sides of the central interface row, the third part of the sixth interface column is located outside the first part of the sixth interface column, and the fourth part of the sixth interface column is located outside the second part of the sixth interface column; the first part of the seventh interface column is used to connect the bootstrap capacitor of the external circuit, the second part and the third part are used to connect the power input signal, the fourth part is used to connect the first auxiliary signal and the address allocation signal, and the fifth part is used to connect the second auxiliary signal and the charge pump output signal of the wireless input sensing signal;Among them, the first part of the seventh interface column is located on both sides of the central interface row and the central interface row, the second part and the third part of the seventh interface column are located on both sides of the first part of the seventh interface column and are adjacent to the first part and the second part of the sixth interface column, the fourth part of the seventh interface column is located outside the second part of the seventh interface column, and the fifth part of the seventh interface column is located outside the third part of the seventh interface column; the eighth interface column is used to connect the negative input signal of the battery voltage sensing, the positive input of the battery voltage sensing, the low power mode enable signal, the state change alarm signal, the data input and / or output signal, the clock signal, the low voltage difference signal, the analog ground signal, wireless input sensing signal, USB input sensing signal, and charge pump output signal of USB input sensing signal; wherein, the interface for connecting data input and / or output signal and the interface for connecting clock signal are located in the middle of the eighth interface column, the interface for connecting wireless input sensing signal and the interface for connecting USB input sensing signal are adjacent to the interface for connecting input signal of switch capacitor power stage, and the interface for connecting charge pump output signal of USB input sensing signal is adjacent to the interface for connecting input signal of switch capacitor power stage or adjacent to the interface of charge pump output signal of wireless input sensing signal. ;

[0016] According to a third aspect of an embodiment of the present disclosure, there is provided an electronic device comprising: a battery, a flying capacitor, a controller, a power supply and a power management chip of any one of the above-mentioned first aspects; wherein a first type of interface of the power management chip is connected to the battery and the flying capacitor, and is used to smooth the fluctuation of the power input signal input to the power management chip; a second type of interface of the power management chip is connected to the controller; and a third type of interface of the power management chip is connected to the power supply.

[0017] The technical solution provided by the embodiments of the present disclosure may have the following beneficial effects:

[0018] In each embodiment of the present disclosure, the power management chip includes: a functional circuit; a packaging layer, encapsulating the functional circuit; and a plurality of interfaces, located on the packaging layer and electrically connected to the functional circuit; wherein the plurality of interfaces are arranged in an array along the row direction and the column direction, and the plurality of interfaces include a first type of interface, a second type of interface, and a third type of interface located between the first type of interface and the second type of interface; the first type of interface includes a plurality of interface columns, at least for connecting a power output signal and for connecting an external circuit with a power buffering function; the second type of interface includes at least one interface column, at least for connecting a data input and / or output signal; the third type of interface includes a plurality of interface columns arranged along the column direction, at least for connecting a power input signal. In this way, the power density of the power management chip can be improved, the power management efficiency can be improved, and the cost can be reduced.

[0019] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0021] Figure 1 is a schematic diagram showing the arrangement of multiple interface arrays of a power management chip according to an exemplary embodiment Figure 1 ;

[0022] Figure 2 is a schematic diagram showing the arrangement of multiple interface arrays of a power management chip according to an exemplary embodiment Figure 2 ;

[0023] Figure 3 is a schematic diagram showing the arrangement of multiple interface arrays of a power management chip according to an exemplary embodiment Figure 3 ;

[0024] Figure 4 is a schematic diagram showing the arrangement of multiple interface arrays of a power management chip according to an exemplary embodiment Figure 4 ;

[0025] Figure 5 is a schematic diagram showing the arrangement of multiple interface arrays of a power management chip according to an exemplary embodiment Figure 5 ;

[0026] Figure 6 is a schematic diagram showing the arrangement of multiple interface arrays of a power management chip according to an exemplary embodiment Figure 6 ;

[0027] Figure 7 is a schematic diagram showing the arrangement of multiple interface arrays of a power management chip according to an exemplary embodiment Figure 7 ;

[0028] Figure 8 is a block diagram of an electronic device according to an exemplary embodiment;

[0029] Fig. 9 is a block diagram of a device according to an exemplary embodiment;

[0030] Fig.10 The figure is a hardware structure block diagram of a device according to an exemplary embodiment. DETAILED DESCRIPTION

[0031] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present disclosure. Instead, they are merely examples of devices and methods consistent with some aspects of the present disclosure as detailed in the appended claims.

[0032] refer to Figure 1 , Figure 2 and Figure 3 According to a first aspect of an embodiment of the present disclosure, a power management chip is provided, comprising: a functional circuit; a packaging layer, encapsulating the functional circuit; and a plurality of interfaces, located on the packaging layer and electrically connected to the functional circuit; wherein the plurality of interfaces are arranged in an array along row and column directions, and the plurality of interfaces include a first type of interface, a second type of interface, and a third type of interface located between the first type of interface and the second type of interface; the first type of interface includes a plurality of interface columns, at least for connecting a power output signal and for connecting an external circuit with a power buffering function; the second type of interface includes at least one interface column, at least for connecting a data input and / or output signal; the third type of interface includes a plurality of interface columns arranged along a column direction, at least for connecting a power input signal.

[0033] In some embodiments, the number of multiple interfaces is less than or equal to 132. For example, the number of multiple interfaces can be 132, and the multiple interfaces can be arranged in an array of 11 rows and 12 columns. The number of multiple interfaces can be 88, and the multiple interfaces can be arranged in an array of 11 rows and 8 columns. The number of multiple interfaces can also be less than 88, and the multiple interfaces can also be arranged in an array of 8 rows and 8 columns. Here and below, the number of multiple interfaces can be 88 as an example, and the multiple interfaces are arranged in an array of 11 rows and 8 columns as an example for detailed description. Specifically, refer to Figures 1 to 6 Shown are rows A, B, C, D, E, F, G, H, J, K, L (11 rows in total) and columns 1 to 8 (8 columns in total).

[0034] In some specific embodiments, the functional circuit ( Figure 1 , Figure 2 and Figure 3The power management chip (not shown) may include active devices and passive devices, such as MOS devices (composed of metal-oxide-semiconductor field-effect transistors (MOSFET)), capacitors, resistors, and inductors. The functional circuit includes a series of MOS tubes (short for MOSFET) and operational amplifiers (OA). The power management chip can reduce the impedance of the output circuit by adjusting the connection mode of the MOS tube, thereby increasing the charging current, or increase the output voltage by changing the operational amplifier of the operational amplifier, thereby increasing the charging current.

[0035] In some embodiments, the encapsulation layer ( Figure 1 , Figure 2 and Figure 3 The interconnect layer may include an insulating layer and an interconnect layer. The material of the insulating layer includes, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. The material of the interconnect layer includes, but is not limited to, tungsten, cobalt, nickel, copper, aluminum, polysilicon, doped silicon, silicide, nitride, or any combination thereof. The interconnect layer may include a conductive wire (metal) and a conductive channel (via).

[0036] In some specific embodiments, the connection between the functional circuit and the multiple interfaces can be realized through the encapsulation layer. For example, the multiple interfaces can be electrically connected to the functional circuit through the interconnection layer of the encapsulation layer.

[0037] In some specific embodiments, the plurality of interfaces may include a plurality of pads arranged in an array along the row direction and the column direction. The material of the pads includes but is not limited to tungsten, cobalt, nickel, copper, aluminum, polysilicon, doped silicon, silicide, nitride or any combination thereof.

[0038] In some specific embodiments, reference Figure 1 , Figure 2 and Figure 3 , the middle row of the first type of interface or the position adjacent to the middle row of the first type of interface can be used to arrange part of the third type of interface. Figure 1 , Figure 2 and Figure 3 The second type of interface can be used for all interfaces arranged for connecting data input and / or output signals. In some specific embodiments, reference Figure 2 and Figure 3 The edge position of the third type interface close to the multiple interfaces can be used to arrange part of the interfaces for connecting data input and / or output signals or part of the first type interface.

[0039] In some embodiments, the number of interfaces for connecting power output signals in the first type of interface is large, and they can be arranged vertically to facilitate internal and / or external routing and connection of the power management chip. In some embodiments, the number of interfaces for connecting external circuits with power buffering functions in the first type of interface is large, and they can be arranged vertically to facilitate external connection; the external circuits with power buffering functions are laid out according to the positions of the functional circuits inside the power management chip to ensure the voltage stability of the functional circuits.

[0040] refer to Figure 4 , Figure 5 and Figure 6 The first type of interface includes a plurality of interface columns including a first interface column and a second interface column; the first interface column is used to connect the power output signal VOUT; the second interface column is used to connect the ground signal GND.

[0041] In some specific embodiments, the interfaces for connecting the power output signal VOUT can be arranged vertically, which is convenient for routing and connection, and a large number of interfaces is conducive to reducing ground bounce, etc. The interfaces for connecting the power output signal VOUT can be connected to a battery. For example, the first interface column can be used to connect the power output signal VOUT, and the second interface column can be used to connect the ground signal GND.

[0042] In some specific embodiments, the interfaces for connecting the ground signal GND can be arranged vertically to facilitate the internal connection of the chip. A large number of interfaces is conducive to reducing output ripples, and the current is large, and the number design is also convenient for routing and connection.

[0043] Here, the routing may include internal interconnection lines, pads, pins, and printed circuit board (PCB) interconnection lines of the power management chip, and the connection may include contact and electrical connection between the internal interconnection lines, pads, pins, and printed circuit board interconnection lines of the power management chip to form a connection relationship.

[0044] In some specific embodiments, an output filter capacitor may be connected between an interface for connecting a power output signal VOUT and an interface for connecting a ground signal GND, so as to filter and stabilize the power output signal VOUT. For example, an output filter capacitor may include two capacitors with a capacitance value of 22uF.

[0045] refer to Figure 4 , Figure 5 and Figure 6In some embodiments, the first type of interface also includes interfaces located on both sides of the first interface column and used to connect the power input-output ratio signal; the interface for connecting the power input-output ratio signal is also located in the center interface row; the power input-output ratio signal is used to represent the ratio of the power input signal to the power output signal.

[0046] In some specific embodiments, the interface for connecting the proportional power output signal is not frequently used and can be arranged in the middle area of ​​the multiple interfaces.

[0047] In some specific embodiments, reference Figure 4 , the interface for connecting the proportional power output signal can be distributed on both sides of the interface for connecting the power output signal VOUT.

[0048] In some specific embodiments, the ratio of the power input signal to the power output signal ranges from 4:1 to 4:2. In some specific embodiments, the proportional power output signal includes a first proportional power output signal VO1 and a second proportional power output signal VO2, and the power input signal can be stepped down according to the first ratio or the second ratio to output the power output signal. For example, the ratio includes a first ratio and a second ratio, and the first proportional power output signal VO1 can be used to represent that the ratio of the power input signal to the power output signal is 4:1, and the second proportional power output signal VO2 can be used to represent that the ratio of the power input signal to the power output signal is 4:2.

[0049] In some specific embodiments, an output filter capacitor may be connected between an interface for connecting the first proportional power output signal VO1 and an interface for connecting the ground signal GND, which may play a role in filtering and stabilizing the first proportional power output signal VO1. For example, an output filter capacitor may include a capacitor with a capacitance value of 10uF. An output filter capacitor may be connected between an interface for connecting the second proportional power output signal VO2 and an interface for connecting the ground signal GND, which may play a role in filtering and stabilizing the second proportional power output signal VO2. For example, an output filter capacitor may include a capacitor with a capacitance value of 10uF.

[0050] In some embodiments, each flying capacitor is arranged according to the position of the functional circuit corresponding to the flying capacitor inside the chip to ensure the voltage stability of each flying capacitor. Each flying capacitor is arranged along the column direction to facilitate routing and connection. Each flying capacitor can be divided into four flying capacitors according to the two electrodes of the flying capacitor and the two phases of the flying capacitor. For example, taking the first flying capacitor as an example, the four flying capacitors can be the first phase C1NA and C1PA of the first flying capacitor, and the second phase C1NB and C1PB of the first flying capacitor.

[0051] refer to Figure 4 , Figure 5 and Figure 6 In some embodiments, the external circuit includes a flying capacitor; the flying capacitor includes a first flying capacitor C1 and a second flying capacitor C2; the first type of interface includes a plurality of interface columns including a third interface column, a fourth interface column and a fifth interface column; the third interface column, the fourth interface column and the fifth interface column each include a plurality of parts symmetrical with respect to a central interface row of the plurality of interfaces; wherein the first part of the third interface column is used to connect the first electrode and the first phasor of the first flying capacitor, the second part is used to connect the second electrode and the second phasor of the first flying capacitor, the third part is used to connect the first electrode and the second phasor of the first flying capacitor, the fourth part is used to connect the second electrode and the first phasor of the first flying capacitor; the first part of the fourth interface column is used to connect the first electrode and the first phasor of the second flying capacitor, and the second part is used to connect the first electrode and the second phasor of the second flying capacitor; the first part of the fifth interface column is used to connect the second electrode and the first phasor of the second flying capacitor, and the second part is used to connect the second electrode and the second phasor of the second flying capacitor.

[0052] It should be noted that the flying capacitor includes a first flying capacitor C1 and a second flying capacitor C2. "N" and "P" correspond to the two electrodes of the flying capacitor: the first electrode and the second electrode, respectively. "A" and "B" correspond to the two phases of the flying capacitor: the first phasor and the second phasor, respectively. For example, the first flying capacitor C1 includes the first electrode C1N of the first flying capacitor and the second electrode C1P of the first flying capacitor; the capacitance value of the first flying capacitor C1 includes the first phasors C1NA and C1PA of the first flying capacitor, and the second phasors C1NB and C1PB of the first flying capacitor. The first part of the third interface column is used to connect the first electrode C1N of the first flying capacitor, for the first phasor C1NA of the first flying capacitor; the second part of the third interface column is used to connect the second electrode C1P of the first flying capacitor, for the second phasor C1PB of the first flying capacitor; the third part of the third interface column is used to connect the first electrode C1N of the first flying capacitor, for the second phasor C1NB of the first flying capacitor; the fourth part of the third interface column is used to connect the second electrode C1P of the first flying capacitor, for the first phasor C1PA of the first flying capacitor; the first part of the fourth interface column is used to connect the first electrode C2N of the second flying capacitor, for the first phasor C2NA of the second flying capacitor; the second part of the fourth interface column is used to connect the first electrode C2N of the second flying capacitor, for the second phasor C2NB of the second flying capacitor; the first part of the fifth interface column is used to connect the second electrode C2P of the second flying capacitor, for the first phasor C2PA of the second flying capacitor; the first part of the fifth interface column is used to connect the second electrode C2P of the second flying capacitor, for the second phasor C2PB of the second flying capacitor.

[0053] In some specific embodiments, the third interface column can be partially used to connect the first phasor C1NA of the first flying capacitor, the second phasor C1NB of the first flying capacitor, the second phasor C1PB of the first flying capacitor, and the first phasor C1PA of the first flying capacitor. The fourth interface column can be partially used to connect the first phasor C2NA of the second flying capacitor and the second phasor C2NB of the second flying capacitor. The fifth interface column can be partially used to connect the first phasor C2PA of the second flying capacitor and the second phasor C2PB of the second flying capacitor.

[0054] In some specific embodiments, the first phasor C1NA of the first flying capacitor and the second phasor C1NB of the first flying capacitor are symmetrically distributed about the center interface row of multiple interfaces, the second phasor C1PB of the first flying capacitor and the first phasor C1PA of the first flying capacitor are symmetrically distributed about the center interface row of multiple interfaces; the first phasors C2NA and C2PA of the second flying capacitor and the second phasors C2NB and C2PB of the second flying capacitor are symmetrically distributed about the center interface row of multiple interfaces.

[0055] In some specific embodiments, a flying capacitor is connected between interfaces for connecting two electrodes of a flying capacitor, which can be used to smooth the fluctuation of the power input signal input to the power management chip. For example, a flying capacitor can be connected between an interface for connecting a first phasor C1NA of a first flying capacitor and an interface for connecting a first phasor C1PA of a first flying capacitor, between an interface for connecting a second phasor C1NB of a first flying capacitor and an interface for connecting a second phasor C1PB of a first flying capacitor, between an interface for connecting a first phasor C2NA of a second flying capacitor and an interface for connecting a first phasor C2PA of a first flying capacitor, and between an interface for connecting a second phasor C2NB of a second flying capacitor and an interface for connecting a second phasor C2PB of a first flying capacitor, which can be used to smooth the fluctuation of the power input signal input to the power management chip. Specifically, a flying capacitor can include four capacitors with a capacitance value of 22uF connected in parallel.

[0056] refer to Figure 4 , Figure 5 and Figure 6 In some embodiments, the first interface column, the second interface column, the third interface column, the fourth interface column and the fifth interface column are arranged adjacent to each other, and one of the first interface column, the second interface column, the third interface column, the fourth interface column and the fifth interface column is located at an edge position of a plurality of interfaces arranged in an array.

[0057] In some specific embodiments, reference Figure 4 , the second interface column is located at the edge of the plurality of interfaces, and the fourth interface column, the first interface column, the fifth interface column and the third interface column are adjacent to the second interface column in sequence. In some specific embodiments, reference Figure 5 , the first interface column is located at the edge of the plurality of interfaces, and the second interface column, the fourth interface column, the fifth interface column and the third interface column are adjacent to the first interface column in sequence. In some specific embodiments, reference Figure 6 The fourth interface column is located at an edge position among the multiple interfaces, and the first interface column, the fifth interface column, the second interface column and the third interface column are adjacent to the fourth interface column in sequence.

[0058] In some embodiments, at least one of the plurality of interfaces arranged along the column direction includes a sixth interface column; the sixth interface column includes a serial interface for connecting to an integrated circuit bus IICBus (Inter-Integrated Circuit Bus) (also referred to as I2C, IIC or I 2 C) interface.

[0059] refer to Figure 4 , Figure 5 and Figure 6 In some embodiments, the second type of interface includes a sixth interface column; the sixth interface column includes an interface for connecting an I2C communication signal and an interface for connecting a data input and / or output signal; the interface for connecting an I2C communication signal is arranged at an edge position among multiple interfaces. For example, the sixth interface column includes an interface for connecting a data input and / or output signal SDA and an interface for connecting a clock signal SCL. The interface for connecting an I2C communication signal is arranged at an edge position among multiple interfaces at the edge, which facilitates differential routing.

[0060] In some specific embodiments, the interface for connecting the I2C communication signal is located in the middle of the sixth interface column.

[0061] In some specific embodiments, the sixth interface row is located at an edge position among the multiple interfaces and is arranged at the edge to facilitate differential routing and connection.

[0062] In some embodiments, the data input and / or output signal SDL is connected to the logic rail through a pull-up resistor (typically 10 kΩ). In some embodiments, the integrated circuit bus IICBus can be reset by enabling (e.g., 30 milliseconds) the data input and / or output signal SDA.

[0063] In some specific embodiments, the clock signal SCL is connected to the logic rail through a pull-up resistor (typically 10 kΩ).

[0064] refer to Figure 4 , Figure 5 and Figure 6In some embodiments, the sixth interface column further includes at least one of the following multiple interfaces: an interface for connecting voltage detection signals BATN and BATP, including an interface for a negative input of battery voltage sensing and an interface for a positive input of battery voltage sensing; the voltage detection signal requires high accuracy; the interface for connecting the voltage detection signal is arranged at an edge position among the multiple interfaces; an interface for connecting a low power mode enable signal nLPM, the low power mode enable signal is a functional signal line for the power management chip to enter a specific mode; the interface for connecting the low power mode enable signal is arranged at an edge position among the multiple interfaces; An interface for connecting the state change alarm signal nINT, which is a functional signal line and is used for issuing a state change alarm for a corresponding event of the power management chip; an interface for connecting the state change alarm signal is arranged at an edge position among multiple interfaces; an interface for connecting the low voltage difference signal REGN, which is used to provide a reference voltage; the layout of the interface for connecting the low voltage difference signal takes into account the internal connection of the power management chip; an interface for connecting the analog ground signal, which is separated from the ground signal of the input signal of the switched capacitor power stage; the current of the analog ground signal is small, and the interface for connecting the analog ground signal is externally connected to the main ground at a single point.

[0065] In some specific embodiments, the voltage detection signals BATN and BATP of the battery require high precision, and the interface for connecting the voltage detection signals BATN and BATP is placed at the edge of multiple interfaces to facilitate direct connection with the battery. In some specific embodiments, the interface connecting the voltage detection signal BATN is used as the negative input of the battery voltage sensing and is connected to the negative terminal of the battery pack. In some specific embodiments, a 100 ohm series resistor is placed between the interface connecting the voltage detection signal BATN and the negative terminal. In some specific embodiments, the interface connecting the voltage detection signal BATP is used as the positive input of the battery voltage sensing and is connected to the positive terminal of the battery pack. In some specific embodiments, a 100 ohm series resistor is placed between the interface connecting the voltage detection signal BATP and the positive terminal.

[0066] In some specific embodiments, the low power mode enable signal nLPM is used as a functional signal line for the chip to enter a specific mode. The interface for connecting the low power mode enable signal nLPM is arranged at the edge area of ​​multiple interfaces, with low utilization and low external connection requirements. In some specific embodiments, the interface for connecting the low power mode enable signal nLPM is used as a low power mode enable interface. The low power mode enable signal nLPM is enabled when it is logic low. Specifically, the rising edge of the low power mode enable signal nLPM is equivalent to writing a logic high, for example, the reset terminal of the mode register is logic high (REG_RST=1).

[0067] In some specific embodiments, the state change alarm signal nINT is used as a functional signal line for the chip to issue a state change alarm for a corresponding event. The interface for connecting the state change alarm signal nINT is arranged at the edge area of ​​multiple interfaces, with a low utilization rate and low external connection requirements. In some specific embodiments, the interface for connecting the state change alarm signal nINT can be used as an output that activates low logic to issue a state change alarm for a corresponding event. In some specific embodiments, a pull-up resistor, typically 10kΩ, can be placed on the rail of the data input / output of the integrated circuit bus IICBus.

[0068] In some specific embodiments, the low voltage difference signal REGN is used to provide a reference voltage. The placement of the interface for connecting the low voltage difference signal REGN needs to take into account the connection of the internal circuit of the power management chip, and can be placed at the edge of multiple interfaces. In some specific embodiments, the interface for connecting the low voltage difference signal REGN is used as the output of a low voltage difference linear regulator (Low Dropout Regulaor, LDO). In some specific embodiments, a capacitor with a capacitance value of 4.7μF is connected between the interface for connecting the low voltage difference signal REGN and the interface for connecting the ground signal GND.

[0069] In some specific embodiments, the voltages of the input signals of the wireless input sensing signal VWPC and the USB input sensing signal VUSB are relatively high and can be placed at the edge of multiple interfaces. In some specific embodiments, the interface for connecting the wireless input sensing signal VWPC is used as the input of the wireless input voltage sensing, and the interface for connecting the USB input sensing signal VUSB is used as the input of the USB input voltage sensing.

[0070] In some specific embodiments, the charge pump output signals OVPGATE and WPCGATE are used as the front-end gate (GATE) voltage and are placed at the edge of multiple interfaces for external connection, wherein the charge pump output signals OVPGATE and WPCGATE correspond to wired gates and wireless gates, respectively. In some specific embodiments, the interface for connecting the charge pump output signals OVPGATE and WPCGATE needs to be located near the interface for connecting the power input signal VBUS. In some specific embodiments, the interface for connecting the charge pump output signal WPCGATE is used as the output of the wireless input sensing signal VWPC charge pump to drive the dual N-type metal oxide semiconductor field effect transistor N-MOSFET (N-type Metal Oxide SemiconductorField-Effect Transistor, N-MOSFET) from the wireless input sensing signal VWPC to the power input signal VBUS. When the on condition is met, when both N-MOSFETs are enabled, the charge pump output signal WPCGATE voltage is 5V higher than the power input signal VBUS voltage. If N-MOSFET is not used, the charge pump output signal WPCGATE is connected to the ground signal GND. In some specific embodiments, the interface for connecting the charge pump output signal OVPGATE is used as the output of the USB input sensing signal VUSB charge pump to drive the dual N-MOSFET from the USB input sensing signal VUSB to the power input signal VBUS. When the on condition is met, when both N-MOSFETs are enabled, the charge pump output signal OVPGATE voltage is 5V higher than the power input signal VBUS voltage. If the N-MOSFET is not used, the charge pump output signal WPCGATE is connected to the ground signal GND.

[0071] refer to Figure 4 , Figure 5 and Figure 6 In some embodiments, the sixth interface column further includes an interface for connecting an analog ground signal AGND. In some specific embodiments, the interface for connecting the analog ground signal AGND is spaced at least two interfaces away from the first type of interface, and the analog ground signal AGND is interfered by the signal transmitted in the first type of interface.

[0072] refer to Figure 4 , Figure 5 and Figure 6In some embodiments, the third type interface includes two parts; the two parts are symmetrical with respect to the central interface row of the multiple interfaces; the multiple interfaces arranged along the column direction include adjacent seventh interface columns and eighth interface columns; the external circuit includes a switching capacitor; wherein the seventh interface column is used to connect the power stage input signal PMID and the ground signal GND of the switching capacitor; the eighth interface column is used to connect the power input signal VBUS.

[0073] In some embodiments, the seventh interface column includes an interface for connecting to a ground signal GND, which may serve as an interface of the ground signal GND corresponding to an interface for connecting to a power input signal VBUS.

[0074] In some specific embodiments, the MOS devices for receiving the power level input signal PMID and the power input signal VBUS in the functional circuit of the power management chip are adjacent, and there is a MOS device between the MOS device receiving the power level input signal PMID and the MOS device receiving the power input signal VBUS. The voltage of the power level input signal PMID is similar to the voltage of the power input signal VBUS, so they are arranged according to the position in the functional circuit of the power management chip and placed near the edge of multiple interfaces to facilitate routing and connection.

[0075] In some specific embodiments, the power stage input signal PMID is an input of the switched capacitor power stage. In some specific embodiments, a capacitor with a capacitance value of 10 μF is connected between the interface for connecting the power stage input signal PMID and the interface for connecting the ground signal GND. In some specific embodiments, the power input signal VBUS is used as the input of the input power. A capacitor with a capacitance value of 10 μF is connected between the interface for connecting the power input signal VBUS and the interface for connecting the ground signal GND, and the capacitor with a capacitance value of 10 μF is as close as possible to the interface for connecting the ground signal GND.

[0076] refer to Figure 4 , Figure 5 and Figure 6 In some embodiments, the third type of interface also includes multiple analysis interfaces BST1A, BST1B, BST2, BST3A, and BST3B located in the center interface row and the eighth interface column; multiple analysis interfaces are arranged in the middle position of the multiple interfaces and are used to connect bootstrap capacitors for problem analysis; the seventh interface column also includes auxiliary interfaces LA, LB and an address allocation interface ADDR, all of which are arranged at the edge positions of the multiple interfaces; the multiple auxiliary interfaces include an interface for connecting to the first power line LA and an interface for connecting to the second power line LB; the address allocation interface ADDR is used to allocate the address of the power management chip during power-on reset (POR).

[0077] In some embodiments, the sixth interface column also includes: an interface for connecting the wireless input sensing signal WPC, adjacent to the interface for connecting the input signal PMID of the switch capacitor power stage; an interface for connecting the USB input sensing signal VUSB, adjacent to the interface for connecting the input signal PMID of the switch capacitor power stage; an interface for connecting the charge pump output signal OVPGATE of the USB input sensing signal, adjacent to the interface for connecting the input signal PMID of the switch capacitor power stage, or adjacent to the interface of the charge pump output signal OVPGATE of the wireless input sensing signal; an interface for connecting the analog ground signal AGND, spaced from the ground signal of the input signal PMID of the switch capacitor power stage; the seventh interface column also includes: an interface for connecting the charge pump output signal WPCGATE of the wireless input sensing signal, adjacent to the interface for connecting the input signal PMID of the switch capacitor power stage, and arranged at the edge position of the multiple interfaces. In some specific embodiments, multiple analysis interfaces BST1A, BST1B, BST2, BST3A, BST3B can be used to connect to the bootstrap capacitor of the gate driver. In some specific embodiments, a capacitor with a capacitance value of 220nF is connected between the analysis interface BST3A and the interface for connecting the first phasor C2PA of the second flying capacitor. A capacitor with a capacitance value of 220nF is connected between the analysis interface BST3B and the interface for connecting the second phasor C2PB of the second flying capacitor. A capacitor with a capacitance value of 100nF is connected between the analysis interface BST1A and the interface for connecting the first phasor C1PA of the first flying capacitor. A capacitor with a capacitance value of 100nF is connected between the analysis interface BST1B and the interface for connecting the second phasor C1PB of the first flying capacitor. A capacitor with a capacitance value of 100nF is connected between the analysis interface BST2 and the interface for connecting the first proportional power supply output signal VO1.

[0078] In some specific embodiments, multiple auxiliary interfaces LA and LB are arranged at the edge area of ​​multiple interfaces, and the external connection requirements are not high. In some specific embodiments, the address allocation interface ADDR is arranged at the edge area of ​​multiple interfaces.

[0079] In some specific embodiments, the external auxiliary circuit can provide additional functions, such as overload protection, short circuit protection, and temperature protection.

[0080] In some embodiments, the power management chip includes a charge pump charging chip.

[0081] refer to Figure 7According to a second aspect of an embodiment of the present disclosure, a second power management chip is provided, including: a functional circuit; a packaging layer encapsulating the functional circuit; and a plurality of interfaces, located on the packaging layer and electrically connected to the functional circuit, including a first interface column to an eighth interface column arranged in an array along a row direction and a column direction; wherein the first interface column is used to connect a ground signal GND; a first part of the second interface column is used to connect a first electrode of a second flying capacitor of an external circuit and a first phase output C2NA, a second part is used to connect a first electrode of the second flying capacitor and a second phase output C2NB, and a central interface row of the second interface column is used to connect a second power input-output ratio signal VO2; wherein the first part of the second interface column and the second part of the second interface column Located on both sides of the center interface row; the third interface column is used to connect the power output signal VOUT; the first part of the fourth interface column is used to connect the second electrode of the second flying capacitor and the first phase C2PA, the second part is used to connect the second electrode of the second flying capacitor and the second phase C2PB, and the center interface row of the fourth interface column is used to connect the first power input-output proportional signal VO1; wherein the first part of the fourth interface column and the second part of the fourth interface column are located on both sides of the center interface row; the first part of the fifth interface column is used to connect the first electrode of the first flying capacitor and the first phase C1NA of the external circuit, the second part is used to connect the second electrode of the first flying capacitor and the second phase C1PB, and the third part is used to connect the first flying capacitor. The first electrode and the second phase of the flying capacitor C1NB, the fourth part is used to connect the second electrode and the first phase of the first flying capacitor C1PA, and the central interface row of the fifth interface column is used to connect the bootstrap capacitor BST3A of the external circuit; wherein, the second part of the fifth interface column and the fourth part of the fifth interface column are located on both sides of the central interface row, the first part of the fifth interface column is located outside the second part of the fifth interface column, and the third part of the fifth interface column is located outside the fourth part of the fifth interface column; the first part and the second part of the sixth interface column are used to connect the input signal PMID of the switched capacitor power stage of the external circuit, the third part and the fourth part of the sixth interface column are used to connect the ground signal GND of the external circuit, and the sixth interface column The central interface row is used to connect the bootstrap capacitor BST3B of the external circuit; wherein the first part of the sixth interface column and the second part of the sixth interface column are located on both sides of the central interface row, the third part of the sixth interface column is located outside the first part of the sixth interface column, and the fourth part of the sixth interface column is located outside the second part of the sixth interface column; the first part of the seventh interface column is used to connect the bootstrap capacitors BST2, BST1A, and BST1B of the external circuit, the second part and the third part are used to connect the power input signal VBUS, the fourth part is used to connect the first auxiliary signal LA and the address allocation signal ADDR, and the fifth part is used to connect the second auxiliary signal LB and the charge pump output signal WPCGATE of the wireless input sensing signal;Among them, the first part of the seventh interface column is located on both sides of the central interface row and the central interface row, the second part and the third part of the seventh interface column are located on both sides of the first part of the seventh interface column and are adjacent to the first part and the second part of the sixth interface column, the fourth part of the seventh interface column is located outside the second part of the seventh interface column, and the fifth part of the seventh interface column is located outside the third part of the seventh interface column; the eighth interface column is used to connect the negative input signal BATN of the battery voltage sensing, the positive input BATP of the battery voltage sensing, the low power mode enable signal nLPM, the state change alarm signal nINT, the data input and / or output signal SDA, the clock signal SCL, the low voltage difference signal RENG, Analog ground signal AGND, wireless input sensing signal WPC, USB input sensing signal VUSB, charge pump output signal OVPGATE of USB input sensing signal; wherein, the interface for connecting data input and / or output signal and the interface for connecting clock signal are located in the middle of the eighth interface column, the interface for connecting wireless input sensing signal and the interface for connecting USB input sensing signal are adjacent to the interface for connecting input signal of switch capacitor power stage, and the interface for connecting charge pump output signal of USB input sensing signal is adjacent to the interface for connecting input signal of switch capacitor power stage or adjacent to the interface of charge pump output signal of wireless input sensing signal. ;

[0082] refer to Figure 7 Table 1 describes in detail the locations of multiple interfaces of the power management chip, the abbreviations of the signals transmitted by the interfaces, the categories of the signals transmitted by the interfaces, and a brief description of the corresponding interfaces (or pins) and the signals transmitted by the interfaces. Figure 7 As shown in the A, B, C, D, E, F, G, H, J, K, L rows (a total of 11 rows) and 1 to 8 columns (representing the first interface column to the eighth interface column, respectively), illustratively, the interface position "A1" represents the interface located in the first row and the first column among the multiple interfaces, the signal abbreviation "GND" transmitted by the interface indicates that the interface located in the first row and the first column is used for grounding, and the category "Power" of the signal transmitted by the interface indicates that the interface class table located in the first row and the first column belongs to the power signal class.

[0083] Table 1

[0084]

[0085]

[0086]

[0087] The power management chip in each embodiment of the present disclosure includes: a functional circuit; a packaging layer, encapsulating the functional circuit; and a plurality of interfaces, located on the packaging layer and electrically connected to the functional circuit; wherein the plurality of interfaces are arranged in an array along the row direction and the column direction, and the plurality of interfaces include a first type of interface, a second type of interface, and a third type of interface located between the first type of interface and the second type of interface; the first type of interface includes a plurality of interface columns, at least for connecting a power output signal and for connecting an external circuit with a power buffering function; the second type of interface includes at least one interface column, at least for connecting a data input and / or output signal; the third type of interface includes a plurality of interface columns arranged along the column direction, at least for connecting a power input signal. In this way, the power density of the power management chip can be improved, the power management efficiency can be improved, and the cost can be reduced.

[0088] refer to Figure 8 According to the second aspect of the embodiment of the present disclosure, there is provided an electronic device 700 comprising: a battery 704, a flying capacitor 706, a controller 708, a power supply 710 and a power management chip 702 of any one of the above-mentioned first aspects; wherein the first type interface of the power management chip is connected to the battery 704 and the flying capacitor 706, and is used to smooth the fluctuation of the power input signal input to the power management chip; the second type interface of the power management chip is connected to the controller 708; and the third type interface of the power management chip 702 is connected to the power supply 710.

[0089] In some specific embodiments, the power management chip 702 may interact with the controller 708 via a bus 707 ; the power management chip 702 may be connected to the power supply 710 via a wired or wireless connection 709 .

[0090] In some specific embodiments, the electronic device 700 also includes an input filter capacitor 712 and an output filter capacitor 714; the power management chip 702 is connected to the input filter capacitor 712 and the output filter capacitor 714; wherein the first type of interface is also used to connect the output filter capacitor 714; and the third type of interface is also used to connect the input filter capacitor 712.

[0091] Fig. 9 800 is a block diagram of a device according to an exemplary embodiment. For example, the device 800 may be a mobile phone, a mobile computer, etc.

[0092] Reference Fig. 9 , the apparatus 800 may include one or more of the following components: a processing component 802 (which may include Figure 8 Controller 708 shown), memory 804, power supply component 806 (which may include Figure 8The power management chip 702 is shown, a multimedia component 808, an audio component 810, an input / output (I / O) interface 812, a sensor component 814, and a communication component 816.

[0093] The processing component 802 generally controls the overall operation of the device 800, such as operations associated with display, phone calls, data communications, camera operations, and recording operations. The processing component 802 may include one or more processors 820 to execute instructions to complete all or part of the steps of the above-mentioned method. In addition, the processing component 802 may include one or more modules to facilitate the interaction between the processing component 802 and other components. For example, the processing component 802 may include a multimedia module to facilitate the interaction between the multimedia component 808 and the processing component 802.

[0094] The memory 804 is configured to store various types of data to support operations on the device 800. Examples of such data include instructions for any application or method operating on the device 800, contact data, phone book data, messages, pictures, videos, etc. The memory 804 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk.

[0095] The power component 806 interacts with the processing component 802 via the bus 807. The power component 806 provides power to various components of the device 800. The power component 806 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power for the device 800.

[0096] The multimedia component 808 includes a screen that provides an output interface between the device 800 and the user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touch screen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touch, slide, and gestures on the touch panel. The touch sensor may not only sense the boundaries of the touch or slide action, but also detect the duration and pressure associated with the touch or slide operation. In some embodiments, the multimedia component 808 includes a front camera and / or a rear camera. When the device 800 is in an operating mode, such as a shooting mode or a video mode, the front camera and / or the rear camera may receive external multimedia data. Each front camera and rear camera may be a fixed optical lens system or have a focal length and optical zoom capability.

[0097] The audio component 810 is configured to output and / or input audio signals. For example, the audio component 810 includes a microphone (MIC), and when the device 800 is in an operating mode, such as a call mode, a recording mode, and a speech recognition mode, the microphone is configured to receive an external audio signal. The received audio signal can be further stored in the memory 804 or sent via the communication component 816. In some embodiments, the audio component 810 also includes a speaker for outputting audio signals.

[0098] I / O interface 812 provides an interface between processing component 802 and peripheral interface modules, such as keyboards, click wheels, buttons, etc. These buttons may include but are not limited to: home button, volume button, start button, and lock button.

[0099] The sensor assembly 814 includes one or more sensors for providing various aspects of status assessment for the device 800. For example, the sensor assembly 814 can detect the open / closed state of the device 800, the relative positioning of components, such as the display and keypad of the device 800, the sensor assembly 814 can also detect the position change of the device 800 or a component of the device 800, the presence or absence of user contact with the device 800, the orientation or acceleration / deceleration of the device 800 and the temperature change of the device 800. The sensor assembly 814 can include a proximity sensor configured to detect the presence of nearby objects without any physical contact. The sensor assembly 814 can also include an optical sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, the sensor assembly 814 can also include an accelerometer, a gyroscope sensor, a magnetic sensor, a pressure sensor or a temperature sensor.

[0100] The communication component 816 is configured to facilitate wired or wireless communication between the device 800 and other devices. The device 800 can access a wireless network based on a communication standard, such as Wi-Fi, 4G or 5G, or a combination thereof. In an exemplary embodiment, the communication component 816 receives a broadcast signal or broadcast-related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component 816 also includes a near field communication (NFC) module to facilitate short-range communication. For example, the NFC module can be implemented based on radio frequency identification (RFID) technology, infrared data association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology and other technologies.

[0101] In an exemplary embodiment, the apparatus 800 may be implemented by one or more application specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors or other electronic components to perform the above method.

[0102] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is also provided, such as a memory 804 including instructions, and the instructions can be executed by the processor 820 of the device 800 to perform the above method. For example, the non-transitory computer-readable storage medium can be a ROM, a random access memory (RAM), a CD-ROM, a magnetic tape, a floppy disk, an optical data storage device, etc.

[0103] Fig.10 900 is a hardware structure block diagram of a device according to an exemplary embodiment. For example, the device 900 may be provided as a server. Fig.10 , the device 900 includes a processing component 922, which further includes one or more processors, and a memory resource represented by a memory 932 for storing instructions, such as applications, that can be executed by the processing component 922. The application stored in the memory 932 may include one or more modules, each corresponding to a set of instructions.

[0104] The device 900 may also include a power supply assembly 926 (see Figure 8 The electronic device 700 shown is understood to be configured to perform power management of the device 900, a wired or wireless network interface 950 configured to connect the device 900 to a network, and an input / output (I / O) interface 958. The device 900 can operate based on an operating system stored in the memory 932, such as Windows ServerTM, Mac OS XTM, UnixTM, LinuxTM, FreeBSDTM or the like.

[0105] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial number of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.

[0106] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0107] In the several embodiments provided in the present disclosure, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored, or not executed. In addition, the coupling, direct coupling, or communication connection between the components shown or discussed can be through some interfaces, and the indirect coupling or communication connection of the devices or units can be electrical, mechanical or other forms.

[0108] The units described above as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units; they may be located in one place or distributed on multiple network units; some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

[0109] In addition, all functional units in the embodiments of the present disclosure may be integrated into one processing unit, or each unit may be separately configured as a unit, or two or more units may be integrated into one unit; the above-mentioned integrated units may be implemented in the form of hardware or in the form of hardware plus software functional units.

[0110] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the schemes disclosed herein. The present disclosure is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary technical means in the art that are not disclosed in the present disclosure. The description and examples are to be regarded as exemplary only, and the true scope and spirit of the present disclosure are indicated by the following claims.

[0111] It should be understood that the present disclosure is not limited to the exact structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A power management chip, characterized in that: include: Functional circuit; A packaging layer encapsulating the functional circuit; and A plurality of interfaces, located on the packaging layer and electrically connected to the functional circuit; The multiple interfaces are arranged in an array along the row direction and the column direction, and the multiple interfaces include a first type of interface, a second type of interface, and a third type of interface located between the first type of interface and the second type of interface; The first type of interface includes a plurality of interface columns, which are used at least for connecting power supply output signals and for connecting external circuits with power buffering functions; The second type of interface includes at least one interface column, which is at least used to connect data input and / or output signals; The third type of interface includes a plurality of interface columns arranged along a column direction, and is at least used for connecting a power input signal.

2. The power management chip according to claim 1, characterized in that: The plurality of interface columns included in the first type of interface include a first interface column and a second interface column; The first interface column is used to connect the power output signal; the second interface column is used to connect the ground signal.

3. The power management chip according to claim 2, characterized in that: The first type of interface also includes interfaces located on both sides of the first interface column and used to connect the power input-output ratio signal; the interface used to connect the power input-output ratio signal is also located in the center interface row; The power input-output ratio signal is used to represent the ratio of the power input signal to the power output signal.

4. The power management chip according to claim 2, characterized in that: The external circuit includes a flying capacitor; the flying capacitor includes a first flying capacitor and a second flying capacitor; The plurality of interface columns included in the first type of interface include a third interface column, a fourth interface column and a fifth interface column; the third interface column, the fourth interface column and the fifth interface column each include a plurality of parts symmetrical with respect to the central interface row; wherein, The first part of the third interface column is used to connect the first electrode of the first flying capacitor and the first phasor, the second part is used to connect the second electrode of the first flying capacitor and the second phasor, the third part is used to connect the first electrode of the first flying capacitor and the second phasor, and the fourth part is used to connect the second electrode of the first flying capacitor and the first phasor; The first part of the fourth interface column is used to connect the first electrode of the second flying capacitor and the first phasor, and the second part is used to connect the first electrode of the second flying capacitor and the second phasor; The first part of the fifth interface column is used to connect the second electrode of the second flying capacitor and the first phasor, and the second part is used to connect the second electrode of the second flying capacitor and the second phasor.

5. The power management chip according to claim 4, characterized in that: The first interface column, the second interface column, the third interface column, the fourth interface column and the fifth interface column are arranged adjacent to each other, and one of the first interface column, the second interface column, the third interface column, the fourth interface column and the fifth interface column is located at an edge position of the multiple interfaces arranged in an array.

6. The power management chip according to claim 1, characterized in that: The second type of interface includes a sixth interface column; The sixth interface column includes an interface for connecting to an I2C communication signal, an interface for connecting to a clock signal, and an interface for connecting to the data input and / or output signal.

7. The power management chip according to claim 6, characterized in that: The sixth interface column further includes at least one of the following multiple interfaces: An interface for connecting a voltage detection signal, including an interface for a negative input of a battery voltage sensing and an interface for a positive input of a battery voltage sensing; Interface for connecting low power mode enable signal; Interface for connecting state change alarm signal; Interface for connecting low voltage dropout signals.

8. The power management chip according to claim 7, characterized in that: The interface for connecting the I2C communication signal, the interface for connecting the voltage detection signal, the interface for connecting the low power mode enable signal, and the interface for connecting the state change alarm signal are all located at the edge of the multiple interfaces arranged in an array.

9. The power management chip according to claim 7, characterized in that: The third type of interface includes two parts; the two parts are symmetrical with respect to the central interface row; the plurality of interface columns arranged along the column direction include the adjacent seventh interface column and the eighth interface column; the external circuit includes a switch capacitor; The seventh interface column is used to connect the input signal and the ground signal of the switch capacitor power stage; and the eighth interface column is used to connect the power input signal.

10. The power management chip according to claim 9, characterized in that: The third type of interface also includes multiple analysis interfaces located in the central interface row and the eighth interface column; the multiple analysis interfaces are arranged in the middle position of the multiple interfaces and are used to connect bootstrap capacitors for problem analysis; the seventh interface column also includes an auxiliary interface and an address allocation interface, both of which are arranged at the edge positions of the multiple interfaces; the auxiliary interface includes an interface for connecting to a first power line and an interface for connecting to a second power line; the address allocation interface is used to allocate the address of the power management chip during power-on reset.

11. The power management chip according to claim 10, characterized in that: The sixth interface column also includes: an interface for connecting a wireless input sensing signal, adjacent to an interface for connecting an input signal of the switched capacitor power stage; an interface for connecting a USB input sensing signal, adjacent to an interface for connecting an input signal of the switched capacitor power stage; An interface for connecting a charge pump output signal of a USB input sensing signal is adjacent to an interface for connecting an input signal of the switched capacitor power stage, or adjacent to an interface for connecting a charge pump output signal of a wireless input sensing signal; An interface for connecting an analog ground signal to a ground signal spacing of an input signal of a switched capacitor power stage; The seventh interface column also includes: The interface for connecting the charge pump output signal of the wireless input sensing signal is adjacent to the interface for connecting the input signal of the switch capacitor power stage and is arranged at an edge position among the multiple interfaces.

12. The power management chip according to claim 1, characterized in that: The power management chip includes a charge pump charging chip.

13. A power management chip, characterized in that: include: Functional circuit; A packaging layer encapsulating the functional circuit; and A plurality of interfaces, located on the packaging layer and electrically connected to the functional circuit, include a first interface column to an eighth interface column arranged in an array along the row direction and the column direction; wherein, The first interface column is used to connect a ground signal; The first part of the second interface column is used to connect the first electrode and the first phasor of the second flying capacitor of the external circuit, the second part is used to connect the first electrode and the second phasor of the second flying capacitor, and the central interface row of the second interface column is used to connect the second power supply input and output proportional signal; wherein the first part of the second interface column and the second part of the second interface column are located on both sides of the central interface row; The third interface column is used to connect the power output signal; The first part of the fourth interface column is used to connect the second electrode of the second flying capacitor and the first phasor, the second part is used to connect the second electrode of the second flying capacitor and the second phasor, and the central interface row of the fourth interface column is used to connect the first power supply input-output proportional signal; wherein the first part of the fourth interface column and the second part of the fourth interface column are located on both sides of the central interface row; The first part of the fifth interface column is used to connect the first electrode and the first phasor of the first flying capacitor of the external circuit, the second part is used to connect the second electrode and the second phasor of the first flying capacitor, the third part is used to connect the first electrode and the second phasor of the first flying capacitor, the fourth part is used to connect the second electrode and the first phasor of the first flying capacitor, and the central interface row of the fifth interface column is used to connect the bootstrap capacitor of the external circuit; wherein the second part of the fifth interface column and the fourth part of the fifth interface column are located on both sides of the central interface row, the first part of the fifth interface column is located outside the second part of the fifth interface column, and the third part of the fifth interface column is located outside the fourth part of the fifth interface column; The first part and the second part of the sixth interface column are used to connect the input signal of the switch capacitor power stage of the external circuit, the third part and the fourth part of the sixth interface column are used to connect the ground signal of the external circuit, and the central interface row of the sixth interface column is used to connect the bootstrap capacitor of the external circuit; wherein the first part of the sixth interface column and the second part of the sixth interface column are located on both sides of the central interface row, the third part of the sixth interface column is located outside the first part of the sixth interface column, and the fourth part of the sixth interface column is located outside the second part of the sixth interface column; The first part of the seventh interface column is used to connect the bootstrap capacitor of the external circuit, the second part and the third part are used to connect the power input signal, the fourth part is used to connect the first auxiliary signal and the address allocation signal, and the fifth part is used to connect the second auxiliary signal and the charge pump output signal of the wireless input sensing signal; wherein the first part of the seventh interface column is located at the center interface row and both sides of the center interface row, the second part and the third part of the seventh interface column are located at both sides of the first part of the seventh interface column and are adjacent to the first part and the second part of the sixth interface column, the fourth part of the seventh interface column is located outside the second part of the seventh interface column, and the fifth part of the seventh interface column is located outside the third part of the seventh interface column; The eighth interface column is used to connect the negative input signal of battery voltage sensing, the positive input of battery voltage sensing, the low power mode enable signal, the state change alarm signal, the data input and / or output signal, the clock signal, the low voltage difference signal, the analog ground signal, the wireless input sensing signal, the USB input sensing signal, and the charge pump output signal of the USB input sensing signal; wherein, the interface for connecting the data input and / or output signal and the interface for connecting the clock signal are located in the middle position of the eighth interface column, the interface for connecting the wireless input sensing signal and the interface for connecting the USB input sensing signal are adjacent to the interface for connecting the input signal of the switch capacitor power stage, and the interface for connecting the charge pump output signal of the USB input sensing signal is adjacent to the interface for connecting the input signal of the switch capacitor power stage or is adjacent to the interface of the charge pump output signal of the wireless input sensing signal.

14. An electronic device, characterized in that: include: A battery, a flying capacitor, a controller, a power supply, and a power management chip as described in any one of claims 1 to 12; wherein: The first type interface of the power management chip is connected to the battery and the flying capacitor, and is used to smooth the fluctuation of the power input signal input to the power management chip; The second type interface of the power management chip is connected to the controller; The third type interface of the power management chip is connected to the power supply.

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